drivers/misc/habanalabs/goya/goya.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * Copyright 2016-2019 HabanaLabs, Ltd.
   5  * All Rights Reserved.
   6  */
   7
   8 #include "goyaP.h"
   9 #include "include/hw_ip/mmu/mmu_general.h"
  10 #include "include/hw_ip/mmu/mmu_v1_0.h"
  11 #include "include/goya/asic_reg/goya_masks.h"
  12 #include "include/goya/goya_reg_map.h"
  13
  14 #include <linux/pci.h>
  15 #include <linux/genalloc.h>
  16 #include <linux/hwmon.h>
  17 #include <linux/io-64-nonatomic-lo-hi.h>
  18 #include <linux/iommu.h>
  19 #include <linux/seq_file.h>
  20
  21 /*
  22  * GOYA security scheme:
  23  *
  24  * 1. Host is protected by:
  25  *        - Range registers (When MMU is enabled, DMA RR does NOT protect host)
  26  *        - MMU
  27  *
  28  * 2. DRAM is protected by:
  29  *        - Range registers (protect the first 512MB)
  30  *        - MMU (isolation between users)
  31  *
  32  * 3. Configuration is protected by:
  33  *        - Range registers
  34  *        - Protection bits
  35  *
  36  * When MMU is disabled:
  37  *
  38  * QMAN DMA: PQ, CQ, CP, DMA are secured.
  39  * PQ, CB and the data are on the host.
  40  *
  41  * QMAN TPC/MME:
  42  * PQ, CQ and CP are not secured.
  43  * PQ, CB and the data are on the SRAM/DRAM.
  44  *
  45  * Since QMAN DMA is secured, KMD is parsing the DMA CB:
  46  *     - KMD checks DMA pointer
  47  *     - WREG, MSG_PROT are not allowed.
  48  *     - MSG_LONG/SHORT are allowed.
  49  *
  50  * A read/write transaction by the QMAN to a protected area will succeed if
  51  * and only if the QMAN's CP is secured and MSG_PROT is used
  52  *
  53  *
  54  * When MMU is enabled:
  55  *
  56  * QMAN DMA: PQ, CQ and CP are secured.
  57  * MMU is set to bypass on the Secure props register of the QMAN.
  58  * The reasons we don't enable MMU for PQ, CQ and CP are:
  59  *     - PQ entry is in kernel address space and KMD doesn't map it.
  60  *     - CP writes to MSIX register and to kernel address space (completion
  61  *       queue).
  62  *
  63  * DMA is not secured but because CP is secured, KMD still needs to parse the
  64  * CB, but doesn't need to check the DMA addresses.
  65  *
  66  * For QMAN DMA 0, DMA is also secured because only KMD uses this DMA and KMD
  67  * doesn't map memory in MMU.
  68  *
  69  * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode)
  70  *
  71  * DMA RR does NOT protect host because DMA is not secured
  72  *
  73  */
  74
  75 #define GOYA_MMU_REGS_NUM               63
  76
  77 #define GOYA_DMA_POOL_BLK_SIZE          0x100           /* 256 bytes */
  78
  79 #define GOYA_RESET_TIMEOUT_MSEC         500             /* 500ms */
  80 #define GOYA_PLDM_RESET_TIMEOUT_MSEC    20000           /* 20s */
  81 #define GOYA_RESET_WAIT_MSEC            1               /* 1ms */
  82 #define GOYA_CPU_RESET_WAIT_MSEC        100             /* 100ms */
  83 #define GOYA_PLDM_RESET_WAIT_MSEC       1000            /* 1s */
  84 #define GOYA_TEST_QUEUE_WAIT_USEC       100000          /* 100ms */
  85 #define GOYA_PLDM_MMU_TIMEOUT_USEC      (MMU_CONFIG_TIMEOUT_USEC * 100)
  86 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC    (HL_DEVICE_TIMEOUT_USEC * 30)
  87
  88 #define GOYA_QMAN0_FENCE_VAL            0xD169B243
  89
  90 #define GOYA_MAX_STRING_LEN             20
  91
  92 #define GOYA_CB_POOL_CB_CNT             512
  93 #define GOYA_CB_POOL_CB_SIZE            0x20000         /* 128KB */
  94
  95 #define IS_QM_IDLE(engine, qm_glbl_sts0) \
  96         (((qm_glbl_sts0) & engine##_QM_IDLE_MASK) == engine##_QM_IDLE_MASK)
  97 #define IS_DMA_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(DMA, qm_glbl_sts0)
  98 #define IS_TPC_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(TPC, qm_glbl_sts0)
  99 #define IS_MME_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(MME, qm_glbl_sts0)
 100
 101 #define IS_CMDQ_IDLE(engine, cmdq_glbl_sts0) \
 102         (((cmdq_glbl_sts0) & engine##_CMDQ_IDLE_MASK) == \
 103                         engine##_CMDQ_IDLE_MASK)
 104 #define IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) \
 105         IS_CMDQ_IDLE(TPC, cmdq_glbl_sts0)
 106 #define IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) \
 107         IS_CMDQ_IDLE(MME, cmdq_glbl_sts0)
 108
 109 #define IS_DMA_IDLE(dma_core_sts0) \
 110         !((dma_core_sts0) & DMA_CH_0_STS0_DMA_BUSY_MASK)
 111
 112 #define IS_TPC_IDLE(tpc_cfg_sts) \
 113         (((tpc_cfg_sts) & TPC_CFG_IDLE_MASK) == TPC_CFG_IDLE_MASK)
 114
 115 #define IS_MME_IDLE(mme_arch_sts) \
 116         (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
 117
 118
 119 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
 120                 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
 121                 "goya cq 4", "goya cpu eq"
 122 };
 123
 124 static u16 goya_packet_sizes[MAX_PACKET_ID] = {
 125         [PACKET_WREG_32]        = sizeof(struct packet_wreg32),
 126         [PACKET_WREG_BULK]      = sizeof(struct packet_wreg_bulk),
 127         [PACKET_MSG_LONG]       = sizeof(struct packet_msg_long),
 128         [PACKET_MSG_SHORT]      = sizeof(struct packet_msg_short),
 129         [PACKET_CP_DMA]         = sizeof(struct packet_cp_dma),
 130         [PACKET_MSG_PROT]       = sizeof(struct packet_msg_prot),
 131         [PACKET_FENCE]          = sizeof(struct packet_fence),
 132         [PACKET_LIN_DMA]        = sizeof(struct packet_lin_dma),
 133         [PACKET_NOP]            = sizeof(struct packet_nop),
 134         [PACKET_STOP]           = sizeof(struct packet_stop)
 135 };
 136
 137 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
 138         mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
 139         mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
 140         mmDMA_QM_2_GLBL_NON_SECURE_PROPS,
 141         mmDMA_QM_3_GLBL_NON_SECURE_PROPS,
 142         mmDMA_QM_4_GLBL_NON_SECURE_PROPS,
 143         mmTPC0_QM_GLBL_SECURE_PROPS,
 144         mmTPC0_QM_GLBL_NON_SECURE_PROPS,
 145         mmTPC0_CMDQ_GLBL_SECURE_PROPS,
 146         mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS,
 147         mmTPC0_CFG_ARUSER,
 148         mmTPC0_CFG_AWUSER,
 149         mmTPC1_QM_GLBL_SECURE_PROPS,
 150         mmTPC1_QM_GLBL_NON_SECURE_PROPS,
 151         mmTPC1_CMDQ_GLBL_SECURE_PROPS,
 152         mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS,
 153         mmTPC1_CFG_ARUSER,
 154         mmTPC1_CFG_AWUSER,
 155         mmTPC2_QM_GLBL_SECURE_PROPS,
 156         mmTPC2_QM_GLBL_NON_SECURE_PROPS,
 157         mmTPC2_CMDQ_GLBL_SECURE_PROPS,
 158         mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS,
 159         mmTPC2_CFG_ARUSER,
 160         mmTPC2_CFG_AWUSER,
 161         mmTPC3_QM_GLBL_SECURE_PROPS,
 162         mmTPC3_QM_GLBL_NON_SECURE_PROPS,
 163         mmTPC3_CMDQ_GLBL_SECURE_PROPS,
 164         mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS,
 165         mmTPC3_CFG_ARUSER,
 166         mmTPC3_CFG_AWUSER,
 167         mmTPC4_QM_GLBL_SECURE_PROPS,
 168         mmTPC4_QM_GLBL_NON_SECURE_PROPS,
 169         mmTPC4_CMDQ_GLBL_SECURE_PROPS,
 170         mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS,
 171         mmTPC4_CFG_ARUSER,
 172         mmTPC4_CFG_AWUSER,
 173         mmTPC5_QM_GLBL_SECURE_PROPS,
 174         mmTPC5_QM_GLBL_NON_SECURE_PROPS,
 175         mmTPC5_CMDQ_GLBL_SECURE_PROPS,
 176         mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS,
 177         mmTPC5_CFG_ARUSER,
 178         mmTPC5_CFG_AWUSER,
 179         mmTPC6_QM_GLBL_SECURE_PROPS,
 180         mmTPC6_QM_GLBL_NON_SECURE_PROPS,
 181         mmTPC6_CMDQ_GLBL_SECURE_PROPS,
 182         mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS,
 183         mmTPC6_CFG_ARUSER,
 184         mmTPC6_CFG_AWUSER,
 185         mmTPC7_QM_GLBL_SECURE_PROPS,
 186         mmTPC7_QM_GLBL_NON_SECURE_PROPS,
 187         mmTPC7_CMDQ_GLBL_SECURE_PROPS,
 188         mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS,
 189         mmTPC7_CFG_ARUSER,
 190         mmTPC7_CFG_AWUSER,
 191         mmMME_QM_GLBL_SECURE_PROPS,
 192         mmMME_QM_GLBL_NON_SECURE_PROPS,
 193         mmMME_CMDQ_GLBL_SECURE_PROPS,
 194         mmMME_CMDQ_GLBL_NON_SECURE_PROPS,
 195         mmMME_SBA_CONTROL_DATA,
 196         mmMME_SBB_CONTROL_DATA,
 197         mmMME_SBC_CONTROL_DATA,
 198         mmMME_WBC_CONTROL_DATA,
 199         mmPCIE_WRAP_PSOC_ARUSER,
 200         mmPCIE_WRAP_PSOC_AWUSER
 201 };
 202
 203 static u32 goya_all_events[] = {
 204         GOYA_ASYNC_EVENT_ID_PCIE_IF,
 205         GOYA_ASYNC_EVENT_ID_TPC0_ECC,
 206         GOYA_ASYNC_EVENT_ID_TPC1_ECC,
 207         GOYA_ASYNC_EVENT_ID_TPC2_ECC,
 208         GOYA_ASYNC_EVENT_ID_TPC3_ECC,
 209         GOYA_ASYNC_EVENT_ID_TPC4_ECC,
 210         GOYA_ASYNC_EVENT_ID_TPC5_ECC,
 211         GOYA_ASYNC_EVENT_ID_TPC6_ECC,
 212         GOYA_ASYNC_EVENT_ID_TPC7_ECC,
 213         GOYA_ASYNC_EVENT_ID_MME_ECC,
 214         GOYA_ASYNC_EVENT_ID_MME_ECC_EXT,
 215         GOYA_ASYNC_EVENT_ID_MMU_ECC,
 216         GOYA_ASYNC_EVENT_ID_DMA_MACRO,
 217         GOYA_ASYNC_EVENT_ID_DMA_ECC,
 218         GOYA_ASYNC_EVENT_ID_CPU_IF_ECC,
 219         GOYA_ASYNC_EVENT_ID_PSOC_MEM,
 220         GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT,
 221         GOYA_ASYNC_EVENT_ID_SRAM0,
 222         GOYA_ASYNC_EVENT_ID_SRAM1,
 223         GOYA_ASYNC_EVENT_ID_SRAM2,
 224         GOYA_ASYNC_EVENT_ID_SRAM3,
 225         GOYA_ASYNC_EVENT_ID_SRAM4,
 226         GOYA_ASYNC_EVENT_ID_SRAM5,
 227         GOYA_ASYNC_EVENT_ID_SRAM6,
 228         GOYA_ASYNC_EVENT_ID_SRAM7,
 229         GOYA_ASYNC_EVENT_ID_SRAM8,
 230         GOYA_ASYNC_EVENT_ID_SRAM9,
 231         GOYA_ASYNC_EVENT_ID_SRAM10,
 232         GOYA_ASYNC_EVENT_ID_SRAM11,
 233         GOYA_ASYNC_EVENT_ID_SRAM12,
 234         GOYA_ASYNC_EVENT_ID_SRAM13,
 235         GOYA_ASYNC_EVENT_ID_SRAM14,
 236         GOYA_ASYNC_EVENT_ID_SRAM15,
 237         GOYA_ASYNC_EVENT_ID_SRAM16,
 238         GOYA_ASYNC_EVENT_ID_SRAM17,
 239         GOYA_ASYNC_EVENT_ID_SRAM18,
 240         GOYA_ASYNC_EVENT_ID_SRAM19,
 241         GOYA_ASYNC_EVENT_ID_SRAM20,
 242         GOYA_ASYNC_EVENT_ID_SRAM21,
 243         GOYA_ASYNC_EVENT_ID_SRAM22,
 244         GOYA_ASYNC_EVENT_ID_SRAM23,
 245         GOYA_ASYNC_EVENT_ID_SRAM24,
 246         GOYA_ASYNC_EVENT_ID_SRAM25,
 247         GOYA_ASYNC_EVENT_ID_SRAM26,
 248         GOYA_ASYNC_EVENT_ID_SRAM27,
 249         GOYA_ASYNC_EVENT_ID_SRAM28,
 250         GOYA_ASYNC_EVENT_ID_SRAM29,
 251         GOYA_ASYNC_EVENT_ID_GIC500,
 252         GOYA_ASYNC_EVENT_ID_PLL0,
 253         GOYA_ASYNC_EVENT_ID_PLL1,
 254         GOYA_ASYNC_EVENT_ID_PLL3,
 255         GOYA_ASYNC_EVENT_ID_PLL4,
 256         GOYA_ASYNC_EVENT_ID_PLL5,
 257         GOYA_ASYNC_EVENT_ID_PLL6,
 258         GOYA_ASYNC_EVENT_ID_AXI_ECC,
 259         GOYA_ASYNC_EVENT_ID_L2_RAM_ECC,
 260         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET,
 261         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT,
 262         GOYA_ASYNC_EVENT_ID_PCIE_DEC,
 263         GOYA_ASYNC_EVENT_ID_TPC0_DEC,
 264         GOYA_ASYNC_EVENT_ID_TPC1_DEC,
 265         GOYA_ASYNC_EVENT_ID_TPC2_DEC,
 266         GOYA_ASYNC_EVENT_ID_TPC3_DEC,
 267         GOYA_ASYNC_EVENT_ID_TPC4_DEC,
 268         GOYA_ASYNC_EVENT_ID_TPC5_DEC,
 269         GOYA_ASYNC_EVENT_ID_TPC6_DEC,
 270         GOYA_ASYNC_EVENT_ID_TPC7_DEC,
 271         GOYA_ASYNC_EVENT_ID_MME_WACS,
 272         GOYA_ASYNC_EVENT_ID_MME_WACSD,
 273         GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER,
 274         GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC,
 275         GOYA_ASYNC_EVENT_ID_PSOC,
 276         GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR,
 277         GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR,
 278         GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR,
 279         GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR,
 280         GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR,
 281         GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR,
 282         GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR,
 283         GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR,
 284         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ,
 285         GOYA_ASYNC_EVENT_ID_TPC1_CMDQ,
 286         GOYA_ASYNC_EVENT_ID_TPC2_CMDQ,
 287         GOYA_ASYNC_EVENT_ID_TPC3_CMDQ,
 288         GOYA_ASYNC_EVENT_ID_TPC4_CMDQ,
 289         GOYA_ASYNC_EVENT_ID_TPC5_CMDQ,
 290         GOYA_ASYNC_EVENT_ID_TPC6_CMDQ,
 291         GOYA_ASYNC_EVENT_ID_TPC7_CMDQ,
 292         GOYA_ASYNC_EVENT_ID_TPC0_QM,
 293         GOYA_ASYNC_EVENT_ID_TPC1_QM,
 294         GOYA_ASYNC_EVENT_ID_TPC2_QM,
 295         GOYA_ASYNC_EVENT_ID_TPC3_QM,
 296         GOYA_ASYNC_EVENT_ID_TPC4_QM,
 297         GOYA_ASYNC_EVENT_ID_TPC5_QM,
 298         GOYA_ASYNC_EVENT_ID_TPC6_QM,
 299         GOYA_ASYNC_EVENT_ID_TPC7_QM,
 300         GOYA_ASYNC_EVENT_ID_MME_QM,
 301         GOYA_ASYNC_EVENT_ID_MME_CMDQ,
 302         GOYA_ASYNC_EVENT_ID_DMA0_QM,
 303         GOYA_ASYNC_EVENT_ID_DMA1_QM,
 304         GOYA_ASYNC_EVENT_ID_DMA2_QM,
 305         GOYA_ASYNC_EVENT_ID_DMA3_QM,
 306         GOYA_ASYNC_EVENT_ID_DMA4_QM,
 307         GOYA_ASYNC_EVENT_ID_DMA0_CH,
 308         GOYA_ASYNC_EVENT_ID_DMA1_CH,
 309         GOYA_ASYNC_EVENT_ID_DMA2_CH,
 310         GOYA_ASYNC_EVENT_ID_DMA3_CH,
 311         GOYA_ASYNC_EVENT_ID_DMA4_CH,
 312         GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU,
 313         GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU,
 314         GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU,
 315         GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU,
 316         GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU,
 317         GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU,
 318         GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU,
 319         GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU,
 320         GOYA_ASYNC_EVENT_ID_DMA_BM_CH0,
 321         GOYA_ASYNC_EVENT_ID_DMA_BM_CH1,
 322         GOYA_ASYNC_EVENT_ID_DMA_BM_CH2,
 323         GOYA_ASYNC_EVENT_ID_DMA_BM_CH3,
 324         GOYA_ASYNC_EVENT_ID_DMA_BM_CH4
 325 };
 326
 327 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
 328 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
 329 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev);
 330 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
 331
 332 void goya_get_fixed_properties(struct hl_device *hdev)
 333 {
 334         struct asic_fixed_properties *prop = &hdev->asic_prop;
 335         int i;
 336
 337         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
 338                 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
 339                 prop->hw_queues_props[i].kmd_only = 0;
 340         }
 341
 342         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
 343                 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
 344                 prop->hw_queues_props[i].kmd_only = 1;
 345         }
 346
 347         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
 348                         NUMBER_OF_INT_HW_QUEUES; i++) {
 349                 prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
 350                 prop->hw_queues_props[i].kmd_only = 0;
 351         }
 352
 353         for (; i < HL_MAX_QUEUES; i++)
 354                 prop->hw_queues_props[i].type = QUEUE_TYPE_NA;
 355
 356         prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
 357
 358         prop->dram_base_address = DRAM_PHYS_BASE;
 359         prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
 360         prop->dram_end_address = prop->dram_base_address + prop->dram_size;
 361         prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
 362
 363         prop->sram_base_address = SRAM_BASE_ADDR;
 364         prop->sram_size = SRAM_SIZE;
 365         prop->sram_end_address = prop->sram_base_address + prop->sram_size;
 366         prop->sram_user_base_address = prop->sram_base_address +
 367                                                 SRAM_USER_BASE_OFFSET;
 368
 369         prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
 370         prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR;
 371         if (hdev->pldm)
 372                 prop->mmu_pgt_size = 0x800000; /* 8MB */
 373         else
 374                 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
 375         prop->mmu_pte_size = HL_PTE_SIZE;
 376         prop->mmu_hop_table_size = HOP_TABLE_SIZE;
 377         prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
 378         prop->dram_page_size = PAGE_SIZE_2MB;
 379
 380         prop->va_space_host_start_address = VA_HOST_SPACE_START;
 381         prop->va_space_host_end_address = VA_HOST_SPACE_END;
 382         prop->va_space_dram_start_address = VA_DDR_SPACE_START;
 383         prop->va_space_dram_end_address = VA_DDR_SPACE_END;
 384         prop->dram_size_for_default_page_mapping =
 385                         prop->va_space_dram_end_address;
 386         prop->cfg_size = CFG_SIZE;
 387         prop->max_asid = MAX_ASID;
 388         prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
 389         prop->high_pll = PLL_HIGH_DEFAULT;
 390         prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
 391         prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
 392         prop->max_power_default = MAX_POWER_DEFAULT;
 393         prop->tpc_enabled_mask = TPC_ENABLED_MASK;
 394         prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
 395         prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
 396 }
 397
 398 /*
 399  * goya_pci_bars_map - Map PCI BARS of Goya device
 400  *
 401  * @hdev: pointer to hl_device structure
 402  *
 403  * Request PCI regions and map them to kernel virtual addresses.
 404  * Returns 0 on success
 405  *
 406  */
 407 static int goya_pci_bars_map(struct hl_device *hdev)
 408 {
 409         static const char * const name[] = {"SRAM_CFG", "MSIX", "DDR"};
 410         bool is_wc[3] = {false, false, true};
 411         int rc;
 412
 413         rc = hl_pci_bars_map(hdev, name, is_wc);
 414         if (rc)
 415                 return rc;
 416
 417         hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
 418                         (CFG_BASE - SRAM_BASE_ADDR);
 419
 420         return 0;
 421 }
 422
 423 static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
 424 {
 425         struct goya_device *goya = hdev->asic_specific;
 426         u64 old_addr = addr;
 427         int rc;
 428
 429         if ((goya) && (goya->ddr_bar_cur_addr == addr))
 430                 return old_addr;
 431
 432         /* Inbound Region 1 - Bar 4 - Point to DDR */
 433         rc = hl_pci_set_dram_bar_base(hdev, 1, 4, addr);
 434         if (rc)
 435                 return U64_MAX;
 436
 437         if (goya) {
 438                 old_addr = goya->ddr_bar_cur_addr;
 439                 goya->ddr_bar_cur_addr = addr;
 440         }
 441
 442         return old_addr;
 443 }
 444
 445 /*
 446  * goya_init_iatu - Initialize the iATU unit inside the PCI controller
 447  *
 448  * @hdev: pointer to hl_device structure
 449  *
 450  * This is needed in case the firmware doesn't initialize the iATU
 451  *
 452  */
 453 static int goya_init_iatu(struct hl_device *hdev)
 454 {
 455         return hl_pci_init_iatu(hdev, SRAM_BASE_ADDR, DRAM_PHYS_BASE,
 456                                 HOST_PHYS_BASE, HOST_PHYS_SIZE);
 457 }
 458
 459 /*
 460  * goya_early_init - GOYA early initialization code
 461  *
 462  * @hdev: pointer to hl_device structure
 463  *
 464  * Verify PCI bars
 465  * Set DMA masks
 466  * PCI controller initialization
 467  * Map PCI bars
 468  *
 469  */
 470 static int goya_early_init(struct hl_device *hdev)
 471 {
 472         struct asic_fixed_properties *prop = &hdev->asic_prop;
 473         struct pci_dev *pdev = hdev->pdev;
 474         u32 val;
 475         int rc;
 476
 477         goya_get_fixed_properties(hdev);
 478
 479         /* Check BAR sizes */
 480         if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) {
 481                 dev_err(hdev->dev,
 482                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 483                         SRAM_CFG_BAR_ID,
 484                         (unsigned long long) pci_resource_len(pdev,
 485                                                         SRAM_CFG_BAR_ID),
 486                         CFG_BAR_SIZE);
 487                 return -ENODEV;
 488         }
 489
 490         if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) {
 491                 dev_err(hdev->dev,
 492                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 493                         MSIX_BAR_ID,
 494                         (unsigned long long) pci_resource_len(pdev,
 495                                                                 MSIX_BAR_ID),
 496                         MSIX_BAR_SIZE);
 497                 return -ENODEV;
 498         }
 499
 500         prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
 501
 502         rc = hl_pci_init(hdev, 48);
 503         if (rc)
 504                 return rc;
 505
 506         if (!hdev->pldm) {
 507                 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
 508                 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
 509                         dev_warn(hdev->dev,
 510                                 "PCI strap is not configured correctly, PCI bus errors may occur\n");
 511         }
 512
 513         return 0;
 514 }
 515
 516 /*
 517  * goya_early_fini - GOYA early finalization code
 518  *
 519  * @hdev: pointer to hl_device structure
 520  *
 521  * Unmap PCI bars
 522  *
 523  */
 524 static int goya_early_fini(struct hl_device *hdev)
 525 {
 526         hl_pci_fini(hdev);
 527
 528         return 0;
 529 }
 530
 531 static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
 532 {
 533         /* mask to zero the MMBP and ASID bits */
 534         WREG32_AND(reg, ~0x7FF);
 535         WREG32_OR(reg, asid);
 536 }
 537
 538 static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
 539 {
 540         struct goya_device *goya = hdev->asic_specific;
 541
 542         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
 543                 return;
 544
 545         if (secure)
 546                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
 547         else
 548                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
 549
 550         RREG32(mmDMA_QM_0_GLBL_PROT);
 551 }
 552
 553 /*
 554  * goya_fetch_psoc_frequency - Fetch PSOC frequency values
 555  *
 556  * @hdev: pointer to hl_device structure
 557  *
 558  */
 559 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
 560 {
 561         struct asic_fixed_properties *prop = &hdev->asic_prop;
 562
 563         prop->psoc_pci_pll_nr = RREG32(mmPSOC_PCI_PLL_NR);
 564         prop->psoc_pci_pll_nf = RREG32(mmPSOC_PCI_PLL_NF);
 565         prop->psoc_pci_pll_od = RREG32(mmPSOC_PCI_PLL_OD);
 566         prop->psoc_pci_pll_div_factor = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
 567 }
 568
 569 int goya_late_init(struct hl_device *hdev)
 570 {
 571         struct asic_fixed_properties *prop = &hdev->asic_prop;
 572         int rc;
 573
 574         goya_fetch_psoc_frequency(hdev);
 575
 576         rc = goya_mmu_clear_pgt_range(hdev);
 577         if (rc) {
 578                 dev_err(hdev->dev,
 579                         "Failed to clear MMU page tables range %d\n", rc);
 580                 return rc;
 581         }
 582
 583         rc = goya_mmu_set_dram_default_page(hdev);
 584         if (rc) {
 585                 dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc);
 586                 return rc;
 587         }
 588
 589         rc = goya_mmu_add_mappings_for_device_cpu(hdev);
 590         if (rc)
 591                 return rc;
 592
 593         rc = goya_init_cpu_queues(hdev);
 594         if (rc)
 595                 return rc;
 596
 597         rc = goya_test_cpu_queue(hdev);
 598         if (rc)
 599                 return rc;
 600
 601         rc = goya_armcp_info_get(hdev);
 602         if (rc) {
 603                 dev_err(hdev->dev, "Failed to get armcp info %d\n", rc);
 604                 return rc;
 605         }
 606
 607         /* Now that we have the DRAM size in ASIC prop, we need to check
 608          * its size and configure the DMA_IF DDR wrap protection (which is in
 609          * the MMU block) accordingly. The value is the log2 of the DRAM size
 610          */
 611         WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
 612
 613         rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS);
 614         if (rc) {
 615                 dev_err(hdev->dev,
 616                         "Failed to enable PCI access from CPU %d\n", rc);
 617                 return rc;
 618         }
 619
 620         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
 621                         GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
 622
 623         return 0;
 624 }
 625
 626 /*
 627  * goya_late_fini - GOYA late tear-down code
 628  *
 629  * @hdev: pointer to hl_device structure
 630  *
 631  * Free sensors allocated structures
 632  */
 633 void goya_late_fini(struct hl_device *hdev)
 634 {
 635         const struct hwmon_channel_info **channel_info_arr;
 636         int i = 0;
 637
 638         if (!hdev->hl_chip_info->info)
 639                 return;
 640
 641         channel_info_arr = hdev->hl_chip_info->info;
 642
 643         while (channel_info_arr[i]) {
 644                 kfree(channel_info_arr[i]->config);
 645                 kfree(channel_info_arr[i]);
 646                 i++;
 647         }
 648
 649         kfree(channel_info_arr);
 650
 651         hdev->hl_chip_info->info = NULL;
 652 }
 653
 654 /*
 655  * goya_sw_init - Goya software initialization code
 656  *
 657  * @hdev: pointer to hl_device structure
 658  *
 659  */
 660 static int goya_sw_init(struct hl_device *hdev)
 661 {
 662         struct goya_device *goya;
 663         int rc;
 664
 665         /* Allocate device structure */
 666         goya = kzalloc(sizeof(*goya), GFP_KERNEL);
 667         if (!goya)
 668                 return -ENOMEM;
 669
 670         /* according to goya_init_iatu */
 671         goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
 672
 673         goya->mme_clk = GOYA_PLL_FREQ_LOW;
 674         goya->tpc_clk = GOYA_PLL_FREQ_LOW;
 675         goya->ic_clk = GOYA_PLL_FREQ_LOW;
 676
 677         hdev->asic_specific = goya;
 678
 679         /* Create DMA pool for small allocations */
 680         hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
 681                         &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
 682         if (!hdev->dma_pool) {
 683                 dev_err(hdev->dev, "failed to create DMA pool\n");
 684                 rc = -ENOMEM;
 685                 goto free_goya_device;
 686         }
 687
 688         hdev->cpu_accessible_dma_mem =
 689                         hdev->asic_funcs->asic_dma_alloc_coherent(hdev,
 690                                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 691                                         &hdev->cpu_accessible_dma_address,
 692                                         GFP_KERNEL | __GFP_ZERO);
 693
 694         if (!hdev->cpu_accessible_dma_mem) {
 695                 rc = -ENOMEM;
 696                 goto free_dma_pool;
 697         }
 698
 699         dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n",
 700                 &hdev->cpu_accessible_dma_address);
 701
 702         hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
 703         if (!hdev->cpu_accessible_dma_pool) {
 704                 dev_err(hdev->dev,
 705                         "Failed to create CPU accessible DMA pool\n");
 706                 rc = -ENOMEM;
 707                 goto free_cpu_dma_mem;
 708         }
 709
 710         rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
 711                                 (uintptr_t) hdev->cpu_accessible_dma_mem,
 712                                 HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
 713         if (rc) {
 714                 dev_err(hdev->dev,
 715                         "Failed to add memory to CPU accessible DMA pool\n");
 716                 rc = -EFAULT;
 717                 goto free_cpu_accessible_dma_pool;
 718         }
 719
 720         spin_lock_init(&goya->hw_queues_lock);
 721
 722         return 0;
 723
 724 free_cpu_accessible_dma_pool:
 725         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 726 free_cpu_dma_mem:
 727         hdev->asic_funcs->asic_dma_free_coherent(hdev,
 728                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 729                         hdev->cpu_accessible_dma_mem,
 730                         hdev->cpu_accessible_dma_address);
 731 free_dma_pool:
 732         dma_pool_destroy(hdev->dma_pool);
 733 free_goya_device:
 734         kfree(goya);
 735
 736         return rc;
 737 }
 738
 739 /*
 740  * goya_sw_fini - Goya software tear-down code
 741  *
 742  * @hdev: pointer to hl_device structure
 743  *
 744  */
 745 static int goya_sw_fini(struct hl_device *hdev)
 746 {
 747         struct goya_device *goya = hdev->asic_specific;
 748
 749         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 750
 751         hdev->asic_funcs->asic_dma_free_coherent(hdev,
 752                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 753                         hdev->cpu_accessible_dma_mem,
 754                         hdev->cpu_accessible_dma_address);
 755
 756         dma_pool_destroy(hdev->dma_pool);
 757
 758         kfree(goya);
 759
 760         return 0;
 761 }
 762
 763 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
 764                 dma_addr_t bus_address)
 765 {
 766         struct goya_device *goya = hdev->asic_specific;
 767         u32 mtr_base_lo, mtr_base_hi;
 768         u32 so_base_lo, so_base_hi;
 769         u32 gic_base_lo, gic_base_hi;
 770         u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
 771
 772         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
 773         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
 774         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
 775         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
 776
 777         gic_base_lo =
 778                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 779         gic_base_hi =
 780                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 781
 782         WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
 783         WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
 784
 785         WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
 786         WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
 787         WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
 788
 789         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
 790         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
 791         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
 792         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
 793         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
 794         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
 795         WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
 796                         GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id);
 797
 798         /* PQ has buffer of 2 cache lines, while CQ has 8 lines */
 799         WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
 800         WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
 801
 802         if (goya->hw_cap_initialized & HW_CAP_MMU)
 803                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
 804         else
 805                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
 806
 807         WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, QMAN_DMA_ERR_MSG_EN);
 808         WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
 809 }
 810
 811 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
 812 {
 813         u32 gic_base_lo, gic_base_hi;
 814         u64 sob_addr;
 815         u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
 816
 817         gic_base_lo =
 818                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 819         gic_base_hi =
 820                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 821
 822         WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
 823         WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
 824         WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
 825                         GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id);
 826
 827         if (dma_id)
 828                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
 829                                 (dma_id - 1) * 4;
 830         else
 831                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
 832
 833         WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
 834         WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
 835 }
 836
 837 /*
 838  * goya_init_dma_qmans - Initialize QMAN DMA registers
 839  *
 840  * @hdev: pointer to hl_device structure
 841  *
 842  * Initialize the H/W registers of the QMAN DMA channels
 843  *
 844  */
 845 void goya_init_dma_qmans(struct hl_device *hdev)
 846 {
 847         struct goya_device *goya = hdev->asic_specific;
 848         struct hl_hw_queue *q;
 849         int i;
 850
 851         if (goya->hw_cap_initialized & HW_CAP_DMA)
 852                 return;
 853
 854         q = &hdev->kernel_queues[0];
 855
 856         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
 857                 goya_init_dma_qman(hdev, i, q->bus_address);
 858                 goya_init_dma_ch(hdev, i);
 859         }
 860
 861         goya->hw_cap_initialized |= HW_CAP_DMA;
 862 }
 863
 864 /*
 865  * goya_disable_external_queues - Disable external queues
 866  *
 867  * @hdev: pointer to hl_device structure
 868  *
 869  */
 870 static void goya_disable_external_queues(struct hl_device *hdev)
 871 {
 872         WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
 873         WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
 874         WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
 875         WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
 876         WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
 877 }
 878
 879 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
 880                                 u32 cp_sts_reg, u32 glbl_sts0_reg)
 881 {
 882         int rc;
 883         u32 status;
 884
 885         /* use the values of TPC0 as they are all the same*/
 886
 887         WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
 888
 889         status = RREG32(cp_sts_reg);
 890         if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) {
 891                 rc = hl_poll_timeout(
 892                         hdev,
 893                         cp_sts_reg,
 894                         status,
 895                         !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK),
 896                         1000,
 897                         QMAN_FENCE_TIMEOUT_USEC);
 898
 899                 /* if QMAN is stuck in fence no need to check for stop */
 900                 if (rc)
 901                         return 0;
 902         }
 903
 904         rc = hl_poll_timeout(
 905                 hdev,
 906                 glbl_sts0_reg,
 907                 status,
 908                 (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK),
 909                 1000,
 910                 QMAN_STOP_TIMEOUT_USEC);
 911
 912         if (rc) {
 913                 dev_err(hdev->dev,
 914                         "Timeout while waiting for QMAN to stop\n");
 915                 return -EINVAL;
 916         }
 917
 918         return 0;
 919 }
 920
 921 /*
 922  * goya_stop_external_queues - Stop external queues
 923  *
 924  * @hdev: pointer to hl_device structure
 925  *
 926  * Returns 0 on success
 927  *
 928  */
 929 static int goya_stop_external_queues(struct hl_device *hdev)
 930 {
 931         int rc, retval = 0;
 932
 933         rc = goya_stop_queue(hdev,
 934                         mmDMA_QM_0_GLBL_CFG1,
 935                         mmDMA_QM_0_CP_STS,
 936                         mmDMA_QM_0_GLBL_STS0);
 937
 938         if (rc) {
 939                 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
 940                 retval = -EIO;
 941         }
 942
 943         rc = goya_stop_queue(hdev,
 944                         mmDMA_QM_1_GLBL_CFG1,
 945                         mmDMA_QM_1_CP_STS,
 946                         mmDMA_QM_1_GLBL_STS0);
 947
 948         if (rc) {
 949                 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
 950                 retval = -EIO;
 951         }
 952
 953         rc = goya_stop_queue(hdev,
 954                         mmDMA_QM_2_GLBL_CFG1,
 955                         mmDMA_QM_2_CP_STS,
 956                         mmDMA_QM_2_GLBL_STS0);
 957
 958         if (rc) {
 959                 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
 960                 retval = -EIO;
 961         }
 962
 963         rc = goya_stop_queue(hdev,
 964                         mmDMA_QM_3_GLBL_CFG1,
 965                         mmDMA_QM_3_CP_STS,
 966                         mmDMA_QM_3_GLBL_STS0);
 967
 968         if (rc) {
 969                 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
 970                 retval = -EIO;
 971         }
 972
 973         rc = goya_stop_queue(hdev,
 974                         mmDMA_QM_4_GLBL_CFG1,
 975                         mmDMA_QM_4_CP_STS,
 976                         mmDMA_QM_4_GLBL_STS0);
 977
 978         if (rc) {
 979                 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
 980                 retval = -EIO;
 981         }
 982
 983         return retval;
 984 }
 985
 986 /*
 987  * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
 988  *
 989  * @hdev: pointer to hl_device structure
 990  *
 991  * Returns 0 on success
 992  *
 993  */
 994 int goya_init_cpu_queues(struct hl_device *hdev)
 995 {
 996         struct goya_device *goya = hdev->asic_specific;
 997         struct hl_eq *eq;
 998         u32 status;
 999         struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
1000         int err;
1001
1002         if (!hdev->cpu_queues_enable)
1003                 return 0;
1004
1005         if (goya->hw_cap_initialized & HW_CAP_CPU_Q)
1006                 return 0;
1007
1008         eq = &hdev->event_queue;
1009
1010         WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
1011         WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
1012
1013         WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
1014         WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
1015
1016         WREG32(mmCPU_CQ_BASE_ADDR_LOW,
1017                         lower_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1018         WREG32(mmCPU_CQ_BASE_ADDR_HIGH,
1019                         upper_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1020
1021         WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
1022         WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
1023         WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
1024
1025         /* Used for EQ CI */
1026         WREG32(mmCPU_EQ_CI, 0);
1027
1028         WREG32(mmCPU_IF_PF_PQ_PI, 0);
1029
1030         WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP);
1031
1032         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1033                         GOYA_ASYNC_EVENT_ID_PI_UPDATE);
1034
1035         err = hl_poll_timeout(
1036                 hdev,
1037                 mmCPU_PQ_INIT_STATUS,
1038                 status,
1039                 (status == PQ_INIT_STATUS_READY_FOR_HOST),
1040                 1000,
1041                 GOYA_CPU_TIMEOUT_USEC);
1042
1043         if (err) {
1044                 dev_err(hdev->dev,
1045                         "Failed to setup communication with device CPU\n");
1046                 return -EIO;
1047         }
1048
1049         goya->hw_cap_initialized |= HW_CAP_CPU_Q;
1050         return 0;
1051 }
1052
1053 static void goya_set_pll_refclk(struct hl_device *hdev)
1054 {
1055         WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1056         WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1057         WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1058         WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1059
1060         WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1061         WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1062         WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1063         WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1064
1065         WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1066         WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1067         WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1068         WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1069
1070         WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1071         WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1072         WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1073         WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1074
1075         WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1076         WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1077         WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1078         WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1079
1080         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1081         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1082         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1083         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1084
1085         WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1086         WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1087         WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1088         WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1089 }
1090
1091 static void goya_disable_clk_rlx(struct hl_device *hdev)
1092 {
1093         WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1094         WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1095 }
1096
1097 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1098 {
1099         u64 tpc_eml_address;
1100         u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1101         int err, slm_index;
1102
1103         tpc_offset = tpc_id * 0x40000;
1104         tpc_eml_offset = tpc_id * 0x200000;
1105         tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE);
1106         tpc_slm_offset = tpc_eml_address + 0x100000;
1107
1108         /*
1109          * Workaround for Bug H2 #2443 :
1110          * "TPC SB is not initialized on chip reset"
1111          */
1112
1113         val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1114         if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1115                 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1116                         tpc_id);
1117
1118         WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1119
1120         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1121         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1122         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1123         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1124         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1125         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1126         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1127         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1128         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1129         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1130
1131         WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1132                 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT);
1133
1134         err = hl_poll_timeout(
1135                 hdev,
1136                 mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1137                 val,
1138                 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1139                 1000,
1140                 HL_DEVICE_TIMEOUT_USEC);
1141
1142         if (err)
1143                 dev_err(hdev->dev,
1144                         "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id);
1145
1146         WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1147                 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT);
1148
1149         msleep(GOYA_RESET_WAIT_MSEC);
1150
1151         WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1152                 ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT));
1153
1154         msleep(GOYA_RESET_WAIT_MSEC);
1155
1156         for (slm_index = 0 ; slm_index < 256 ; slm_index++)
1157                 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1158
1159         val = RREG32(tpc_slm_offset);
1160 }
1161
1162 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1163 {
1164         struct goya_device *goya = hdev->asic_specific;
1165         int i;
1166
1167         if (hdev->pldm)
1168                 return;
1169
1170         if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST)
1171                 return;
1172
1173         /* Workaround for H2 #2443 */
1174
1175         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1176                 _goya_tpc_mbist_workaround(hdev, i);
1177
1178         goya->hw_cap_initialized |= HW_CAP_TPC_MBIST;
1179 }
1180
1181 /*
1182  * goya_init_golden_registers - Initialize golden registers
1183  *
1184  * @hdev: pointer to hl_device structure
1185  *
1186  * Initialize the H/W registers of the device
1187  *
1188  */
1189 static void goya_init_golden_registers(struct hl_device *hdev)
1190 {
1191         struct goya_device *goya = hdev->asic_specific;
1192         u32 polynom[10], tpc_intr_mask, offset;
1193         int i;
1194
1195         if (goya->hw_cap_initialized & HW_CAP_GOLDEN)
1196                 return;
1197
1198         polynom[0] = 0x00020080;
1199         polynom[1] = 0x00401000;
1200         polynom[2] = 0x00200800;
1201         polynom[3] = 0x00002000;
1202         polynom[4] = 0x00080200;
1203         polynom[5] = 0x00040100;
1204         polynom[6] = 0x00100400;
1205         polynom[7] = 0x00004000;
1206         polynom[8] = 0x00010000;
1207         polynom[9] = 0x00008000;
1208
1209         /* Mask all arithmetic interrupts from TPC */
1210         tpc_intr_mask = 0x7FFF;
1211
1212         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) {
1213                 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1214                 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1215                 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1216                 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1217                 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1218
1219                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1220                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1221                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1222                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1223                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1224
1225
1226                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1227                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1228                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1229                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1230                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1231
1232                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1233                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1234                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1235                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1236                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1237
1238                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1239                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1240                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1241                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1242                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1243
1244                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1245                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1246                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1247                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1248                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1249         }
1250
1251         WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1252         WREG32(mmMME_AGU, 0x0f0f0f10);
1253         WREG32(mmMME_SEI_MASK, ~0x0);
1254
1255         WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1256         WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1257         WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1258         WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1259         WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1260         WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1261         WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1262         WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1263         WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1264         WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1265         WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1266         WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1267         WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1268         WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1269         WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1270         WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1271         WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1272         WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1273         WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1274         WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1275         WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1276         WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1277         WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1278         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1279         WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1280         WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1281         WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1282         WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1283         WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1284         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1285         WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1286         WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1287         WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1288         WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1289         WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1290         WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1291         WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1292         WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1293         WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1294         WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1295         WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1296         WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1297         WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1298         WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1299         WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1300         WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1301         WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1302         WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1303         WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1304         WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1305         WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1306         WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1307         WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1308         WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1309         WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1310         WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1311         WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1312         WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1313         WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1314         WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1315         WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1316         WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1317         WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1318         WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1319         WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1320         WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1321         WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1322         WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1323         WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1324         WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1325         WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1326         WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1327         WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1328         WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1329         WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1330         WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1331         WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1332         WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1333         WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1334         WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1335         WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1336         WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1337         WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1338         WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1339
1340         WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1341         WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1342         WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1343         WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1344         WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1345         WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1346         WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1347         WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1348         WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1349         WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1350         WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1351         WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1352
1353         WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1354         WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1355         WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1356         WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1357         WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1358         WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1359         WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1360         WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1361         WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1362         WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1363         WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1364         WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1365
1366         WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1367         WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1368         WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1369         WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1370         WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1371         WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1372         WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1373         WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1374         WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1375         WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1376         WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1377         WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1378
1379         WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1380         WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1381         WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1382         WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1383         WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1384         WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1385         WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1386         WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1387         WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1388         WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1389         WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1390         WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1391
1392         WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1393         WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1394         WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1395         WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1396         WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1397         WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1398         WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1399         WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1400         WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1401         WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1402         WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1403         WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1404
1405         WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1406         WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1407         WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1408         WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1409         WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1410         WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1411         WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1412         WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1413         WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1414         WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1415         WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1416         WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1417
1418         for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) {
1419                 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1420                 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1421                 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1422                 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1423                 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1424                 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1425
1426                 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1427                 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1428                 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1429                 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1430                 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1431                 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1432                 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1433                 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1434
1435                 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1436                 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1437         }
1438
1439         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) {
1440                 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1441                                 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT);
1442                 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1443                                 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT);
1444         }
1445
1446         for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) {
1447                 /*
1448                  * Workaround for Bug H2 #2441 :
1449                  * "ST.NOP set trace event illegal opcode"
1450                  */
1451                 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1452
1453                 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1454                                 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
1455                 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1456                                 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1457         }
1458
1459         WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1460         WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1461                         1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1462
1463         WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1464         WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1465                         1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1466
1467         /*
1468          * Workaround for H2 #HW-23 bug
1469          * Set DMA max outstanding read requests to 240 on DMA CH 1.
1470          * This limitation is still large enough to not affect Gen4 bandwidth.
1471          * We need to only limit that DMA channel because the user can only read
1472          * from Host using DMA CH 1
1473          */
1474         WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1475
1476         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1477
1478         goya->hw_cap_initialized |= HW_CAP_GOLDEN;
1479 }
1480
1481 static void goya_init_mme_qman(struct hl_device *hdev)
1482 {
1483         u32 mtr_base_lo, mtr_base_hi;
1484         u32 so_base_lo, so_base_hi;
1485         u32 gic_base_lo, gic_base_hi;
1486         u64 qman_base_addr;
1487
1488         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1489         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1490         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1491         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1492
1493         gic_base_lo =
1494                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1495         gic_base_hi =
1496                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1497
1498         qman_base_addr = hdev->asic_prop.sram_base_address +
1499                                 MME_QMAN_BASE_OFFSET;
1500
1501         WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1502         WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1503         WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1504         WREG32(mmMME_QM_PQ_PI, 0);
1505         WREG32(mmMME_QM_PQ_CI, 0);
1506         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1507         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1508         WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1509         WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1510
1511         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1512         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1513         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1514         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1515
1516         /* QMAN CQ has 8 cache lines */
1517         WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1518
1519         WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1520         WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1521
1522         WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1523
1524         WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1525
1526         WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1527
1528         WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1529 }
1530
1531 static void goya_init_mme_cmdq(struct hl_device *hdev)
1532 {
1533         u32 mtr_base_lo, mtr_base_hi;
1534         u32 so_base_lo, so_base_hi;
1535         u32 gic_base_lo, gic_base_hi;
1536         u64 qman_base_addr;
1537
1538         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1539         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1540         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1541         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1542
1543         gic_base_lo =
1544                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1545         gic_base_hi =
1546                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1547
1548         qman_base_addr = hdev->asic_prop.sram_base_address +
1549                                 MME_QMAN_BASE_OFFSET;
1550
1551         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1552         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1553         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1554         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1555
1556         /* CMDQ CQ has 20 cache lines */
1557         WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1558
1559         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1560         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1561
1562         WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1563
1564         WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1565
1566         WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1567
1568         WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1569 }
1570
1571 void goya_init_mme_qmans(struct hl_device *hdev)
1572 {
1573         struct goya_device *goya = hdev->asic_specific;
1574         u32 so_base_lo, so_base_hi;
1575
1576         if (goya->hw_cap_initialized & HW_CAP_MME)
1577                 return;
1578
1579         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1580         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1581
1582         WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1583         WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1584
1585         goya_init_mme_qman(hdev);
1586         goya_init_mme_cmdq(hdev);
1587
1588         goya->hw_cap_initialized |= HW_CAP_MME;
1589 }
1590
1591 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1592 {
1593         u32 mtr_base_lo, mtr_base_hi;
1594         u32 so_base_lo, so_base_hi;
1595         u32 gic_base_lo, gic_base_hi;
1596         u64 qman_base_addr;
1597         u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
1598
1599         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1600         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1601         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1602         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1603
1604         gic_base_lo =
1605                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1606         gic_base_hi =
1607                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1608
1609         qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1610
1611         WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1612         WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1613         WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1614         WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1615         WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1616         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1617         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1618         WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1619         WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1620
1621         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1622         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1623         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1624         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1625
1626         WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1627
1628         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1629         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1630
1631         WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1632                         GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id);
1633
1634         WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1635
1636         WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1637
1638         WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1639 }
1640
1641 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
1642 {
1643         u32 mtr_base_lo, mtr_base_hi;
1644         u32 so_base_lo, so_base_hi;
1645         u32 gic_base_lo, gic_base_hi;
1646         u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
1647
1648         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1649         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1650         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1651         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1652
1653         gic_base_lo =
1654                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1655         gic_base_hi =
1656                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1657
1658         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1659         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1660         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1661         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1662
1663         WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
1664
1665         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1666         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1667
1668         WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
1669                         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id);
1670
1671         WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
1672
1673         WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
1674
1675         WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
1676 }
1677
1678 void goya_init_tpc_qmans(struct hl_device *hdev)
1679 {
1680         struct goya_device *goya = hdev->asic_specific;
1681         u32 so_base_lo, so_base_hi;
1682         u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW -
1683                         mmTPC0_CFG_SM_BASE_ADDRESS_LOW;
1684         int i;
1685
1686         if (goya->hw_cap_initialized & HW_CAP_TPC)
1687                 return;
1688
1689         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1690         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1691
1692         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
1693                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
1694                                 so_base_lo);
1695                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
1696                                 so_base_hi);
1697         }
1698
1699         goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
1700         goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
1701         goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
1702         goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
1703         goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
1704         goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
1705         goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
1706         goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
1707
1708         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1709                 goya_init_tpc_cmdq(hdev, i);
1710
1711         goya->hw_cap_initialized |= HW_CAP_TPC;
1712 }
1713
1714 /*
1715  * goya_disable_internal_queues - Disable internal queues
1716  *
1717  * @hdev: pointer to hl_device structure
1718  *
1719  */
1720 static void goya_disable_internal_queues(struct hl_device *hdev)
1721 {
1722         WREG32(mmMME_QM_GLBL_CFG0, 0);
1723         WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
1724
1725         WREG32(mmTPC0_QM_GLBL_CFG0, 0);
1726         WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
1727
1728         WREG32(mmTPC1_QM_GLBL_CFG0, 0);
1729         WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
1730
1731         WREG32(mmTPC2_QM_GLBL_CFG0, 0);
1732         WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
1733
1734         WREG32(mmTPC3_QM_GLBL_CFG0, 0);
1735         WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
1736
1737         WREG32(mmTPC4_QM_GLBL_CFG0, 0);
1738         WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
1739
1740         WREG32(mmTPC5_QM_GLBL_CFG0, 0);
1741         WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
1742
1743         WREG32(mmTPC6_QM_GLBL_CFG0, 0);
1744         WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
1745
1746         WREG32(mmTPC7_QM_GLBL_CFG0, 0);
1747         WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
1748 }
1749
1750 /*
1751  * goya_stop_internal_queues - Stop internal queues
1752  *
1753  * @hdev: pointer to hl_device structure
1754  *
1755  * Returns 0 on success
1756  *
1757  */
1758 static int goya_stop_internal_queues(struct hl_device *hdev)
1759 {
1760         int rc, retval = 0;
1761
1762         /*
1763          * Each queue (QMAN) is a separate H/W logic. That means that each
1764          * QMAN can be stopped independently and failure to stop one does NOT
1765          * mandate we should not try to stop other QMANs
1766          */
1767
1768         rc = goya_stop_queue(hdev,
1769                         mmMME_QM_GLBL_CFG1,
1770                         mmMME_QM_CP_STS,
1771                         mmMME_QM_GLBL_STS0);
1772
1773         if (rc) {
1774                 dev_err(hdev->dev, "failed to stop MME QMAN\n");
1775                 retval = -EIO;
1776         }
1777
1778         rc = goya_stop_queue(hdev,
1779                         mmMME_CMDQ_GLBL_CFG1,
1780                         mmMME_CMDQ_CP_STS,
1781                         mmMME_CMDQ_GLBL_STS0);
1782
1783         if (rc) {
1784                 dev_err(hdev->dev, "failed to stop MME CMDQ\n");
1785                 retval = -EIO;
1786         }
1787
1788         rc = goya_stop_queue(hdev,
1789                         mmTPC0_QM_GLBL_CFG1,
1790                         mmTPC0_QM_CP_STS,
1791                         mmTPC0_QM_GLBL_STS0);
1792
1793         if (rc) {
1794                 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
1795                 retval = -EIO;
1796         }
1797
1798         rc = goya_stop_queue(hdev,
1799                         mmTPC0_CMDQ_GLBL_CFG1,
1800                         mmTPC0_CMDQ_CP_STS,
1801                         mmTPC0_CMDQ_GLBL_STS0);
1802
1803         if (rc) {
1804                 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
1805                 retval = -EIO;
1806         }
1807
1808         rc = goya_stop_queue(hdev,
1809                         mmTPC1_QM_GLBL_CFG1,
1810                         mmTPC1_QM_CP_STS,
1811                         mmTPC1_QM_GLBL_STS0);
1812
1813         if (rc) {
1814                 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
1815                 retval = -EIO;
1816         }
1817
1818         rc = goya_stop_queue(hdev,
1819                         mmTPC1_CMDQ_GLBL_CFG1,
1820                         mmTPC1_CMDQ_CP_STS,
1821                         mmTPC1_CMDQ_GLBL_STS0);
1822
1823         if (rc) {
1824                 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
1825                 retval = -EIO;
1826         }
1827
1828         rc = goya_stop_queue(hdev,
1829                         mmTPC2_QM_GLBL_CFG1,
1830                         mmTPC2_QM_CP_STS,
1831                         mmTPC2_QM_GLBL_STS0);
1832
1833         if (rc) {
1834                 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
1835                 retval = -EIO;
1836         }
1837
1838         rc = goya_stop_queue(hdev,
1839                         mmTPC2_CMDQ_GLBL_CFG1,
1840                         mmTPC2_CMDQ_CP_STS,
1841                         mmTPC2_CMDQ_GLBL_STS0);
1842
1843         if (rc) {
1844                 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
1845                 retval = -EIO;
1846         }
1847
1848         rc = goya_stop_queue(hdev,
1849                         mmTPC3_QM_GLBL_CFG1,
1850                         mmTPC3_QM_CP_STS,
1851                         mmTPC3_QM_GLBL_STS0);
1852
1853         if (rc) {
1854                 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
1855                 retval = -EIO;
1856         }
1857
1858         rc = goya_stop_queue(hdev,
1859                         mmTPC3_CMDQ_GLBL_CFG1,
1860                         mmTPC3_CMDQ_CP_STS,
1861                         mmTPC3_CMDQ_GLBL_STS0);
1862
1863         if (rc) {
1864                 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
1865                 retval = -EIO;
1866         }
1867
1868         rc = goya_stop_queue(hdev,
1869                         mmTPC4_QM_GLBL_CFG1,
1870                         mmTPC4_QM_CP_STS,
1871                         mmTPC4_QM_GLBL_STS0);
1872
1873         if (rc) {
1874                 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
1875                 retval = -EIO;
1876         }
1877
1878         rc = goya_stop_queue(hdev,
1879                         mmTPC4_CMDQ_GLBL_CFG1,
1880                         mmTPC4_CMDQ_CP_STS,
1881                         mmTPC4_CMDQ_GLBL_STS0);
1882
1883         if (rc) {
1884                 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
1885                 retval = -EIO;
1886         }
1887
1888         rc = goya_stop_queue(hdev,
1889                         mmTPC5_QM_GLBL_CFG1,
1890                         mmTPC5_QM_CP_STS,
1891                         mmTPC5_QM_GLBL_STS0);
1892
1893         if (rc) {
1894                 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
1895                 retval = -EIO;
1896         }
1897
1898         rc = goya_stop_queue(hdev,
1899                         mmTPC5_CMDQ_GLBL_CFG1,
1900                         mmTPC5_CMDQ_CP_STS,
1901                         mmTPC5_CMDQ_GLBL_STS0);
1902
1903         if (rc) {
1904                 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
1905                 retval = -EIO;
1906         }
1907
1908         rc = goya_stop_queue(hdev,
1909                         mmTPC6_QM_GLBL_CFG1,
1910                         mmTPC6_QM_CP_STS,
1911                         mmTPC6_QM_GLBL_STS0);
1912
1913         if (rc) {
1914                 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
1915                 retval = -EIO;
1916         }
1917
1918         rc = goya_stop_queue(hdev,
1919                         mmTPC6_CMDQ_GLBL_CFG1,
1920                         mmTPC6_CMDQ_CP_STS,
1921                         mmTPC6_CMDQ_GLBL_STS0);
1922
1923         if (rc) {
1924                 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
1925                 retval = -EIO;
1926         }
1927
1928         rc = goya_stop_queue(hdev,
1929                         mmTPC7_QM_GLBL_CFG1,
1930                         mmTPC7_QM_CP_STS,
1931                         mmTPC7_QM_GLBL_STS0);
1932
1933         if (rc) {
1934                 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
1935                 retval = -EIO;
1936         }
1937
1938         rc = goya_stop_queue(hdev,
1939                         mmTPC7_CMDQ_GLBL_CFG1,
1940                         mmTPC7_CMDQ_CP_STS,
1941                         mmTPC7_CMDQ_GLBL_STS0);
1942
1943         if (rc) {
1944                 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
1945                 retval = -EIO;
1946         }
1947
1948         return retval;
1949 }
1950
1951 static void goya_dma_stall(struct hl_device *hdev)
1952 {
1953         WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
1954         WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
1955         WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
1956         WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
1957         WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
1958 }
1959
1960 static void goya_tpc_stall(struct hl_device *hdev)
1961 {
1962         WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
1963         WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
1964         WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
1965         WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
1966         WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
1967         WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
1968         WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
1969         WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
1970 }
1971
1972 static void goya_mme_stall(struct hl_device *hdev)
1973 {
1974         WREG32(mmMME_STALL, 0xFFFFFFFF);
1975 }
1976
1977 static int goya_enable_msix(struct hl_device *hdev)
1978 {
1979         struct goya_device *goya = hdev->asic_specific;
1980         int cq_cnt = hdev->asic_prop.completion_queues_count;
1981         int rc, i, irq_cnt_init, irq;
1982
1983         if (goya->hw_cap_initialized & HW_CAP_MSIX)
1984                 return 0;
1985
1986         rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
1987                                 GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX);
1988         if (rc < 0) {
1989                 dev_err(hdev->dev,
1990                         "MSI-X: Failed to enable support -- %d/%d\n",
1991                         GOYA_MSIX_ENTRIES, rc);
1992                 return rc;
1993         }
1994
1995         for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
1996                 irq = pci_irq_vector(hdev->pdev, i);
1997                 rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i],
1998                                 &hdev->completion_queue[i]);
1999                 if (rc) {
2000                         dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2001                         goto free_irqs;
2002                 }
2003         }
2004
2005         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2006
2007         rc = request_irq(irq, hl_irq_handler_eq, 0,
2008                         goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX],
2009                         &hdev->event_queue);
2010         if (rc) {
2011                 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2012                 goto free_irqs;
2013         }
2014
2015         goya->hw_cap_initialized |= HW_CAP_MSIX;
2016         return 0;
2017
2018 free_irqs:
2019         for (i = 0 ; i < irq_cnt_init ; i++)
2020                 free_irq(pci_irq_vector(hdev->pdev, i),
2021                         &hdev->completion_queue[i]);
2022
2023         pci_free_irq_vectors(hdev->pdev);
2024         return rc;
2025 }
2026
2027 static void goya_sync_irqs(struct hl_device *hdev)
2028 {
2029         struct goya_device *goya = hdev->asic_specific;
2030         int i;
2031
2032         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2033                 return;
2034
2035         /* Wait for all pending IRQs to be finished */
2036         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2037                 synchronize_irq(pci_irq_vector(hdev->pdev, i));
2038
2039         synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
2040 }
2041
2042 static void goya_disable_msix(struct hl_device *hdev)
2043 {
2044         struct goya_device *goya = hdev->asic_specific;
2045         int i, irq;
2046
2047         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2048                 return;
2049
2050         goya_sync_irqs(hdev);
2051
2052         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2053         free_irq(irq, &hdev->event_queue);
2054
2055         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2056                 irq = pci_irq_vector(hdev->pdev, i);
2057                 free_irq(irq, &hdev->completion_queue[i]);
2058         }
2059
2060         pci_free_irq_vectors(hdev->pdev);
2061
2062         goya->hw_cap_initialized &= ~HW_CAP_MSIX;
2063 }
2064
2065 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset)
2066 {
2067         u32 wait_timeout_ms, cpu_timeout_ms;
2068
2069         dev_info(hdev->dev,
2070                 "Halting compute engines and disabling interrupts\n");
2071
2072         if (hdev->pldm) {
2073                 wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2074                 cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2075         } else {
2076                 wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
2077                 cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
2078         }
2079
2080         if (hard_reset) {
2081                 /*
2082                  * I don't know what is the state of the CPU so make sure it is
2083                  * stopped in any means necessary
2084                  */
2085                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2086                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2087                         GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
2088                 msleep(cpu_timeout_ms);
2089         }
2090
2091         goya_stop_external_queues(hdev);
2092         goya_stop_internal_queues(hdev);
2093
2094         msleep(wait_timeout_ms);
2095
2096         goya_dma_stall(hdev);
2097         goya_tpc_stall(hdev);
2098         goya_mme_stall(hdev);
2099
2100         msleep(wait_timeout_ms);
2101
2102         goya_disable_external_queues(hdev);
2103         goya_disable_internal_queues(hdev);
2104
2105         if (hard_reset) {
2106                 goya_disable_msix(hdev);
2107                 goya_mmu_remove_device_cpu_mappings(hdev);
2108         } else {
2109                 goya_sync_irqs(hdev);
2110         }
2111 }
2112
2113 /*
2114  * goya_push_uboot_to_device() - Push u-boot FW code to device.
2115  * @hdev: Pointer to hl_device structure.
2116  *
2117  * Copy u-boot fw code from firmware file to SRAM BAR.
2118  *
2119  * Return: 0 on success, non-zero for failure.
2120  */
2121 static int goya_push_uboot_to_device(struct hl_device *hdev)
2122 {
2123         char fw_name[200];
2124         void __iomem *dst;
2125
2126         snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-u-boot.bin");
2127         dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + UBOOT_FW_OFFSET;
2128
2129         return hl_fw_push_fw_to_device(hdev, fw_name, dst);
2130 }
2131
2132 /*
2133  * goya_push_linux_to_device() - Push LINUX FW code to device.
2134  * @hdev: Pointer to hl_device structure.
2135  *
2136  * Copy LINUX fw code from firmware file to HBM BAR.
2137  *
2138  * Return: 0 on success, non-zero for failure.
2139  */
2140 static int goya_push_linux_to_device(struct hl_device *hdev)
2141 {
2142         char fw_name[200];
2143         void __iomem *dst;
2144
2145         snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-fit.itb");
2146         dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2147
2148         return hl_fw_push_fw_to_device(hdev, fw_name, dst);
2149 }
2150
2151 static int goya_pldm_init_cpu(struct hl_device *hdev)
2152 {
2153         u32 val, unit_rst_val;
2154         int rc;
2155
2156         /* Must initialize SRAM scrambler before pushing u-boot to SRAM */
2157         goya_init_golden_registers(hdev);
2158
2159         /* Put ARM cores into reset */
2160         WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, CPU_RESET_ASSERT);
2161         val = RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL);
2162
2163         /* Reset the CA53 MACRO */
2164         unit_rst_val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2165         WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, CA53_RESET);
2166         val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2167         WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, unit_rst_val);
2168         val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2169
2170         rc = goya_push_uboot_to_device(hdev);
2171         if (rc)
2172                 return rc;
2173
2174         rc = goya_push_linux_to_device(hdev);
2175         if (rc)
2176                 return rc;
2177
2178         WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY);
2179         WREG32(mmPSOC_GLOBAL_CONF_WARM_REBOOT, CPU_BOOT_STATUS_NA);
2180
2181         WREG32(mmCPU_CA53_CFG_RST_ADDR_LSB_0,
2182                 lower_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET));
2183         WREG32(mmCPU_CA53_CFG_RST_ADDR_MSB_0,
2184                 upper_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET));
2185
2186         /* Release ARM core 0 from reset */
2187         WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL,
2188                                         CPU_RESET_CORE0_DEASSERT);
2189         val = RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL);
2190
2191         return 0;
2192 }
2193
2194 /*
2195  * FW component passes an offset from SRAM_BASE_ADDR in SCRATCHPAD_xx.
2196  * The version string should be located by that offset.
2197  */
2198 static void goya_read_device_fw_version(struct hl_device *hdev,
2199                                         enum goya_fw_component fwc)
2200 {
2201         const char *name;
2202         u32 ver_off;
2203         char *dest;
2204
2205         switch (fwc) {
2206         case FW_COMP_UBOOT:
2207                 ver_off = RREG32(mmUBOOT_VER_OFFSET);
2208                 dest = hdev->asic_prop.uboot_ver;
2209                 name = "U-Boot";
2210                 break;
2211         case FW_COMP_PREBOOT:
2212                 ver_off = RREG32(mmPREBOOT_VER_OFFSET);
2213                 dest = hdev->asic_prop.preboot_ver;
2214                 name = "Preboot";
2215                 break;
2216         default:
2217                 dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc);
2218                 return;
2219         }
2220
2221         ver_off &= ~((u32)SRAM_BASE_ADDR);
2222
2223         if (ver_off < SRAM_SIZE - VERSION_MAX_LEN) {
2224                 memcpy_fromio(dest, hdev->pcie_bar[SRAM_CFG_BAR_ID] + ver_off,
2225                                                         VERSION_MAX_LEN);
2226         } else {
2227                 dev_err(hdev->dev, "%s version offset (0x%x) is above SRAM\n",
2228                                                                 name, ver_off);
2229                 strcpy(dest, "unavailable");
2230         }
2231 }
2232
2233 static int goya_init_cpu(struct hl_device *hdev, u32 cpu_timeout)
2234 {
2235         struct goya_device *goya = hdev->asic_specific;
2236         u32 status;
2237         int rc;
2238
2239         if (!hdev->cpu_enable)
2240                 return 0;
2241
2242         if (goya->hw_cap_initialized & HW_CAP_CPU)
2243                 return 0;
2244
2245         /*
2246          * Before pushing u-boot/linux to device, need to set the ddr bar to
2247          * base address of dram
2248          */
2249         if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
2250                 dev_err(hdev->dev,
2251                         "failed to map DDR bar to DRAM base address\n");
2252                 return -EIO;
2253         }
2254
2255         if (hdev->pldm) {
2256                 rc = goya_pldm_init_cpu(hdev);
2257                 if (rc)
2258                         return rc;
2259
2260                 goto out;
2261         }
2262
2263         /* Make sure CPU boot-loader is running */
2264         rc = hl_poll_timeout(
2265                 hdev,
2266                 mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2267                 status,
2268                 (status == CPU_BOOT_STATUS_DRAM_RDY) ||
2269                 (status == CPU_BOOT_STATUS_SRAM_AVAIL),
2270                 10000,
2271                 cpu_timeout);
2272
2273         if (rc) {
2274                 dev_err(hdev->dev, "Error in ARM u-boot!");
2275                 switch (status) {
2276                 case CPU_BOOT_STATUS_NA:
2277                         dev_err(hdev->dev,
2278                                 "ARM status %d - BTL did NOT run\n", status);
2279                         break;
2280                 case CPU_BOOT_STATUS_IN_WFE:
2281                         dev_err(hdev->dev,
2282                                 "ARM status %d - Inside WFE loop\n", status);
2283                         break;
2284                 case CPU_BOOT_STATUS_IN_BTL:
2285                         dev_err(hdev->dev,
2286                                 "ARM status %d - Stuck in BTL\n", status);
2287                         break;
2288                 case CPU_BOOT_STATUS_IN_PREBOOT:
2289                         dev_err(hdev->dev,
2290                                 "ARM status %d - Stuck in Preboot\n", status);
2291                         break;
2292                 case CPU_BOOT_STATUS_IN_SPL:
2293                         dev_err(hdev->dev,
2294                                 "ARM status %d - Stuck in SPL\n", status);
2295                         break;
2296                 case CPU_BOOT_STATUS_IN_UBOOT:
2297                         dev_err(hdev->dev,
2298                                 "ARM status %d - Stuck in u-boot\n", status);
2299                         break;
2300                 case CPU_BOOT_STATUS_DRAM_INIT_FAIL:
2301                         dev_err(hdev->dev,
2302                                 "ARM status %d - DDR initialization failed\n",
2303                                 status);
2304                         break;
2305                 case CPU_BOOT_STATUS_UBOOT_NOT_READY:
2306                         dev_err(hdev->dev,
2307                                 "ARM status %d - u-boot stopped by user\n",
2308                                 status);
2309                         break;
2310                 default:
2311                         dev_err(hdev->dev,
2312                                 "ARM status %d - Invalid status code\n",
2313                                 status);
2314                         break;
2315                 }
2316                 return -EIO;
2317         }
2318
2319         /* Read U-Boot version now in case we will later fail */
2320         goya_read_device_fw_version(hdev, FW_COMP_UBOOT);
2321         goya_read_device_fw_version(hdev, FW_COMP_PREBOOT);
2322
2323         if (!hdev->fw_loading) {
2324                 dev_info(hdev->dev, "Skip loading FW\n");
2325                 goto out;
2326         }
2327
2328         if (status == CPU_BOOT_STATUS_SRAM_AVAIL)
2329                 goto out;
2330
2331         rc = goya_push_linux_to_device(hdev);
2332         if (rc)
2333                 return rc;
2334
2335         WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY);
2336
2337         rc = hl_poll_timeout(
2338                 hdev,
2339                 mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2340                 status,
2341                 (status == CPU_BOOT_STATUS_SRAM_AVAIL),
2342                 10000,
2343                 cpu_timeout);
2344
2345         if (rc) {
2346                 if (status == CPU_BOOT_STATUS_FIT_CORRUPTED)
2347                         dev_err(hdev->dev,
2348                                 "ARM u-boot reports FIT image is corrupted\n");
2349                 else
2350                         dev_err(hdev->dev,
2351                                 "ARM Linux failed to load, %d\n", status);
2352                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_NA);
2353                 return -EIO;
2354         }
2355
2356         dev_info(hdev->dev, "Successfully loaded firmware to device\n");
2357
2358 out:
2359         goya->hw_cap_initialized |= HW_CAP_CPU;
2360
2361         return 0;
2362 }
2363
2364 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
2365                                                 u64 phys_addr)
2366 {
2367         u32 status, timeout_usec;
2368         int rc;
2369
2370         if (hdev->pldm)
2371                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
2372         else
2373                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
2374
2375         WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2376         WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2377         WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2378
2379         rc = hl_poll_timeout(
2380                 hdev,
2381                 MMU_ASID_BUSY,
2382                 status,
2383                 !(status & 0x80000000),
2384                 1000,
2385                 timeout_usec);
2386
2387         if (rc) {
2388                 dev_err(hdev->dev,
2389                         "Timeout during MMU hop0 config of asid %d\n", asid);
2390                 return rc;
2391         }
2392
2393         return 0;
2394 }
2395
2396 int goya_mmu_init(struct hl_device *hdev)
2397 {
2398         struct asic_fixed_properties *prop = &hdev->asic_prop;
2399         struct goya_device *goya = hdev->asic_specific;
2400         u64 hop0_addr;
2401         int rc, i;
2402
2403         if (!hdev->mmu_enable)
2404                 return 0;
2405
2406         if (goya->hw_cap_initialized & HW_CAP_MMU)
2407                 return 0;
2408
2409         hdev->dram_supports_virtual_memory = true;
2410         hdev->dram_default_page_mapping = true;
2411
2412         for (i = 0 ; i < prop->max_asid ; i++) {
2413                 hop0_addr = prop->mmu_pgt_addr +
2414                                 (i * prop->mmu_hop_table_size);
2415
2416                 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2417                 if (rc) {
2418                         dev_err(hdev->dev,
2419                                 "failed to set hop0 addr for asid %d\n", i);
2420                         goto err;
2421                 }
2422         }
2423
2424         goya->hw_cap_initialized |= HW_CAP_MMU;
2425
2426         /* init MMU cache manage page */
2427         WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2428                                 lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
2429         WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2430
2431         /* Remove follower feature due to performance bug */
2432         WREG32_AND(mmSTLB_STLB_FEATURE_EN,
2433                         (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
2434
2435         hdev->asic_funcs->mmu_invalidate_cache(hdev, true);
2436
2437         WREG32(mmMMU_MMU_ENABLE, 1);
2438         WREG32(mmMMU_SPI_MASK, 0xF);
2439
2440         return 0;
2441
2442 err:
2443         return rc;
2444 }
2445
2446 /*
2447  * goya_hw_init - Goya hardware initialization code
2448  *
2449  * @hdev: pointer to hl_device structure
2450  *
2451  * Returns 0 on success
2452  *
2453  */
2454 static int goya_hw_init(struct hl_device *hdev)
2455 {
2456         struct asic_fixed_properties *prop = &hdev->asic_prop;
2457         u32 val;
2458         int rc;
2459
2460         dev_info(hdev->dev, "Starting initialization of H/W\n");
2461
2462         /* Perform read from the device to make sure device is up */
2463         val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2464
2465         /*
2466          * Let's mark in the H/W that we have reached this point. We check
2467          * this value in the reset_before_init function to understand whether
2468          * we need to reset the chip before doing H/W init. This register is
2469          * cleared by the H/W upon H/W reset
2470          */
2471         WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2472
2473         rc = goya_init_cpu(hdev, GOYA_CPU_TIMEOUT_USEC);
2474         if (rc) {
2475                 dev_err(hdev->dev, "failed to initialize CPU\n");
2476                 return rc;
2477         }
2478
2479         goya_tpc_mbist_workaround(hdev);
2480
2481         goya_init_golden_registers(hdev);
2482
2483         /*
2484          * After CPU initialization is finished, change DDR bar mapping inside
2485          * iATU to point to the start address of the MMU page tables
2486          */
2487         if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE +
2488                         (MMU_PAGE_TABLES_ADDR &
2489                         ~(prop->dram_pci_bar_size - 0x1ull))) == U64_MAX) {
2490                 dev_err(hdev->dev,
2491                         "failed to map DDR bar to MMU page tables\n");
2492                 return -EIO;
2493         }
2494
2495         rc = goya_mmu_init(hdev);
2496         if (rc)
2497                 return rc;
2498
2499         goya_init_security(hdev);
2500
2501         goya_init_dma_qmans(hdev);
2502
2503         goya_init_mme_qmans(hdev);
2504
2505         goya_init_tpc_qmans(hdev);
2506
2507         /* MSI-X must be enabled before CPU queues are initialized */
2508         rc = goya_enable_msix(hdev);
2509         if (rc)
2510                 goto disable_queues;
2511
2512         /* Perform read from the device to flush all MSI-X configuration */
2513         val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2514
2515         return 0;
2516
2517 disable_queues:
2518         goya_disable_internal_queues(hdev);
2519         goya_disable_external_queues(hdev);
2520
2521         return rc;
2522 }
2523
2524 /*
2525  * goya_hw_fini - Goya hardware tear-down code
2526  *
2527  * @hdev: pointer to hl_device structure
2528  * @hard_reset: should we do hard reset to all engines or just reset the
2529  *              compute/dma engines
2530  */
2531 static void goya_hw_fini(struct hl_device *hdev, bool hard_reset)
2532 {
2533         struct goya_device *goya = hdev->asic_specific;
2534         u32 reset_timeout_ms, status;
2535
2536         if (hdev->pldm)
2537                 reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
2538         else
2539                 reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
2540
2541         if (hard_reset) {
2542                 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2543                 goya_disable_clk_rlx(hdev);
2544                 goya_set_pll_refclk(hdev);
2545
2546                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2547                 dev_info(hdev->dev,
2548                         "Issued HARD reset command, going to wait %dms\n",
2549                         reset_timeout_ms);
2550         } else {
2551                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2552                 dev_info(hdev->dev,
2553                         "Issued SOFT reset command, going to wait %dms\n",
2554                         reset_timeout_ms);
2555         }
2556
2557         /*
2558          * After hard reset, we can't poll the BTM_FSM register because the PSOC
2559          * itself is in reset. In either reset we need to wait until the reset
2560          * is deasserted
2561          */
2562         msleep(reset_timeout_ms);
2563
2564         status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
2565         if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
2566                 dev_err(hdev->dev,
2567                         "Timeout while waiting for device to reset 0x%x\n",
2568                         status);
2569
2570         if (!hard_reset) {
2571                 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
2572                                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2573                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2574                                 GOYA_ASYNC_EVENT_ID_SOFT_RESET);
2575                 return;
2576         }
2577
2578         /* Chicken bit to re-initiate boot sequencer flow */
2579         WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2580                 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT);
2581         /* Move boot manager FSM to pre boot sequencer init state */
2582         WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2583                         0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
2584
2585         goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
2586                                         HW_CAP_DDR_0 | HW_CAP_DDR_1 |
2587                                         HW_CAP_DMA | HW_CAP_MME |
2588                                         HW_CAP_MMU | HW_CAP_TPC_MBIST |
2589                                         HW_CAP_GOLDEN | HW_CAP_TPC);
2590         memset(goya->events_stat, 0, sizeof(goya->events_stat));
2591
2592         if (!hdev->pldm) {
2593                 int rc;
2594                 /* In case we are running inside VM and the VM is
2595                  * shutting down, we need to make sure CPU boot-loader
2596                  * is running before we can continue the VM shutdown.
2597                  * That is because the VM will send an FLR signal that
2598                  * we must answer
2599                  */
2600                 dev_info(hdev->dev,
2601                         "Going to wait up to %ds for CPU boot loader\n",
2602                         GOYA_CPU_TIMEOUT_USEC / 1000 / 1000);
2603
2604                 rc = hl_poll_timeout(
2605                         hdev,
2606                         mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2607                         status,
2608                         (status == CPU_BOOT_STATUS_DRAM_RDY),
2609                         10000,
2610                         GOYA_CPU_TIMEOUT_USEC);
2611                 if (rc)
2612                         dev_err(hdev->dev,
2613                                 "failed to wait for CPU boot loader\n");
2614         }
2615 }
2616
2617 int goya_suspend(struct hl_device *hdev)
2618 {
2619         int rc;
2620
2621         rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS);
2622         if (rc)
2623                 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2624
2625         return rc;
2626 }
2627
2628 int goya_resume(struct hl_device *hdev)
2629 {
2630         return goya_init_iatu(hdev);
2631 }
2632
2633 static int goya_cb_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2634                 u64 kaddress, phys_addr_t paddress, u32 size)
2635 {
2636         int rc;
2637
2638         vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
2639                         VM_DONTCOPY | VM_NORESERVE;
2640
2641         rc = remap_pfn_range(vma, vma->vm_start, paddress >> PAGE_SHIFT,
2642                                 size, vma->vm_page_prot);
2643         if (rc)
2644                 dev_err(hdev->dev, "remap_pfn_range error %d", rc);
2645
2646         return rc;
2647 }
2648
2649 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2650 {
2651         u32 db_reg_offset, db_value;
2652
2653         switch (hw_queue_id) {
2654         case GOYA_QUEUE_ID_DMA_0:
2655                 db_reg_offset = mmDMA_QM_0_PQ_PI;
2656                 break;
2657
2658         case GOYA_QUEUE_ID_DMA_1:
2659                 db_reg_offset = mmDMA_QM_1_PQ_PI;
2660                 break;
2661
2662         case GOYA_QUEUE_ID_DMA_2:
2663                 db_reg_offset = mmDMA_QM_2_PQ_PI;
2664                 break;
2665
2666         case GOYA_QUEUE_ID_DMA_3:
2667                 db_reg_offset = mmDMA_QM_3_PQ_PI;
2668                 break;
2669
2670         case GOYA_QUEUE_ID_DMA_4:
2671                 db_reg_offset = mmDMA_QM_4_PQ_PI;
2672                 break;
2673
2674         case GOYA_QUEUE_ID_CPU_PQ:
2675                 db_reg_offset = mmCPU_IF_PF_PQ_PI;
2676                 break;
2677
2678         case GOYA_QUEUE_ID_MME:
2679                 db_reg_offset = mmMME_QM_PQ_PI;
2680                 break;
2681
2682         case GOYA_QUEUE_ID_TPC0:
2683                 db_reg_offset = mmTPC0_QM_PQ_PI;
2684                 break;
2685
2686         case GOYA_QUEUE_ID_TPC1:
2687                 db_reg_offset = mmTPC1_QM_PQ_PI;
2688                 break;
2689
2690         case GOYA_QUEUE_ID_TPC2:
2691                 db_reg_offset = mmTPC2_QM_PQ_PI;
2692                 break;
2693
2694         case GOYA_QUEUE_ID_TPC3:
2695                 db_reg_offset = mmTPC3_QM_PQ_PI;
2696                 break;
2697
2698         case GOYA_QUEUE_ID_TPC4:
2699                 db_reg_offset = mmTPC4_QM_PQ_PI;
2700                 break;
2701
2702         case GOYA_QUEUE_ID_TPC5:
2703                 db_reg_offset = mmTPC5_QM_PQ_PI;
2704                 break;
2705
2706         case GOYA_QUEUE_ID_TPC6:
2707                 db_reg_offset = mmTPC6_QM_PQ_PI;
2708                 break;
2709
2710         case GOYA_QUEUE_ID_TPC7:
2711                 db_reg_offset = mmTPC7_QM_PQ_PI;
2712                 break;
2713
2714         default:
2715                 /* Should never get here */
2716                 dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n",
2717                         hw_queue_id);
2718                 return;
2719         }
2720
2721         db_value = pi;
2722
2723         /* ring the doorbell */
2724         WREG32(db_reg_offset, db_value);
2725
2726         if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ)
2727                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2728                                 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2729 }
2730
2731 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
2732 {
2733         /* The QMANs are on the SRAM so need to copy to IO space */
2734         memcpy_toio((void __iomem *) pqe, bd, sizeof(struct hl_bd));
2735 }
2736
2737 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2738                                         dma_addr_t *dma_handle, gfp_t flags)
2739 {
2740         void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
2741                                                 dma_handle, flags);
2742
2743         /* Shift to the device's base physical address of host memory */
2744         if (kernel_addr)
2745                 *dma_handle += HOST_PHYS_BASE;
2746
2747         return kernel_addr;
2748 }
2749
2750 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
2751                                         void *cpu_addr, dma_addr_t dma_handle)
2752 {
2753         /* Cancel the device's base physical address of host memory */
2754         dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE;
2755
2756         dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
2757 }
2758
2759 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
2760                                 dma_addr_t *dma_handle, u16 *queue_len)
2761 {
2762         void *base;
2763         u32 offset;
2764
2765         *dma_handle = hdev->asic_prop.sram_base_address;
2766
2767         base = (void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
2768
2769         switch (queue_id) {
2770         case GOYA_QUEUE_ID_MME:
2771                 offset = MME_QMAN_BASE_OFFSET;
2772                 *queue_len = MME_QMAN_LENGTH;
2773                 break;
2774         case GOYA_QUEUE_ID_TPC0:
2775                 offset = TPC0_QMAN_BASE_OFFSET;
2776                 *queue_len = TPC_QMAN_LENGTH;
2777                 break;
2778         case GOYA_QUEUE_ID_TPC1:
2779                 offset = TPC1_QMAN_BASE_OFFSET;
2780                 *queue_len = TPC_QMAN_LENGTH;
2781                 break;
2782         case GOYA_QUEUE_ID_TPC2:
2783                 offset = TPC2_QMAN_BASE_OFFSET;
2784                 *queue_len = TPC_QMAN_LENGTH;
2785                 break;
2786         case GOYA_QUEUE_ID_TPC3:
2787                 offset = TPC3_QMAN_BASE_OFFSET;
2788                 *queue_len = TPC_QMAN_LENGTH;
2789                 break;
2790         case GOYA_QUEUE_ID_TPC4:
2791                 offset = TPC4_QMAN_BASE_OFFSET;
2792                 *queue_len = TPC_QMAN_LENGTH;
2793                 break;
2794         case GOYA_QUEUE_ID_TPC5:
2795                 offset = TPC5_QMAN_BASE_OFFSET;
2796                 *queue_len = TPC_QMAN_LENGTH;
2797                 break;
2798         case GOYA_QUEUE_ID_TPC6:
2799                 offset = TPC6_QMAN_BASE_OFFSET;
2800                 *queue_len = TPC_QMAN_LENGTH;
2801                 break;
2802         case GOYA_QUEUE_ID_TPC7:
2803                 offset = TPC7_QMAN_BASE_OFFSET;
2804                 *queue_len = TPC_QMAN_LENGTH;
2805                 break;
2806         default:
2807                 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
2808                 return NULL;
2809         }
2810
2811         base += offset;
2812         *dma_handle += offset;
2813
2814         return base;
2815 }
2816
2817 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
2818 {
2819         struct packet_msg_prot *fence_pkt;
2820         u32 *fence_ptr;
2821         dma_addr_t fence_dma_addr;
2822         struct hl_cb *cb;
2823         u32 tmp, timeout;
2824         int rc;
2825
2826         if (hdev->pldm)
2827                 timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC;
2828         else
2829                 timeout = HL_DEVICE_TIMEOUT_USEC;
2830
2831         if (!hdev->asic_funcs->is_device_idle(hdev, NULL, NULL)) {
2832                 dev_err_ratelimited(hdev->dev,
2833                         "Can't send KMD job on QMAN0 because the device is not idle\n");
2834                 return -EBUSY;
2835         }
2836
2837         fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
2838                                                         &fence_dma_addr);
2839         if (!fence_ptr) {
2840                 dev_err(hdev->dev,
2841                         "Failed to allocate fence memory for QMAN0\n");
2842                 return -ENOMEM;
2843         }
2844
2845         goya_qman0_set_security(hdev, true);
2846
2847         cb = job->patched_cb;
2848
2849         fence_pkt = (struct packet_msg_prot *) (uintptr_t) (cb->kernel_address +
2850                         job->job_cb_size - sizeof(struct packet_msg_prot));
2851
2852         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
2853                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
2854                         (1 << GOYA_PKT_CTL_MB_SHIFT);
2855         fence_pkt->ctl = cpu_to_le32(tmp);
2856         fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
2857         fence_pkt->addr = cpu_to_le64(fence_dma_addr);
2858
2859         rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
2860                                         job->job_cb_size, cb->bus_address);
2861         if (rc) {
2862                 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
2863                 goto free_fence_ptr;
2864         }
2865
2866         rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp,
2867                                 (tmp == GOYA_QMAN0_FENCE_VAL), 1000,
2868                                 timeout, true);
2869
2870         hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
2871
2872         if (rc == -ETIMEDOUT) {
2873                 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp);
2874                 goto free_fence_ptr;
2875         }
2876
2877 free_fence_ptr:
2878         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
2879                                         fence_dma_addr);
2880
2881         goya_qman0_set_security(hdev, false);
2882
2883         return rc;
2884 }
2885
2886 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
2887                                 u32 timeout, long *result)
2888 {
2889         struct goya_device *goya = hdev->asic_specific;
2890
2891         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) {
2892                 if (result)
2893                         *result = 0;
2894                 return 0;
2895         }
2896
2897         return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len,
2898                                         timeout, result);
2899 }
2900
2901 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
2902 {
2903         struct packet_msg_prot *fence_pkt;
2904         dma_addr_t pkt_dma_addr;
2905         u32 fence_val, tmp;
2906         dma_addr_t fence_dma_addr;
2907         u32 *fence_ptr;
2908         int rc;
2909
2910         fence_val = GOYA_QMAN0_FENCE_VAL;
2911
2912         fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
2913                                                         &fence_dma_addr);
2914         if (!fence_ptr) {
2915                 dev_err(hdev->dev,
2916                         "Failed to allocate memory for queue testing\n");
2917                 return -ENOMEM;
2918         }
2919
2920         *fence_ptr = 0;
2921
2922         fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev,
2923                                         sizeof(struct packet_msg_prot),
2924                                         GFP_KERNEL, &pkt_dma_addr);
2925         if (!fence_pkt) {
2926                 dev_err(hdev->dev,
2927                         "Failed to allocate packet for queue testing\n");
2928                 rc = -ENOMEM;
2929                 goto free_fence_ptr;
2930         }
2931
2932         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
2933                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
2934                         (1 << GOYA_PKT_CTL_MB_SHIFT);
2935         fence_pkt->ctl = cpu_to_le32(tmp);
2936         fence_pkt->value = cpu_to_le32(fence_val);
2937         fence_pkt->addr = cpu_to_le64(fence_dma_addr);
2938
2939         rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
2940                                         sizeof(struct packet_msg_prot),
2941                                         pkt_dma_addr);
2942         if (rc) {
2943                 dev_err(hdev->dev,
2944                         "Failed to send fence packet\n");
2945                 goto free_pkt;
2946         }
2947
2948         rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val),
2949                                         1000, GOYA_TEST_QUEUE_WAIT_USEC, true);
2950
2951         hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
2952
2953         if (rc == -ETIMEDOUT) {
2954                 dev_err(hdev->dev,
2955                         "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
2956                         hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
2957                 rc = -EIO;
2958         } else {
2959                 dev_info(hdev->dev, "queue test on H/W queue %d succeeded\n",
2960                         hw_queue_id);
2961         }
2962
2963 free_pkt:
2964         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt,
2965                                         pkt_dma_addr);
2966 free_fence_ptr:
2967         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
2968                                         fence_dma_addr);
2969         return rc;
2970 }
2971
2972 int goya_test_cpu_queue(struct hl_device *hdev)
2973 {
2974         struct goya_device *goya = hdev->asic_specific;
2975
2976         /*
2977          * check capability here as send_cpu_message() won't update the result
2978          * value if no capability
2979          */
2980         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
2981                 return 0;
2982
2983         return hl_fw_test_cpu_queue(hdev);
2984 }
2985
2986 int goya_test_queues(struct hl_device *hdev)
2987 {
2988         int i, rc, ret_val = 0;
2989
2990         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
2991                 rc = goya_test_queue(hdev, i);
2992                 if (rc)
2993                         ret_val = -EINVAL;
2994         }
2995
2996         return ret_val;
2997 }
2998
2999 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3000                                         gfp_t mem_flags, dma_addr_t *dma_handle)
3001 {
3002         void *kernel_addr;
3003
3004         if (size > GOYA_DMA_POOL_BLK_SIZE)
3005                 return NULL;
3006
3007         kernel_addr =  dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3008
3009         /* Shift to the device's base physical address of host memory */
3010         if (kernel_addr)
3011                 *dma_handle += HOST_PHYS_BASE;
3012
3013         return kernel_addr;
3014 }
3015
3016 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3017                                 dma_addr_t dma_addr)
3018 {
3019         /* Cancel the device's base physical address of host memory */
3020         dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE;
3021
3022         dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
3023 }
3024
3025 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
3026                                         dma_addr_t *dma_handle)
3027 {
3028         void *vaddr;
3029
3030         vaddr = hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
3031         *dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address +
3032                         VA_CPU_ACCESSIBLE_MEM_ADDR;
3033
3034         return vaddr;
3035 }
3036
3037 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
3038                                         void *vaddr)
3039 {
3040         hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
3041 }
3042
3043 static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sgl,
3044                                 int nents, enum dma_data_direction dir)
3045 {
3046         struct scatterlist *sg;
3047         int i;
3048
3049         if (!dma_map_sg(&hdev->pdev->dev, sgl, nents, dir))
3050                 return -ENOMEM;
3051
3052         /* Shift to the device's base physical address of host memory */
3053         for_each_sg(sgl, sg, nents, i)
3054                 sg->dma_address += HOST_PHYS_BASE;
3055
3056         return 0;
3057 }
3058
3059 static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sgl,
3060                                 int nents, enum dma_data_direction dir)
3061 {
3062         struct scatterlist *sg;
3063         int i;
3064
3065         /* Cancel the device's base physical address of host memory */
3066         for_each_sg(sgl, sg, nents, i)
3067                 sg->dma_address -= HOST_PHYS_BASE;
3068
3069         dma_unmap_sg(&hdev->pdev->dev, sgl, nents, dir);
3070 }
3071
3072 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3073 {
3074         struct scatterlist *sg, *sg_next_iter;
3075         u32 count, dma_desc_cnt;
3076         u64 len, len_next;
3077         dma_addr_t addr, addr_next;
3078
3079         dma_desc_cnt = 0;
3080
3081         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3082
3083                 len = sg_dma_len(sg);
3084                 addr = sg_dma_address(sg);
3085
3086                 if (len == 0)
3087                         break;
3088
3089                 while ((count + 1) < sgt->nents) {
3090                         sg_next_iter = sg_next(sg);
3091                         len_next = sg_dma_len(sg_next_iter);
3092                         addr_next = sg_dma_address(sg_next_iter);
3093
3094                         if (len_next == 0)
3095                                 break;
3096
3097                         if ((addr + len == addr_next) &&
3098                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3099                                 len += len_next;
3100                                 count++;
3101                                 sg = sg_next_iter;
3102                         } else {
3103                                 break;
3104                         }
3105                 }
3106
3107                 dma_desc_cnt++;
3108         }
3109
3110         return dma_desc_cnt * sizeof(struct packet_lin_dma);
3111 }
3112
3113 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3114                                 struct hl_cs_parser *parser,
3115                                 struct packet_lin_dma *user_dma_pkt,
3116                                 u64 addr, enum dma_data_direction dir)
3117 {
3118         struct hl_userptr *userptr;
3119         int rc;
3120
3121         if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3122                         parser->job_userptr_list, &userptr))
3123                 goto already_pinned;
3124
3125         userptr = kzalloc(sizeof(*userptr), GFP_ATOMIC);
3126         if (!userptr)
3127                 return -ENOMEM;
3128
3129         rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3130                                 userptr);
3131         if (rc)
3132                 goto free_userptr;
3133
3134         list_add_tail(&userptr->job_node, parser->job_userptr_list);
3135
3136         rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl,
3137                                         userptr->sgt->nents, dir);
3138         if (rc) {
3139                 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3140                 goto unpin_memory;
3141         }
3142
3143         userptr->dma_mapped = true;
3144         userptr->dir = dir;
3145
3146 already_pinned:
3147         parser->patched_cb_size +=
3148                         goya_get_dma_desc_list_size(hdev, userptr->sgt);
3149
3150         return 0;
3151
3152 unpin_memory:
3153         hl_unpin_host_memory(hdev, userptr);
3154 free_userptr:
3155         kfree(userptr);
3156         return rc;
3157 }
3158
3159 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3160                                 struct hl_cs_parser *parser,
3161                                 struct packet_lin_dma *user_dma_pkt)
3162 {
3163         u64 device_memory_addr, addr;
3164         enum dma_data_direction dir;
3165         enum goya_dma_direction user_dir;
3166         bool sram_addr = true;
3167         bool skip_host_mem_pin = false;
3168         bool user_memset;
3169         u32 ctl;
3170         int rc = 0;
3171
3172         ctl = le32_to_cpu(user_dma_pkt->ctl);
3173
3174         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3175                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3176
3177         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3178                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3179
3180         switch (user_dir) {
3181         case DMA_HOST_TO_DRAM:
3182                 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3183                 dir = DMA_TO_DEVICE;
3184                 sram_addr = false;
3185                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3186                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3187                 if (user_memset)
3188                         skip_host_mem_pin = true;
3189                 break;
3190
3191         case DMA_DRAM_TO_HOST:
3192                 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3193                 dir = DMA_FROM_DEVICE;
3194                 sram_addr = false;
3195                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3196                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3197                 break;
3198
3199         case DMA_HOST_TO_SRAM:
3200                 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3201                 dir = DMA_TO_DEVICE;
3202                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3203                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3204                 if (user_memset)
3205                         skip_host_mem_pin = true;
3206                 break;
3207
3208         case DMA_SRAM_TO_HOST:
3209                 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3210                 dir = DMA_FROM_DEVICE;
3211                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3212                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3213                 break;
3214         default:
3215                 dev_err(hdev->dev, "DMA direction is undefined\n");
3216                 return -EFAULT;
3217         }
3218
3219         if (sram_addr) {
3220                 if (!hl_mem_area_inside_range(device_memory_addr,
3221                                 le32_to_cpu(user_dma_pkt->tsize),
3222                                 hdev->asic_prop.sram_user_base_address,
3223                                 hdev->asic_prop.sram_end_address)) {
3224
3225                         dev_err(hdev->dev,
3226                                 "SRAM address 0x%llx + 0x%x is invalid\n",
3227                                 device_memory_addr,
3228                                 user_dma_pkt->tsize);
3229                         return -EFAULT;
3230                 }
3231         } else {
3232                 if (!hl_mem_area_inside_range(device_memory_addr,
3233                                 le32_to_cpu(user_dma_pkt->tsize),
3234                                 hdev->asic_prop.dram_user_base_address,
3235                                 hdev->asic_prop.dram_end_address)) {
3236
3237                         dev_err(hdev->dev,
3238                                 "DRAM address 0x%llx + 0x%x is invalid\n",
3239                                 device_memory_addr,
3240                                 user_dma_pkt->tsize);
3241                         return -EFAULT;
3242                 }
3243         }
3244
3245         if (skip_host_mem_pin)
3246                 parser->patched_cb_size += sizeof(*user_dma_pkt);
3247         else {
3248                 if ((dir == DMA_TO_DEVICE) &&
3249                                 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) {
3250                         dev_err(hdev->dev,
3251                                 "Can't DMA from host on queue other then 1\n");
3252                         return -EFAULT;
3253                 }
3254
3255                 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3256                                                 addr, dir);
3257         }
3258
3259         return rc;
3260 }
3261
3262 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3263                                 struct hl_cs_parser *parser,
3264                                 struct packet_lin_dma *user_dma_pkt)
3265 {
3266         u64 sram_memory_addr, dram_memory_addr;
3267         enum goya_dma_direction user_dir;
3268         u32 ctl;
3269
3270         ctl = le32_to_cpu(user_dma_pkt->ctl);
3271         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3272                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3273
3274         if (user_dir == DMA_DRAM_TO_SRAM) {
3275                 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3276                 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3277                 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3278         } else {
3279                 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3280                 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3281                 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3282         }
3283
3284         if (!hl_mem_area_inside_range(sram_memory_addr,
3285                                 le32_to_cpu(user_dma_pkt->tsize),
3286                                 hdev->asic_prop.sram_user_base_address,
3287                                 hdev->asic_prop.sram_end_address)) {
3288                 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3289                         sram_memory_addr, user_dma_pkt->tsize);
3290                 return -EFAULT;
3291         }
3292
3293         if (!hl_mem_area_inside_range(dram_memory_addr,
3294                                 le32_to_cpu(user_dma_pkt->tsize),
3295                                 hdev->asic_prop.dram_user_base_address,
3296                                 hdev->asic_prop.dram_end_address)) {
3297                 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3298                         dram_memory_addr, user_dma_pkt->tsize);
3299                 return -EFAULT;
3300         }
3301
3302         parser->patched_cb_size += sizeof(*user_dma_pkt);
3303
3304         return 0;
3305 }
3306
3307 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3308                                 struct hl_cs_parser *parser,
3309                                 struct packet_lin_dma *user_dma_pkt)
3310 {
3311         enum goya_dma_direction user_dir;
3312         u32 ctl;
3313         int rc;
3314
3315         dev_dbg(hdev->dev, "DMA packet details:\n");
3316         dev_dbg(hdev->dev, "source == 0x%llx\n",
3317                 le64_to_cpu(user_dma_pkt->src_addr));
3318         dev_dbg(hdev->dev, "destination == 0x%llx\n",
3319                 le64_to_cpu(user_dma_pkt->dst_addr));
3320         dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3321
3322         ctl = le32_to_cpu(user_dma_pkt->ctl);
3323         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3324                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3325
3326         /*
3327          * Special handling for DMA with size 0. The H/W has a bug where
3328          * this can cause the QMAN DMA to get stuck, so block it here.
3329          */
3330         if (user_dma_pkt->tsize == 0) {
3331                 dev_err(hdev->dev,
3332                         "Got DMA with size 0, might reset the device\n");
3333                 return -EINVAL;
3334         }
3335
3336         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM))
3337                 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3338         else
3339                 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3340
3341         return rc;
3342 }
3343
3344 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3345                                 struct hl_cs_parser *parser,
3346                                 struct packet_lin_dma *user_dma_pkt)
3347 {
3348         dev_dbg(hdev->dev, "DMA packet details:\n");
3349         dev_dbg(hdev->dev, "source == 0x%llx\n",
3350                 le64_to_cpu(user_dma_pkt->src_addr));
3351         dev_dbg(hdev->dev, "destination == 0x%llx\n",
3352                 le64_to_cpu(user_dma_pkt->dst_addr));
3353         dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3354
3355         /*
3356          * WA for HW-23.
3357          * We can't allow user to read from Host using QMANs other than 1.
3358          */
3359         if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 &&
3360                 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr),
3361                                 le32_to_cpu(user_dma_pkt->tsize),
3362                                 hdev->asic_prop.va_space_host_start_address,
3363                                 hdev->asic_prop.va_space_host_end_address)) {
3364                 dev_err(hdev->dev,
3365                         "Can't DMA from host on queue other then 1\n");
3366                 return -EFAULT;
3367         }
3368
3369         if (user_dma_pkt->tsize == 0) {
3370                 dev_err(hdev->dev,
3371                         "Got DMA with size 0, might reset the device\n");
3372                 return -EINVAL;
3373         }
3374
3375         parser->patched_cb_size += sizeof(*user_dma_pkt);
3376
3377         return 0;
3378 }
3379
3380 static int goya_validate_wreg32(struct hl_device *hdev,
3381                                 struct hl_cs_parser *parser,
3382                                 struct packet_wreg32 *wreg_pkt)
3383 {
3384         struct goya_device *goya = hdev->asic_specific;
3385         u32 sob_start_addr, sob_end_addr;
3386         u16 reg_offset;
3387
3388         reg_offset = le32_to_cpu(wreg_pkt->ctl) &
3389                         GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK;
3390
3391         dev_dbg(hdev->dev, "WREG32 packet details:\n");
3392         dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3393         dev_dbg(hdev->dev, "value      == 0x%x\n",
3394                 le32_to_cpu(wreg_pkt->value));
3395
3396         if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3397                 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3398                         reg_offset);
3399                 return -EPERM;
3400         }
3401
3402         /*
3403          * With MMU, DMA channels are not secured, so it doesn't matter where
3404          * the WR COMP will be written to because it will go out with
3405          * non-secured property
3406          */
3407         if (goya->hw_cap_initialized & HW_CAP_MMU)
3408                 return 0;
3409
3410         sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
3411         sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023);
3412
3413         if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) ||
3414                         (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) {
3415
3416                 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3417                         wreg_pkt->value);
3418                 return -EPERM;
3419         }
3420
3421         return 0;
3422 }
3423
3424 static int goya_validate_cb(struct hl_device *hdev,
3425                         struct hl_cs_parser *parser, bool is_mmu)
3426 {
3427         u32 cb_parsed_length = 0;
3428         int rc = 0;
3429
3430         parser->patched_cb_size = 0;
3431
3432         /* cb_user_size is more than 0 so loop will always be executed */
3433         while (cb_parsed_length < parser->user_cb_size) {
3434                 enum packet_id pkt_id;
3435                 u16 pkt_size;
3436                 struct goya_packet *user_pkt;
3437
3438                 user_pkt = (struct goya_packet *) (uintptr_t)
3439                         (parser->user_cb->kernel_address + cb_parsed_length);
3440
3441                 pkt_id = (enum packet_id) (
3442                                 (le64_to_cpu(user_pkt->header) &
3443                                 PACKET_HEADER_PACKET_ID_MASK) >>
3444                                         PACKET_HEADER_PACKET_ID_SHIFT);
3445
3446                 pkt_size = goya_packet_sizes[pkt_id];
3447                 cb_parsed_length += pkt_size;
3448                 if (cb_parsed_length > parser->user_cb_size) {
3449                         dev_err(hdev->dev,
3450                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3451                         rc = -EINVAL;
3452                         break;
3453                 }
3454
3455                 switch (pkt_id) {
3456                 case PACKET_WREG_32:
3457                         /*
3458                          * Although it is validated after copy in patch_cb(),
3459                          * need to validate here as well because patch_cb() is
3460                          * not called in MMU path while this function is called
3461                          */
3462                         rc = goya_validate_wreg32(hdev,
3463                                 parser, (struct packet_wreg32 *) user_pkt);
3464                         break;
3465
3466                 case PACKET_WREG_BULK:
3467                         dev_err(hdev->dev,
3468                                 "User not allowed to use WREG_BULK\n");
3469                         rc = -EPERM;
3470                         break;
3471
3472                 case PACKET_MSG_PROT:
3473                         dev_err(hdev->dev,
3474                                 "User not allowed to use MSG_PROT\n");
3475                         rc = -EPERM;
3476                         break;
3477
3478                 case PACKET_CP_DMA:
3479                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3480                         rc = -EPERM;
3481                         break;
3482
3483                 case PACKET_STOP:
3484                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3485                         rc = -EPERM;
3486                         break;
3487
3488                 case PACKET_LIN_DMA:
3489                         if (is_mmu)
3490                                 rc = goya_validate_dma_pkt_mmu(hdev, parser,
3491                                         (struct packet_lin_dma *) user_pkt);
3492                         else
3493                                 rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3494                                         (struct packet_lin_dma *) user_pkt);
3495                         break;
3496
3497                 case PACKET_MSG_LONG:
3498                 case PACKET_MSG_SHORT:
3499                 case PACKET_FENCE:
3500                 case PACKET_NOP:
3501                         parser->patched_cb_size += pkt_size;
3502                         break;
3503
3504                 default:
3505                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3506                                 pkt_id);
3507                         rc = -EINVAL;
3508                         break;
3509                 }
3510
3511                 if (rc)
3512                         break;
3513         }
3514
3515         /*
3516          * The new CB should have space at the end for two MSG_PROT packets:
3517          * 1. A packet that will act as a completion packet
3518          * 2. A packet that will generate MSI-X interrupt
3519          */
3520         parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
3521
3522         return rc;
3523 }
3524
3525 static int goya_patch_dma_packet(struct hl_device *hdev,
3526                                 struct hl_cs_parser *parser,
3527                                 struct packet_lin_dma *user_dma_pkt,
3528                                 struct packet_lin_dma *new_dma_pkt,
3529                                 u32 *new_dma_pkt_size)
3530 {
3531         struct hl_userptr *userptr;
3532         struct scatterlist *sg, *sg_next_iter;
3533         u32 count, dma_desc_cnt;
3534         u64 len, len_next;
3535         dma_addr_t dma_addr, dma_addr_next;
3536         enum goya_dma_direction user_dir;
3537         u64 device_memory_addr, addr;
3538         enum dma_data_direction dir;
3539         struct sg_table *sgt;
3540         bool skip_host_mem_pin = false;
3541         bool user_memset;
3542         u32 user_rdcomp_mask, user_wrcomp_mask, ctl;
3543
3544         ctl = le32_to_cpu(user_dma_pkt->ctl);
3545
3546         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3547                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3548
3549         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3550                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3551
3552         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) ||
3553                         (user_dma_pkt->tsize == 0)) {
3554                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
3555                 *new_dma_pkt_size = sizeof(*new_dma_pkt);
3556                 return 0;
3557         }
3558
3559         if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) {
3560                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3561                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3562                 dir = DMA_TO_DEVICE;
3563                 if (user_memset)
3564                         skip_host_mem_pin = true;
3565         } else {
3566                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3567                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3568                 dir = DMA_FROM_DEVICE;
3569         }
3570
3571         if ((!skip_host_mem_pin) &&
3572                 (hl_userptr_is_pinned(hdev, addr,
3573                         le32_to_cpu(user_dma_pkt->tsize),
3574                         parser->job_userptr_list, &userptr) == false)) {
3575                 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3576                                 addr, user_dma_pkt->tsize);
3577                 return -EFAULT;
3578         }
3579
3580         if ((user_memset) && (dir == DMA_TO_DEVICE)) {
3581                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
3582                 *new_dma_pkt_size = sizeof(*user_dma_pkt);
3583                 return 0;
3584         }
3585
3586         user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK;
3587
3588         user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK;
3589
3590         sgt = userptr->sgt;
3591         dma_desc_cnt = 0;
3592
3593         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3594                 len = sg_dma_len(sg);
3595                 dma_addr = sg_dma_address(sg);
3596
3597                 if (len == 0)
3598                         break;
3599
3600                 while ((count + 1) < sgt->nents) {
3601                         sg_next_iter = sg_next(sg);
3602                         len_next = sg_dma_len(sg_next_iter);
3603                         dma_addr_next = sg_dma_address(sg_next_iter);
3604
3605                         if (len_next == 0)
3606                                 break;
3607
3608                         if ((dma_addr + len == dma_addr_next) &&
3609                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3610                                 len += len_next;
3611                                 count++;
3612                                 sg = sg_next_iter;
3613                         } else {
3614                                 break;
3615                         }
3616                 }
3617
3618                 ctl = le32_to_cpu(user_dma_pkt->ctl);
3619                 if (likely(dma_desc_cnt))
3620                         ctl &= ~GOYA_PKT_CTL_EB_MASK;
3621                 ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK |
3622                                 GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK);
3623                 new_dma_pkt->ctl = cpu_to_le32(ctl);
3624                 new_dma_pkt->tsize = cpu_to_le32((u32) len);
3625
3626                 if (dir == DMA_TO_DEVICE) {
3627                         new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
3628                         new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
3629                 } else {
3630                         new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
3631                         new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
3632                 }
3633
3634                 if (!user_memset)
3635                         device_memory_addr += len;
3636                 dma_desc_cnt++;
3637                 new_dma_pkt++;
3638         }
3639
3640         if (!dma_desc_cnt) {
3641                 dev_err(hdev->dev,
3642                         "Error of 0 SG entries when patching DMA packet\n");
3643                 return -EFAULT;
3644         }
3645
3646         /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */
3647         new_dma_pkt--;
3648         new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask);
3649
3650         *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
3651
3652         return 0;
3653 }
3654
3655 static int goya_patch_cb(struct hl_device *hdev,
3656                                 struct hl_cs_parser *parser)
3657 {
3658         u32 cb_parsed_length = 0;
3659         u32 cb_patched_cur_length = 0;
3660         int rc = 0;
3661
3662         /* cb_user_size is more than 0 so loop will always be executed */
3663         while (cb_parsed_length < parser->user_cb_size) {
3664                 enum packet_id pkt_id;
3665                 u16 pkt_size;
3666                 u32 new_pkt_size = 0;
3667                 struct goya_packet *user_pkt, *kernel_pkt;
3668
3669                 user_pkt = (struct goya_packet *) (uintptr_t)
3670                         (parser->user_cb->kernel_address + cb_parsed_length);
3671                 kernel_pkt = (struct goya_packet *) (uintptr_t)
3672                         (parser->patched_cb->kernel_address +
3673                                         cb_patched_cur_length);
3674
3675                 pkt_id = (enum packet_id) (
3676                                 (le64_to_cpu(user_pkt->header) &
3677                                 PACKET_HEADER_PACKET_ID_MASK) >>
3678                                         PACKET_HEADER_PACKET_ID_SHIFT);
3679
3680                 pkt_size = goya_packet_sizes[pkt_id];
3681                 cb_parsed_length += pkt_size;
3682                 if (cb_parsed_length > parser->user_cb_size) {
3683                         dev_err(hdev->dev,
3684                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3685                         rc = -EINVAL;
3686                         break;
3687                 }
3688
3689                 switch (pkt_id) {
3690                 case PACKET_LIN_DMA:
3691                         rc = goya_patch_dma_packet(hdev, parser,
3692                                         (struct packet_lin_dma *) user_pkt,
3693                                         (struct packet_lin_dma *) kernel_pkt,
3694                                         &new_pkt_size);
3695                         cb_patched_cur_length += new_pkt_size;
3696                         break;
3697
3698                 case PACKET_WREG_32:
3699                         memcpy(kernel_pkt, user_pkt, pkt_size);
3700                         cb_patched_cur_length += pkt_size;
3701                         rc = goya_validate_wreg32(hdev, parser,
3702                                         (struct packet_wreg32 *) kernel_pkt);
3703                         break;
3704
3705                 case PACKET_WREG_BULK:
3706                         dev_err(hdev->dev,
3707                                 "User not allowed to use WREG_BULK\n");
3708                         rc = -EPERM;
3709                         break;
3710
3711                 case PACKET_MSG_PROT:
3712                         dev_err(hdev->dev,
3713                                 "User not allowed to use MSG_PROT\n");
3714                         rc = -EPERM;
3715                         break;
3716
3717                 case PACKET_CP_DMA:
3718                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3719                         rc = -EPERM;
3720                         break;
3721
3722                 case PACKET_STOP:
3723                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3724                         rc = -EPERM;
3725                         break;
3726
3727                 case PACKET_MSG_LONG:
3728                 case PACKET_MSG_SHORT:
3729                 case PACKET_FENCE:
3730                 case PACKET_NOP:
3731                         memcpy(kernel_pkt, user_pkt, pkt_size);
3732                         cb_patched_cur_length += pkt_size;
3733                         break;
3734
3735                 default:
3736                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3737                                 pkt_id);
3738                         rc = -EINVAL;
3739                         break;
3740                 }
3741
3742                 if (rc)
3743                         break;
3744         }
3745
3746         return rc;
3747 }
3748
3749 static int goya_parse_cb_mmu(struct hl_device *hdev,
3750                 struct hl_cs_parser *parser)
3751 {
3752         u64 patched_cb_handle;
3753         u32 patched_cb_size;
3754         struct hl_cb *user_cb;
3755         int rc;
3756
3757         /*
3758          * The new CB should have space at the end for two MSG_PROT pkt:
3759          * 1. A packet that will act as a completion packet
3760          * 2. A packet that will generate MSI-X interrupt
3761          */
3762         parser->patched_cb_size = parser->user_cb_size +
3763                         sizeof(struct packet_msg_prot) * 2;
3764
3765         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr,
3766                                 parser->patched_cb_size,
3767                                 &patched_cb_handle, HL_KERNEL_ASID_ID);
3768
3769         if (rc) {
3770                 dev_err(hdev->dev,
3771                         "Failed to allocate patched CB for DMA CS %d\n",
3772                         rc);
3773                 return rc;
3774         }
3775
3776         patched_cb_handle >>= PAGE_SHIFT;
3777         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
3778                                 (u32) patched_cb_handle);
3779         /* hl_cb_get should never fail here so use kernel WARN */
3780         WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
3781                         (u32) patched_cb_handle);
3782         if (!parser->patched_cb) {
3783                 rc = -EFAULT;
3784                 goto out;
3785         }
3786
3787         /*
3788          * The check that parser->user_cb_size <= parser->user_cb->size was done
3789          * in validate_queue_index().
3790          */
3791         memcpy((void *) (uintptr_t) parser->patched_cb->kernel_address,
3792                 (void *) (uintptr_t) parser->user_cb->kernel_address,
3793                 parser->user_cb_size);
3794
3795         patched_cb_size = parser->patched_cb_size;
3796
3797         /* validate patched CB instead of user CB */
3798         user_cb = parser->user_cb;
3799         parser->user_cb = parser->patched_cb;
3800         rc = goya_validate_cb(hdev, parser, true);
3801         parser->user_cb = user_cb;
3802
3803         if (rc) {
3804                 hl_cb_put(parser->patched_cb);
3805                 goto out;
3806         }
3807
3808         if (patched_cb_size != parser->patched_cb_size) {
3809                 dev_err(hdev->dev, "user CB size mismatch\n");
3810                 hl_cb_put(parser->patched_cb);
3811                 rc = -EINVAL;
3812                 goto out;
3813         }
3814
3815 out:
3816         /*
3817          * Always call cb destroy here because we still have 1 reference
3818          * to it by calling cb_get earlier. After the job will be completed,
3819          * cb_put will release it, but here we want to remove it from the
3820          * idr
3821          */
3822         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
3823                                         patched_cb_handle << PAGE_SHIFT);
3824
3825         return rc;
3826 }
3827
3828 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
3829                                 struct hl_cs_parser *parser)
3830 {
3831         u64 patched_cb_handle;
3832         int rc;
3833
3834         rc = goya_validate_cb(hdev, parser, false);
3835
3836         if (rc)
3837                 goto free_userptr;
3838
3839         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr,
3840                                 parser->patched_cb_size,
3841                                 &patched_cb_handle, HL_KERNEL_ASID_ID);
3842         if (rc) {
3843                 dev_err(hdev->dev,
3844                         "Failed to allocate patched CB for DMA CS %d\n", rc);
3845                 goto free_userptr;
3846         }
3847
3848         patched_cb_handle >>= PAGE_SHIFT;
3849         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
3850                                 (u32) patched_cb_handle);
3851         /* hl_cb_get should never fail here so use kernel WARN */
3852         WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
3853                         (u32) patched_cb_handle);
3854         if (!parser->patched_cb) {
3855                 rc = -EFAULT;
3856                 goto out;
3857         }
3858
3859         rc = goya_patch_cb(hdev, parser);
3860
3861         if (rc)
3862                 hl_cb_put(parser->patched_cb);
3863
3864 out:
3865         /*
3866          * Always call cb destroy here because we still have 1 reference
3867          * to it by calling cb_get earlier. After the job will be completed,
3868          * cb_put will release it, but here we want to remove it from the
3869          * idr
3870          */
3871         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
3872                                 patched_cb_handle << PAGE_SHIFT);
3873
3874 free_userptr:
3875         if (rc)
3876                 hl_userptr_delete_list(hdev, parser->job_userptr_list);
3877         return rc;
3878 }
3879
3880 static int goya_parse_cb_no_ext_queue(struct hl_device *hdev,
3881                                         struct hl_cs_parser *parser)
3882 {
3883         struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
3884         struct goya_device *goya = hdev->asic_specific;
3885
3886         if (goya->hw_cap_initialized & HW_CAP_MMU)
3887                 return 0;
3888
3889         /* For internal queue jobs, just check if CB address is valid */
3890         if (hl_mem_area_inside_range(
3891                         (u64) (uintptr_t) parser->user_cb,
3892                         parser->user_cb_size,
3893                         asic_prop->sram_user_base_address,
3894                         asic_prop->sram_end_address))
3895                 return 0;
3896
3897         if (hl_mem_area_inside_range(
3898                         (u64) (uintptr_t) parser->user_cb,
3899                         parser->user_cb_size,
3900                         asic_prop->dram_user_base_address,
3901                         asic_prop->dram_end_address))
3902                 return 0;
3903
3904         dev_err(hdev->dev,
3905                 "Internal CB address %px + 0x%x is not in SRAM nor in DRAM\n",
3906                 parser->user_cb, parser->user_cb_size);
3907
3908         return -EFAULT;
3909 }
3910
3911 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
3912 {
3913         struct goya_device *goya = hdev->asic_specific;
3914
3915         if (!parser->ext_queue)
3916                 return goya_parse_cb_no_ext_queue(hdev, parser);
3917
3918         if (goya->hw_cap_initialized & HW_CAP_MMU)
3919                 return goya_parse_cb_mmu(hdev, parser);
3920         else
3921                 return goya_parse_cb_no_mmu(hdev, parser);
3922 }
3923
3924 void goya_add_end_of_cb_packets(struct hl_device *hdev, u64 kernel_address,
3925                                 u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec)
3926 {
3927         struct packet_msg_prot *cq_pkt;
3928         u32 tmp;
3929
3930         cq_pkt = (struct packet_msg_prot *) (uintptr_t)
3931                 (kernel_address + len - (sizeof(struct packet_msg_prot) * 2));
3932
3933         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3934                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3935                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3936         cq_pkt->ctl = cpu_to_le32(tmp);
3937         cq_pkt->value = cpu_to_le32(cq_val);
3938         cq_pkt->addr = cpu_to_le64(cq_addr);
3939
3940         cq_pkt++;
3941
3942         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3943                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3944         cq_pkt->ctl = cpu_to_le32(tmp);
3945         cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF);
3946         cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF);
3947 }
3948
3949 void goya_update_eq_ci(struct hl_device *hdev, u32 val)
3950 {
3951         WREG32(mmCPU_EQ_CI, val);
3952 }
3953
3954 void goya_restore_phase_topology(struct hl_device *hdev)
3955 {
3956
3957 }
3958
3959 static void goya_clear_sm_regs(struct hl_device *hdev)
3960 {
3961         int i, num_of_sob_in_longs, num_of_mon_in_longs;
3962
3963         num_of_sob_in_longs =
3964                 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4);
3965
3966         num_of_mon_in_longs =
3967                 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4);
3968
3969         for (i = 0 ; i < num_of_sob_in_longs ; i += 4)
3970                 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
3971
3972         for (i = 0 ; i < num_of_mon_in_longs ; i += 4)
3973                 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
3974
3975         /* Flush all WREG to prevent race */
3976         i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
3977 }
3978
3979 /*
3980  * goya_debugfs_read32 - read a 32bit value from a given device or a host mapped
3981  *                       address.
3982  *
3983  * @hdev:       pointer to hl_device structure
3984  * @addr:       device or host mapped address
3985  * @val:        returned value
3986  *
3987  * In case of DDR address that is not mapped into the default aperture that
3988  * the DDR bar exposes, the function will configure the iATU so that the DDR
3989  * bar will be positioned at a base address that allows reading from the
3990  * required address. Configuring the iATU during normal operation can
3991  * lead to undefined behavior and therefore, should be done with extreme care
3992  *
3993  */
3994 static int goya_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val)
3995 {
3996         struct asic_fixed_properties *prop = &hdev->asic_prop;
3997         u64 ddr_bar_addr;
3998         int rc = 0;
3999
4000         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4001                 *val = RREG32(addr - CFG_BASE);
4002
4003         } else if ((addr >= SRAM_BASE_ADDR) &&
4004                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4005
4006                 *val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4007                                 (addr - SRAM_BASE_ADDR));
4008
4009         } else if ((addr >= DRAM_PHYS_BASE) &&
4010                         (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) {
4011
4012                 u64 bar_base_addr = DRAM_PHYS_BASE +
4013                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4014
4015                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4016                 if (ddr_bar_addr != U64_MAX) {
4017                         *val = readl(hdev->pcie_bar[DDR_BAR_ID] +
4018                                                 (addr - bar_base_addr));
4019
4020                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4021                                                         ddr_bar_addr);
4022                 }
4023                 if (ddr_bar_addr == U64_MAX)
4024                         rc = -EIO;
4025
4026         } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
4027                 *val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);
4028
4029         } else {
4030                 rc = -EFAULT;
4031         }
4032
4033         return rc;
4034 }
4035
4036 /*
4037  * goya_debugfs_write32 - write a 32bit value to a given device or a host mapped
4038  *                        address.
4039  *
4040  * @hdev:       pointer to hl_device structure
4041  * @addr:       device or host mapped address
4042  * @val:        returned value
4043  *
4044  * In case of DDR address that is not mapped into the default aperture that
4045  * the DDR bar exposes, the function will configure the iATU so that the DDR
4046  * bar will be positioned at a base address that allows writing to the
4047  * required address. Configuring the iATU during normal operation can
4048  * lead to undefined behavior and therefore, should be done with extreme care
4049  *
4050  */
4051 static int goya_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val)
4052 {
4053         struct asic_fixed_properties *prop = &hdev->asic_prop;
4054         u64 ddr_bar_addr;
4055         int rc = 0;
4056
4057         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4058                 WREG32(addr - CFG_BASE, val);
4059
4060         } else if ((addr >= SRAM_BASE_ADDR) &&
4061                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4062
4063                 writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4064                                         (addr - SRAM_BASE_ADDR));
4065
4066         } else if ((addr >= DRAM_PHYS_BASE) &&
4067                         (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) {
4068
4069                 u64 bar_base_addr = DRAM_PHYS_BASE +
4070                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4071
4072                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4073                 if (ddr_bar_addr != U64_MAX) {
4074                         writel(val, hdev->pcie_bar[DDR_BAR_ID] +
4075                                                 (addr - bar_base_addr));
4076
4077                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4078                                                         ddr_bar_addr);
4079                 }
4080                 if (ddr_bar_addr == U64_MAX)
4081                         rc = -EIO;
4082
4083         } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
4084                 *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
4085
4086         } else {
4087                 rc = -EFAULT;
4088         }
4089
4090         return rc;
4091 }
4092
4093 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4094 {
4095         struct goya_device *goya = hdev->asic_specific;
4096
4097         if (hdev->hard_reset_pending)
4098                 return U64_MAX;
4099
4100         return readq(hdev->pcie_bar[DDR_BAR_ID] +
4101                         (addr - goya->ddr_bar_cur_addr));
4102 }
4103
4104 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4105 {
4106         struct goya_device *goya = hdev->asic_specific;
4107
4108         if (hdev->hard_reset_pending)
4109                 return;
4110
4111         writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4112                         (addr - goya->ddr_bar_cur_addr));
4113 }
4114
4115 static const char *_goya_get_event_desc(u16 event_type)
4116 {
4117         switch (event_type) {
4118         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4119                 return "PCIe_if";
4120         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4121         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4122         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4123         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4124         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4125         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4126         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4127         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4128                 return "TPC%d_ecc";
4129         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4130                 return "MME_ecc";
4131         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4132                 return "MME_ecc_ext";
4133         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4134                 return "MMU_ecc";
4135         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4136                 return "DMA_macro";
4137         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4138                 return "DMA_ecc";
4139         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4140                 return "CPU_if_ecc";
4141         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4142                 return "PSOC_mem";
4143         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4144                 return "PSOC_coresight";
4145         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4146                 return "SRAM%d";
4147         case GOYA_ASYNC_EVENT_ID_GIC500:
4148                 return "GIC500";
4149         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4150                 return "PLL%d";
4151         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4152                 return "AXI_ecc";
4153         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4154                 return "L2_ram_ecc";
4155         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4156                 return "PSOC_gpio_05_sw_reset";
4157         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4158                 return "PSOC_gpio_10_vrhot_icrit";
4159         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4160                 return "PCIe_dec";
4161         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4162         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4163         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4164         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4165         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4166         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4167         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4168         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4169                 return "TPC%d_dec";
4170         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4171                 return "MME_wacs";
4172         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4173                 return "MME_wacsd";
4174         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4175                 return "CPU_axi_splitter";
4176         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4177                 return "PSOC_axi_dec";
4178         case GOYA_ASYNC_EVENT_ID_PSOC:
4179                 return "PSOC";
4180         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4181         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4182         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4183         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4184         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4185         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4186         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4187         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4188                 return "TPC%d_krn_err";
4189         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4190                 return "TPC%d_cq";
4191         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4192                 return "TPC%d_qm";
4193         case GOYA_ASYNC_EVENT_ID_MME_QM:
4194                 return "MME_qm";
4195         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4196                 return "MME_cq";
4197         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4198                 return "DMA%d_qm";
4199         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4200                 return "DMA%d_ch";
4201         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4202         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4203         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4204         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4205         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4206         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4207         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4208         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4209                 return "TPC%d_bmon_spmu";
4210         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4211                 return "DMA_bm_ch%d";
4212         default:
4213                 return "N/A";
4214         }
4215 }
4216
4217 static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
4218 {
4219         u8 index;
4220
4221         switch (event_type) {
4222         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4223         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4224         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4225         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4226         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4227         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4228         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4229         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4230                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_ECC) / 3;
4231                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4232                 break;
4233         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4234                 index = event_type - GOYA_ASYNC_EVENT_ID_SRAM0;
4235                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4236                 break;
4237         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4238                 index = event_type - GOYA_ASYNC_EVENT_ID_PLL0;
4239                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4240                 break;
4241         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4242         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4243         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4244         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4245         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4246         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4247         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4248         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4249                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3;
4250                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4251                 break;
4252         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4253         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4254         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4255         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4256         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4257         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4258         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4259         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4260                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10;
4261                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4262                 break;
4263         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4264                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ;
4265                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4266                 break;
4267         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4268                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM;
4269                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4270                 break;
4271         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4272                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM;
4273                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4274                 break;
4275         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4276                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH;
4277                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4278                 break;
4279         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4280         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4281         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4282         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4283         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4284         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4285         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4286         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4287                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU) / 10;
4288                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4289                 break;
4290         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4291                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0;
4292                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4293                 break;
4294         default:
4295                 snprintf(desc, size, _goya_get_event_desc(event_type));
4296                 break;
4297         }
4298 }
4299
4300 static void goya_print_razwi_info(struct hl_device *hdev)
4301 {
4302         if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {
4303                 dev_err(hdev->dev, "Illegal write to LBW\n");
4304                 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4305         }
4306
4307         if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {
4308                 dev_err(hdev->dev, "Illegal read from LBW\n");
4309                 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4310         }
4311
4312         if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {
4313                 dev_err(hdev->dev, "Illegal write to HBW\n");
4314                 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4315         }
4316
4317         if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {
4318                 dev_err(hdev->dev, "Illegal read from HBW\n");
4319                 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4320         }
4321 }
4322
4323 static void goya_print_mmu_error_info(struct hl_device *hdev)
4324 {
4325         struct goya_device *goya = hdev->asic_specific;
4326         u64 addr;
4327         u32 val;
4328
4329         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4330                 return;
4331
4332         val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4333         if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4334                 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4335                 addr <<= 32;
4336                 addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);
4337
4338                 dev_err(hdev->dev, "MMU page fault on va 0x%llx\n", addr);
4339
4340                 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4341         }
4342 }
4343
4344 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type,
4345                                 bool razwi)
4346 {
4347         char desc[20] = "";
4348
4349         goya_get_event_desc(event_type, desc, sizeof(desc));
4350         dev_err(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4351                 event_type, desc);
4352
4353         if (razwi) {
4354                 goya_print_razwi_info(hdev);
4355                 goya_print_mmu_error_info(hdev);
4356         }
4357 }
4358
4359 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4360                 size_t irq_arr_size)
4361 {
4362         struct armcp_unmask_irq_arr_packet *pkt;
4363         size_t total_pkt_size;
4364         long result;
4365         int rc;
4366         int irq_num_entries, irq_arr_index;
4367         __le32 *goya_irq_arr;
4368
4369         total_pkt_size = sizeof(struct armcp_unmask_irq_arr_packet) +
4370                         irq_arr_size;
4371
4372         /* data should be aligned to 8 bytes in order to ArmCP to copy it */
4373         total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
4374
4375         /* total_pkt_size is casted to u16 later on */
4376         if (total_pkt_size > USHRT_MAX) {
4377                 dev_err(hdev->dev, "too many elements in IRQ array\n");
4378                 return -EINVAL;
4379         }
4380
4381         pkt = kzalloc(total_pkt_size, GFP_KERNEL);
4382         if (!pkt)
4383                 return -ENOMEM;
4384
4385         irq_num_entries = irq_arr_size / sizeof(irq_arr[0]);
4386         pkt->length = cpu_to_le32(irq_num_entries);
4387
4388         /* We must perform any necessary endianness conversation on the irq
4389          * array being passed to the goya hardware
4390          */
4391         for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs;
4392                         irq_arr_index < irq_num_entries ; irq_arr_index++)
4393                 goya_irq_arr[irq_arr_index] =
4394                                 cpu_to_le32(irq_arr[irq_arr_index]);
4395
4396         pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4397                                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
4398
4399         rc = goya_send_cpu_message(hdev, (u32 *) pkt, total_pkt_size,
4400                         HL_DEVICE_TIMEOUT_USEC, &result);
4401
4402         if (rc)
4403                 dev_err(hdev->dev, "failed to unmask IRQ array\n");
4404
4405         kfree(pkt);
4406
4407         return rc;
4408 }
4409
4410 static int goya_soft_reset_late_init(struct hl_device *hdev)
4411 {
4412         /*
4413          * Unmask all IRQs since some could have been received
4414          * during the soft reset
4415          */
4416         return goya_unmask_irq_arr(hdev, goya_all_events,
4417                                         sizeof(goya_all_events));
4418 }
4419
4420 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4421 {
4422         struct armcp_packet pkt;
4423         long result;
4424         int rc;
4425
4426         memset(&pkt, 0, sizeof(pkt));
4427
4428         pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ <<
4429                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
4430         pkt.value = cpu_to_le64(event_type);
4431
4432         rc = goya_send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4433                         HL_DEVICE_TIMEOUT_USEC, &result);
4434
4435         if (rc)
4436                 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4437
4438         return rc;
4439 }
4440
4441 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4442 {
4443         u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
4444         u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
4445                                 >> EQ_CTL_EVENT_TYPE_SHIFT);
4446         struct goya_device *goya = hdev->asic_specific;
4447
4448         goya->events_stat[event_type]++;
4449
4450         switch (event_type) {
4451         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4452         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4453         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4454         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4455         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4456         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4457         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4458         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4459         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4460         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4461         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4462         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4463         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4464         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4465         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4466         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4467         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4468         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4469         case GOYA_ASYNC_EVENT_ID_GIC500:
4470         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4471         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4472         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4473         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4474                 goya_print_irq_info(hdev, event_type, false);
4475                 hl_device_reset(hdev, true, false);
4476                 break;
4477
4478         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4479         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4480         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4481         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4482         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4483         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4484         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4485         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4486         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4487         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4488         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4489         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4490         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4491         case GOYA_ASYNC_EVENT_ID_PSOC:
4492         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4493         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4494         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4495         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4496         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4497         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4498         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4499         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4500         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4501         case GOYA_ASYNC_EVENT_ID_MME_QM:
4502         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4503         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4504         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4505                 goya_print_irq_info(hdev, event_type, true);
4506                 goya_unmask_irq(hdev, event_type);
4507                 break;
4508
4509         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4510         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4511         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4512         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4513         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4514         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4515         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4516         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4517         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4518         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4519                 goya_print_irq_info(hdev, event_type, false);
4520                 goya_unmask_irq(hdev, event_type);
4521                 break;
4522
4523         default:
4524                 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
4525                                 event_type);
4526                 break;
4527         }
4528 }
4529
4530 void *goya_get_events_stat(struct hl_device *hdev, u32 *size)
4531 {
4532         struct goya_device *goya = hdev->asic_specific;
4533
4534         *size = (u32) sizeof(goya->events_stat);
4535
4536         return goya->events_stat;
4537 }
4538
4539 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
4540                                 u64 val, bool is_dram)
4541 {
4542         struct packet_lin_dma *lin_dma_pkt;
4543         struct hl_cs_job *job;
4544         u32 cb_size, ctl;
4545         struct hl_cb *cb;
4546         int rc, lin_dma_pkts_cnt;
4547
4548         lin_dma_pkts_cnt = DIV_ROUND_UP_ULL(size, SZ_2G);
4549         cb_size = lin_dma_pkts_cnt * sizeof(struct packet_lin_dma) +
4550                                                 sizeof(struct packet_msg_prot);
4551         cb = hl_cb_kernel_create(hdev, cb_size);
4552         if (!cb)
4553                 return -ENOMEM;
4554
4555         lin_dma_pkt = (struct packet_lin_dma *) (uintptr_t) cb->kernel_address;
4556
4557         do {
4558                 memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
4559
4560                 ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) |
4561                                 (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |
4562                                 (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
4563                                 (1 << GOYA_PKT_CTL_RB_SHIFT) |
4564                                 (1 << GOYA_PKT_CTL_MB_SHIFT));
4565                 ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) <<
4566                                 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
4567                 lin_dma_pkt->ctl = cpu_to_le32(ctl);
4568
4569                 lin_dma_pkt->src_addr = cpu_to_le64(val);
4570                 lin_dma_pkt->dst_addr = cpu_to_le64(addr);
4571                 if (lin_dma_pkts_cnt > 1)
4572                         lin_dma_pkt->tsize = cpu_to_le32(SZ_2G);
4573                 else
4574                         lin_dma_pkt->tsize = cpu_to_le32(size);
4575
4576                 size -= SZ_2G;
4577                 addr += SZ_2G;
4578                 lin_dma_pkt++;
4579         } while (--lin_dma_pkts_cnt);
4580
4581         job = hl_cs_allocate_job(hdev, true);
4582         if (!job) {
4583                 dev_err(hdev->dev, "Failed to allocate a new job\n");
4584                 rc = -ENOMEM;
4585                 goto release_cb;
4586         }
4587
4588         job->id = 0;
4589         job->user_cb = cb;
4590         job->user_cb->cs_cnt++;
4591         job->user_cb_size = cb_size;
4592         job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
4593         job->patched_cb = job->user_cb;
4594         job->job_cb_size = job->user_cb_size;
4595
4596         hl_debugfs_add_job(hdev, job);
4597
4598         rc = goya_send_job_on_qman0(hdev, job);
4599
4600         hl_cb_put(job->patched_cb);
4601
4602         hl_debugfs_remove_job(hdev, job);
4603         kfree(job);
4604         cb->cs_cnt--;
4605
4606 release_cb:
4607         hl_cb_put(cb);
4608         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
4609
4610         return rc;
4611 }
4612
4613 int goya_context_switch(struct hl_device *hdev, u32 asid)
4614 {
4615         struct asic_fixed_properties *prop = &hdev->asic_prop;
4616         u64 addr = prop->sram_base_address, sob_addr;
4617         u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
4618         u64 val = 0x7777777777777777ull;
4619         int rc, dma_id;
4620         u32 channel_off = mmDMA_CH_1_WR_COMP_ADDR_LO -
4621                                         mmDMA_CH_0_WR_COMP_ADDR_LO;
4622
4623         rc = goya_memset_device_memory(hdev, addr, size, val, false);
4624         if (rc) {
4625                 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
4626                 return rc;
4627         }
4628
4629         /* we need to reset registers that the user is allowed to change */
4630         sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
4631         WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr));
4632
4633         for (dma_id = 1 ; dma_id < NUMBER_OF_EXT_HW_QUEUES ; dma_id++) {
4634                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
4635                                                         (dma_id - 1) * 4;
4636                 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id,
4637                                                 lower_32_bits(sob_addr));
4638         }
4639
4640         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
4641
4642         goya_mmu_prepare(hdev, asid);
4643
4644         goya_clear_sm_regs(hdev);
4645
4646         return 0;
4647 }
4648
4649 static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
4650 {
4651         struct asic_fixed_properties *prop = &hdev->asic_prop;
4652         struct goya_device *goya = hdev->asic_specific;
4653         u64 addr = prop->mmu_pgt_addr;
4654         u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE +
4655                         MMU_CACHE_MNG_SIZE;
4656
4657         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4658                 return 0;
4659
4660         return goya_memset_device_memory(hdev, addr, size, 0, true);
4661 }
4662
4663 static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
4664 {
4665         struct goya_device *goya = hdev->asic_specific;
4666         u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
4667         u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE;
4668         u64 val = 0x9999999999999999ull;
4669
4670         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4671                 return 0;
4672
4673         return goya_memset_device_memory(hdev, addr, size, val, true);
4674 }
4675
4676 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
4677 {
4678         struct asic_fixed_properties *prop = &hdev->asic_prop;
4679         struct goya_device *goya = hdev->asic_specific;
4680         s64 off, cpu_off;
4681         int rc;
4682
4683         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4684                 return 0;
4685
4686         for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB) {
4687                 rc = hl_mmu_map(hdev->kernel_ctx, prop->dram_base_address + off,
4688                                 prop->dram_base_address + off, PAGE_SIZE_2MB);
4689                 if (rc) {
4690                         dev_err(hdev->dev, "Map failed for address 0x%llx\n",
4691                                 prop->dram_base_address + off);
4692                         goto unmap;
4693                 }
4694         }
4695
4696         if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
4697                 rc = hl_mmu_map(hdev->kernel_ctx, VA_CPU_ACCESSIBLE_MEM_ADDR,
4698                         hdev->cpu_accessible_dma_address, PAGE_SIZE_2MB);
4699
4700                 if (rc) {
4701                         dev_err(hdev->dev,
4702                                 "Map failed for CPU accessible memory\n");
4703                         off -= PAGE_SIZE_2MB;
4704                         goto unmap;
4705                 }
4706         } else {
4707                 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB) {
4708                         rc = hl_mmu_map(hdev->kernel_ctx,
4709                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
4710                                 hdev->cpu_accessible_dma_address + cpu_off,
4711                                 PAGE_SIZE_4KB);
4712                         if (rc) {
4713                                 dev_err(hdev->dev,
4714                                         "Map failed for CPU accessible memory\n");
4715                                 cpu_off -= PAGE_SIZE_4KB;
4716                                 goto unmap_cpu;
4717                         }
4718                 }
4719         }
4720
4721         goya_mmu_prepare_reg(hdev, mmCPU_IF_ARUSER_OVR, HL_KERNEL_ASID_ID);
4722         goya_mmu_prepare_reg(hdev, mmCPU_IF_AWUSER_OVR, HL_KERNEL_ASID_ID);
4723         WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF);
4724         WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF);
4725
4726         /* Make sure configuration is flushed to device */
4727         RREG32(mmCPU_IF_AWUSER_OVR_EN);
4728
4729         goya->device_cpu_mmu_mappings_done = true;
4730
4731         return 0;
4732
4733 unmap_cpu:
4734         for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB)
4735                 if (hl_mmu_unmap(hdev->kernel_ctx,
4736                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
4737                                 PAGE_SIZE_4KB))
4738                         dev_warn_ratelimited(hdev->dev,
4739                                 "failed to unmap address 0x%llx\n",
4740                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
4741 unmap:
4742         for (; off >= 0 ; off -= PAGE_SIZE_2MB)
4743                 if (hl_mmu_unmap(hdev->kernel_ctx,
4744                                 prop->dram_base_address + off, PAGE_SIZE_2MB))
4745                         dev_warn_ratelimited(hdev->dev,
4746                                 "failed to unmap address 0x%llx\n",
4747                                 prop->dram_base_address + off);
4748
4749         return rc;
4750 }
4751
4752 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev)
4753 {
4754         struct asic_fixed_properties *prop = &hdev->asic_prop;
4755         struct goya_device *goya = hdev->asic_specific;
4756         u32 off, cpu_off;
4757
4758         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4759                 return;
4760
4761         if (!goya->device_cpu_mmu_mappings_done)
4762                 return;
4763
4764         WREG32(mmCPU_IF_ARUSER_OVR_EN, 0);
4765         WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
4766
4767         if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
4768                 if (hl_mmu_unmap(hdev->kernel_ctx, VA_CPU_ACCESSIBLE_MEM_ADDR,
4769                                 PAGE_SIZE_2MB))
4770                         dev_warn(hdev->dev,
4771                                 "Failed to unmap CPU accessible memory\n");
4772         } else {
4773                 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB)
4774                         if (hl_mmu_unmap(hdev->kernel_ctx,
4775                                         VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
4776                                         PAGE_SIZE_4KB))
4777                                 dev_warn_ratelimited(hdev->dev,
4778                                         "failed to unmap address 0x%llx\n",
4779                                         VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
4780         }
4781
4782         for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB)
4783                 if (hl_mmu_unmap(hdev->kernel_ctx,
4784                                 prop->dram_base_address + off, PAGE_SIZE_2MB))
4785                         dev_warn_ratelimited(hdev->dev,
4786                                         "Failed to unmap address 0x%llx\n",
4787                                         prop->dram_base_address + off);
4788
4789         goya->device_cpu_mmu_mappings_done = false;
4790 }
4791
4792 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
4793 {
4794         struct goya_device *goya = hdev->asic_specific;
4795         int i;
4796
4797         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4798                 return;
4799
4800         if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
4801                 WARN(1, "asid %u is too big\n", asid);
4802                 return;
4803         }
4804
4805         /* zero the MMBP and ASID bits and then set the ASID */
4806         for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++)
4807                 goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
4808 }
4809
4810 static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard)
4811 {
4812         struct goya_device *goya = hdev->asic_specific;
4813         u32 status, timeout_usec;
4814         int rc;
4815
4816         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4817                 return;
4818
4819         /* no need in L1 only invalidation in Goya */
4820         if (!is_hard)
4821                 return;
4822
4823         if (hdev->pldm)
4824                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
4825         else
4826                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
4827
4828         mutex_lock(&hdev->mmu_cache_lock);
4829
4830         /* L0 & L1 invalidation */
4831         WREG32(mmSTLB_INV_ALL_START, 1);
4832
4833         rc = hl_poll_timeout(
4834                 hdev,
4835                 mmSTLB_INV_ALL_START,
4836                 status,
4837                 !status,
4838                 1000,
4839                 timeout_usec);
4840
4841         mutex_unlock(&hdev->mmu_cache_lock);
4842
4843         if (rc)
4844                 dev_notice_ratelimited(hdev->dev,
4845                         "Timeout when waiting for MMU cache invalidation\n");
4846 }
4847
4848 static void goya_mmu_invalidate_cache_range(struct hl_device *hdev,
4849                 bool is_hard, u32 asid, u64 va, u64 size)
4850 {
4851         struct goya_device *goya = hdev->asic_specific;
4852         u32 status, timeout_usec, inv_data, pi;
4853         int rc;
4854
4855         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4856                 return;
4857
4858         /* no need in L1 only invalidation in Goya */
4859         if (!is_hard)
4860                 return;
4861
4862         if (hdev->pldm)
4863                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
4864         else
4865                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
4866
4867         mutex_lock(&hdev->mmu_cache_lock);
4868
4869         /*
4870          * TODO: currently invalidate entire L0 & L1 as in regular hard
4871          * invalidation. Need to apply invalidation of specific cache lines with
4872          * mask of ASID & VA & size.
4873          * Note that L1 with be flushed entirely in any case.
4874          */
4875
4876         /* L0 & L1 invalidation */
4877         inv_data = RREG32(mmSTLB_CACHE_INV);
4878         /* PI is 8 bit */
4879         pi = ((inv_data & STLB_CACHE_INV_PRODUCER_INDEX_MASK) + 1) & 0xFF;
4880         WREG32(mmSTLB_CACHE_INV,
4881                         (inv_data & STLB_CACHE_INV_INDEX_MASK_MASK) | pi);
4882
4883         rc = hl_poll_timeout(
4884                 hdev,
4885                 mmSTLB_INV_CONSUMER_INDEX,
4886                 status,
4887                 status == pi,
4888                 1000,
4889                 timeout_usec);
4890
4891         mutex_unlock(&hdev->mmu_cache_lock);
4892
4893         if (rc)
4894                 dev_notice_ratelimited(hdev->dev,
4895                         "Timeout when waiting for MMU cache invalidation\n");
4896 }
4897
4898 int goya_send_heartbeat(struct hl_device *hdev)
4899 {
4900         struct goya_device *goya = hdev->asic_specific;
4901
4902         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
4903                 return 0;
4904
4905         return hl_fw_send_heartbeat(hdev);
4906 }
4907
4908 int goya_armcp_info_get(struct hl_device *hdev)
4909 {
4910         struct goya_device *goya = hdev->asic_specific;
4911         struct asic_fixed_properties *prop = &hdev->asic_prop;
4912         u64 dram_size;
4913         int rc;
4914
4915         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
4916                 return 0;
4917
4918         rc = hl_fw_armcp_info_get(hdev);
4919         if (rc)
4920                 return rc;
4921
4922         dram_size = le64_to_cpu(prop->armcp_info.dram_size);
4923         if (dram_size) {
4924                 if ((!is_power_of_2(dram_size)) ||
4925                                 (dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
4926                         dev_err(hdev->dev,
4927                                 "F/W reported invalid DRAM size %llu. Trying to use default size\n",
4928                                 dram_size);
4929                         dram_size = DRAM_PHYS_DEFAULT_SIZE;
4930                 }
4931
4932                 prop->dram_size = dram_size;
4933                 prop->dram_end_address = prop->dram_base_address + dram_size;
4934         }
4935
4936         return 0;
4937 }
4938
4939 static bool goya_is_device_idle(struct hl_device *hdev, u32 *mask,
4940                                 struct seq_file *s)
4941 {
4942         const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n";
4943         const char *dma_fmt = "%-5d%-9s%#-14x%#x\n";
4944         u32 qm_glbl_sts0, cmdq_glbl_sts0, dma_core_sts0, tpc_cfg_sts,
4945                 mme_arch_sts;
4946         bool is_idle = true, is_eng_idle;
4947         u64 offset;
4948         int i;
4949
4950         if (s)
4951                 seq_puts(s, "\nDMA  is_idle  QM_GLBL_STS0  DMA_CORE_STS0\n"
4952                                 "---  -------  ------------  -------------\n");
4953
4954         offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
4955
4956         for (i = 0 ; i < DMA_MAX_NUM ; i++) {
4957                 qm_glbl_sts0 = RREG32(mmDMA_QM_0_GLBL_STS0 + i * offset);
4958                 dma_core_sts0 = RREG32(mmDMA_CH_0_STS0 + i * offset);
4959                 is_eng_idle = IS_DMA_QM_IDLE(qm_glbl_sts0) &&
4960                                 IS_DMA_IDLE(dma_core_sts0);
4961                 is_idle &= is_eng_idle;
4962
4963                 if (mask)
4964                         *mask |= !is_eng_idle << (GOYA_ENGINE_ID_DMA_0 + i);
4965                 if (s)
4966                         seq_printf(s, dma_fmt, i, is_eng_idle ? "Y" : "N",
4967                                         qm_glbl_sts0, dma_core_sts0);
4968         }
4969
4970         if (s)
4971                 seq_puts(s,
4972                         "\nTPC  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  CFG_STATUS\n"
4973                         "---  -------  ------------  --------------  ----------\n");
4974
4975         offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
4976
4977         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
4978                 qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + i * offset);
4979                 cmdq_glbl_sts0 = RREG32(mmTPC0_CMDQ_GLBL_STS0 + i * offset);
4980                 tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + i * offset);
4981                 is_eng_idle = IS_TPC_QM_IDLE(qm_glbl_sts0) &&
4982                                 IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) &&
4983                                 IS_TPC_IDLE(tpc_cfg_sts);
4984                 is_idle &= is_eng_idle;
4985
4986                 if (mask)
4987                         *mask |= !is_eng_idle << (GOYA_ENGINE_ID_TPC_0 + i);
4988                 if (s)
4989                         seq_printf(s, fmt, i, is_eng_idle ? "Y" : "N",
4990                                 qm_glbl_sts0, cmdq_glbl_sts0, tpc_cfg_sts);
4991         }
4992
4993         if (s)
4994                 seq_puts(s,
4995                         "\nMME  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  ARCH_STATUS\n"
4996                         "---  -------  ------------  --------------  -----------\n");
4997
4998         qm_glbl_sts0 = RREG32(mmMME_QM_GLBL_STS0);
4999         cmdq_glbl_sts0 = RREG32(mmMME_CMDQ_GLBL_STS0);
5000         mme_arch_sts = RREG32(mmMME_ARCH_STATUS);
5001         is_eng_idle = IS_MME_QM_IDLE(qm_glbl_sts0) &&
5002                         IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) &&
5003                         IS_MME_IDLE(mme_arch_sts);
5004         is_idle &= is_eng_idle;
5005
5006         if (mask)
5007                 *mask |= !is_eng_idle << GOYA_ENGINE_ID_MME_0;
5008         if (s) {
5009                 seq_printf(s, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0,
5010                                 cmdq_glbl_sts0, mme_arch_sts);
5011                 seq_puts(s, "\n");
5012         }
5013
5014         return is_idle;
5015 }
5016
5017 static void goya_hw_queues_lock(struct hl_device *hdev)
5018 {
5019         struct goya_device *goya = hdev->asic_specific;
5020
5021         spin_lock(&goya->hw_queues_lock);
5022 }
5023
5024 static void goya_hw_queues_unlock(struct hl_device *hdev)
5025 {
5026         struct goya_device *goya = hdev->asic_specific;
5027
5028         spin_unlock(&goya->hw_queues_lock);
5029 }
5030
5031 static u32 goya_get_pci_id(struct hl_device *hdev)
5032 {
5033         return hdev->pdev->device;
5034 }
5035
5036 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
5037                                 size_t max_size)
5038 {
5039         struct goya_device *goya = hdev->asic_specific;
5040
5041         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5042                 return 0;
5043
5044         return hl_fw_get_eeprom_data(hdev, data, max_size);
5045 }
5046
5047 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
5048 {
5049         return RREG32(mmHW_STATE);
5050 }
5051
5052 static const struct hl_asic_funcs goya_funcs = {
5053         .early_init = goya_early_init,
5054         .early_fini = goya_early_fini,
5055         .late_init = goya_late_init,
5056         .late_fini = goya_late_fini,
5057         .sw_init = goya_sw_init,
5058         .sw_fini = goya_sw_fini,
5059         .hw_init = goya_hw_init,
5060         .hw_fini = goya_hw_fini,
5061         .halt_engines = goya_halt_engines,
5062         .suspend = goya_suspend,
5063         .resume = goya_resume,
5064         .cb_mmap = goya_cb_mmap,
5065         .ring_doorbell = goya_ring_doorbell,
5066         .pqe_write = goya_pqe_write,
5067         .asic_dma_alloc_coherent = goya_dma_alloc_coherent,
5068         .asic_dma_free_coherent = goya_dma_free_coherent,
5069         .get_int_queue_base = goya_get_int_queue_base,
5070         .test_queues = goya_test_queues,
5071         .asic_dma_pool_zalloc = goya_dma_pool_zalloc,
5072         .asic_dma_pool_free = goya_dma_pool_free,
5073         .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
5074         .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
5075         .hl_dma_unmap_sg = goya_dma_unmap_sg,
5076         .cs_parser = goya_cs_parser,
5077         .asic_dma_map_sg = goya_dma_map_sg,
5078         .get_dma_desc_list_size = goya_get_dma_desc_list_size,
5079         .add_end_of_cb_packets = goya_add_end_of_cb_packets,
5080         .update_eq_ci = goya_update_eq_ci,
5081         .context_switch = goya_context_switch,
5082         .restore_phase_topology = goya_restore_phase_topology,
5083         .debugfs_read32 = goya_debugfs_read32,
5084         .debugfs_write32 = goya_debugfs_write32,
5085         .add_device_attr = goya_add_device_attr,
5086         .handle_eqe = goya_handle_eqe,
5087         .set_pll_profile = goya_set_pll_profile,
5088         .get_events_stat = goya_get_events_stat,
5089         .read_pte = goya_read_pte,
5090         .write_pte = goya_write_pte,
5091         .mmu_invalidate_cache = goya_mmu_invalidate_cache,
5092         .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
5093         .send_heartbeat = goya_send_heartbeat,
5094         .debug_coresight = goya_debug_coresight,
5095         .is_device_idle = goya_is_device_idle,
5096         .soft_reset_late_init = goya_soft_reset_late_init,
5097         .hw_queues_lock = goya_hw_queues_lock,
5098         .hw_queues_unlock = goya_hw_queues_unlock,
5099         .get_pci_id = goya_get_pci_id,
5100         .get_eeprom_data = goya_get_eeprom_data,
5101         .send_cpu_message = goya_send_cpu_message,
5102         .get_hw_state = goya_get_hw_state,
5103         .pci_bars_map = goya_pci_bars_map,
5104         .set_dram_bar_base = goya_set_ddr_bar_base,
5105         .init_iatu = goya_init_iatu,
5106         .rreg = hl_rreg,
5107         .wreg = hl_wreg,
5108         .halt_coresight = goya_halt_coresight
5109 };
5110
5111 /*
5112  * goya_set_asic_funcs - set Goya function pointers
5113  *
5114  * @*hdev: pointer to hl_device structure
5115  *
5116  */
5117 void goya_set_asic_funcs(struct hl_device *hdev)
5118 {
5119         hdev->asic_funcs = &goya_funcs;
5120 }