drivers/misc/habanalabs/goya/goya.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * Copyright 2016-2019 HabanaLabs, Ltd.
   5  * All Rights Reserved.
   6  */
   7
   8 #include "goyaP.h"
   9 #include "../include/hw_ip/mmu/mmu_general.h"
  10 #include "../include/hw_ip/mmu/mmu_v1_0.h"
  11 #include "../include/goya/asic_reg/goya_masks.h"
  12 #include "../include/goya/goya_reg_map.h"
  13
  14 #include <linux/pci.h>
  15 #include <linux/hwmon.h>
  16 #include <linux/iommu.h>
  17 #include <linux/seq_file.h>
  18
  19 /*
  20  * GOYA security scheme:
  21  *
  22  * 1. Host is protected by:
  23  *        - Range registers (When MMU is enabled, DMA RR does NOT protect host)
  24  *        - MMU
  25  *
  26  * 2. DRAM is protected by:
  27  *        - Range registers (protect the first 512MB)
  28  *        - MMU (isolation between users)
  29  *
  30  * 3. Configuration is protected by:
  31  *        - Range registers
  32  *        - Protection bits
  33  *
  34  * When MMU is disabled:
  35  *
  36  * QMAN DMA: PQ, CQ, CP, DMA are secured.
  37  * PQ, CB and the data are on the host.
  38  *
  39  * QMAN TPC/MME:
  40  * PQ, CQ and CP are not secured.
  41  * PQ, CB and the data are on the SRAM/DRAM.
  42  *
  43  * Since QMAN DMA is secured, the driver is parsing the DMA CB:
  44  *     - checks DMA pointer
  45  *     - WREG, MSG_PROT are not allowed.
  46  *     - MSG_LONG/SHORT are allowed.
  47  *
  48  * A read/write transaction by the QMAN to a protected area will succeed if
  49  * and only if the QMAN's CP is secured and MSG_PROT is used
  50  *
  51  *
  52  * When MMU is enabled:
  53  *
  54  * QMAN DMA: PQ, CQ and CP are secured.
  55  * MMU is set to bypass on the Secure props register of the QMAN.
  56  * The reasons we don't enable MMU for PQ, CQ and CP are:
  57  *     - PQ entry is in kernel address space and the driver doesn't map it.
  58  *     - CP writes to MSIX register and to kernel address space (completion
  59  *       queue).
  60  *
  61  * DMA is not secured but because CP is secured, the driver still needs to parse
  62  * the CB, but doesn't need to check the DMA addresses.
  63  *
  64  * For QMAN DMA 0, DMA is also secured because only the driver uses this DMA and
  65  * the driver doesn't map memory in MMU.
  66  *
  67  * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode)
  68  *
  69  * DMA RR does NOT protect host because DMA is not secured
  70  *
  71  */
  72
  73 #define GOYA_BOOT_FIT_FILE      "habanalabs/goya/goya-boot-fit.itb"
  74 #define GOYA_LINUX_FW_FILE      "habanalabs/goya/goya-fit.itb"
  75
  76 #define GOYA_MMU_REGS_NUM               63
  77
  78 #define GOYA_DMA_POOL_BLK_SIZE          0x100           /* 256 bytes */
  79
  80 #define GOYA_RESET_TIMEOUT_MSEC         500             /* 500ms */
  81 #define GOYA_PLDM_RESET_TIMEOUT_MSEC    20000           /* 20s */
  82 #define GOYA_RESET_WAIT_MSEC            1               /* 1ms */
  83 #define GOYA_CPU_RESET_WAIT_MSEC        100             /* 100ms */
  84 #define GOYA_PLDM_RESET_WAIT_MSEC       1000            /* 1s */
  85 #define GOYA_TEST_QUEUE_WAIT_USEC       100000          /* 100ms */
  86 #define GOYA_PLDM_MMU_TIMEOUT_USEC      (MMU_CONFIG_TIMEOUT_USEC * 100)
  87 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC    (HL_DEVICE_TIMEOUT_USEC * 30)
  88 #define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC  1000000         /* 1s */
  89 #define GOYA_MSG_TO_CPU_TIMEOUT_USEC    4000000         /* 4s */
  90 #define GOYA_WAIT_FOR_BL_TIMEOUT_USEC   15000000        /* 15s */
  91
  92 #define GOYA_QMAN0_FENCE_VAL            0xD169B243
  93
  94 #define GOYA_MAX_STRING_LEN             20
  95
  96 #define GOYA_CB_POOL_CB_CNT             512
  97 #define GOYA_CB_POOL_CB_SIZE            0x20000         /* 128KB */
  98
  99 #define IS_QM_IDLE(engine, qm_glbl_sts0) \
 100         (((qm_glbl_sts0) & engine##_QM_IDLE_MASK) == engine##_QM_IDLE_MASK)
 101 #define IS_DMA_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(DMA, qm_glbl_sts0)
 102 #define IS_TPC_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(TPC, qm_glbl_sts0)
 103 #define IS_MME_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(MME, qm_glbl_sts0)
 104
 105 #define IS_CMDQ_IDLE(engine, cmdq_glbl_sts0) \
 106         (((cmdq_glbl_sts0) & engine##_CMDQ_IDLE_MASK) == \
 107                         engine##_CMDQ_IDLE_MASK)
 108 #define IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) \
 109         IS_CMDQ_IDLE(TPC, cmdq_glbl_sts0)
 110 #define IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) \
 111         IS_CMDQ_IDLE(MME, cmdq_glbl_sts0)
 112
 113 #define IS_DMA_IDLE(dma_core_sts0) \
 114         !((dma_core_sts0) & DMA_CH_0_STS0_DMA_BUSY_MASK)
 115
 116 #define IS_TPC_IDLE(tpc_cfg_sts) \
 117         (((tpc_cfg_sts) & TPC_CFG_IDLE_MASK) == TPC_CFG_IDLE_MASK)
 118
 119 #define IS_MME_IDLE(mme_arch_sts) \
 120         (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
 121
 122 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
 123                 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
 124                 "goya cq 4", "goya cpu eq"
 125 };
 126
 127 static u16 goya_packet_sizes[MAX_PACKET_ID] = {
 128         [PACKET_WREG_32]        = sizeof(struct packet_wreg32),
 129         [PACKET_WREG_BULK]      = sizeof(struct packet_wreg_bulk),
 130         [PACKET_MSG_LONG]       = sizeof(struct packet_msg_long),
 131         [PACKET_MSG_SHORT]      = sizeof(struct packet_msg_short),
 132         [PACKET_CP_DMA]         = sizeof(struct packet_cp_dma),
 133         [PACKET_MSG_PROT]       = sizeof(struct packet_msg_prot),
 134         [PACKET_FENCE]          = sizeof(struct packet_fence),
 135         [PACKET_LIN_DMA]        = sizeof(struct packet_lin_dma),
 136         [PACKET_NOP]            = sizeof(struct packet_nop),
 137         [PACKET_STOP]           = sizeof(struct packet_stop)
 138 };
 139
 140 static inline bool validate_packet_id(enum packet_id id)
 141 {
 142         switch (id) {
 143         case PACKET_WREG_32:
 144         case PACKET_WREG_BULK:
 145         case PACKET_MSG_LONG:
 146         case PACKET_MSG_SHORT:
 147         case PACKET_CP_DMA:
 148         case PACKET_MSG_PROT:
 149         case PACKET_FENCE:
 150         case PACKET_LIN_DMA:
 151         case PACKET_NOP:
 152         case PACKET_STOP:
 153                 return true;
 154         default:
 155                 return false;
 156         }
 157 }
 158
 159 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
 160         mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
 161         mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
 162         mmDMA_QM_2_GLBL_NON_SECURE_PROPS,
 163         mmDMA_QM_3_GLBL_NON_SECURE_PROPS,
 164         mmDMA_QM_4_GLBL_NON_SECURE_PROPS,
 165         mmTPC0_QM_GLBL_SECURE_PROPS,
 166         mmTPC0_QM_GLBL_NON_SECURE_PROPS,
 167         mmTPC0_CMDQ_GLBL_SECURE_PROPS,
 168         mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS,
 169         mmTPC0_CFG_ARUSER,
 170         mmTPC0_CFG_AWUSER,
 171         mmTPC1_QM_GLBL_SECURE_PROPS,
 172         mmTPC1_QM_GLBL_NON_SECURE_PROPS,
 173         mmTPC1_CMDQ_GLBL_SECURE_PROPS,
 174         mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS,
 175         mmTPC1_CFG_ARUSER,
 176         mmTPC1_CFG_AWUSER,
 177         mmTPC2_QM_GLBL_SECURE_PROPS,
 178         mmTPC2_QM_GLBL_NON_SECURE_PROPS,
 179         mmTPC2_CMDQ_GLBL_SECURE_PROPS,
 180         mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS,
 181         mmTPC2_CFG_ARUSER,
 182         mmTPC2_CFG_AWUSER,
 183         mmTPC3_QM_GLBL_SECURE_PROPS,
 184         mmTPC3_QM_GLBL_NON_SECURE_PROPS,
 185         mmTPC3_CMDQ_GLBL_SECURE_PROPS,
 186         mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS,
 187         mmTPC3_CFG_ARUSER,
 188         mmTPC3_CFG_AWUSER,
 189         mmTPC4_QM_GLBL_SECURE_PROPS,
 190         mmTPC4_QM_GLBL_NON_SECURE_PROPS,
 191         mmTPC4_CMDQ_GLBL_SECURE_PROPS,
 192         mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS,
 193         mmTPC4_CFG_ARUSER,
 194         mmTPC4_CFG_AWUSER,
 195         mmTPC5_QM_GLBL_SECURE_PROPS,
 196         mmTPC5_QM_GLBL_NON_SECURE_PROPS,
 197         mmTPC5_CMDQ_GLBL_SECURE_PROPS,
 198         mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS,
 199         mmTPC5_CFG_ARUSER,
 200         mmTPC5_CFG_AWUSER,
 201         mmTPC6_QM_GLBL_SECURE_PROPS,
 202         mmTPC6_QM_GLBL_NON_SECURE_PROPS,
 203         mmTPC6_CMDQ_GLBL_SECURE_PROPS,
 204         mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS,
 205         mmTPC6_CFG_ARUSER,
 206         mmTPC6_CFG_AWUSER,
 207         mmTPC7_QM_GLBL_SECURE_PROPS,
 208         mmTPC7_QM_GLBL_NON_SECURE_PROPS,
 209         mmTPC7_CMDQ_GLBL_SECURE_PROPS,
 210         mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS,
 211         mmTPC7_CFG_ARUSER,
 212         mmTPC7_CFG_AWUSER,
 213         mmMME_QM_GLBL_SECURE_PROPS,
 214         mmMME_QM_GLBL_NON_SECURE_PROPS,
 215         mmMME_CMDQ_GLBL_SECURE_PROPS,
 216         mmMME_CMDQ_GLBL_NON_SECURE_PROPS,
 217         mmMME_SBA_CONTROL_DATA,
 218         mmMME_SBB_CONTROL_DATA,
 219         mmMME_SBC_CONTROL_DATA,
 220         mmMME_WBC_CONTROL_DATA,
 221         mmPCIE_WRAP_PSOC_ARUSER,
 222         mmPCIE_WRAP_PSOC_AWUSER
 223 };
 224
 225 static u32 goya_all_events[] = {
 226         GOYA_ASYNC_EVENT_ID_PCIE_IF,
 227         GOYA_ASYNC_EVENT_ID_TPC0_ECC,
 228         GOYA_ASYNC_EVENT_ID_TPC1_ECC,
 229         GOYA_ASYNC_EVENT_ID_TPC2_ECC,
 230         GOYA_ASYNC_EVENT_ID_TPC3_ECC,
 231         GOYA_ASYNC_EVENT_ID_TPC4_ECC,
 232         GOYA_ASYNC_EVENT_ID_TPC5_ECC,
 233         GOYA_ASYNC_EVENT_ID_TPC6_ECC,
 234         GOYA_ASYNC_EVENT_ID_TPC7_ECC,
 235         GOYA_ASYNC_EVENT_ID_MME_ECC,
 236         GOYA_ASYNC_EVENT_ID_MME_ECC_EXT,
 237         GOYA_ASYNC_EVENT_ID_MMU_ECC,
 238         GOYA_ASYNC_EVENT_ID_DMA_MACRO,
 239         GOYA_ASYNC_EVENT_ID_DMA_ECC,
 240         GOYA_ASYNC_EVENT_ID_CPU_IF_ECC,
 241         GOYA_ASYNC_EVENT_ID_PSOC_MEM,
 242         GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT,
 243         GOYA_ASYNC_EVENT_ID_SRAM0,
 244         GOYA_ASYNC_EVENT_ID_SRAM1,
 245         GOYA_ASYNC_EVENT_ID_SRAM2,
 246         GOYA_ASYNC_EVENT_ID_SRAM3,
 247         GOYA_ASYNC_EVENT_ID_SRAM4,
 248         GOYA_ASYNC_EVENT_ID_SRAM5,
 249         GOYA_ASYNC_EVENT_ID_SRAM6,
 250         GOYA_ASYNC_EVENT_ID_SRAM7,
 251         GOYA_ASYNC_EVENT_ID_SRAM8,
 252         GOYA_ASYNC_EVENT_ID_SRAM9,
 253         GOYA_ASYNC_EVENT_ID_SRAM10,
 254         GOYA_ASYNC_EVENT_ID_SRAM11,
 255         GOYA_ASYNC_EVENT_ID_SRAM12,
 256         GOYA_ASYNC_EVENT_ID_SRAM13,
 257         GOYA_ASYNC_EVENT_ID_SRAM14,
 258         GOYA_ASYNC_EVENT_ID_SRAM15,
 259         GOYA_ASYNC_EVENT_ID_SRAM16,
 260         GOYA_ASYNC_EVENT_ID_SRAM17,
 261         GOYA_ASYNC_EVENT_ID_SRAM18,
 262         GOYA_ASYNC_EVENT_ID_SRAM19,
 263         GOYA_ASYNC_EVENT_ID_SRAM20,
 264         GOYA_ASYNC_EVENT_ID_SRAM21,
 265         GOYA_ASYNC_EVENT_ID_SRAM22,
 266         GOYA_ASYNC_EVENT_ID_SRAM23,
 267         GOYA_ASYNC_EVENT_ID_SRAM24,
 268         GOYA_ASYNC_EVENT_ID_SRAM25,
 269         GOYA_ASYNC_EVENT_ID_SRAM26,
 270         GOYA_ASYNC_EVENT_ID_SRAM27,
 271         GOYA_ASYNC_EVENT_ID_SRAM28,
 272         GOYA_ASYNC_EVENT_ID_SRAM29,
 273         GOYA_ASYNC_EVENT_ID_GIC500,
 274         GOYA_ASYNC_EVENT_ID_PLL0,
 275         GOYA_ASYNC_EVENT_ID_PLL1,
 276         GOYA_ASYNC_EVENT_ID_PLL3,
 277         GOYA_ASYNC_EVENT_ID_PLL4,
 278         GOYA_ASYNC_EVENT_ID_PLL5,
 279         GOYA_ASYNC_EVENT_ID_PLL6,
 280         GOYA_ASYNC_EVENT_ID_AXI_ECC,
 281         GOYA_ASYNC_EVENT_ID_L2_RAM_ECC,
 282         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET,
 283         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT,
 284         GOYA_ASYNC_EVENT_ID_PCIE_DEC,
 285         GOYA_ASYNC_EVENT_ID_TPC0_DEC,
 286         GOYA_ASYNC_EVENT_ID_TPC1_DEC,
 287         GOYA_ASYNC_EVENT_ID_TPC2_DEC,
 288         GOYA_ASYNC_EVENT_ID_TPC3_DEC,
 289         GOYA_ASYNC_EVENT_ID_TPC4_DEC,
 290         GOYA_ASYNC_EVENT_ID_TPC5_DEC,
 291         GOYA_ASYNC_EVENT_ID_TPC6_DEC,
 292         GOYA_ASYNC_EVENT_ID_TPC7_DEC,
 293         GOYA_ASYNC_EVENT_ID_MME_WACS,
 294         GOYA_ASYNC_EVENT_ID_MME_WACSD,
 295         GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER,
 296         GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC,
 297         GOYA_ASYNC_EVENT_ID_PSOC,
 298         GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR,
 299         GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR,
 300         GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR,
 301         GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR,
 302         GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR,
 303         GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR,
 304         GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR,
 305         GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR,
 306         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ,
 307         GOYA_ASYNC_EVENT_ID_TPC1_CMDQ,
 308         GOYA_ASYNC_EVENT_ID_TPC2_CMDQ,
 309         GOYA_ASYNC_EVENT_ID_TPC3_CMDQ,
 310         GOYA_ASYNC_EVENT_ID_TPC4_CMDQ,
 311         GOYA_ASYNC_EVENT_ID_TPC5_CMDQ,
 312         GOYA_ASYNC_EVENT_ID_TPC6_CMDQ,
 313         GOYA_ASYNC_EVENT_ID_TPC7_CMDQ,
 314         GOYA_ASYNC_EVENT_ID_TPC0_QM,
 315         GOYA_ASYNC_EVENT_ID_TPC1_QM,
 316         GOYA_ASYNC_EVENT_ID_TPC2_QM,
 317         GOYA_ASYNC_EVENT_ID_TPC3_QM,
 318         GOYA_ASYNC_EVENT_ID_TPC4_QM,
 319         GOYA_ASYNC_EVENT_ID_TPC5_QM,
 320         GOYA_ASYNC_EVENT_ID_TPC6_QM,
 321         GOYA_ASYNC_EVENT_ID_TPC7_QM,
 322         GOYA_ASYNC_EVENT_ID_MME_QM,
 323         GOYA_ASYNC_EVENT_ID_MME_CMDQ,
 324         GOYA_ASYNC_EVENT_ID_DMA0_QM,
 325         GOYA_ASYNC_EVENT_ID_DMA1_QM,
 326         GOYA_ASYNC_EVENT_ID_DMA2_QM,
 327         GOYA_ASYNC_EVENT_ID_DMA3_QM,
 328         GOYA_ASYNC_EVENT_ID_DMA4_QM,
 329         GOYA_ASYNC_EVENT_ID_DMA0_CH,
 330         GOYA_ASYNC_EVENT_ID_DMA1_CH,
 331         GOYA_ASYNC_EVENT_ID_DMA2_CH,
 332         GOYA_ASYNC_EVENT_ID_DMA3_CH,
 333         GOYA_ASYNC_EVENT_ID_DMA4_CH,
 334         GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU,
 335         GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU,
 336         GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU,
 337         GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU,
 338         GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU,
 339         GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU,
 340         GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU,
 341         GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU,
 342         GOYA_ASYNC_EVENT_ID_DMA_BM_CH0,
 343         GOYA_ASYNC_EVENT_ID_DMA_BM_CH1,
 344         GOYA_ASYNC_EVENT_ID_DMA_BM_CH2,
 345         GOYA_ASYNC_EVENT_ID_DMA_BM_CH3,
 346         GOYA_ASYNC_EVENT_ID_DMA_BM_CH4,
 347         GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S,
 348         GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E,
 349         GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S,
 350         GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E
 351 };
 352
 353 static s64 goya_state_dump_specs_props[SP_MAX] = {0};
 354
 355 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
 356 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
 357 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev);
 358 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
 359
 360 int goya_set_fixed_properties(struct hl_device *hdev)
 361 {
 362         struct asic_fixed_properties *prop = &hdev->asic_prop;
 363         int i;
 364
 365         prop->max_queues = GOYA_QUEUE_ID_SIZE;
 366         prop->hw_queues_props = kcalloc(prop->max_queues,
 367                         sizeof(struct hw_queue_properties),
 368                         GFP_KERNEL);
 369
 370         if (!prop->hw_queues_props)
 371                 return -ENOMEM;
 372
 373         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
 374                 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
 375                 prop->hw_queues_props[i].driver_only = 0;
 376                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
 377         }
 378
 379         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
 380                 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
 381                 prop->hw_queues_props[i].driver_only = 1;
 382                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
 383         }
 384
 385         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
 386                         NUMBER_OF_INT_HW_QUEUES; i++) {
 387                 prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
 388                 prop->hw_queues_props[i].driver_only = 0;
 389                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER;
 390         }
 391
 392         prop->device_dma_offset_for_host_access = HOST_PHYS_BASE;
 393         prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
 394
 395         prop->dram_base_address = DRAM_PHYS_BASE;
 396         prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
 397         prop->dram_end_address = prop->dram_base_address + prop->dram_size;
 398         prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
 399
 400         prop->sram_base_address = SRAM_BASE_ADDR;
 401         prop->sram_size = SRAM_SIZE;
 402         prop->sram_end_address = prop->sram_base_address + prop->sram_size;
 403         prop->sram_user_base_address = prop->sram_base_address +
 404                                                 SRAM_USER_BASE_OFFSET;
 405
 406         prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
 407         prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR;
 408         if (hdev->pldm)
 409                 prop->mmu_pgt_size = 0x800000; /* 8MB */
 410         else
 411                 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
 412         prop->mmu_pte_size = HL_PTE_SIZE;
 413         prop->mmu_hop_table_size = HOP_TABLE_SIZE;
 414         prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
 415         prop->dram_page_size = PAGE_SIZE_2MB;
 416         prop->dram_supports_virtual_memory = true;
 417
 418         prop->dmmu.hop0_shift = HOP0_SHIFT;
 419         prop->dmmu.hop1_shift = HOP1_SHIFT;
 420         prop->dmmu.hop2_shift = HOP2_SHIFT;
 421         prop->dmmu.hop3_shift = HOP3_SHIFT;
 422         prop->dmmu.hop4_shift = HOP4_SHIFT;
 423         prop->dmmu.hop0_mask = HOP0_MASK;
 424         prop->dmmu.hop1_mask = HOP1_MASK;
 425         prop->dmmu.hop2_mask = HOP2_MASK;
 426         prop->dmmu.hop3_mask = HOP3_MASK;
 427         prop->dmmu.hop4_mask = HOP4_MASK;
 428         prop->dmmu.start_addr = VA_DDR_SPACE_START;
 429         prop->dmmu.end_addr = VA_DDR_SPACE_END;
 430         prop->dmmu.page_size = PAGE_SIZE_2MB;
 431         prop->dmmu.num_hops = MMU_ARCH_5_HOPS;
 432         prop->dmmu.last_mask = LAST_MASK;
 433
 434         /* shifts and masks are the same in PMMU and DMMU */
 435         memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu));
 436         prop->pmmu.start_addr = VA_HOST_SPACE_START;
 437         prop->pmmu.end_addr = VA_HOST_SPACE_END;
 438         prop->pmmu.page_size = PAGE_SIZE_4KB;
 439         prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
 440         prop->pmmu.last_mask = LAST_MASK;
 441
 442         /* PMMU and HPMMU are the same except of page size */
 443         memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
 444         prop->pmmu_huge.page_size = PAGE_SIZE_2MB;
 445
 446         prop->dram_size_for_default_page_mapping = VA_DDR_SPACE_END;
 447         prop->cfg_size = CFG_SIZE;
 448         prop->max_asid = MAX_ASID;
 449         prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
 450         prop->high_pll = PLL_HIGH_DEFAULT;
 451         prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
 452         prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
 453         prop->max_power_default = MAX_POWER_DEFAULT;
 454         prop->dc_power_default = DC_POWER_DEFAULT;
 455         prop->tpc_enabled_mask = TPC_ENABLED_MASK;
 456         prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
 457         prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
 458
 459         strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
 460                 CARD_NAME_MAX_LEN);
 461
 462         prop->max_pending_cs = GOYA_MAX_PENDING_CS;
 463
 464         prop->first_available_user_msix_interrupt = USHRT_MAX;
 465
 466         for (i = 0 ; i < HL_MAX_DCORES ; i++)
 467                 prop->first_available_cq[i] = USHRT_MAX;
 468
 469         prop->fw_cpu_boot_dev_sts0_valid = false;
 470         prop->fw_cpu_boot_dev_sts1_valid = false;
 471         prop->hard_reset_done_by_fw = false;
 472         prop->gic_interrupts_enable = true;
 473
 474         prop->server_type = HL_SERVER_TYPE_UNKNOWN;
 475
 476         prop->clk_pll_index = HL_GOYA_MME_PLL;
 477
 478         return 0;
 479 }
 480
 481 /*
 482  * goya_pci_bars_map - Map PCI BARS of Goya device
 483  *
 484  * @hdev: pointer to hl_device structure
 485  *
 486  * Request PCI regions and map them to kernel virtual addresses.
 487  * Returns 0 on success
 488  *
 489  */
 490 static int goya_pci_bars_map(struct hl_device *hdev)
 491 {
 492         static const char * const name[] = {"SRAM_CFG", "MSIX", "DDR"};
 493         bool is_wc[3] = {false, false, true};
 494         int rc;
 495
 496         rc = hl_pci_bars_map(hdev, name, is_wc);
 497         if (rc)
 498                 return rc;
 499
 500         hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
 501                         (CFG_BASE - SRAM_BASE_ADDR);
 502
 503         return 0;
 504 }
 505
 506 static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
 507 {
 508         struct goya_device *goya = hdev->asic_specific;
 509         struct hl_inbound_pci_region pci_region;
 510         u64 old_addr = addr;
 511         int rc;
 512
 513         if ((goya) && (goya->ddr_bar_cur_addr == addr))
 514                 return old_addr;
 515
 516         /* Inbound Region 1 - Bar 4 - Point to DDR */
 517         pci_region.mode = PCI_BAR_MATCH_MODE;
 518         pci_region.bar = DDR_BAR_ID;
 519         pci_region.addr = addr;
 520         rc = hl_pci_set_inbound_region(hdev, 1, &pci_region);
 521         if (rc)
 522                 return U64_MAX;
 523
 524         if (goya) {
 525                 old_addr = goya->ddr_bar_cur_addr;
 526                 goya->ddr_bar_cur_addr = addr;
 527         }
 528
 529         return old_addr;
 530 }
 531
 532 /*
 533  * goya_init_iatu - Initialize the iATU unit inside the PCI controller
 534  *
 535  * @hdev: pointer to hl_device structure
 536  *
 537  * This is needed in case the firmware doesn't initialize the iATU
 538  *
 539  */
 540 static int goya_init_iatu(struct hl_device *hdev)
 541 {
 542         struct hl_inbound_pci_region inbound_region;
 543         struct hl_outbound_pci_region outbound_region;
 544         int rc;
 545
 546         if (hdev->asic_prop.iatu_done_by_fw)
 547                 return 0;
 548
 549         /* Inbound Region 0 - Bar 0 - Point to SRAM and CFG */
 550         inbound_region.mode = PCI_BAR_MATCH_MODE;
 551         inbound_region.bar = SRAM_CFG_BAR_ID;
 552         inbound_region.addr = SRAM_BASE_ADDR;
 553         rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
 554         if (rc)
 555                 goto done;
 556
 557         /* Inbound Region 1 - Bar 4 - Point to DDR */
 558         inbound_region.mode = PCI_BAR_MATCH_MODE;
 559         inbound_region.bar = DDR_BAR_ID;
 560         inbound_region.addr = DRAM_PHYS_BASE;
 561         rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
 562         if (rc)
 563                 goto done;
 564
 565         hdev->asic_funcs->set_dma_mask_from_fw(hdev);
 566
 567         /* Outbound Region 0 - Point to Host  */
 568         outbound_region.addr = HOST_PHYS_BASE;
 569         outbound_region.size = HOST_PHYS_SIZE;
 570         rc = hl_pci_set_outbound_region(hdev, &outbound_region);
 571
 572 done:
 573         return rc;
 574 }
 575
 576 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
 577 {
 578         return RREG32(mmHW_STATE);
 579 }
 580
 581 /*
 582  * goya_early_init - GOYA early initialization code
 583  *
 584  * @hdev: pointer to hl_device structure
 585  *
 586  * Verify PCI bars
 587  * Set DMA masks
 588  * PCI controller initialization
 589  * Map PCI bars
 590  *
 591  */
 592 static int goya_early_init(struct hl_device *hdev)
 593 {
 594         struct asic_fixed_properties *prop = &hdev->asic_prop;
 595         struct pci_dev *pdev = hdev->pdev;
 596         u32 fw_boot_status, val;
 597         int rc;
 598
 599         rc = goya_set_fixed_properties(hdev);
 600         if (rc) {
 601                 dev_err(hdev->dev, "Failed to get fixed properties\n");
 602                 return rc;
 603         }
 604
 605         /* Check BAR sizes */
 606         if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) {
 607                 dev_err(hdev->dev,
 608                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 609                         SRAM_CFG_BAR_ID,
 610                         (unsigned long long) pci_resource_len(pdev,
 611                                                         SRAM_CFG_BAR_ID),
 612                         CFG_BAR_SIZE);
 613                 rc = -ENODEV;
 614                 goto free_queue_props;
 615         }
 616
 617         if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) {
 618                 dev_err(hdev->dev,
 619                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 620                         MSIX_BAR_ID,
 621                         (unsigned long long) pci_resource_len(pdev,
 622                                                                 MSIX_BAR_ID),
 623                         MSIX_BAR_SIZE);
 624                 rc = -ENODEV;
 625                 goto free_queue_props;
 626         }
 627
 628         prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
 629         hdev->dram_pci_bar_start = pci_resource_start(pdev, DDR_BAR_ID);
 630
 631         /* If FW security is enabled at this point it means no access to ELBI */
 632         if (hdev->asic_prop.fw_security_enabled) {
 633                 hdev->asic_prop.iatu_done_by_fw = true;
 634                 goto pci_init;
 635         }
 636
 637         rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0,
 638                                 &fw_boot_status);
 639         if (rc)
 640                 goto free_queue_props;
 641
 642         /* Check whether FW is configuring iATU */
 643         if ((fw_boot_status & CPU_BOOT_DEV_STS0_ENABLED) &&
 644                         (fw_boot_status & CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN))
 645                 hdev->asic_prop.iatu_done_by_fw = true;
 646
 647 pci_init:
 648         rc = hl_pci_init(hdev);
 649         if (rc)
 650                 goto free_queue_props;
 651
 652         /* Before continuing in the initialization, we need to read the preboot
 653          * version to determine whether we run with a security-enabled firmware
 654          */
 655         rc = hl_fw_read_preboot_status(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS,
 656                                         mmCPU_BOOT_DEV_STS0,
 657                                         mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
 658                                         mmCPU_BOOT_ERR1,
 659                                         GOYA_BOOT_FIT_REQ_TIMEOUT_USEC);
 660         if (rc) {
 661                 if (hdev->reset_on_preboot_fail)
 662                         hdev->asic_funcs->hw_fini(hdev, true, false);
 663                 goto pci_fini;
 664         }
 665
 666         if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
 667                 dev_info(hdev->dev,
 668                         "H/W state is dirty, must reset before initializing\n");
 669                 hdev->asic_funcs->hw_fini(hdev, true, false);
 670         }
 671
 672         if (!hdev->pldm) {
 673                 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
 674                 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
 675                         dev_warn(hdev->dev,
 676                                 "PCI strap is not configured correctly, PCI bus errors may occur\n");
 677         }
 678
 679         return 0;
 680
 681 pci_fini:
 682         hl_pci_fini(hdev);
 683 free_queue_props:
 684         kfree(hdev->asic_prop.hw_queues_props);
 685         return rc;
 686 }
 687
 688 /*
 689  * goya_early_fini - GOYA early finalization code
 690  *
 691  * @hdev: pointer to hl_device structure
 692  *
 693  * Unmap PCI bars
 694  *
 695  */
 696 static int goya_early_fini(struct hl_device *hdev)
 697 {
 698         kfree(hdev->asic_prop.hw_queues_props);
 699         hl_pci_fini(hdev);
 700
 701         return 0;
 702 }
 703
 704 static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
 705 {
 706         /* mask to zero the MMBP and ASID bits */
 707         WREG32_AND(reg, ~0x7FF);
 708         WREG32_OR(reg, asid);
 709 }
 710
 711 static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
 712 {
 713         struct goya_device *goya = hdev->asic_specific;
 714
 715         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
 716                 return;
 717
 718         if (secure)
 719                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
 720         else
 721                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
 722
 723         RREG32(mmDMA_QM_0_GLBL_PROT);
 724 }
 725
 726 /*
 727  * goya_fetch_psoc_frequency - Fetch PSOC frequency values
 728  *
 729  * @hdev: pointer to hl_device structure
 730  *
 731  */
 732 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
 733 {
 734         struct asic_fixed_properties *prop = &hdev->asic_prop;
 735         u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
 736         u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
 737         int rc;
 738
 739         if (hdev->asic_prop.fw_security_enabled) {
 740                 rc = hl_fw_cpucp_pll_info_get(hdev, HL_GOYA_PCI_PLL,
 741                                 pll_freq_arr);
 742
 743                 if (rc)
 744                         return;
 745
 746                 freq = pll_freq_arr[1];
 747         } else {
 748                 div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
 749                 div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);
 750                 nr = RREG32(mmPSOC_PCI_PLL_NR);
 751                 nf = RREG32(mmPSOC_PCI_PLL_NF);
 752                 od = RREG32(mmPSOC_PCI_PLL_OD);
 753
 754                 if (div_sel == DIV_SEL_REF_CLK ||
 755                                 div_sel == DIV_SEL_DIVIDED_REF) {
 756                         if (div_sel == DIV_SEL_REF_CLK)
 757                                 freq = PLL_REF_CLK;
 758                         else
 759                                 freq = PLL_REF_CLK / (div_fctr + 1);
 760                 } else if (div_sel == DIV_SEL_PLL_CLK ||
 761                                 div_sel == DIV_SEL_DIVIDED_PLL) {
 762                         pll_clk = PLL_REF_CLK * (nf + 1) /
 763                                         ((nr + 1) * (od + 1));
 764                         if (div_sel == DIV_SEL_PLL_CLK)
 765                                 freq = pll_clk;
 766                         else
 767                                 freq = pll_clk / (div_fctr + 1);
 768                 } else {
 769                         dev_warn(hdev->dev,
 770                                 "Received invalid div select value: %d",
 771                                 div_sel);
 772                         freq = 0;
 773                 }
 774         }
 775
 776         prop->psoc_timestamp_frequency = freq;
 777         prop->psoc_pci_pll_nr = nr;
 778         prop->psoc_pci_pll_nf = nf;
 779         prop->psoc_pci_pll_od = od;
 780         prop->psoc_pci_pll_div_factor = div_fctr;
 781 }
 782
 783 int goya_late_init(struct hl_device *hdev)
 784 {
 785         struct asic_fixed_properties *prop = &hdev->asic_prop;
 786         int rc;
 787
 788         goya_fetch_psoc_frequency(hdev);
 789
 790         rc = goya_mmu_clear_pgt_range(hdev);
 791         if (rc) {
 792                 dev_err(hdev->dev,
 793                         "Failed to clear MMU page tables range %d\n", rc);
 794                 return rc;
 795         }
 796
 797         rc = goya_mmu_set_dram_default_page(hdev);
 798         if (rc) {
 799                 dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc);
 800                 return rc;
 801         }
 802
 803         rc = goya_mmu_add_mappings_for_device_cpu(hdev);
 804         if (rc)
 805                 return rc;
 806
 807         rc = goya_init_cpu_queues(hdev);
 808         if (rc)
 809                 return rc;
 810
 811         rc = goya_test_cpu_queue(hdev);
 812         if (rc)
 813                 return rc;
 814
 815         rc = goya_cpucp_info_get(hdev);
 816         if (rc) {
 817                 dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc);
 818                 return rc;
 819         }
 820
 821         /* Now that we have the DRAM size in ASIC prop, we need to check
 822          * its size and configure the DMA_IF DDR wrap protection (which is in
 823          * the MMU block) accordingly. The value is the log2 of the DRAM size
 824          */
 825         WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
 826
 827         rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS);
 828         if (rc) {
 829                 dev_err(hdev->dev,
 830                         "Failed to enable PCI access from CPU %d\n", rc);
 831                 return rc;
 832         }
 833
 834         return 0;
 835 }
 836
 837 /*
 838  * goya_late_fini - GOYA late tear-down code
 839  *
 840  * @hdev: pointer to hl_device structure
 841  *
 842  * Free sensors allocated structures
 843  */
 844 void goya_late_fini(struct hl_device *hdev)
 845 {
 846         const struct hwmon_channel_info **channel_info_arr;
 847         int i = 0;
 848
 849         if (!hdev->hl_chip_info->info)
 850                 return;
 851
 852         channel_info_arr = hdev->hl_chip_info->info;
 853
 854         while (channel_info_arr[i]) {
 855                 kfree(channel_info_arr[i]->config);
 856                 kfree(channel_info_arr[i]);
 857                 i++;
 858         }
 859
 860         kfree(channel_info_arr);
 861
 862         hdev->hl_chip_info->info = NULL;
 863 }
 864
 865 static void goya_set_pci_memory_regions(struct hl_device *hdev)
 866 {
 867         struct asic_fixed_properties *prop = &hdev->asic_prop;
 868         struct pci_mem_region *region;
 869
 870         /* CFG */
 871         region = &hdev->pci_mem_region[PCI_REGION_CFG];
 872         region->region_base = CFG_BASE;
 873         region->region_size = CFG_SIZE;
 874         region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR;
 875         region->bar_size = CFG_BAR_SIZE;
 876         region->bar_id = SRAM_CFG_BAR_ID;
 877         region->used = 1;
 878
 879         /* SRAM */
 880         region = &hdev->pci_mem_region[PCI_REGION_SRAM];
 881         region->region_base = SRAM_BASE_ADDR;
 882         region->region_size = SRAM_SIZE;
 883         region->offset_in_bar = 0;
 884         region->bar_size = CFG_BAR_SIZE;
 885         region->bar_id = SRAM_CFG_BAR_ID;
 886         region->used = 1;
 887
 888         /* DRAM */
 889         region = &hdev->pci_mem_region[PCI_REGION_DRAM];
 890         region->region_base = DRAM_PHYS_BASE;
 891         region->region_size = hdev->asic_prop.dram_size;
 892         region->offset_in_bar = 0;
 893         region->bar_size = prop->dram_pci_bar_size;
 894         region->bar_id = DDR_BAR_ID;
 895         region->used = 1;
 896 }
 897
 898 /*
 899  * goya_sw_init - Goya software initialization code
 900  *
 901  * @hdev: pointer to hl_device structure
 902  *
 903  */
 904 static int goya_sw_init(struct hl_device *hdev)
 905 {
 906         struct goya_device *goya;
 907         int rc;
 908
 909         /* Allocate device structure */
 910         goya = kzalloc(sizeof(*goya), GFP_KERNEL);
 911         if (!goya)
 912                 return -ENOMEM;
 913
 914         /* according to goya_init_iatu */
 915         goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
 916
 917         goya->mme_clk = GOYA_PLL_FREQ_LOW;
 918         goya->tpc_clk = GOYA_PLL_FREQ_LOW;
 919         goya->ic_clk = GOYA_PLL_FREQ_LOW;
 920
 921         hdev->asic_specific = goya;
 922
 923         /* Create DMA pool for small allocations */
 924         hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
 925                         &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
 926         if (!hdev->dma_pool) {
 927                 dev_err(hdev->dev, "failed to create DMA pool\n");
 928                 rc = -ENOMEM;
 929                 goto free_goya_device;
 930         }
 931
 932         hdev->cpu_accessible_dma_mem =
 933                         hdev->asic_funcs->asic_dma_alloc_coherent(hdev,
 934                                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 935                                         &hdev->cpu_accessible_dma_address,
 936                                         GFP_KERNEL | __GFP_ZERO);
 937
 938         if (!hdev->cpu_accessible_dma_mem) {
 939                 rc = -ENOMEM;
 940                 goto free_dma_pool;
 941         }
 942
 943         dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n",
 944                 &hdev->cpu_accessible_dma_address);
 945
 946         hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
 947         if (!hdev->cpu_accessible_dma_pool) {
 948                 dev_err(hdev->dev,
 949                         "Failed to create CPU accessible DMA pool\n");
 950                 rc = -ENOMEM;
 951                 goto free_cpu_dma_mem;
 952         }
 953
 954         rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
 955                                 (uintptr_t) hdev->cpu_accessible_dma_mem,
 956                                 HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
 957         if (rc) {
 958                 dev_err(hdev->dev,
 959                         "Failed to add memory to CPU accessible DMA pool\n");
 960                 rc = -EFAULT;
 961                 goto free_cpu_accessible_dma_pool;
 962         }
 963
 964         spin_lock_init(&goya->hw_queues_lock);
 965         hdev->supports_coresight = true;
 966         hdev->supports_soft_reset = true;
 967         hdev->allow_inference_soft_reset = true;
 968         hdev->supports_wait_for_multi_cs = false;
 969
 970         hdev->asic_funcs->set_pci_memory_regions(hdev);
 971
 972         return 0;
 973
 974 free_cpu_accessible_dma_pool:
 975         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 976 free_cpu_dma_mem:
 977         hdev->asic_funcs->asic_dma_free_coherent(hdev,
 978                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 979                         hdev->cpu_accessible_dma_mem,
 980                         hdev->cpu_accessible_dma_address);
 981 free_dma_pool:
 982         dma_pool_destroy(hdev->dma_pool);
 983 free_goya_device:
 984         kfree(goya);
 985
 986         return rc;
 987 }
 988
 989 /*
 990  * goya_sw_fini - Goya software tear-down code
 991  *
 992  * @hdev: pointer to hl_device structure
 993  *
 994  */
 995 static int goya_sw_fini(struct hl_device *hdev)
 996 {
 997         struct goya_device *goya = hdev->asic_specific;
 998
 999         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
1000
1001         hdev->asic_funcs->asic_dma_free_coherent(hdev,
1002                         HL_CPU_ACCESSIBLE_MEM_SIZE,
1003                         hdev->cpu_accessible_dma_mem,
1004                         hdev->cpu_accessible_dma_address);
1005
1006         dma_pool_destroy(hdev->dma_pool);
1007
1008         kfree(goya);
1009
1010         return 0;
1011 }
1012
1013 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
1014                 dma_addr_t bus_address)
1015 {
1016         struct goya_device *goya = hdev->asic_specific;
1017         u32 mtr_base_lo, mtr_base_hi;
1018         u32 so_base_lo, so_base_hi;
1019         u32 gic_base_lo, gic_base_hi;
1020         u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
1021         u32 dma_err_cfg = QMAN_DMA_ERR_MSG_EN;
1022
1023         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1024         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1025         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1026         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1027
1028         gic_base_lo =
1029                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1030         gic_base_hi =
1031                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1032
1033         WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
1034         WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
1035
1036         WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
1037         WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
1038         WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
1039
1040         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1041         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1042         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1043         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1044         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1045         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1046         WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
1047                         GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id);
1048
1049         /* PQ has buffer of 2 cache lines, while CQ has 8 lines */
1050         WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
1051         WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
1052
1053         if (goya->hw_cap_initialized & HW_CAP_MMU)
1054                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
1055         else
1056                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
1057
1058         if (hdev->stop_on_err)
1059                 dma_err_cfg |= 1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT;
1060
1061         WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
1062         WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
1063 }
1064
1065 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
1066 {
1067         u32 gic_base_lo, gic_base_hi;
1068         u64 sob_addr;
1069         u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
1070
1071         gic_base_lo =
1072                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1073         gic_base_hi =
1074                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1075
1076         WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
1077         WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
1078         WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
1079                         GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id);
1080
1081         if (dma_id)
1082                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
1083                                 (dma_id - 1) * 4;
1084         else
1085                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
1086
1087         WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
1088         WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1089 }
1090
1091 /*
1092  * goya_init_dma_qmans - Initialize QMAN DMA registers
1093  *
1094  * @hdev: pointer to hl_device structure
1095  *
1096  * Initialize the H/W registers of the QMAN DMA channels
1097  *
1098  */
1099 void goya_init_dma_qmans(struct hl_device *hdev)
1100 {
1101         struct goya_device *goya = hdev->asic_specific;
1102         struct hl_hw_queue *q;
1103         int i;
1104
1105         if (goya->hw_cap_initialized & HW_CAP_DMA)
1106                 return;
1107
1108         q = &hdev->kernel_queues[0];
1109
1110         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
1111                 q->cq_id = q->msi_vec = i;
1112                 goya_init_dma_qman(hdev, i, q->bus_address);
1113                 goya_init_dma_ch(hdev, i);
1114         }
1115
1116         goya->hw_cap_initialized |= HW_CAP_DMA;
1117 }
1118
1119 /*
1120  * goya_disable_external_queues - Disable external queues
1121  *
1122  * @hdev: pointer to hl_device structure
1123  *
1124  */
1125 static void goya_disable_external_queues(struct hl_device *hdev)
1126 {
1127         struct goya_device *goya = hdev->asic_specific;
1128
1129         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1130                 return;
1131
1132         WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1133         WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1134         WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1135         WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1136         WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1137 }
1138
1139 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
1140                                 u32 cp_sts_reg, u32 glbl_sts0_reg)
1141 {
1142         int rc;
1143         u32 status;
1144
1145         /* use the values of TPC0 as they are all the same*/
1146
1147         WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1148
1149         status = RREG32(cp_sts_reg);
1150         if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) {
1151                 rc = hl_poll_timeout(
1152                         hdev,
1153                         cp_sts_reg,
1154                         status,
1155                         !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK),
1156                         1000,
1157                         QMAN_FENCE_TIMEOUT_USEC);
1158
1159                 /* if QMAN is stuck in fence no need to check for stop */
1160                 if (rc)
1161                         return 0;
1162         }
1163
1164         rc = hl_poll_timeout(
1165                 hdev,
1166                 glbl_sts0_reg,
1167                 status,
1168                 (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK),
1169                 1000,
1170                 QMAN_STOP_TIMEOUT_USEC);
1171
1172         if (rc) {
1173                 dev_err(hdev->dev,
1174                         "Timeout while waiting for QMAN to stop\n");
1175                 return -EINVAL;
1176         }
1177
1178         return 0;
1179 }
1180
1181 /*
1182  * goya_stop_external_queues - Stop external queues
1183  *
1184  * @hdev: pointer to hl_device structure
1185  *
1186  * Returns 0 on success
1187  *
1188  */
1189 static int goya_stop_external_queues(struct hl_device *hdev)
1190 {
1191         int rc, retval = 0;
1192
1193         struct goya_device *goya = hdev->asic_specific;
1194
1195         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1196                 return retval;
1197
1198         rc = goya_stop_queue(hdev,
1199                         mmDMA_QM_0_GLBL_CFG1,
1200                         mmDMA_QM_0_CP_STS,
1201                         mmDMA_QM_0_GLBL_STS0);
1202
1203         if (rc) {
1204                 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
1205                 retval = -EIO;
1206         }
1207
1208         rc = goya_stop_queue(hdev,
1209                         mmDMA_QM_1_GLBL_CFG1,
1210                         mmDMA_QM_1_CP_STS,
1211                         mmDMA_QM_1_GLBL_STS0);
1212
1213         if (rc) {
1214                 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
1215                 retval = -EIO;
1216         }
1217
1218         rc = goya_stop_queue(hdev,
1219                         mmDMA_QM_2_GLBL_CFG1,
1220                         mmDMA_QM_2_CP_STS,
1221                         mmDMA_QM_2_GLBL_STS0);
1222
1223         if (rc) {
1224                 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
1225                 retval = -EIO;
1226         }
1227
1228         rc = goya_stop_queue(hdev,
1229                         mmDMA_QM_3_GLBL_CFG1,
1230                         mmDMA_QM_3_CP_STS,
1231                         mmDMA_QM_3_GLBL_STS0);
1232
1233         if (rc) {
1234                 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
1235                 retval = -EIO;
1236         }
1237
1238         rc = goya_stop_queue(hdev,
1239                         mmDMA_QM_4_GLBL_CFG1,
1240                         mmDMA_QM_4_CP_STS,
1241                         mmDMA_QM_4_GLBL_STS0);
1242
1243         if (rc) {
1244                 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
1245                 retval = -EIO;
1246         }
1247
1248         return retval;
1249 }
1250
1251 /*
1252  * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
1253  *
1254  * @hdev: pointer to hl_device structure
1255  *
1256  * Returns 0 on success
1257  *
1258  */
1259 int goya_init_cpu_queues(struct hl_device *hdev)
1260 {
1261         struct goya_device *goya = hdev->asic_specific;
1262         struct asic_fixed_properties *prop = &hdev->asic_prop;
1263         struct hl_eq *eq;
1264         u32 status;
1265         struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
1266         int err;
1267
1268         if (!hdev->cpu_queues_enable)
1269                 return 0;
1270
1271         if (goya->hw_cap_initialized & HW_CAP_CPU_Q)
1272                 return 0;
1273
1274         eq = &hdev->event_queue;
1275
1276         WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
1277         WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
1278
1279         WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
1280         WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
1281
1282         WREG32(mmCPU_CQ_BASE_ADDR_LOW,
1283                         lower_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1284         WREG32(mmCPU_CQ_BASE_ADDR_HIGH,
1285                         upper_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1286
1287         WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
1288         WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
1289         WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
1290
1291         /* Used for EQ CI */
1292         WREG32(mmCPU_EQ_CI, 0);
1293
1294         WREG32(mmCPU_IF_PF_PQ_PI, 0);
1295
1296         WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP);
1297
1298         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1299                         GOYA_ASYNC_EVENT_ID_PI_UPDATE);
1300
1301         err = hl_poll_timeout(
1302                 hdev,
1303                 mmCPU_PQ_INIT_STATUS,
1304                 status,
1305                 (status == PQ_INIT_STATUS_READY_FOR_HOST),
1306                 1000,
1307                 GOYA_CPU_TIMEOUT_USEC);
1308
1309         if (err) {
1310                 dev_err(hdev->dev,
1311                         "Failed to setup communication with device CPU\n");
1312                 return -EIO;
1313         }
1314
1315         /* update FW application security bits */
1316         if (prop->fw_cpu_boot_dev_sts0_valid)
1317                 prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);
1318
1319         if (prop->fw_cpu_boot_dev_sts1_valid)
1320                 prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);
1321
1322         goya->hw_cap_initialized |= HW_CAP_CPU_Q;
1323         return 0;
1324 }
1325
1326 static void goya_set_pll_refclk(struct hl_device *hdev)
1327 {
1328         WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1329         WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1330         WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1331         WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1332
1333         WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1334         WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1335         WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1336         WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1337
1338         WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1339         WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1340         WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1341         WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1342
1343         WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1344         WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1345         WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1346         WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1347
1348         WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1349         WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1350         WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1351         WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1352
1353         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1354         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1355         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1356         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1357
1358         WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1359         WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1360         WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1361         WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1362 }
1363
1364 static void goya_disable_clk_rlx(struct hl_device *hdev)
1365 {
1366         WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1367         WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1368 }
1369
1370 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1371 {
1372         u64 tpc_eml_address;
1373         u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1374         int err, slm_index;
1375
1376         tpc_offset = tpc_id * 0x40000;
1377         tpc_eml_offset = tpc_id * 0x200000;
1378         tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE);
1379         tpc_slm_offset = tpc_eml_address + 0x100000;
1380
1381         /*
1382          * Workaround for Bug H2 #2443 :
1383          * "TPC SB is not initialized on chip reset"
1384          */
1385
1386         val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1387         if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1388                 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1389                         tpc_id);
1390
1391         WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1392
1393         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1394         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1395         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1396         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1397         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1398         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1399         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1400         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1401         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1402         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1403
1404         WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1405                 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT);
1406
1407         err = hl_poll_timeout(
1408                 hdev,
1409                 mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1410                 val,
1411                 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1412                 1000,
1413                 HL_DEVICE_TIMEOUT_USEC);
1414
1415         if (err)
1416                 dev_err(hdev->dev,
1417                         "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id);
1418
1419         WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1420                 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT);
1421
1422         msleep(GOYA_RESET_WAIT_MSEC);
1423
1424         WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1425                 ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT));
1426
1427         msleep(GOYA_RESET_WAIT_MSEC);
1428
1429         for (slm_index = 0 ; slm_index < 256 ; slm_index++)
1430                 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1431
1432         val = RREG32(tpc_slm_offset);
1433 }
1434
1435 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1436 {
1437         struct goya_device *goya = hdev->asic_specific;
1438         int i;
1439
1440         if (hdev->pldm)
1441                 return;
1442
1443         if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST)
1444                 return;
1445
1446         /* Workaround for H2 #2443 */
1447
1448         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1449                 _goya_tpc_mbist_workaround(hdev, i);
1450
1451         goya->hw_cap_initialized |= HW_CAP_TPC_MBIST;
1452 }
1453
1454 /*
1455  * goya_init_golden_registers - Initialize golden registers
1456  *
1457  * @hdev: pointer to hl_device structure
1458  *
1459  * Initialize the H/W registers of the device
1460  *
1461  */
1462 static void goya_init_golden_registers(struct hl_device *hdev)
1463 {
1464         struct goya_device *goya = hdev->asic_specific;
1465         u32 polynom[10], tpc_intr_mask, offset;
1466         int i;
1467
1468         if (goya->hw_cap_initialized & HW_CAP_GOLDEN)
1469                 return;
1470
1471         polynom[0] = 0x00020080;
1472         polynom[1] = 0x00401000;
1473         polynom[2] = 0x00200800;
1474         polynom[3] = 0x00002000;
1475         polynom[4] = 0x00080200;
1476         polynom[5] = 0x00040100;
1477         polynom[6] = 0x00100400;
1478         polynom[7] = 0x00004000;
1479         polynom[8] = 0x00010000;
1480         polynom[9] = 0x00008000;
1481
1482         /* Mask all arithmetic interrupts from TPC */
1483         tpc_intr_mask = 0x7FFF;
1484
1485         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) {
1486                 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1487                 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1488                 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1489                 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1490                 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1491
1492                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1493                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1494                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1495                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1496                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1497
1498
1499                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1500                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1501                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1502                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1503                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1504
1505                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1506                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1507                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1508                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1509                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1510
1511                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1512                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1513                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1514                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1515                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1516
1517                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1518                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1519                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1520                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1521                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1522         }
1523
1524         WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1525         WREG32(mmMME_AGU, 0x0f0f0f10);
1526         WREG32(mmMME_SEI_MASK, ~0x0);
1527
1528         WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1529         WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1530         WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1531         WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1532         WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1533         WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1534         WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1535         WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1536         WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1537         WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1538         WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1539         WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1540         WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1541         WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1542         WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1543         WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1544         WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1545         WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1546         WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1547         WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1548         WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1549         WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1550         WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1551         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1552         WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1553         WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1554         WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1555         WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1556         WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1557         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1558         WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1559         WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1560         WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1561         WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1562         WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1563         WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1564         WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1565         WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1566         WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1567         WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1568         WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1569         WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1570         WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1571         WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1572         WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1573         WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1574         WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1575         WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1576         WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1577         WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1578         WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1579         WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1580         WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1581         WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1582         WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1583         WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1584         WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1585         WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1586         WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1587         WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1588         WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1589         WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1590         WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1591         WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1592         WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1593         WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1594         WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1595         WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1596         WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1597         WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1598         WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1599         WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1600         WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1601         WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1602         WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1603         WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1604         WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1605         WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1606         WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1607         WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1608         WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1609         WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1610         WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1611         WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1612
1613         WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1614         WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1615         WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1616         WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1617         WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1618         WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1619         WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1620         WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1621         WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1622         WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1623         WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1624         WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1625
1626         WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1627         WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1628         WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1629         WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1630         WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1631         WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1632         WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1633         WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1634         WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1635         WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1636         WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1637         WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1638
1639         WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1640         WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1641         WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1642         WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1643         WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1644         WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1645         WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1646         WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1647         WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1648         WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1649         WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1650         WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1651
1652         WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1653         WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1654         WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1655         WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1656         WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1657         WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1658         WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1659         WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1660         WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1661         WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1662         WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1663         WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1664
1665         WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1666         WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1667         WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1668         WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1669         WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1670         WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1671         WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1672         WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1673         WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1674         WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1675         WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1676         WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1677
1678         WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1679         WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1680         WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1681         WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1682         WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1683         WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1684         WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1685         WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1686         WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1687         WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1688         WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1689         WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1690
1691         for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) {
1692                 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1693                 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1694                 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1695                 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1696                 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1697                 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1698
1699                 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1700                 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1701                 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1702                 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1703                 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1704                 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1705                 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1706                 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1707
1708                 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1709                 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1710         }
1711
1712         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) {
1713                 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1714                                 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT);
1715                 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1716                                 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT);
1717         }
1718
1719         for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) {
1720                 /*
1721                  * Workaround for Bug H2 #2441 :
1722                  * "ST.NOP set trace event illegal opcode"
1723                  */
1724                 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1725
1726                 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1727                                 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
1728                 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1729                                 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1730
1731                 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset,
1732                                 ICACHE_FETCH_LINE_NUM, 2);
1733         }
1734
1735         WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1736         WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1737                         1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1738
1739         WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1740         WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1741                         1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1742
1743         /*
1744          * Workaround for H2 #HW-23 bug
1745          * Set DMA max outstanding read requests to 240 on DMA CH 1.
1746          * This limitation is still large enough to not affect Gen4 bandwidth.
1747          * We need to only limit that DMA channel because the user can only read
1748          * from Host using DMA CH 1
1749          */
1750         WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1751
1752         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1753
1754         goya->hw_cap_initialized |= HW_CAP_GOLDEN;
1755 }
1756
1757 static void goya_init_mme_qman(struct hl_device *hdev)
1758 {
1759         u32 mtr_base_lo, mtr_base_hi;
1760         u32 so_base_lo, so_base_hi;
1761         u32 gic_base_lo, gic_base_hi;
1762         u64 qman_base_addr;
1763
1764         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1765         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1766         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1767         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1768
1769         gic_base_lo =
1770                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1771         gic_base_hi =
1772                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1773
1774         qman_base_addr = hdev->asic_prop.sram_base_address +
1775                                 MME_QMAN_BASE_OFFSET;
1776
1777         WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1778         WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1779         WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1780         WREG32(mmMME_QM_PQ_PI, 0);
1781         WREG32(mmMME_QM_PQ_CI, 0);
1782         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1783         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1784         WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1785         WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1786
1787         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1788         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1789         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1790         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1791
1792         /* QMAN CQ has 8 cache lines */
1793         WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1794
1795         WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1796         WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1797
1798         WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1799
1800         WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1801
1802         WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1803
1804         WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1805 }
1806
1807 static void goya_init_mme_cmdq(struct hl_device *hdev)
1808 {
1809         u32 mtr_base_lo, mtr_base_hi;
1810         u32 so_base_lo, so_base_hi;
1811         u32 gic_base_lo, gic_base_hi;
1812
1813         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1814         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1815         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1816         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1817
1818         gic_base_lo =
1819                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1820         gic_base_hi =
1821                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1822
1823         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1824         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1825         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1826         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1827
1828         /* CMDQ CQ has 20 cache lines */
1829         WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1830
1831         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1832         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1833
1834         WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1835
1836         WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1837
1838         WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1839
1840         WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1841 }
1842
1843 void goya_init_mme_qmans(struct hl_device *hdev)
1844 {
1845         struct goya_device *goya = hdev->asic_specific;
1846         u32 so_base_lo, so_base_hi;
1847
1848         if (goya->hw_cap_initialized & HW_CAP_MME)
1849                 return;
1850
1851         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1852         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1853
1854         WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1855         WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1856
1857         goya_init_mme_qman(hdev);
1858         goya_init_mme_cmdq(hdev);
1859
1860         goya->hw_cap_initialized |= HW_CAP_MME;
1861 }
1862
1863 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1864 {
1865         u32 mtr_base_lo, mtr_base_hi;
1866         u32 so_base_lo, so_base_hi;
1867         u32 gic_base_lo, gic_base_hi;
1868         u64 qman_base_addr;
1869         u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
1870
1871         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1872         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1873         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1874         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1875
1876         gic_base_lo =
1877                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1878         gic_base_hi =
1879                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1880
1881         qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1882
1883         WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1884         WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1885         WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1886         WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1887         WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1888         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1889         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1890         WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1891         WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1892
1893         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1894         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1895         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1896         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1897
1898         WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1899
1900         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1901         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1902
1903         WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1904                         GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id);
1905
1906         WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1907
1908         WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1909
1910         WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1911 }
1912
1913 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
1914 {
1915         u32 mtr_base_lo, mtr_base_hi;
1916         u32 so_base_lo, so_base_hi;
1917         u32 gic_base_lo, gic_base_hi;
1918         u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
1919
1920         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1921         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1922         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1923         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1924
1925         gic_base_lo =
1926                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1927         gic_base_hi =
1928                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1929
1930         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1931         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1932         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1933         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1934
1935         WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
1936
1937         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1938         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1939
1940         WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
1941                         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id);
1942
1943         WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
1944
1945         WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
1946
1947         WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
1948 }
1949
1950 void goya_init_tpc_qmans(struct hl_device *hdev)
1951 {
1952         struct goya_device *goya = hdev->asic_specific;
1953         u32 so_base_lo, so_base_hi;
1954         u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW -
1955                         mmTPC0_CFG_SM_BASE_ADDRESS_LOW;
1956         int i;
1957
1958         if (goya->hw_cap_initialized & HW_CAP_TPC)
1959                 return;
1960
1961         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1962         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1963
1964         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
1965                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
1966                                 so_base_lo);
1967                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
1968                                 so_base_hi);
1969         }
1970
1971         goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
1972         goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
1973         goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
1974         goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
1975         goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
1976         goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
1977         goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
1978         goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
1979
1980         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1981                 goya_init_tpc_cmdq(hdev, i);
1982
1983         goya->hw_cap_initialized |= HW_CAP_TPC;
1984 }
1985
1986 /*
1987  * goya_disable_internal_queues - Disable internal queues
1988  *
1989  * @hdev: pointer to hl_device structure
1990  *
1991  */
1992 static void goya_disable_internal_queues(struct hl_device *hdev)
1993 {
1994         struct goya_device *goya = hdev->asic_specific;
1995
1996         if (!(goya->hw_cap_initialized & HW_CAP_MME))
1997                 goto disable_tpc;
1998
1999         WREG32(mmMME_QM_GLBL_CFG0, 0);
2000         WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
2001
2002 disable_tpc:
2003         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2004                 return;
2005
2006         WREG32(mmTPC0_QM_GLBL_CFG0, 0);
2007         WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
2008
2009         WREG32(mmTPC1_QM_GLBL_CFG0, 0);
2010         WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
2011
2012         WREG32(mmTPC2_QM_GLBL_CFG0, 0);
2013         WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
2014
2015         WREG32(mmTPC3_QM_GLBL_CFG0, 0);
2016         WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
2017
2018         WREG32(mmTPC4_QM_GLBL_CFG0, 0);
2019         WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
2020
2021         WREG32(mmTPC5_QM_GLBL_CFG0, 0);
2022         WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
2023
2024         WREG32(mmTPC6_QM_GLBL_CFG0, 0);
2025         WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
2026
2027         WREG32(mmTPC7_QM_GLBL_CFG0, 0);
2028         WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
2029 }
2030
2031 /*
2032  * goya_stop_internal_queues - Stop internal queues
2033  *
2034  * @hdev: pointer to hl_device structure
2035  *
2036  * Returns 0 on success
2037  *
2038  */
2039 static int goya_stop_internal_queues(struct hl_device *hdev)
2040 {
2041         struct goya_device *goya = hdev->asic_specific;
2042         int rc, retval = 0;
2043
2044         if (!(goya->hw_cap_initialized & HW_CAP_MME))
2045                 goto stop_tpc;
2046
2047         /*
2048          * Each queue (QMAN) is a separate H/W logic. That means that each
2049          * QMAN can be stopped independently and failure to stop one does NOT
2050          * mandate we should not try to stop other QMANs
2051          */
2052
2053         rc = goya_stop_queue(hdev,
2054                         mmMME_QM_GLBL_CFG1,
2055                         mmMME_QM_CP_STS,
2056                         mmMME_QM_GLBL_STS0);
2057
2058         if (rc) {
2059                 dev_err(hdev->dev, "failed to stop MME QMAN\n");
2060                 retval = -EIO;
2061         }
2062
2063         rc = goya_stop_queue(hdev,
2064                         mmMME_CMDQ_GLBL_CFG1,
2065                         mmMME_CMDQ_CP_STS,
2066                         mmMME_CMDQ_GLBL_STS0);
2067
2068         if (rc) {
2069                 dev_err(hdev->dev, "failed to stop MME CMDQ\n");
2070                 retval = -EIO;
2071         }
2072
2073 stop_tpc:
2074         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2075                 return retval;
2076
2077         rc = goya_stop_queue(hdev,
2078                         mmTPC0_QM_GLBL_CFG1,
2079                         mmTPC0_QM_CP_STS,
2080                         mmTPC0_QM_GLBL_STS0);
2081
2082         if (rc) {
2083                 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
2084                 retval = -EIO;
2085         }
2086
2087         rc = goya_stop_queue(hdev,
2088                         mmTPC0_CMDQ_GLBL_CFG1,
2089                         mmTPC0_CMDQ_CP_STS,
2090                         mmTPC0_CMDQ_GLBL_STS0);
2091
2092         if (rc) {
2093                 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
2094                 retval = -EIO;
2095         }
2096
2097         rc = goya_stop_queue(hdev,
2098                         mmTPC1_QM_GLBL_CFG1,
2099                         mmTPC1_QM_CP_STS,
2100                         mmTPC1_QM_GLBL_STS0);
2101
2102         if (rc) {
2103                 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
2104                 retval = -EIO;
2105         }
2106
2107         rc = goya_stop_queue(hdev,
2108                         mmTPC1_CMDQ_GLBL_CFG1,
2109                         mmTPC1_CMDQ_CP_STS,
2110                         mmTPC1_CMDQ_GLBL_STS0);
2111
2112         if (rc) {
2113                 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
2114                 retval = -EIO;
2115         }
2116
2117         rc = goya_stop_queue(hdev,
2118                         mmTPC2_QM_GLBL_CFG1,
2119                         mmTPC2_QM_CP_STS,
2120                         mmTPC2_QM_GLBL_STS0);
2121
2122         if (rc) {
2123                 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
2124                 retval = -EIO;
2125         }
2126
2127         rc = goya_stop_queue(hdev,
2128                         mmTPC2_CMDQ_GLBL_CFG1,
2129                         mmTPC2_CMDQ_CP_STS,
2130                         mmTPC2_CMDQ_GLBL_STS0);
2131
2132         if (rc) {
2133                 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
2134                 retval = -EIO;
2135         }
2136
2137         rc = goya_stop_queue(hdev,
2138                         mmTPC3_QM_GLBL_CFG1,
2139                         mmTPC3_QM_CP_STS,
2140                         mmTPC3_QM_GLBL_STS0);
2141
2142         if (rc) {
2143                 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
2144                 retval = -EIO;
2145         }
2146
2147         rc = goya_stop_queue(hdev,
2148                         mmTPC3_CMDQ_GLBL_CFG1,
2149                         mmTPC3_CMDQ_CP_STS,
2150                         mmTPC3_CMDQ_GLBL_STS0);
2151
2152         if (rc) {
2153                 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
2154                 retval = -EIO;
2155         }
2156
2157         rc = goya_stop_queue(hdev,
2158                         mmTPC4_QM_GLBL_CFG1,
2159                         mmTPC4_QM_CP_STS,
2160                         mmTPC4_QM_GLBL_STS0);
2161
2162         if (rc) {
2163                 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
2164                 retval = -EIO;
2165         }
2166
2167         rc = goya_stop_queue(hdev,
2168                         mmTPC4_CMDQ_GLBL_CFG1,
2169                         mmTPC4_CMDQ_CP_STS,
2170                         mmTPC4_CMDQ_GLBL_STS0);
2171
2172         if (rc) {
2173                 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
2174                 retval = -EIO;
2175         }
2176
2177         rc = goya_stop_queue(hdev,
2178                         mmTPC5_QM_GLBL_CFG1,
2179                         mmTPC5_QM_CP_STS,
2180                         mmTPC5_QM_GLBL_STS0);
2181
2182         if (rc) {
2183                 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
2184                 retval = -EIO;
2185         }
2186
2187         rc = goya_stop_queue(hdev,
2188                         mmTPC5_CMDQ_GLBL_CFG1,
2189                         mmTPC5_CMDQ_CP_STS,
2190                         mmTPC5_CMDQ_GLBL_STS0);
2191
2192         if (rc) {
2193                 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
2194                 retval = -EIO;
2195         }
2196
2197         rc = goya_stop_queue(hdev,
2198                         mmTPC6_QM_GLBL_CFG1,
2199                         mmTPC6_QM_CP_STS,
2200                         mmTPC6_QM_GLBL_STS0);
2201
2202         if (rc) {
2203                 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
2204                 retval = -EIO;
2205         }
2206
2207         rc = goya_stop_queue(hdev,
2208                         mmTPC6_CMDQ_GLBL_CFG1,
2209                         mmTPC6_CMDQ_CP_STS,
2210                         mmTPC6_CMDQ_GLBL_STS0);
2211
2212         if (rc) {
2213                 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
2214                 retval = -EIO;
2215         }
2216
2217         rc = goya_stop_queue(hdev,
2218                         mmTPC7_QM_GLBL_CFG1,
2219                         mmTPC7_QM_CP_STS,
2220                         mmTPC7_QM_GLBL_STS0);
2221
2222         if (rc) {
2223                 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
2224                 retval = -EIO;
2225         }
2226
2227         rc = goya_stop_queue(hdev,
2228                         mmTPC7_CMDQ_GLBL_CFG1,
2229                         mmTPC7_CMDQ_CP_STS,
2230                         mmTPC7_CMDQ_GLBL_STS0);
2231
2232         if (rc) {
2233                 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
2234                 retval = -EIO;
2235         }
2236
2237         return retval;
2238 }
2239
2240 static void goya_dma_stall(struct hl_device *hdev)
2241 {
2242         struct goya_device *goya = hdev->asic_specific;
2243
2244         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
2245                 return;
2246
2247         WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2248         WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2249         WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2250         WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2251         WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2252 }
2253
2254 static void goya_tpc_stall(struct hl_device *hdev)
2255 {
2256         struct goya_device *goya = hdev->asic_specific;
2257
2258         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2259                 return;
2260
2261         WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2262         WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2263         WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2264         WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2265         WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2266         WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2267         WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2268         WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2269 }
2270
2271 static void goya_mme_stall(struct hl_device *hdev)
2272 {
2273         struct goya_device *goya = hdev->asic_specific;
2274
2275         if (!(goya->hw_cap_initialized & HW_CAP_MME))
2276                 return;
2277
2278         WREG32(mmMME_STALL, 0xFFFFFFFF);
2279 }
2280
2281 static int goya_enable_msix(struct hl_device *hdev)
2282 {
2283         struct goya_device *goya = hdev->asic_specific;
2284         int cq_cnt = hdev->asic_prop.completion_queues_count;
2285         int rc, i, irq_cnt_init, irq;
2286
2287         if (goya->hw_cap_initialized & HW_CAP_MSIX)
2288                 return 0;
2289
2290         rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
2291                                 GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX);
2292         if (rc < 0) {
2293                 dev_err(hdev->dev,
2294                         "MSI-X: Failed to enable support -- %d/%d\n",
2295                         GOYA_MSIX_ENTRIES, rc);
2296                 return rc;
2297         }
2298
2299         for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
2300                 irq = pci_irq_vector(hdev->pdev, i);
2301                 rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i],
2302                                 &hdev->completion_queue[i]);
2303                 if (rc) {
2304                         dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2305                         goto free_irqs;
2306                 }
2307         }
2308
2309         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2310
2311         rc = request_irq(irq, hl_irq_handler_eq, 0,
2312                         goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX],
2313                         &hdev->event_queue);
2314         if (rc) {
2315                 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2316                 goto free_irqs;
2317         }
2318
2319         goya->hw_cap_initialized |= HW_CAP_MSIX;
2320         return 0;
2321
2322 free_irqs:
2323         for (i = 0 ; i < irq_cnt_init ; i++)
2324                 free_irq(pci_irq_vector(hdev->pdev, i),
2325                         &hdev->completion_queue[i]);
2326
2327         pci_free_irq_vectors(hdev->pdev);
2328         return rc;
2329 }
2330
2331 static void goya_sync_irqs(struct hl_device *hdev)
2332 {
2333         struct goya_device *goya = hdev->asic_specific;
2334         int i;
2335
2336         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2337                 return;
2338
2339         /* Wait for all pending IRQs to be finished */
2340         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2341                 synchronize_irq(pci_irq_vector(hdev->pdev, i));
2342
2343         synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
2344 }
2345
2346 static void goya_disable_msix(struct hl_device *hdev)
2347 {
2348         struct goya_device *goya = hdev->asic_specific;
2349         int i, irq;
2350
2351         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2352                 return;
2353
2354         goya_sync_irqs(hdev);
2355
2356         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2357         free_irq(irq, &hdev->event_queue);
2358
2359         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2360                 irq = pci_irq_vector(hdev->pdev, i);
2361                 free_irq(irq, &hdev->completion_queue[i]);
2362         }
2363
2364         pci_free_irq_vectors(hdev->pdev);
2365
2366         goya->hw_cap_initialized &= ~HW_CAP_MSIX;
2367 }
2368
2369 static void goya_enable_timestamp(struct hl_device *hdev)
2370 {
2371         /* Disable the timestamp counter */
2372         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2373
2374         /* Zero the lower/upper parts of the 64-bit counter */
2375         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
2376         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
2377
2378         /* Enable the counter */
2379         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
2380 }
2381
2382 static void goya_disable_timestamp(struct hl_device *hdev)
2383 {
2384         /* Disable the timestamp counter */
2385         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2386 }
2387
2388 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2389 {
2390         u32 wait_timeout_ms;
2391
2392         dev_info(hdev->dev,
2393                 "Halting compute engines and disabling interrupts\n");
2394
2395         if (hdev->pldm)
2396                 wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2397         else
2398                 wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
2399
2400         goya_stop_external_queues(hdev);
2401         goya_stop_internal_queues(hdev);
2402
2403         msleep(wait_timeout_ms);
2404
2405         goya_dma_stall(hdev);
2406         goya_tpc_stall(hdev);
2407         goya_mme_stall(hdev);
2408
2409         msleep(wait_timeout_ms);
2410
2411         goya_disable_external_queues(hdev);
2412         goya_disable_internal_queues(hdev);
2413
2414         goya_disable_timestamp(hdev);
2415
2416         if (hard_reset) {
2417                 goya_disable_msix(hdev);
2418                 goya_mmu_remove_device_cpu_mappings(hdev);
2419         } else {
2420                 goya_sync_irqs(hdev);
2421         }
2422 }
2423
2424 /*
2425  * goya_load_firmware_to_device() - Load LINUX FW code to device.
2426  * @hdev: Pointer to hl_device structure.
2427  *
2428  * Copy LINUX fw code from firmware file to HBM BAR.
2429  *
2430  * Return: 0 on success, non-zero for failure.
2431  */
2432 static int goya_load_firmware_to_device(struct hl_device *hdev)
2433 {
2434         void __iomem *dst;
2435
2436         dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2437
2438         return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst, 0, 0);
2439 }
2440
2441 /*
2442  * goya_load_boot_fit_to_device() - Load boot fit to device.
2443  * @hdev: Pointer to hl_device structure.
2444  *
2445  * Copy boot fit file to SRAM BAR.
2446  *
2447  * Return: 0 on success, non-zero for failure.
2448  */
2449 static int goya_load_boot_fit_to_device(struct hl_device *hdev)
2450 {
2451         void __iomem *dst;
2452
2453         dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET;
2454
2455         return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst, 0, 0);
2456 }
2457
2458 static void goya_init_dynamic_firmware_loader(struct hl_device *hdev)
2459 {
2460         struct dynamic_fw_load_mgr *dynamic_loader;
2461         struct cpu_dyn_regs *dyn_regs;
2462
2463         dynamic_loader = &hdev->fw_loader.dynamic_loader;
2464
2465         /*
2466          * here we update initial values for few specific dynamic regs (as
2467          * before reading the first descriptor from FW those value has to be
2468          * hard-coded) in later stages of the protocol those values will be
2469          * updated automatically by reading the FW descriptor so data there
2470          * will always be up-to-date
2471          */
2472         dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs;
2473         dyn_regs->kmd_msg_to_cpu =
2474                                 cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
2475         dyn_regs->cpu_cmd_status_to_host =
2476                                 cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
2477
2478         dynamic_loader->wait_for_bl_timeout = GOYA_WAIT_FOR_BL_TIMEOUT_USEC;
2479 }
2480
2481 static void goya_init_static_firmware_loader(struct hl_device *hdev)
2482 {
2483         struct static_fw_load_mgr *static_loader;
2484
2485         static_loader = &hdev->fw_loader.static_loader;
2486
2487         static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2488         static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2489         static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU;
2490         static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST;
2491         static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
2492         static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0;
2493         static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1;
2494         static_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
2495         static_loader->boot_err1_reg = mmCPU_BOOT_ERR1;
2496         static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
2497         static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
2498         static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR));
2499 }
2500
2501 static void goya_init_firmware_loader(struct hl_device *hdev)
2502 {
2503         struct asic_fixed_properties *prop = &hdev->asic_prop;
2504         struct fw_load_mgr *fw_loader = &hdev->fw_loader;
2505
2506         /* fill common fields */
2507         fw_loader->linux_loaded = false;
2508         fw_loader->boot_fit_img.image_name = GOYA_BOOT_FIT_FILE;
2509         fw_loader->linux_img.image_name = GOYA_LINUX_FW_FILE;
2510         fw_loader->cpu_timeout = GOYA_CPU_TIMEOUT_USEC;
2511         fw_loader->boot_fit_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC;
2512         fw_loader->skip_bmc = false;
2513         fw_loader->sram_bar_id = SRAM_CFG_BAR_ID;
2514         fw_loader->dram_bar_id = DDR_BAR_ID;
2515
2516         if (prop->dynamic_fw_load)
2517                 goya_init_dynamic_firmware_loader(hdev);
2518         else
2519                 goya_init_static_firmware_loader(hdev);
2520 }
2521
2522 static int goya_init_cpu(struct hl_device *hdev)
2523 {
2524         struct goya_device *goya = hdev->asic_specific;
2525         int rc;
2526
2527         if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
2528                 return 0;
2529
2530         if (goya->hw_cap_initialized & HW_CAP_CPU)
2531                 return 0;
2532
2533         /*
2534          * Before pushing u-boot/linux to device, need to set the ddr bar to
2535          * base address of dram
2536          */
2537         if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
2538                 dev_err(hdev->dev,
2539                         "failed to map DDR bar to DRAM base address\n");
2540                 return -EIO;
2541         }
2542
2543         rc = hl_fw_init_cpu(hdev);
2544
2545         if (rc)
2546                 return rc;
2547
2548         goya->hw_cap_initialized |= HW_CAP_CPU;
2549
2550         return 0;
2551 }
2552
2553 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
2554                                                 u64 phys_addr)
2555 {
2556         u32 status, timeout_usec;
2557         int rc;
2558
2559         if (hdev->pldm)
2560                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
2561         else
2562                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
2563
2564         WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2565         WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2566         WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2567
2568         rc = hl_poll_timeout(
2569                 hdev,
2570                 MMU_ASID_BUSY,
2571                 status,
2572                 !(status & 0x80000000),
2573                 1000,
2574                 timeout_usec);
2575
2576         if (rc) {
2577                 dev_err(hdev->dev,
2578                         "Timeout during MMU hop0 config of asid %d\n", asid);
2579                 return rc;
2580         }
2581
2582         return 0;
2583 }
2584
2585 int goya_mmu_init(struct hl_device *hdev)
2586 {
2587         struct asic_fixed_properties *prop = &hdev->asic_prop;
2588         struct goya_device *goya = hdev->asic_specific;
2589         u64 hop0_addr;
2590         int rc, i;
2591
2592         if (!hdev->mmu_enable)
2593                 return 0;
2594
2595         if (goya->hw_cap_initialized & HW_CAP_MMU)
2596                 return 0;
2597
2598         hdev->dram_default_page_mapping = true;
2599
2600         for (i = 0 ; i < prop->max_asid ; i++) {
2601                 hop0_addr = prop->mmu_pgt_addr +
2602                                 (i * prop->mmu_hop_table_size);
2603
2604                 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2605                 if (rc) {
2606                         dev_err(hdev->dev,
2607                                 "failed to set hop0 addr for asid %d\n", i);
2608                         goto err;
2609                 }
2610         }
2611
2612         goya->hw_cap_initialized |= HW_CAP_MMU;
2613
2614         /* init MMU cache manage page */
2615         WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2616                                 lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
2617         WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2618
2619         /* Remove follower feature due to performance bug */
2620         WREG32_AND(mmSTLB_STLB_FEATURE_EN,
2621                         (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
2622
2623         hdev->asic_funcs->mmu_invalidate_cache(hdev, true,
2624                                         MMU_OP_USERPTR | MMU_OP_PHYS_PACK);
2625
2626         WREG32(mmMMU_MMU_ENABLE, 1);
2627         WREG32(mmMMU_SPI_MASK, 0xF);
2628
2629         return 0;
2630
2631 err:
2632         return rc;
2633 }
2634
2635 /*
2636  * goya_hw_init - Goya hardware initialization code
2637  *
2638  * @hdev: pointer to hl_device structure
2639  *
2640  * Returns 0 on success
2641  *
2642  */
2643 static int goya_hw_init(struct hl_device *hdev)
2644 {
2645         struct asic_fixed_properties *prop = &hdev->asic_prop;
2646         int rc;
2647
2648         /* Perform read from the device to make sure device is up */
2649         RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2650
2651         /*
2652          * Let's mark in the H/W that we have reached this point. We check
2653          * this value in the reset_before_init function to understand whether
2654          * we need to reset the chip before doing H/W init. This register is
2655          * cleared by the H/W upon H/W reset
2656          */
2657         WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2658
2659         rc = goya_init_cpu(hdev);
2660         if (rc) {
2661                 dev_err(hdev->dev, "failed to initialize CPU\n");
2662                 return rc;
2663         }
2664
2665         goya_tpc_mbist_workaround(hdev);
2666
2667         goya_init_golden_registers(hdev);
2668
2669         /*
2670          * After CPU initialization is finished, change DDR bar mapping inside
2671          * iATU to point to the start address of the MMU page tables
2672          */
2673         if (goya_set_ddr_bar_base(hdev, (MMU_PAGE_TABLES_ADDR &
2674                         ~(prop->dram_pci_bar_size - 0x1ull))) == U64_MAX) {
2675                 dev_err(hdev->dev,
2676                         "failed to map DDR bar to MMU page tables\n");
2677                 return -EIO;
2678         }
2679
2680         rc = goya_mmu_init(hdev);
2681         if (rc)
2682                 return rc;
2683
2684         goya_init_security(hdev);
2685
2686         goya_init_dma_qmans(hdev);
2687
2688         goya_init_mme_qmans(hdev);
2689
2690         goya_init_tpc_qmans(hdev);
2691
2692         goya_enable_timestamp(hdev);
2693
2694         /* MSI-X must be enabled before CPU queues are initialized */
2695         rc = goya_enable_msix(hdev);
2696         if (rc)
2697                 goto disable_queues;
2698
2699         /* Perform read from the device to flush all MSI-X configuration */
2700         RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2701
2702         return 0;
2703
2704 disable_queues:
2705         goya_disable_internal_queues(hdev);
2706         goya_disable_external_queues(hdev);
2707
2708         return rc;
2709 }
2710
2711 static void goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2712 {
2713         struct goya_device *goya = hdev->asic_specific;
2714         u32 reset_timeout_ms, cpu_timeout_ms, status;
2715
2716         if (hdev->pldm) {
2717                 reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
2718                 cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2719         } else {
2720                 reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
2721                 cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
2722         }
2723
2724         if (hard_reset) {
2725                 /* I don't know what is the state of the CPU so make sure it is
2726                  * stopped in any means necessary
2727                  */
2728                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2729                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2730                         GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
2731
2732                 msleep(cpu_timeout_ms);
2733
2734                 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2735                 goya_disable_clk_rlx(hdev);
2736                 goya_set_pll_refclk(hdev);
2737
2738                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2739                 dev_info(hdev->dev,
2740                         "Issued HARD reset command, going to wait %dms\n",
2741                         reset_timeout_ms);
2742         } else {
2743                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2744                 dev_info(hdev->dev,
2745                         "Issued SOFT reset command, going to wait %dms\n",
2746                         reset_timeout_ms);
2747         }
2748
2749         /*
2750          * After hard reset, we can't poll the BTM_FSM register because the PSOC
2751          * itself is in reset. In either reset we need to wait until the reset
2752          * is deasserted
2753          */
2754         msleep(reset_timeout_ms);
2755
2756         status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
2757         if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
2758                 dev_err(hdev->dev,
2759                         "Timeout while waiting for device to reset 0x%x\n",
2760                         status);
2761
2762         if (!hard_reset && goya) {
2763                 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
2764                                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2765                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2766                                 GOYA_ASYNC_EVENT_ID_SOFT_RESET);
2767                 return;
2768         }
2769
2770         /* Chicken bit to re-initiate boot sequencer flow */
2771         WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2772                 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT);
2773         /* Move boot manager FSM to pre boot sequencer init state */
2774         WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2775                         0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
2776
2777         if (goya) {
2778                 goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
2779                                 HW_CAP_DDR_0 | HW_CAP_DDR_1 |
2780                                 HW_CAP_DMA | HW_CAP_MME |
2781                                 HW_CAP_MMU | HW_CAP_TPC_MBIST |
2782                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2783
2784                 memset(goya->events_stat, 0, sizeof(goya->events_stat));
2785         }
2786 }
2787
2788 int goya_suspend(struct hl_device *hdev)
2789 {
2790         int rc;
2791
2792         rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS);
2793         if (rc)
2794                 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2795
2796         return rc;
2797 }
2798
2799 int goya_resume(struct hl_device *hdev)
2800 {
2801         return goya_init_iatu(hdev);
2802 }
2803
2804 static int goya_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2805                         void *cpu_addr, dma_addr_t dma_addr, size_t size)
2806 {
2807         int rc;
2808
2809         vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
2810                         VM_DONTCOPY | VM_NORESERVE;
2811
2812         rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr,
2813                                 (dma_addr - HOST_PHYS_BASE), size);
2814         if (rc)
2815                 dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
2816
2817         return rc;
2818 }
2819
2820 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2821 {
2822         u32 db_reg_offset, db_value;
2823
2824         switch (hw_queue_id) {
2825         case GOYA_QUEUE_ID_DMA_0:
2826                 db_reg_offset = mmDMA_QM_0_PQ_PI;
2827                 break;
2828
2829         case GOYA_QUEUE_ID_DMA_1:
2830                 db_reg_offset = mmDMA_QM_1_PQ_PI;
2831                 break;
2832
2833         case GOYA_QUEUE_ID_DMA_2:
2834                 db_reg_offset = mmDMA_QM_2_PQ_PI;
2835                 break;
2836
2837         case GOYA_QUEUE_ID_DMA_3:
2838                 db_reg_offset = mmDMA_QM_3_PQ_PI;
2839                 break;
2840
2841         case GOYA_QUEUE_ID_DMA_4:
2842                 db_reg_offset = mmDMA_QM_4_PQ_PI;
2843                 break;
2844
2845         case GOYA_QUEUE_ID_CPU_PQ:
2846                 db_reg_offset = mmCPU_IF_PF_PQ_PI;
2847                 break;
2848
2849         case GOYA_QUEUE_ID_MME:
2850                 db_reg_offset = mmMME_QM_PQ_PI;
2851                 break;
2852
2853         case GOYA_QUEUE_ID_TPC0:
2854                 db_reg_offset = mmTPC0_QM_PQ_PI;
2855                 break;
2856
2857         case GOYA_QUEUE_ID_TPC1:
2858                 db_reg_offset = mmTPC1_QM_PQ_PI;
2859                 break;
2860
2861         case GOYA_QUEUE_ID_TPC2:
2862                 db_reg_offset = mmTPC2_QM_PQ_PI;
2863                 break;
2864
2865         case GOYA_QUEUE_ID_TPC3:
2866                 db_reg_offset = mmTPC3_QM_PQ_PI;
2867                 break;
2868
2869         case GOYA_QUEUE_ID_TPC4:
2870                 db_reg_offset = mmTPC4_QM_PQ_PI;
2871                 break;
2872
2873         case GOYA_QUEUE_ID_TPC5:
2874                 db_reg_offset = mmTPC5_QM_PQ_PI;
2875                 break;
2876
2877         case GOYA_QUEUE_ID_TPC6:
2878                 db_reg_offset = mmTPC6_QM_PQ_PI;
2879                 break;
2880
2881         case GOYA_QUEUE_ID_TPC7:
2882                 db_reg_offset = mmTPC7_QM_PQ_PI;
2883                 break;
2884
2885         default:
2886                 /* Should never get here */
2887                 dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n",
2888                         hw_queue_id);
2889                 return;
2890         }
2891
2892         db_value = pi;
2893
2894         /* ring the doorbell */
2895         WREG32(db_reg_offset, db_value);
2896
2897         if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ) {
2898                 /* make sure device CPU will read latest data from host */
2899                 mb();
2900                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2901                                 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2902         }
2903 }
2904
2905 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
2906 {
2907         /* The QMANs are on the SRAM so need to copy to IO space */
2908         memcpy_toio((void __iomem *) pqe, bd, sizeof(struct hl_bd));
2909 }
2910
2911 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2912                                         dma_addr_t *dma_handle, gfp_t flags)
2913 {
2914         void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
2915                                                 dma_handle, flags);
2916
2917         /* Shift to the device's base physical address of host memory */
2918         if (kernel_addr)
2919                 *dma_handle += HOST_PHYS_BASE;
2920
2921         return kernel_addr;
2922 }
2923
2924 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
2925                                         void *cpu_addr, dma_addr_t dma_handle)
2926 {
2927         /* Cancel the device's base physical address of host memory */
2928         dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE;
2929
2930         dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
2931 }
2932
2933 int goya_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size)
2934 {
2935         return 0;
2936 }
2937
2938 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
2939                                 dma_addr_t *dma_handle, u16 *queue_len)
2940 {
2941         void *base;
2942         u32 offset;
2943
2944         *dma_handle = hdev->asic_prop.sram_base_address;
2945
2946         base = (__force void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
2947
2948         switch (queue_id) {
2949         case GOYA_QUEUE_ID_MME:
2950                 offset = MME_QMAN_BASE_OFFSET;
2951                 *queue_len = MME_QMAN_LENGTH;
2952                 break;
2953         case GOYA_QUEUE_ID_TPC0:
2954                 offset = TPC0_QMAN_BASE_OFFSET;
2955                 *queue_len = TPC_QMAN_LENGTH;
2956                 break;
2957         case GOYA_QUEUE_ID_TPC1:
2958                 offset = TPC1_QMAN_BASE_OFFSET;
2959                 *queue_len = TPC_QMAN_LENGTH;
2960                 break;
2961         case GOYA_QUEUE_ID_TPC2:
2962                 offset = TPC2_QMAN_BASE_OFFSET;
2963                 *queue_len = TPC_QMAN_LENGTH;
2964                 break;
2965         case GOYA_QUEUE_ID_TPC3:
2966                 offset = TPC3_QMAN_BASE_OFFSET;
2967                 *queue_len = TPC_QMAN_LENGTH;
2968                 break;
2969         case GOYA_QUEUE_ID_TPC4:
2970                 offset = TPC4_QMAN_BASE_OFFSET;
2971                 *queue_len = TPC_QMAN_LENGTH;
2972                 break;
2973         case GOYA_QUEUE_ID_TPC5:
2974                 offset = TPC5_QMAN_BASE_OFFSET;
2975                 *queue_len = TPC_QMAN_LENGTH;
2976                 break;
2977         case GOYA_QUEUE_ID_TPC6:
2978                 offset = TPC6_QMAN_BASE_OFFSET;
2979                 *queue_len = TPC_QMAN_LENGTH;
2980                 break;
2981         case GOYA_QUEUE_ID_TPC7:
2982                 offset = TPC7_QMAN_BASE_OFFSET;
2983                 *queue_len = TPC_QMAN_LENGTH;
2984                 break;
2985         default:
2986                 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
2987                 return NULL;
2988         }
2989
2990         base += offset;
2991         *dma_handle += offset;
2992
2993         return base;
2994 }
2995
2996 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
2997 {
2998         struct packet_msg_prot *fence_pkt;
2999         u32 *fence_ptr;
3000         dma_addr_t fence_dma_addr;
3001         struct hl_cb *cb;
3002         u32 tmp, timeout;
3003         int rc;
3004
3005         if (hdev->pldm)
3006                 timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC;
3007         else
3008                 timeout = HL_DEVICE_TIMEOUT_USEC;
3009
3010         if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) {
3011                 dev_err_ratelimited(hdev->dev,
3012                         "Can't send driver job on QMAN0 because the device is not idle\n");
3013                 return -EBUSY;
3014         }
3015
3016         fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3017                                                         &fence_dma_addr);
3018         if (!fence_ptr) {
3019                 dev_err(hdev->dev,
3020                         "Failed to allocate fence memory for QMAN0\n");
3021                 return -ENOMEM;
3022         }
3023
3024         goya_qman0_set_security(hdev, true);
3025
3026         cb = job->patched_cb;
3027
3028         fence_pkt = cb->kernel_address +
3029                         job->job_cb_size - sizeof(struct packet_msg_prot);
3030
3031         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3032                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3033                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3034         fence_pkt->ctl = cpu_to_le32(tmp);
3035         fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
3036         fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3037
3038         rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
3039                                         job->job_cb_size, cb->bus_address);
3040         if (rc) {
3041                 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
3042                 goto free_fence_ptr;
3043         }
3044
3045         rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp,
3046                                 (tmp == GOYA_QMAN0_FENCE_VAL), 1000,
3047                                 timeout, true);
3048
3049         hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
3050
3051         if (rc == -ETIMEDOUT) {
3052                 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp);
3053                 goto free_fence_ptr;
3054         }
3055
3056 free_fence_ptr:
3057         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
3058                                         fence_dma_addr);
3059
3060         goya_qman0_set_security(hdev, false);
3061
3062         return rc;
3063 }
3064
3065 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
3066                                 u32 timeout, u64 *result)
3067 {
3068         struct goya_device *goya = hdev->asic_specific;
3069
3070         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) {
3071                 if (result)
3072                         *result = 0;
3073                 return 0;
3074         }
3075
3076         if (!timeout)
3077                 timeout = GOYA_MSG_TO_CPU_TIMEOUT_USEC;
3078
3079         return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len,
3080                                         timeout, result);
3081 }
3082
3083 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
3084 {
3085         struct packet_msg_prot *fence_pkt;
3086         dma_addr_t pkt_dma_addr;
3087         u32 fence_val, tmp;
3088         dma_addr_t fence_dma_addr;
3089         u32 *fence_ptr;
3090         int rc;
3091
3092         fence_val = GOYA_QMAN0_FENCE_VAL;
3093
3094         fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3095                                                         &fence_dma_addr);
3096         if (!fence_ptr) {
3097                 dev_err(hdev->dev,
3098                         "Failed to allocate memory for H/W queue %d testing\n",
3099                         hw_queue_id);
3100                 return -ENOMEM;
3101         }
3102
3103         *fence_ptr = 0;
3104
3105         fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev,
3106                                         sizeof(struct packet_msg_prot),
3107                                         GFP_KERNEL, &pkt_dma_addr);
3108         if (!fence_pkt) {
3109                 dev_err(hdev->dev,
3110                         "Failed to allocate packet for H/W queue %d testing\n",
3111                         hw_queue_id);
3112                 rc = -ENOMEM;
3113                 goto free_fence_ptr;
3114         }
3115
3116         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3117                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3118                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3119         fence_pkt->ctl = cpu_to_le32(tmp);
3120         fence_pkt->value = cpu_to_le32(fence_val);
3121         fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3122
3123         rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
3124                                         sizeof(struct packet_msg_prot),
3125                                         pkt_dma_addr);
3126         if (rc) {
3127                 dev_err(hdev->dev,
3128                         "Failed to send fence packet to H/W queue %d\n",
3129                         hw_queue_id);
3130                 goto free_pkt;
3131         }
3132
3133         rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val),
3134                                         1000, GOYA_TEST_QUEUE_WAIT_USEC, true);
3135
3136         hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
3137
3138         if (rc == -ETIMEDOUT) {
3139                 dev_err(hdev->dev,
3140                         "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
3141                         hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
3142                 rc = -EIO;
3143         }
3144
3145 free_pkt:
3146         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt,
3147                                         pkt_dma_addr);
3148 free_fence_ptr:
3149         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
3150                                         fence_dma_addr);
3151         return rc;
3152 }
3153
3154 int goya_test_cpu_queue(struct hl_device *hdev)
3155 {
3156         struct goya_device *goya = hdev->asic_specific;
3157
3158         /*
3159          * check capability here as send_cpu_message() won't update the result
3160          * value if no capability
3161          */
3162         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
3163                 return 0;
3164
3165         return hl_fw_test_cpu_queue(hdev);
3166 }
3167
3168 int goya_test_queues(struct hl_device *hdev)
3169 {
3170         int i, rc, ret_val = 0;
3171
3172         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
3173                 rc = goya_test_queue(hdev, i);
3174                 if (rc)
3175                         ret_val = -EINVAL;
3176         }
3177
3178         return ret_val;
3179 }
3180
3181 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3182                                         gfp_t mem_flags, dma_addr_t *dma_handle)
3183 {
3184         void *kernel_addr;
3185
3186         if (size > GOYA_DMA_POOL_BLK_SIZE)
3187                 return NULL;
3188
3189         kernel_addr =  dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3190
3191         /* Shift to the device's base physical address of host memory */
3192         if (kernel_addr)
3193                 *dma_handle += HOST_PHYS_BASE;
3194
3195         return kernel_addr;
3196 }
3197
3198 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3199                                 dma_addr_t dma_addr)
3200 {
3201         /* Cancel the device's base physical address of host memory */
3202         dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE;
3203
3204         dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
3205 }
3206
3207 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
3208                                         dma_addr_t *dma_handle)
3209 {
3210         void *vaddr;
3211
3212         vaddr = hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
3213         *dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address +
3214                         VA_CPU_ACCESSIBLE_MEM_ADDR;
3215
3216         return vaddr;
3217 }
3218
3219 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
3220                                         void *vaddr)
3221 {
3222         hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
3223 }
3224
3225 static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sgl,
3226                                 int nents, enum dma_data_direction dir)
3227 {
3228         struct scatterlist *sg;
3229         int i;
3230
3231         if (!dma_map_sg(&hdev->pdev->dev, sgl, nents, dir))
3232                 return -ENOMEM;
3233
3234         /* Shift to the device's base physical address of host memory */
3235         for_each_sg(sgl, sg, nents, i)
3236                 sg->dma_address += HOST_PHYS_BASE;
3237
3238         return 0;
3239 }
3240
3241 static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sgl,
3242                                 int nents, enum dma_data_direction dir)
3243 {
3244         struct scatterlist *sg;
3245         int i;
3246
3247         /* Cancel the device's base physical address of host memory */
3248         for_each_sg(sgl, sg, nents, i)
3249                 sg->dma_address -= HOST_PHYS_BASE;
3250
3251         dma_unmap_sg(&hdev->pdev->dev, sgl, nents, dir);
3252 }
3253
3254 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3255 {
3256         struct scatterlist *sg, *sg_next_iter;
3257         u32 count, dma_desc_cnt;
3258         u64 len, len_next;
3259         dma_addr_t addr, addr_next;
3260
3261         dma_desc_cnt = 0;
3262
3263         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3264
3265                 len = sg_dma_len(sg);
3266                 addr = sg_dma_address(sg);
3267
3268                 if (len == 0)
3269                         break;
3270
3271                 while ((count + 1) < sgt->nents) {
3272                         sg_next_iter = sg_next(sg);
3273                         len_next = sg_dma_len(sg_next_iter);
3274                         addr_next = sg_dma_address(sg_next_iter);
3275
3276                         if (len_next == 0)
3277                                 break;
3278
3279                         if ((addr + len == addr_next) &&
3280                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3281                                 len += len_next;
3282                                 count++;
3283                                 sg = sg_next_iter;
3284                         } else {
3285                                 break;
3286                         }
3287                 }
3288
3289                 dma_desc_cnt++;
3290         }
3291
3292         return dma_desc_cnt * sizeof(struct packet_lin_dma);
3293 }
3294
3295 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3296                                 struct hl_cs_parser *parser,
3297                                 struct packet_lin_dma *user_dma_pkt,
3298                                 u64 addr, enum dma_data_direction dir)
3299 {
3300         struct hl_userptr *userptr;
3301         int rc;
3302
3303         if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3304                         parser->job_userptr_list, &userptr))
3305                 goto already_pinned;
3306
3307         userptr = kzalloc(sizeof(*userptr), GFP_KERNEL);
3308         if (!userptr)
3309                 return -ENOMEM;
3310
3311         rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3312                                 userptr);
3313         if (rc)
3314                 goto free_userptr;
3315
3316         list_add_tail(&userptr->job_node, parser->job_userptr_list);
3317
3318         rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl,
3319                                         userptr->sgt->nents, dir);
3320         if (rc) {
3321                 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3322                 goto unpin_memory;
3323         }
3324
3325         userptr->dma_mapped = true;
3326         userptr->dir = dir;
3327
3328 already_pinned:
3329         parser->patched_cb_size +=
3330                         goya_get_dma_desc_list_size(hdev, userptr->sgt);
3331
3332         return 0;
3333
3334 unpin_memory:
3335         list_del(&userptr->job_node);
3336         hl_unpin_host_memory(hdev, userptr);
3337 free_userptr:
3338         kfree(userptr);
3339         return rc;
3340 }
3341
3342 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3343                                 struct hl_cs_parser *parser,
3344                                 struct packet_lin_dma *user_dma_pkt)
3345 {
3346         u64 device_memory_addr, addr;
3347         enum dma_data_direction dir;
3348         enum goya_dma_direction user_dir;
3349         bool sram_addr = true;
3350         bool skip_host_mem_pin = false;
3351         bool user_memset;
3352         u32 ctl;
3353         int rc = 0;
3354
3355         ctl = le32_to_cpu(user_dma_pkt->ctl);
3356
3357         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3358                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3359
3360         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3361                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3362
3363         switch (user_dir) {
3364         case DMA_HOST_TO_DRAM:
3365                 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3366                 dir = DMA_TO_DEVICE;
3367                 sram_addr = false;
3368                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3369                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3370                 if (user_memset)
3371                         skip_host_mem_pin = true;
3372                 break;
3373
3374         case DMA_DRAM_TO_HOST:
3375                 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3376                 dir = DMA_FROM_DEVICE;
3377                 sram_addr = false;
3378                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3379                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3380                 break;
3381
3382         case DMA_HOST_TO_SRAM:
3383                 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3384                 dir = DMA_TO_DEVICE;
3385                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3386                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3387                 if (user_memset)
3388                         skip_host_mem_pin = true;
3389                 break;
3390
3391         case DMA_SRAM_TO_HOST:
3392                 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3393                 dir = DMA_FROM_DEVICE;
3394                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3395                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3396                 break;
3397         default:
3398                 dev_err(hdev->dev, "DMA direction is undefined\n");
3399                 return -EFAULT;
3400         }
3401
3402         if (sram_addr) {
3403                 if (!hl_mem_area_inside_range(device_memory_addr,
3404                                 le32_to_cpu(user_dma_pkt->tsize),
3405                                 hdev->asic_prop.sram_user_base_address,
3406                                 hdev->asic_prop.sram_end_address)) {
3407
3408                         dev_err(hdev->dev,
3409                                 "SRAM address 0x%llx + 0x%x is invalid\n",
3410                                 device_memory_addr,
3411                                 user_dma_pkt->tsize);
3412                         return -EFAULT;
3413                 }
3414         } else {
3415                 if (!hl_mem_area_inside_range(device_memory_addr,
3416                                 le32_to_cpu(user_dma_pkt->tsize),
3417                                 hdev->asic_prop.dram_user_base_address,
3418                                 hdev->asic_prop.dram_end_address)) {
3419
3420                         dev_err(hdev->dev,
3421                                 "DRAM address 0x%llx + 0x%x is invalid\n",
3422                                 device_memory_addr,
3423                                 user_dma_pkt->tsize);
3424                         return -EFAULT;
3425                 }
3426         }
3427
3428         if (skip_host_mem_pin)
3429                 parser->patched_cb_size += sizeof(*user_dma_pkt);
3430         else {
3431                 if ((dir == DMA_TO_DEVICE) &&
3432                                 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) {
3433                         dev_err(hdev->dev,
3434                                 "Can't DMA from host on queue other then 1\n");
3435                         return -EFAULT;
3436                 }
3437
3438                 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3439                                                 addr, dir);
3440         }
3441
3442         return rc;
3443 }
3444
3445 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3446                                 struct hl_cs_parser *parser,
3447                                 struct packet_lin_dma *user_dma_pkt)
3448 {
3449         u64 sram_memory_addr, dram_memory_addr;
3450         enum goya_dma_direction user_dir;
3451         u32 ctl;
3452
3453         ctl = le32_to_cpu(user_dma_pkt->ctl);
3454         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3455                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3456
3457         if (user_dir == DMA_DRAM_TO_SRAM) {
3458                 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3459                 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3460                 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3461         } else {
3462                 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3463                 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3464                 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3465         }
3466
3467         if (!hl_mem_area_inside_range(sram_memory_addr,
3468                                 le32_to_cpu(user_dma_pkt->tsize),
3469                                 hdev->asic_prop.sram_user_base_address,
3470                                 hdev->asic_prop.sram_end_address)) {
3471                 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3472                         sram_memory_addr, user_dma_pkt->tsize);
3473                 return -EFAULT;
3474         }
3475
3476         if (!hl_mem_area_inside_range(dram_memory_addr,
3477                                 le32_to_cpu(user_dma_pkt->tsize),
3478                                 hdev->asic_prop.dram_user_base_address,
3479                                 hdev->asic_prop.dram_end_address)) {
3480                 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3481                         dram_memory_addr, user_dma_pkt->tsize);
3482                 return -EFAULT;
3483         }
3484
3485         parser->patched_cb_size += sizeof(*user_dma_pkt);
3486
3487         return 0;
3488 }
3489
3490 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3491                                 struct hl_cs_parser *parser,
3492                                 struct packet_lin_dma *user_dma_pkt)
3493 {
3494         enum goya_dma_direction user_dir;
3495         u32 ctl;
3496         int rc;
3497
3498         dev_dbg(hdev->dev, "DMA packet details:\n");
3499         dev_dbg(hdev->dev, "source == 0x%llx\n",
3500                 le64_to_cpu(user_dma_pkt->src_addr));
3501         dev_dbg(hdev->dev, "destination == 0x%llx\n",
3502                 le64_to_cpu(user_dma_pkt->dst_addr));
3503         dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3504
3505         ctl = le32_to_cpu(user_dma_pkt->ctl);
3506         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3507                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3508
3509         /*
3510          * Special handling for DMA with size 0. The H/W has a bug where
3511          * this can cause the QMAN DMA to get stuck, so block it here.
3512          */
3513         if (user_dma_pkt->tsize == 0) {
3514                 dev_err(hdev->dev,
3515                         "Got DMA with size 0, might reset the device\n");
3516                 return -EINVAL;
3517         }
3518
3519         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM))
3520                 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3521         else
3522                 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3523
3524         return rc;
3525 }
3526
3527 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3528                                 struct hl_cs_parser *parser,
3529                                 struct packet_lin_dma *user_dma_pkt)
3530 {
3531         dev_dbg(hdev->dev, "DMA packet details:\n");
3532         dev_dbg(hdev->dev, "source == 0x%llx\n",
3533                 le64_to_cpu(user_dma_pkt->src_addr));
3534         dev_dbg(hdev->dev, "destination == 0x%llx\n",
3535                 le64_to_cpu(user_dma_pkt->dst_addr));
3536         dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3537
3538         /*
3539          * WA for HW-23.
3540          * We can't allow user to read from Host using QMANs other than 1.
3541          * PMMU and HPMMU addresses are equal, check only one of them.
3542          */
3543         if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 &&
3544                 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr),
3545                                 le32_to_cpu(user_dma_pkt->tsize),
3546                                 hdev->asic_prop.pmmu.start_addr,
3547                                 hdev->asic_prop.pmmu.end_addr)) {
3548                 dev_err(hdev->dev,
3549                         "Can't DMA from host on queue other then 1\n");
3550                 return -EFAULT;
3551         }
3552
3553         if (user_dma_pkt->tsize == 0) {
3554                 dev_err(hdev->dev,
3555                         "Got DMA with size 0, might reset the device\n");
3556                 return -EINVAL;
3557         }
3558
3559         parser->patched_cb_size += sizeof(*user_dma_pkt);
3560
3561         return 0;
3562 }
3563
3564 static int goya_validate_wreg32(struct hl_device *hdev,
3565                                 struct hl_cs_parser *parser,
3566                                 struct packet_wreg32 *wreg_pkt)
3567 {
3568         struct goya_device *goya = hdev->asic_specific;
3569         u32 sob_start_addr, sob_end_addr;
3570         u16 reg_offset;
3571
3572         reg_offset = le32_to_cpu(wreg_pkt->ctl) &
3573                         GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK;
3574
3575         dev_dbg(hdev->dev, "WREG32 packet details:\n");
3576         dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3577         dev_dbg(hdev->dev, "value      == 0x%x\n",
3578                 le32_to_cpu(wreg_pkt->value));
3579
3580         if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3581                 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3582                         reg_offset);
3583                 return -EPERM;
3584         }
3585
3586         /*
3587          * With MMU, DMA channels are not secured, so it doesn't matter where
3588          * the WR COMP will be written to because it will go out with
3589          * non-secured property
3590          */
3591         if (goya->hw_cap_initialized & HW_CAP_MMU)
3592                 return 0;
3593
3594         sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
3595         sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023);
3596
3597         if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) ||
3598                         (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) {
3599
3600                 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3601                         wreg_pkt->value);
3602                 return -EPERM;
3603         }
3604
3605         return 0;
3606 }
3607
3608 static int goya_validate_cb(struct hl_device *hdev,
3609                         struct hl_cs_parser *parser, bool is_mmu)
3610 {
3611         u32 cb_parsed_length = 0;
3612         int rc = 0;
3613
3614         parser->patched_cb_size = 0;
3615
3616         /* cb_user_size is more than 0 so loop will always be executed */
3617         while (cb_parsed_length < parser->user_cb_size) {
3618                 enum packet_id pkt_id;
3619                 u16 pkt_size;
3620                 struct goya_packet *user_pkt;
3621
3622                 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3623
3624                 pkt_id = (enum packet_id) (
3625                                 (le64_to_cpu(user_pkt->header) &
3626                                 PACKET_HEADER_PACKET_ID_MASK) >>
3627                                         PACKET_HEADER_PACKET_ID_SHIFT);
3628
3629                 if (!validate_packet_id(pkt_id)) {
3630                         dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3631                         rc = -EINVAL;
3632                         break;
3633                 }
3634
3635                 pkt_size = goya_packet_sizes[pkt_id];
3636                 cb_parsed_length += pkt_size;
3637                 if (cb_parsed_length > parser->user_cb_size) {
3638                         dev_err(hdev->dev,
3639                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3640                         rc = -EINVAL;
3641                         break;
3642                 }
3643
3644                 switch (pkt_id) {
3645                 case PACKET_WREG_32:
3646                         /*
3647                          * Although it is validated after copy in patch_cb(),
3648                          * need to validate here as well because patch_cb() is
3649                          * not called in MMU path while this function is called
3650                          */
3651                         rc = goya_validate_wreg32(hdev,
3652                                 parser, (struct packet_wreg32 *) user_pkt);
3653                         parser->patched_cb_size += pkt_size;
3654                         break;
3655
3656                 case PACKET_WREG_BULK:
3657                         dev_err(hdev->dev,
3658                                 "User not allowed to use WREG_BULK\n");
3659                         rc = -EPERM;
3660                         break;
3661
3662                 case PACKET_MSG_PROT:
3663                         dev_err(hdev->dev,
3664                                 "User not allowed to use MSG_PROT\n");
3665                         rc = -EPERM;
3666                         break;
3667
3668                 case PACKET_CP_DMA:
3669                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3670                         rc = -EPERM;
3671                         break;
3672
3673                 case PACKET_STOP:
3674                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3675                         rc = -EPERM;
3676                         break;
3677
3678                 case PACKET_LIN_DMA:
3679                         if (is_mmu)
3680                                 rc = goya_validate_dma_pkt_mmu(hdev, parser,
3681                                         (struct packet_lin_dma *) user_pkt);
3682                         else
3683                                 rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3684                                         (struct packet_lin_dma *) user_pkt);
3685                         break;
3686
3687                 case PACKET_MSG_LONG:
3688                 case PACKET_MSG_SHORT:
3689                 case PACKET_FENCE:
3690                 case PACKET_NOP:
3691                         parser->patched_cb_size += pkt_size;
3692                         break;
3693
3694                 default:
3695                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3696                                 pkt_id);
3697                         rc = -EINVAL;
3698                         break;
3699                 }
3700
3701                 if (rc)
3702                         break;
3703         }
3704
3705         /*
3706          * The new CB should have space at the end for two MSG_PROT packets:
3707          * 1. A packet that will act as a completion packet
3708          * 2. A packet that will generate MSI-X interrupt
3709          */
3710         parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
3711
3712         return rc;
3713 }
3714
3715 static int goya_patch_dma_packet(struct hl_device *hdev,
3716                                 struct hl_cs_parser *parser,
3717                                 struct packet_lin_dma *user_dma_pkt,
3718                                 struct packet_lin_dma *new_dma_pkt,
3719                                 u32 *new_dma_pkt_size)
3720 {
3721         struct hl_userptr *userptr;
3722         struct scatterlist *sg, *sg_next_iter;
3723         u32 count, dma_desc_cnt;
3724         u64 len, len_next;
3725         dma_addr_t dma_addr, dma_addr_next;
3726         enum goya_dma_direction user_dir;
3727         u64 device_memory_addr, addr;
3728         enum dma_data_direction dir;
3729         struct sg_table *sgt;
3730         bool skip_host_mem_pin = false;
3731         bool user_memset;
3732         u32 user_rdcomp_mask, user_wrcomp_mask, ctl;
3733
3734         ctl = le32_to_cpu(user_dma_pkt->ctl);
3735
3736         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3737                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3738
3739         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3740                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3741
3742         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) ||
3743                         (user_dma_pkt->tsize == 0)) {
3744                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
3745                 *new_dma_pkt_size = sizeof(*new_dma_pkt);
3746                 return 0;
3747         }
3748
3749         if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) {
3750                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3751                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3752                 dir = DMA_TO_DEVICE;
3753                 if (user_memset)
3754                         skip_host_mem_pin = true;
3755         } else {
3756                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3757                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3758                 dir = DMA_FROM_DEVICE;
3759         }
3760
3761         if ((!skip_host_mem_pin) &&
3762                 (hl_userptr_is_pinned(hdev, addr,
3763                         le32_to_cpu(user_dma_pkt->tsize),
3764                         parser->job_userptr_list, &userptr) == false)) {
3765                 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3766                                 addr, user_dma_pkt->tsize);
3767                 return -EFAULT;
3768         }
3769
3770         if ((user_memset) && (dir == DMA_TO_DEVICE)) {
3771                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
3772                 *new_dma_pkt_size = sizeof(*user_dma_pkt);
3773                 return 0;
3774         }
3775
3776         user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK;
3777
3778         user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK;
3779
3780         sgt = userptr->sgt;
3781         dma_desc_cnt = 0;
3782
3783         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3784                 len = sg_dma_len(sg);
3785                 dma_addr = sg_dma_address(sg);
3786
3787                 if (len == 0)
3788                         break;
3789
3790                 while ((count + 1) < sgt->nents) {
3791                         sg_next_iter = sg_next(sg);
3792                         len_next = sg_dma_len(sg_next_iter);
3793                         dma_addr_next = sg_dma_address(sg_next_iter);
3794
3795                         if (len_next == 0)
3796                                 break;
3797
3798                         if ((dma_addr + len == dma_addr_next) &&
3799                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3800                                 len += len_next;
3801                                 count++;
3802                                 sg = sg_next_iter;
3803                         } else {
3804                                 break;
3805                         }
3806                 }
3807
3808                 ctl = le32_to_cpu(user_dma_pkt->ctl);
3809                 if (likely(dma_desc_cnt))
3810                         ctl &= ~GOYA_PKT_CTL_EB_MASK;
3811                 ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK |
3812                                 GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK);
3813                 new_dma_pkt->ctl = cpu_to_le32(ctl);
3814                 new_dma_pkt->tsize = cpu_to_le32((u32) len);
3815
3816                 if (dir == DMA_TO_DEVICE) {
3817                         new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
3818                         new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
3819                 } else {
3820                         new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
3821                         new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
3822                 }
3823
3824                 if (!user_memset)
3825                         device_memory_addr += len;
3826                 dma_desc_cnt++;
3827                 new_dma_pkt++;
3828         }
3829
3830         if (!dma_desc_cnt) {
3831                 dev_err(hdev->dev,
3832                         "Error of 0 SG entries when patching DMA packet\n");
3833                 return -EFAULT;
3834         }
3835
3836         /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */
3837         new_dma_pkt--;
3838         new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask);
3839
3840         *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
3841
3842         return 0;
3843 }
3844
3845 static int goya_patch_cb(struct hl_device *hdev,
3846                                 struct hl_cs_parser *parser)
3847 {
3848         u32 cb_parsed_length = 0;
3849         u32 cb_patched_cur_length = 0;
3850         int rc = 0;
3851
3852         /* cb_user_size is more than 0 so loop will always be executed */
3853         while (cb_parsed_length < parser->user_cb_size) {
3854                 enum packet_id pkt_id;
3855                 u16 pkt_size;
3856                 u32 new_pkt_size = 0;
3857                 struct goya_packet *user_pkt, *kernel_pkt;
3858
3859                 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3860                 kernel_pkt = parser->patched_cb->kernel_address +
3861                                         cb_patched_cur_length;
3862
3863                 pkt_id = (enum packet_id) (
3864                                 (le64_to_cpu(user_pkt->header) &
3865                                 PACKET_HEADER_PACKET_ID_MASK) >>
3866                                         PACKET_HEADER_PACKET_ID_SHIFT);
3867
3868                 if (!validate_packet_id(pkt_id)) {
3869                         dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3870                         rc = -EINVAL;
3871                         break;
3872                 }
3873
3874                 pkt_size = goya_packet_sizes[pkt_id];
3875                 cb_parsed_length += pkt_size;
3876                 if (cb_parsed_length > parser->user_cb_size) {
3877                         dev_err(hdev->dev,
3878                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3879                         rc = -EINVAL;
3880                         break;
3881                 }
3882
3883                 switch (pkt_id) {
3884                 case PACKET_LIN_DMA:
3885                         rc = goya_patch_dma_packet(hdev, parser,
3886                                         (struct packet_lin_dma *) user_pkt,
3887                                         (struct packet_lin_dma *) kernel_pkt,
3888                                         &new_pkt_size);
3889                         cb_patched_cur_length += new_pkt_size;
3890                         break;
3891
3892                 case PACKET_WREG_32:
3893                         memcpy(kernel_pkt, user_pkt, pkt_size);
3894                         cb_patched_cur_length += pkt_size;
3895                         rc = goya_validate_wreg32(hdev, parser,
3896                                         (struct packet_wreg32 *) kernel_pkt);
3897                         break;
3898
3899                 case PACKET_WREG_BULK:
3900                         dev_err(hdev->dev,
3901                                 "User not allowed to use WREG_BULK\n");
3902                         rc = -EPERM;
3903                         break;
3904
3905                 case PACKET_MSG_PROT:
3906                         dev_err(hdev->dev,
3907                                 "User not allowed to use MSG_PROT\n");
3908                         rc = -EPERM;
3909                         break;
3910
3911                 case PACKET_CP_DMA:
3912                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3913                         rc = -EPERM;
3914                         break;
3915
3916                 case PACKET_STOP:
3917                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3918                         rc = -EPERM;
3919                         break;
3920
3921                 case PACKET_MSG_LONG:
3922                 case PACKET_MSG_SHORT:
3923                 case PACKET_FENCE:
3924                 case PACKET_NOP:
3925                         memcpy(kernel_pkt, user_pkt, pkt_size);
3926                         cb_patched_cur_length += pkt_size;
3927                         break;
3928
3929                 default:
3930                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3931                                 pkt_id);
3932                         rc = -EINVAL;
3933                         break;
3934                 }
3935
3936                 if (rc)
3937                         break;
3938         }
3939
3940         return rc;
3941 }
3942
3943 static int goya_parse_cb_mmu(struct hl_device *hdev,
3944                 struct hl_cs_parser *parser)
3945 {
3946         u64 patched_cb_handle;
3947         u32 patched_cb_size;
3948         struct hl_cb *user_cb;
3949         int rc;
3950
3951         /*
3952          * The new CB should have space at the end for two MSG_PROT pkt:
3953          * 1. A packet that will act as a completion packet
3954          * 2. A packet that will generate MSI-X interrupt
3955          */
3956         parser->patched_cb_size = parser->user_cb_size +
3957                         sizeof(struct packet_msg_prot) * 2;
3958
3959         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
3960                                 parser->patched_cb_size, false, false,
3961                                 &patched_cb_handle);
3962
3963         if (rc) {
3964                 dev_err(hdev->dev,
3965                         "Failed to allocate patched CB for DMA CS %d\n",
3966                         rc);
3967                 return rc;
3968         }
3969
3970         patched_cb_handle >>= PAGE_SHIFT;
3971         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
3972                                 (u32) patched_cb_handle);
3973         /* hl_cb_get should never fail here */
3974         if (!parser->patched_cb) {
3975                 dev_crit(hdev->dev, "DMA CB handle invalid 0x%x\n",
3976                         (u32) patched_cb_handle);
3977                 rc = -EFAULT;
3978                 goto out;
3979         }
3980
3981         /*
3982          * The check that parser->user_cb_size <= parser->user_cb->size was done
3983          * in validate_queue_index().
3984          */
3985         memcpy(parser->patched_cb->kernel_address,
3986                 parser->user_cb->kernel_address,
3987                 parser->user_cb_size);
3988
3989         patched_cb_size = parser->patched_cb_size;
3990
3991         /* validate patched CB instead of user CB */
3992         user_cb = parser->user_cb;
3993         parser->user_cb = parser->patched_cb;
3994         rc = goya_validate_cb(hdev, parser, true);
3995         parser->user_cb = user_cb;
3996
3997         if (rc) {
3998                 hl_cb_put(parser->patched_cb);
3999                 goto out;
4000         }
4001
4002         if (patched_cb_size != parser->patched_cb_size) {
4003                 dev_err(hdev->dev, "user CB size mismatch\n");
4004                 hl_cb_put(parser->patched_cb);
4005                 rc = -EINVAL;
4006                 goto out;
4007         }
4008
4009 out:
4010         /*
4011          * Always call cb destroy here because we still have 1 reference
4012          * to it by calling cb_get earlier. After the job will be completed,
4013          * cb_put will release it, but here we want to remove it from the
4014          * idr
4015          */
4016         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4017                                         patched_cb_handle << PAGE_SHIFT);
4018
4019         return rc;
4020 }
4021
4022 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
4023                                 struct hl_cs_parser *parser)
4024 {
4025         u64 patched_cb_handle;
4026         int rc;
4027
4028         rc = goya_validate_cb(hdev, parser, false);
4029
4030         if (rc)
4031                 goto free_userptr;
4032
4033         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
4034                                 parser->patched_cb_size, false, false,
4035                                 &patched_cb_handle);
4036         if (rc) {
4037                 dev_err(hdev->dev,
4038                         "Failed to allocate patched CB for DMA CS %d\n", rc);
4039                 goto free_userptr;
4040         }
4041
4042         patched_cb_handle >>= PAGE_SHIFT;
4043         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
4044                                 (u32) patched_cb_handle);
4045         /* hl_cb_get should never fail here */
4046         if (!parser->patched_cb) {
4047                 dev_crit(hdev->dev, "DMA CB handle invalid 0x%x\n",
4048                         (u32) patched_cb_handle);
4049                 rc = -EFAULT;
4050                 goto out;
4051         }
4052
4053         rc = goya_patch_cb(hdev, parser);
4054
4055         if (rc)
4056                 hl_cb_put(parser->patched_cb);
4057
4058 out:
4059         /*
4060          * Always call cb destroy here because we still have 1 reference
4061          * to it by calling cb_get earlier. After the job will be completed,
4062          * cb_put will release it, but here we want to remove it from the
4063          * idr
4064          */
4065         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4066                                 patched_cb_handle << PAGE_SHIFT);
4067
4068 free_userptr:
4069         if (rc)
4070                 hl_userptr_delete_list(hdev, parser->job_userptr_list);
4071         return rc;
4072 }
4073
4074 static int goya_parse_cb_no_ext_queue(struct hl_device *hdev,
4075                                         struct hl_cs_parser *parser)
4076 {
4077         struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
4078         struct goya_device *goya = hdev->asic_specific;
4079
4080         if (goya->hw_cap_initialized & HW_CAP_MMU)
4081                 return 0;
4082
4083         /* For internal queue jobs, just check if CB address is valid */
4084         if (hl_mem_area_inside_range(
4085                         (u64) (uintptr_t) parser->user_cb,
4086                         parser->user_cb_size,
4087                         asic_prop->sram_user_base_address,
4088                         asic_prop->sram_end_address))
4089                 return 0;
4090
4091         if (hl_mem_area_inside_range(
4092                         (u64) (uintptr_t) parser->user_cb,
4093                         parser->user_cb_size,
4094                         asic_prop->dram_user_base_address,
4095                         asic_prop->dram_end_address))
4096                 return 0;
4097
4098         dev_err(hdev->dev,
4099                 "Internal CB address 0x%px + 0x%x is not in SRAM nor in DRAM\n",
4100                 parser->user_cb, parser->user_cb_size);
4101
4102         return -EFAULT;
4103 }
4104
4105 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
4106 {
4107         struct goya_device *goya = hdev->asic_specific;
4108
4109         if (parser->queue_type == QUEUE_TYPE_INT)
4110                 return goya_parse_cb_no_ext_queue(hdev, parser);
4111
4112         if (goya->hw_cap_initialized & HW_CAP_MMU)
4113                 return goya_parse_cb_mmu(hdev, parser);
4114         else
4115                 return goya_parse_cb_no_mmu(hdev, parser);
4116 }
4117
4118 void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
4119                                 u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec,
4120                                 bool eb)
4121 {
4122         struct packet_msg_prot *cq_pkt;
4123         u32 tmp;
4124
4125         cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2);
4126
4127         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4128                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
4129                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4130         cq_pkt->ctl = cpu_to_le32(tmp);
4131         cq_pkt->value = cpu_to_le32(cq_val);
4132         cq_pkt->addr = cpu_to_le64(cq_addr);
4133
4134         cq_pkt++;
4135
4136         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4137                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4138         cq_pkt->ctl = cpu_to_le32(tmp);
4139         cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF);
4140         cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF);
4141 }
4142
4143 void goya_update_eq_ci(struct hl_device *hdev, u32 val)
4144 {
4145         WREG32(mmCPU_EQ_CI, val);
4146 }
4147
4148 void goya_restore_phase_topology(struct hl_device *hdev)
4149 {
4150
4151 }
4152
4153 static void goya_clear_sm_regs(struct hl_device *hdev)
4154 {
4155         int i, num_of_sob_in_longs, num_of_mon_in_longs;
4156
4157         num_of_sob_in_longs =
4158                 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4);
4159
4160         num_of_mon_in_longs =
4161                 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4);
4162
4163         for (i = 0 ; i < num_of_sob_in_longs ; i += 4)
4164                 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4165
4166         for (i = 0 ; i < num_of_mon_in_longs ; i += 4)
4167                 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4168
4169         /* Flush all WREG to prevent race */
4170         i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
4171 }
4172
4173 /*
4174  * goya_debugfs_read32 - read a 32bit value from a given device or a host mapped
4175  *                       address.
4176  *
4177  * @hdev:       pointer to hl_device structure
4178  * @addr:       device or host mapped address
4179  * @val:        returned value
4180  *
4181  * In case of DDR address that is not mapped into the default aperture that
4182  * the DDR bar exposes, the function will configure the iATU so that the DDR
4183  * bar will be positioned at a base address that allows reading from the
4184  * required address. Configuring the iATU during normal operation can
4185  * lead to undefined behavior and therefore, should be done with extreme care
4186  *
4187  */
4188 static int goya_debugfs_read32(struct hl_device *hdev, u64 addr,
4189                         bool user_address, u32 *val)
4190 {
4191         struct asic_fixed_properties *prop = &hdev->asic_prop;
4192         u64 ddr_bar_addr, host_phys_end;
4193         int rc = 0;
4194
4195         host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4196
4197         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4198                 *val = RREG32(addr - CFG_BASE);
4199
4200         } else if ((addr >= SRAM_BASE_ADDR) &&
4201                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4202
4203                 *val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4204                                 (addr - SRAM_BASE_ADDR));
4205
4206         } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
4207
4208                 u64 bar_base_addr = DRAM_PHYS_BASE +
4209                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4210
4211                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4212                 if (ddr_bar_addr != U64_MAX) {
4213                         *val = readl(hdev->pcie_bar[DDR_BAR_ID] +
4214                                                 (addr - bar_base_addr));
4215
4216                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4217                                                         ddr_bar_addr);
4218                 }
4219                 if (ddr_bar_addr == U64_MAX)
4220                         rc = -EIO;
4221
4222         } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4223                         user_address && !iommu_present(&pci_bus_type)) {
4224                 *val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);
4225
4226         } else {
4227                 rc = -EFAULT;
4228         }
4229
4230         return rc;
4231 }
4232
4233 /*
4234  * goya_debugfs_write32 - write a 32bit value to a given device or a host mapped
4235  *                        address.
4236  *
4237  * @hdev:       pointer to hl_device structure
4238  * @addr:       device or host mapped address
4239  * @val:        returned value
4240  *
4241  * In case of DDR address that is not mapped into the default aperture that
4242  * the DDR bar exposes, the function will configure the iATU so that the DDR
4243  * bar will be positioned at a base address that allows writing to the
4244  * required address. Configuring the iATU during normal operation can
4245  * lead to undefined behavior and therefore, should be done with extreme care
4246  *
4247  */
4248 static int goya_debugfs_write32(struct hl_device *hdev, u64 addr,
4249                         bool user_address, u32 val)
4250 {
4251         struct asic_fixed_properties *prop = &hdev->asic_prop;
4252         u64 ddr_bar_addr, host_phys_end;
4253         int rc = 0;
4254
4255         host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4256
4257         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4258                 WREG32(addr - CFG_BASE, val);
4259
4260         } else if ((addr >= SRAM_BASE_ADDR) &&
4261                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4262
4263                 writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4264                                         (addr - SRAM_BASE_ADDR));
4265
4266         } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
4267
4268                 u64 bar_base_addr = DRAM_PHYS_BASE +
4269                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4270
4271                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4272                 if (ddr_bar_addr != U64_MAX) {
4273                         writel(val, hdev->pcie_bar[DDR_BAR_ID] +
4274                                                 (addr - bar_base_addr));
4275
4276                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4277                                                         ddr_bar_addr);
4278                 }
4279                 if (ddr_bar_addr == U64_MAX)
4280                         rc = -EIO;
4281
4282         } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4283                         user_address && !iommu_present(&pci_bus_type)) {
4284                 *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
4285
4286         } else {
4287                 rc = -EFAULT;
4288         }
4289
4290         return rc;
4291 }
4292
4293 static int goya_debugfs_read64(struct hl_device *hdev, u64 addr,
4294                         bool user_address, u64 *val)
4295 {
4296         struct asic_fixed_properties *prop = &hdev->asic_prop;
4297         u64 ddr_bar_addr, host_phys_end;
4298         int rc = 0;
4299
4300         host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4301
4302         if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
4303                 u32 val_l = RREG32(addr - CFG_BASE);
4304                 u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);
4305
4306                 *val = (((u64) val_h) << 32) | val_l;
4307
4308         } else if ((addr >= SRAM_BASE_ADDR) &&
4309                         (addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
4310
4311                 *val = readq(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4312                                 (addr - SRAM_BASE_ADDR));
4313
4314         } else if (addr <=
4315                    DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
4316
4317                 u64 bar_base_addr = DRAM_PHYS_BASE +
4318                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4319
4320                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4321                 if (ddr_bar_addr != U64_MAX) {
4322                         *val = readq(hdev->pcie_bar[DDR_BAR_ID] +
4323                                                 (addr - bar_base_addr));
4324
4325                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4326                                                         ddr_bar_addr);
4327                 }
4328                 if (ddr_bar_addr == U64_MAX)
4329                         rc = -EIO;
4330
4331         } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4332                         user_address && !iommu_present(&pci_bus_type)) {
4333                 *val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);
4334
4335         } else {
4336                 rc = -EFAULT;
4337         }
4338
4339         return rc;
4340 }
4341
4342 static int goya_debugfs_write64(struct hl_device *hdev, u64 addr,
4343                                 bool user_address, u64 val)
4344 {
4345         struct asic_fixed_properties *prop = &hdev->asic_prop;
4346         u64 ddr_bar_addr, host_phys_end;
4347         int rc = 0;
4348
4349         host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4350
4351         if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
4352                 WREG32(addr - CFG_BASE, lower_32_bits(val));
4353                 WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));
4354
4355         } else if ((addr >= SRAM_BASE_ADDR) &&
4356                         (addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
4357
4358                 writeq(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4359                                         (addr - SRAM_BASE_ADDR));
4360
4361         } else if (addr <=
4362                    DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
4363
4364                 u64 bar_base_addr = DRAM_PHYS_BASE +
4365                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4366
4367                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4368                 if (ddr_bar_addr != U64_MAX) {
4369                         writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4370                                                 (addr - bar_base_addr));
4371
4372                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4373                                                         ddr_bar_addr);
4374                 }
4375                 if (ddr_bar_addr == U64_MAX)
4376                         rc = -EIO;
4377
4378         } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4379                         user_address && !iommu_present(&pci_bus_type)) {
4380                 *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
4381
4382         } else {
4383                 rc = -EFAULT;
4384         }
4385
4386         return rc;
4387 }
4388
4389 static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size,
4390                                 void *blob_addr)
4391 {
4392         dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n");
4393         return -EPERM;
4394 }
4395
4396 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4397 {
4398         struct goya_device *goya = hdev->asic_specific;
4399
4400         if (hdev->hard_reset_pending)
4401                 return U64_MAX;
4402
4403         return readq(hdev->pcie_bar[DDR_BAR_ID] +
4404                         (addr - goya->ddr_bar_cur_addr));
4405 }
4406
4407 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4408 {
4409         struct goya_device *goya = hdev->asic_specific;
4410
4411         if (hdev->hard_reset_pending)
4412                 return;
4413
4414         writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4415                         (addr - goya->ddr_bar_cur_addr));
4416 }
4417
4418 static const char *_goya_get_event_desc(u16 event_type)
4419 {
4420         switch (event_type) {
4421         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4422                 return "PCIe_if";
4423         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4424         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4425         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4426         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4427         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4428         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4429         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4430         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4431                 return "TPC%d_ecc";
4432         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4433                 return "MME_ecc";
4434         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4435                 return "MME_ecc_ext";
4436         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4437                 return "MMU_ecc";
4438         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4439                 return "DMA_macro";
4440         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4441                 return "DMA_ecc";
4442         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4443                 return "CPU_if_ecc";
4444         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4445                 return "PSOC_mem";
4446         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4447                 return "PSOC_coresight";
4448         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4449                 return "SRAM%d";
4450         case GOYA_ASYNC_EVENT_ID_GIC500:
4451                 return "GIC500";
4452         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4453                 return "PLL%d";
4454         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4455                 return "AXI_ecc";
4456         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4457                 return "L2_ram_ecc";
4458         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4459                 return "PSOC_gpio_05_sw_reset";
4460         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4461                 return "PSOC_gpio_10_vrhot_icrit";
4462         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4463                 return "PCIe_dec";
4464         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4465         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4466         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4467         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4468         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4469         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4470         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4471         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4472                 return "TPC%d_dec";
4473         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4474                 return "MME_wacs";
4475         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4476                 return "MME_wacsd";
4477         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4478                 return "CPU_axi_splitter";
4479         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4480                 return "PSOC_axi_dec";
4481         case GOYA_ASYNC_EVENT_ID_PSOC:
4482                 return "PSOC";
4483         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4484         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4485         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4486         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4487         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4488         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4489         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4490         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4491                 return "TPC%d_krn_err";
4492         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4493                 return "TPC%d_cq";
4494         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4495                 return "TPC%d_qm";
4496         case GOYA_ASYNC_EVENT_ID_MME_QM:
4497                 return "MME_qm";
4498         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4499                 return "MME_cq";
4500         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4501                 return "DMA%d_qm";
4502         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4503                 return "DMA%d_ch";
4504         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4505         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4506         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4507         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4508         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4509         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4510         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4511         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4512                 return "TPC%d_bmon_spmu";
4513         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4514                 return "DMA_bm_ch%d";
4515         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4516                 return "POWER_ENV_S";
4517         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4518                 return "POWER_ENV_E";
4519         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4520                 return "THERMAL_ENV_S";
4521         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4522                 return "THERMAL_ENV_E";
4523         case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4524                 return "QUEUE_OUT_OF_SYNC";
4525         default:
4526                 return "N/A";
4527         }
4528 }
4529
4530 static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
4531 {
4532         u8 index;
4533
4534         switch (event_type) {
4535         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4536         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4537         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4538         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4539         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4540         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4541         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4542         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4543                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_ECC) / 3;
4544                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4545                 break;
4546         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4547                 index = event_type - GOYA_ASYNC_EVENT_ID_SRAM0;
4548                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4549                 break;
4550         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4551                 index = event_type - GOYA_ASYNC_EVENT_ID_PLL0;
4552                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4553                 break;
4554         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4555         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4556         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4557         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4558         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4559         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4560         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4561         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4562                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3;
4563                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4564                 break;
4565         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4566         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4567         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4568         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4569         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4570         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4571         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4572         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4573                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10;
4574                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4575                 break;
4576         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4577                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ;
4578                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4579                 break;
4580         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4581                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM;
4582                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4583                 break;
4584         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4585                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM;
4586                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4587                 break;
4588         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4589                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH;
4590                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4591                 break;
4592         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4593         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4594         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4595         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4596         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4597         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4598         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4599         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4600                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU) / 10;
4601                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4602                 break;
4603         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4604                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0;
4605                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4606                 break;
4607         case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4608                 snprintf(desc, size, _goya_get_event_desc(event_type));
4609                 break;
4610         default:
4611                 snprintf(desc, size, _goya_get_event_desc(event_type));
4612                 break;
4613         }
4614 }
4615
4616 static void goya_print_razwi_info(struct hl_device *hdev)
4617 {
4618         if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {
4619                 dev_err_ratelimited(hdev->dev, "Illegal write to LBW\n");
4620                 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4621         }
4622
4623         if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {
4624                 dev_err_ratelimited(hdev->dev, "Illegal read from LBW\n");
4625                 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4626         }
4627
4628         if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {
4629                 dev_err_ratelimited(hdev->dev, "Illegal write to HBW\n");
4630                 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4631         }
4632
4633         if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {
4634                 dev_err_ratelimited(hdev->dev, "Illegal read from HBW\n");
4635                 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4636         }
4637 }
4638
4639 static void goya_print_mmu_error_info(struct hl_device *hdev)
4640 {
4641         struct goya_device *goya = hdev->asic_specific;
4642         u64 addr;
4643         u32 val;
4644
4645         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4646                 return;
4647
4648         val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4649         if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4650                 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4651                 addr <<= 32;
4652                 addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);
4653
4654                 dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n",
4655                                         addr);
4656
4657                 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4658         }
4659 }
4660
4661 static void goya_print_out_of_sync_info(struct hl_device *hdev,
4662                                         struct cpucp_pkt_sync_err *sync_err)
4663 {
4664         struct hl_hw_queue *q = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
4665
4666         dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%u\n",
4667                         sync_err->pi, sync_err->ci, q->pi, atomic_read(&q->ci));
4668 }
4669
4670 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type,
4671                                 bool razwi)
4672 {
4673         char desc[20] = "";
4674
4675         goya_get_event_desc(event_type, desc, sizeof(desc));
4676         dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4677                 event_type, desc);
4678
4679         if (razwi) {
4680                 goya_print_razwi_info(hdev);
4681                 goya_print_mmu_error_info(hdev);
4682         }
4683 }
4684
4685 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4686                 size_t irq_arr_size)
4687 {
4688         struct cpucp_unmask_irq_arr_packet *pkt;
4689         size_t total_pkt_size;
4690         u64 result;
4691         int rc;
4692         int irq_num_entries, irq_arr_index;
4693         __le32 *goya_irq_arr;
4694
4695         total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) +
4696                         irq_arr_size;
4697
4698         /* data should be aligned to 8 bytes in order to CPU-CP to copy it */
4699         total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
4700
4701         /* total_pkt_size is casted to u16 later on */
4702         if (total_pkt_size > USHRT_MAX) {
4703                 dev_err(hdev->dev, "too many elements in IRQ array\n");
4704                 return -EINVAL;
4705         }
4706
4707         pkt = kzalloc(total_pkt_size, GFP_KERNEL);
4708         if (!pkt)
4709                 return -ENOMEM;
4710
4711         irq_num_entries = irq_arr_size / sizeof(irq_arr[0]);
4712         pkt->length = cpu_to_le32(irq_num_entries);
4713
4714         /* We must perform any necessary endianness conversation on the irq
4715          * array being passed to the goya hardware
4716          */
4717         for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs;
4718                         irq_arr_index < irq_num_entries ; irq_arr_index++)
4719                 goya_irq_arr[irq_arr_index] =
4720                                 cpu_to_le32(irq_arr[irq_arr_index]);
4721
4722         pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4723                                                 CPUCP_PKT_CTL_OPCODE_SHIFT);
4724
4725         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
4726                                                 total_pkt_size, 0, &result);
4727
4728         if (rc)
4729                 dev_err(hdev->dev, "failed to unmask IRQ array\n");
4730
4731         kfree(pkt);
4732
4733         return rc;
4734 }
4735
4736 static int goya_soft_reset_late_init(struct hl_device *hdev)
4737 {
4738         /*
4739          * Unmask all IRQs since some could have been received
4740          * during the soft reset
4741          */
4742         return goya_unmask_irq_arr(hdev, goya_all_events,
4743                                         sizeof(goya_all_events));
4744 }
4745
4746 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4747 {
4748         struct cpucp_packet pkt;
4749         u64 result;
4750         int rc;
4751
4752         memset(&pkt, 0, sizeof(pkt));
4753
4754         pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ <<
4755                                 CPUCP_PKT_CTL_OPCODE_SHIFT);
4756         pkt.value = cpu_to_le64(event_type);
4757
4758         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4759                                                 0, &result);
4760
4761         if (rc)
4762                 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4763
4764         return rc;
4765 }
4766
4767 static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type)
4768 {
4769         switch (event_type) {
4770         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4771                 hdev->clk_throttling_reason |= HL_CLK_THROTTLE_POWER;
4772                 dev_info_ratelimited(hdev->dev,
4773                         "Clock throttling due to power consumption\n");
4774                 break;
4775         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4776                 hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_POWER;
4777                 dev_info_ratelimited(hdev->dev,
4778                         "Power envelop is safe, back to optimal clock\n");
4779                 break;
4780         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4781                 hdev->clk_throttling_reason |= HL_CLK_THROTTLE_THERMAL;
4782                 dev_info_ratelimited(hdev->dev,
4783                         "Clock throttling due to overheating\n");
4784                 break;
4785         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4786                 hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_THERMAL;
4787                 dev_info_ratelimited(hdev->dev,
4788                         "Thermal envelop is safe, back to optimal clock\n");
4789                 break;
4790
4791         default:
4792                 dev_err(hdev->dev, "Received invalid clock change event %d\n",
4793                         event_type);
4794                 break;
4795         }
4796 }
4797
4798 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4799 {
4800         u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
4801         u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
4802                                 >> EQ_CTL_EVENT_TYPE_SHIFT);
4803         struct goya_device *goya = hdev->asic_specific;
4804
4805         if (event_type >= GOYA_ASYNC_EVENT_ID_SIZE) {
4806                 dev_err(hdev->dev, "Event type %u exceeds maximum of %u",
4807                                 event_type, GOYA_ASYNC_EVENT_ID_SIZE - 1);
4808                 return;
4809         }
4810
4811         goya->events_stat[event_type]++;
4812         goya->events_stat_aggregate[event_type]++;
4813
4814         switch (event_type) {
4815         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4816         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4817         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4818         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4819         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4820         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4821         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4822         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4823         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4824         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4825         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4826         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4827         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4828         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4829         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4830         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4831         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4832         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4833         case GOYA_ASYNC_EVENT_ID_GIC500:
4834         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4835         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4836         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4837                 goya_print_irq_info(hdev, event_type, false);
4838                 if (hdev->hard_reset_on_fw_events)
4839                         hl_device_reset(hdev, (HL_RESET_HARD |
4840                                                 HL_RESET_FW_FATAL_ERR));
4841                 break;
4842
4843         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4844                 goya_print_irq_info(hdev, event_type, false);
4845                 if (hdev->hard_reset_on_fw_events)
4846                         hl_device_reset(hdev, HL_RESET_HARD);
4847                 break;
4848
4849         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4850         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4851         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4852         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4853         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4854         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4855         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4856         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4857         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4858         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4859         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4860         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4861         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4862         case GOYA_ASYNC_EVENT_ID_PSOC:
4863         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4864         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4865         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4866         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4867         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4868         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4869         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4870         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4871         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4872         case GOYA_ASYNC_EVENT_ID_MME_QM:
4873         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4874         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4875         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4876                 goya_print_irq_info(hdev, event_type, true);
4877                 goya_unmask_irq(hdev, event_type);
4878                 break;
4879
4880         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4881         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4882         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4883         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4884         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4885         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4886         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4887         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4888         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4889         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4890                 goya_print_irq_info(hdev, event_type, false);
4891                 goya_unmask_irq(hdev, event_type);
4892                 break;
4893
4894         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4895         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4896         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4897         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4898                 goya_print_clk_change_info(hdev, event_type);
4899                 goya_unmask_irq(hdev, event_type);
4900                 break;
4901
4902         case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4903                 goya_print_irq_info(hdev, event_type, false);
4904                 goya_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err);
4905                 if (hdev->hard_reset_on_fw_events)
4906                         hl_device_reset(hdev, HL_RESET_HARD);
4907                 else
4908                         hl_fw_unmask_irq(hdev, event_type);
4909                 break;
4910
4911         default:
4912                 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
4913                                 event_type);
4914                 break;
4915         }
4916 }
4917
4918 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size)
4919 {
4920         struct goya_device *goya = hdev->asic_specific;
4921
4922         if (aggregate) {
4923                 *size = (u32) sizeof(goya->events_stat_aggregate);
4924                 return goya->events_stat_aggregate;
4925         }
4926
4927         *size = (u32) sizeof(goya->events_stat);
4928         return goya->events_stat;
4929 }
4930
4931 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
4932                                 u64 val, bool is_dram)
4933 {
4934         struct packet_lin_dma *lin_dma_pkt;
4935         struct hl_cs_job *job;
4936         u32 cb_size, ctl;
4937         struct hl_cb *cb;
4938         int rc, lin_dma_pkts_cnt;
4939
4940         lin_dma_pkts_cnt = DIV_ROUND_UP_ULL(size, SZ_2G);
4941         cb_size = lin_dma_pkts_cnt * sizeof(struct packet_lin_dma) +
4942                                                 sizeof(struct packet_msg_prot);
4943         cb = hl_cb_kernel_create(hdev, cb_size, false);
4944         if (!cb)
4945                 return -ENOMEM;
4946
4947         lin_dma_pkt = cb->kernel_address;
4948
4949         do {
4950                 memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
4951
4952                 ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) |
4953                                 (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |
4954                                 (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
4955                                 (1 << GOYA_PKT_CTL_RB_SHIFT) |
4956                                 (1 << GOYA_PKT_CTL_MB_SHIFT));
4957                 ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) <<
4958                                 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
4959                 lin_dma_pkt->ctl = cpu_to_le32(ctl);
4960
4961                 lin_dma_pkt->src_addr = cpu_to_le64(val);
4962                 lin_dma_pkt->dst_addr = cpu_to_le64(addr);
4963                 if (lin_dma_pkts_cnt > 1)
4964                         lin_dma_pkt->tsize = cpu_to_le32(SZ_2G);
4965                 else
4966                         lin_dma_pkt->tsize = cpu_to_le32(size);
4967
4968                 size -= SZ_2G;
4969                 addr += SZ_2G;
4970                 lin_dma_pkt++;
4971         } while (--lin_dma_pkts_cnt);
4972
4973         job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
4974         if (!job) {
4975                 dev_err(hdev->dev, "Failed to allocate a new job\n");
4976                 rc = -ENOMEM;
4977                 goto release_cb;
4978         }
4979
4980         job->id = 0;
4981         job->user_cb = cb;
4982         atomic_inc(&job->user_cb->cs_cnt);
4983         job->user_cb_size = cb_size;
4984         job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
4985         job->patched_cb = job->user_cb;
4986         job->job_cb_size = job->user_cb_size;
4987
4988         hl_debugfs_add_job(hdev, job);
4989
4990         rc = goya_send_job_on_qman0(hdev, job);
4991
4992         hl_debugfs_remove_job(hdev, job);
4993         kfree(job);
4994         atomic_dec(&cb->cs_cnt);
4995
4996 release_cb:
4997         hl_cb_put(cb);
4998         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
4999
5000         return rc;
5001 }
5002
5003 int goya_context_switch(struct hl_device *hdev, u32 asid)
5004 {
5005         struct asic_fixed_properties *prop = &hdev->asic_prop;
5006         u64 addr = prop->sram_base_address, sob_addr;
5007         u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
5008         u64 val = 0x7777777777777777ull;
5009         int rc, dma_id;
5010         u32 channel_off = mmDMA_CH_1_WR_COMP_ADDR_LO -
5011                                         mmDMA_CH_0_WR_COMP_ADDR_LO;
5012
5013         rc = goya_memset_device_memory(hdev, addr, size, val, false);
5014         if (rc) {
5015                 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
5016                 return rc;
5017         }
5018
5019         /* we need to reset registers that the user is allowed to change */
5020         sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
5021         WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr));
5022
5023         for (dma_id = 1 ; dma_id < NUMBER_OF_EXT_HW_QUEUES ; dma_id++) {
5024                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
5025                                                         (dma_id - 1) * 4;
5026                 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id,
5027                                                 lower_32_bits(sob_addr));
5028         }
5029
5030         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
5031
5032         goya_clear_sm_regs(hdev);
5033
5034         return 0;
5035 }
5036
5037 static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
5038 {
5039         struct asic_fixed_properties *prop = &hdev->asic_prop;
5040         struct goya_device *goya = hdev->asic_specific;
5041         u64 addr = prop->mmu_pgt_addr;
5042         u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE +
5043                         MMU_CACHE_MNG_SIZE;
5044
5045         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5046                 return 0;
5047
5048         return goya_memset_device_memory(hdev, addr, size, 0, true);
5049 }
5050
5051 static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
5052 {
5053         struct goya_device *goya = hdev->asic_specific;
5054         u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
5055         u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE;
5056         u64 val = 0x9999999999999999ull;
5057
5058         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5059                 return 0;
5060
5061         return goya_memset_device_memory(hdev, addr, size, val, true);
5062 }
5063
5064 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
5065 {
5066         struct asic_fixed_properties *prop = &hdev->asic_prop;
5067         struct goya_device *goya = hdev->asic_specific;
5068         s64 off, cpu_off;
5069         int rc;
5070
5071         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5072                 return 0;
5073
5074         for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB) {
5075                 rc = hl_mmu_map_page(hdev->kernel_ctx,
5076                         prop->dram_base_address + off,
5077                         prop->dram_base_address + off, PAGE_SIZE_2MB,
5078                         (off + PAGE_SIZE_2MB) == CPU_FW_IMAGE_SIZE);
5079                 if (rc) {
5080                         dev_err(hdev->dev, "Map failed for address 0x%llx\n",
5081                                 prop->dram_base_address + off);
5082                         goto unmap;
5083                 }
5084         }
5085
5086         if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
5087                 rc = hl_mmu_map_page(hdev->kernel_ctx,
5088                         VA_CPU_ACCESSIBLE_MEM_ADDR,
5089                         hdev->cpu_accessible_dma_address,
5090                         PAGE_SIZE_2MB, true);
5091
5092                 if (rc) {
5093                         dev_err(hdev->dev,
5094                                 "Map failed for CPU accessible memory\n");
5095                         off -= PAGE_SIZE_2MB;
5096                         goto unmap;
5097                 }
5098         } else {
5099                 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB) {
5100                         rc = hl_mmu_map_page(hdev->kernel_ctx,
5101                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5102                                 hdev->cpu_accessible_dma_address + cpu_off,
5103                                 PAGE_SIZE_4KB, true);
5104                         if (rc) {
5105                                 dev_err(hdev->dev,
5106                                         "Map failed for CPU accessible memory\n");
5107                                 cpu_off -= PAGE_SIZE_4KB;
5108                                 goto unmap_cpu;
5109                         }
5110                 }
5111         }
5112
5113         goya_mmu_prepare_reg(hdev, mmCPU_IF_ARUSER_OVR, HL_KERNEL_ASID_ID);
5114         goya_mmu_prepare_reg(hdev, mmCPU_IF_AWUSER_OVR, HL_KERNEL_ASID_ID);
5115         WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF);
5116         WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF);
5117
5118         /* Make sure configuration is flushed to device */
5119         RREG32(mmCPU_IF_AWUSER_OVR_EN);
5120
5121         goya->device_cpu_mmu_mappings_done = true;
5122
5123         return 0;
5124
5125 unmap_cpu:
5126         for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB)
5127                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5128                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5129                                 PAGE_SIZE_4KB, true))
5130                         dev_warn_ratelimited(hdev->dev,
5131                                 "failed to unmap address 0x%llx\n",
5132                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
5133 unmap:
5134         for (; off >= 0 ; off -= PAGE_SIZE_2MB)
5135                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5136                                 prop->dram_base_address + off, PAGE_SIZE_2MB,
5137                                 true))
5138                         dev_warn_ratelimited(hdev->dev,
5139                                 "failed to unmap address 0x%llx\n",
5140                                 prop->dram_base_address + off);
5141
5142         return rc;
5143 }
5144
5145 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev)
5146 {
5147         struct asic_fixed_properties *prop = &hdev->asic_prop;
5148         struct goya_device *goya = hdev->asic_specific;
5149         u32 off, cpu_off;
5150
5151         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5152                 return;
5153
5154         if (!goya->device_cpu_mmu_mappings_done)
5155                 return;
5156
5157         WREG32(mmCPU_IF_ARUSER_OVR_EN, 0);
5158         WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
5159
5160         if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
5161                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5162                                 VA_CPU_ACCESSIBLE_MEM_ADDR,
5163                                 PAGE_SIZE_2MB, true))
5164                         dev_warn(hdev->dev,
5165                                 "Failed to unmap CPU accessible memory\n");
5166         } else {
5167                 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB)
5168                         if (hl_mmu_unmap_page(hdev->kernel_ctx,
5169                                         VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5170                                         PAGE_SIZE_4KB,
5171                                         (cpu_off + PAGE_SIZE_4KB) >= SZ_2M))
5172                                 dev_warn_ratelimited(hdev->dev,
5173                                         "failed to unmap address 0x%llx\n",
5174                                         VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
5175         }
5176
5177         for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB)
5178                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5179                                 prop->dram_base_address + off, PAGE_SIZE_2MB,
5180                                 (off + PAGE_SIZE_2MB) >= CPU_FW_IMAGE_SIZE))
5181                         dev_warn_ratelimited(hdev->dev,
5182                                         "Failed to unmap address 0x%llx\n",
5183                                         prop->dram_base_address + off);
5184
5185         goya->device_cpu_mmu_mappings_done = false;
5186 }
5187
5188 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
5189 {
5190         struct goya_device *goya = hdev->asic_specific;
5191         int i;
5192
5193         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5194                 return;
5195
5196         if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
5197                 dev_crit(hdev->dev, "asid %u is too big\n", asid);
5198                 return;
5199         }
5200
5201         /* zero the MMBP and ASID bits and then set the ASID */
5202         for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++)
5203                 goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
5204 }
5205
5206 static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
5207                                         u32 flags)
5208 {
5209         struct goya_device *goya = hdev->asic_specific;
5210         u32 status, timeout_usec;
5211         int rc;
5212
5213         if (!(goya->hw_cap_initialized & HW_CAP_MMU) ||
5214                 hdev->hard_reset_pending)
5215                 return 0;
5216
5217         /* no need in L1 only invalidation in Goya */
5218         if (!is_hard)
5219                 return 0;
5220
5221         if (hdev->pldm)
5222                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
5223         else
5224                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
5225
5226         /* L0 & L1 invalidation */
5227         WREG32(mmSTLB_INV_ALL_START, 1);
5228
5229         rc = hl_poll_timeout(
5230                 hdev,
5231                 mmSTLB_INV_ALL_START,
5232                 status,
5233                 !status,
5234                 1000,
5235                 timeout_usec);
5236
5237         if (rc) {
5238                 dev_err_ratelimited(hdev->dev,
5239                                         "MMU cache invalidation timeout\n");
5240                 hl_device_reset(hdev, HL_RESET_HARD);
5241         }
5242
5243         return rc;
5244 }
5245
5246 static int goya_mmu_invalidate_cache_range(struct hl_device *hdev,
5247                                                 bool is_hard, u32 flags,
5248                                                 u32 asid, u64 va, u64 size)
5249 {
5250         /* Treat as invalidate all because there is no range invalidation
5251          * in Goya
5252          */
5253         return hdev->asic_funcs->mmu_invalidate_cache(hdev, is_hard, flags);
5254 }
5255
5256 int goya_send_heartbeat(struct hl_device *hdev)
5257 {
5258         struct goya_device *goya = hdev->asic_specific;
5259
5260         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5261                 return 0;
5262
5263         return hl_fw_send_heartbeat(hdev);
5264 }
5265
5266 int goya_cpucp_info_get(struct hl_device *hdev)
5267 {
5268         struct goya_device *goya = hdev->asic_specific;
5269         struct asic_fixed_properties *prop = &hdev->asic_prop;
5270         u64 dram_size;
5271         int rc;
5272
5273         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5274                 return 0;
5275
5276         rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0,
5277                                         mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
5278                                         mmCPU_BOOT_ERR1);
5279         if (rc)
5280                 return rc;
5281
5282         dram_size = le64_to_cpu(prop->cpucp_info.dram_size);
5283         if (dram_size) {
5284                 if ((!is_power_of_2(dram_size)) ||
5285                                 (dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
5286                         dev_err(hdev->dev,
5287                                 "F/W reported invalid DRAM size %llu. Trying to use default size\n",
5288                                 dram_size);
5289                         dram_size = DRAM_PHYS_DEFAULT_SIZE;
5290                 }
5291
5292                 prop->dram_size = dram_size;
5293                 prop->dram_end_address = prop->dram_base_address + dram_size;
5294         }
5295
5296         if (!strlen(prop->cpucp_info.card_name))
5297                 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
5298                                 CARD_NAME_MAX_LEN);
5299
5300         return 0;
5301 }
5302
5303 static void goya_set_clock_gating(struct hl_device *hdev)
5304 {
5305         /* clock gating not supported in Goya */
5306 }
5307
5308 static void goya_disable_clock_gating(struct hl_device *hdev)
5309 {
5310         /* clock gating not supported in Goya */
5311 }
5312
5313 static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask_arr,
5314                                         u8 mask_len, struct seq_file *s)
5315 {
5316         const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n";
5317         const char *dma_fmt = "%-5d%-9s%#-14x%#x\n";
5318         unsigned long *mask = (unsigned long *)mask_arr;
5319         u32 qm_glbl_sts0, cmdq_glbl_sts0, dma_core_sts0, tpc_cfg_sts,
5320                 mme_arch_sts;
5321         bool is_idle = true, is_eng_idle;
5322         u64 offset;
5323         int i;
5324
5325         if (s)
5326                 seq_puts(s, "\nDMA  is_idle  QM_GLBL_STS0  DMA_CORE_STS0\n"
5327                                 "---  -------  ------------  -------------\n");
5328
5329         offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
5330
5331         for (i = 0 ; i < DMA_MAX_NUM ; i++) {
5332                 qm_glbl_sts0 = RREG32(mmDMA_QM_0_GLBL_STS0 + i * offset);
5333                 dma_core_sts0 = RREG32(mmDMA_CH_0_STS0 + i * offset);
5334                 is_eng_idle = IS_DMA_QM_IDLE(qm_glbl_sts0) &&
5335                                 IS_DMA_IDLE(dma_core_sts0);
5336                 is_idle &= is_eng_idle;
5337
5338                 if (mask && !is_eng_idle)
5339                         set_bit(GOYA_ENGINE_ID_DMA_0 + i, mask);
5340                 if (s)
5341                         seq_printf(s, dma_fmt, i, is_eng_idle ? "Y" : "N",
5342                                         qm_glbl_sts0, dma_core_sts0);
5343         }
5344
5345         if (s)
5346                 seq_puts(s,
5347                         "\nTPC  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  CFG_STATUS\n"
5348                         "---  -------  ------------  --------------  ----------\n");
5349
5350         offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
5351
5352         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
5353                 qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + i * offset);
5354                 cmdq_glbl_sts0 = RREG32(mmTPC0_CMDQ_GLBL_STS0 + i * offset);
5355                 tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + i * offset);
5356                 is_eng_idle = IS_TPC_QM_IDLE(qm_glbl_sts0) &&
5357                                 IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) &&
5358                                 IS_TPC_IDLE(tpc_cfg_sts);
5359                 is_idle &= is_eng_idle;
5360
5361                 if (mask && !is_eng_idle)
5362                         set_bit(GOYA_ENGINE_ID_TPC_0 + i, mask);
5363                 if (s)
5364                         seq_printf(s, fmt, i, is_eng_idle ? "Y" : "N",
5365                                 qm_glbl_sts0, cmdq_glbl_sts0, tpc_cfg_sts);
5366         }
5367
5368         if (s)
5369                 seq_puts(s,
5370                         "\nMME  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  ARCH_STATUS\n"
5371                         "---  -------  ------------  --------------  -----------\n");
5372
5373         qm_glbl_sts0 = RREG32(mmMME_QM_GLBL_STS0);
5374         cmdq_glbl_sts0 = RREG32(mmMME_CMDQ_GLBL_STS0);
5375         mme_arch_sts = RREG32(mmMME_ARCH_STATUS);
5376         is_eng_idle = IS_MME_QM_IDLE(qm_glbl_sts0) &&
5377                         IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) &&
5378                         IS_MME_IDLE(mme_arch_sts);
5379         is_idle &= is_eng_idle;
5380
5381         if (mask && !is_eng_idle)
5382                 set_bit(GOYA_ENGINE_ID_MME_0, mask);
5383         if (s) {
5384                 seq_printf(s, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0,
5385                                 cmdq_glbl_sts0, mme_arch_sts);
5386                 seq_puts(s, "\n");
5387         }
5388
5389         return is_idle;
5390 }
5391
5392 static void goya_hw_queues_lock(struct hl_device *hdev)
5393         __acquires(&goya->hw_queues_lock)
5394 {
5395         struct goya_device *goya = hdev->asic_specific;
5396
5397         spin_lock(&goya->hw_queues_lock);
5398 }
5399
5400 static void goya_hw_queues_unlock(struct hl_device *hdev)
5401         __releases(&goya->hw_queues_lock)
5402 {
5403         struct goya_device *goya = hdev->asic_specific;
5404
5405         spin_unlock(&goya->hw_queues_lock);
5406 }
5407
5408 static u32 goya_get_pci_id(struct hl_device *hdev)
5409 {
5410         return hdev->pdev->device;
5411 }
5412
5413 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
5414                                 size_t max_size)
5415 {
5416         struct goya_device *goya = hdev->asic_specific;
5417
5418         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5419                 return 0;
5420
5421         return hl_fw_get_eeprom_data(hdev, data, max_size);
5422 }
5423
5424 static void goya_cpu_init_scrambler_dram(struct hl_device *hdev)
5425 {
5426
5427 }
5428
5429 static int goya_ctx_init(struct hl_ctx *ctx)
5430 {
5431         if (ctx->asid != HL_KERNEL_ASID_ID)
5432                 goya_mmu_prepare(ctx->hdev, ctx->asid);
5433
5434         return 0;
5435 }
5436
5437 u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
5438 {
5439         return cq_idx;
5440 }
5441
5442 static u32 goya_get_signal_cb_size(struct hl_device *hdev)
5443 {
5444         return 0;
5445 }
5446
5447 static u32 goya_get_wait_cb_size(struct hl_device *hdev)
5448 {
5449         return 0;
5450 }
5451
5452 static u32 goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
5453                                 u32 size, bool eb)
5454 {
5455         return 0;
5456 }
5457
5458 static u32 goya_gen_wait_cb(struct hl_device *hdev,
5459                 struct hl_gen_wait_properties *prop)
5460 {
5461         return 0;
5462 }
5463
5464 static void goya_reset_sob(struct hl_device *hdev, void *data)
5465 {
5466
5467 }
5468
5469 static void goya_reset_sob_group(struct hl_device *hdev, u16 sob_group)
5470 {
5471
5472 }
5473
5474 static void goya_set_dma_mask_from_fw(struct hl_device *hdev)
5475 {
5476         if (RREG32(mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0) ==
5477                                                         HL_POWER9_HOST_MAGIC) {
5478                 dev_dbg(hdev->dev, "Working in 64-bit DMA mode\n");
5479                 hdev->power9_64bit_dma_enable = 1;
5480                 hdev->dma_mask = 64;
5481         } else {
5482                 dev_dbg(hdev->dev, "Working in 48-bit DMA mode\n");
5483                 hdev->power9_64bit_dma_enable = 0;
5484                 hdev->dma_mask = 48;
5485         }
5486 }
5487
5488 u64 goya_get_device_time(struct hl_device *hdev)
5489 {
5490         u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;
5491
5492         return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);
5493 }
5494
5495 static int goya_collective_wait_init_cs(struct hl_cs *cs)
5496 {
5497         return 0;
5498 }
5499
5500 static int goya_collective_wait_create_jobs(struct hl_device *hdev,
5501                 struct hl_ctx *ctx, struct hl_cs *cs, u32 wait_queue_id,
5502                 u32 collective_engine_id, u32 encaps_signal_offset)
5503 {
5504         return -EINVAL;
5505 }
5506
5507 static void goya_ctx_fini(struct hl_ctx *ctx)
5508 {
5509
5510 }
5511
5512 static int goya_get_hw_block_id(struct hl_device *hdev, u64 block_addr,
5513                         u32 *block_size, u32 *block_id)
5514 {
5515         return -EPERM;
5516 }
5517
5518 static int goya_block_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
5519                                 u32 block_id, u32 block_size)
5520 {
5521         return -EPERM;
5522 }
5523
5524 static void goya_enable_events_from_fw(struct hl_device *hdev)
5525 {
5526         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
5527                         GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
5528 }
5529
5530 static int goya_map_pll_idx_to_fw_idx(u32 pll_idx)
5531 {
5532         switch (pll_idx) {
5533         case HL_GOYA_CPU_PLL: return CPU_PLL;
5534         case HL_GOYA_PCI_PLL: return PCI_PLL;
5535         case HL_GOYA_MME_PLL: return MME_PLL;
5536         case HL_GOYA_TPC_PLL: return TPC_PLL;
5537         case HL_GOYA_IC_PLL: return IC_PLL;
5538         case HL_GOYA_MC_PLL: return MC_PLL;
5539         case HL_GOYA_EMMC_PLL: return EMMC_PLL;
5540         default: return -EINVAL;
5541         }
5542 }
5543
5544 static int goya_gen_sync_to_engine_map(struct hl_device *hdev,
5545                                 struct hl_sync_to_engine_map *map)
5546 {
5547         /* Not implemented */
5548         return 0;
5549 }
5550
5551 static int goya_monitor_valid(struct hl_mon_state_dump *mon)
5552 {
5553         /* Not implemented */
5554         return 0;
5555 }
5556
5557 static int goya_print_single_monitor(char **buf, size_t *size, size_t *offset,
5558                                 struct hl_device *hdev,
5559                                 struct hl_mon_state_dump *mon)
5560 {
5561         /* Not implemented */
5562         return 0;
5563 }
5564
5565
5566 static int goya_print_fences_single_engine(
5567         struct hl_device *hdev, u64 base_offset, u64 status_base_offset,
5568         enum hl_sync_engine_type engine_type, u32 engine_id, char **buf,
5569         size_t *size, size_t *offset)
5570 {
5571         /* Not implemented */
5572         return 0;
5573 }
5574
5575
5576 static struct hl_state_dump_specs_funcs goya_state_dump_funcs = {
5577         .monitor_valid = goya_monitor_valid,
5578         .print_single_monitor = goya_print_single_monitor,
5579         .gen_sync_to_engine_map = goya_gen_sync_to_engine_map,
5580         .print_fences_single_engine = goya_print_fences_single_engine,
5581 };
5582
5583 static void goya_state_dump_init(struct hl_device *hdev)
5584 {
5585         /* Not implemented */
5586         hdev->state_dump_specs.props = goya_state_dump_specs_props;
5587         hdev->state_dump_specs.funcs = goya_state_dump_funcs;
5588 }
5589
5590 static u32 goya_get_sob_addr(struct hl_device *hdev, u32 sob_id)
5591 {
5592         return 0;
5593 }
5594
5595 static u32 *goya_get_stream_master_qid_arr(void)
5596 {
5597         return NULL;
5598 }
5599
5600 static const struct hl_asic_funcs goya_funcs = {
5601         .early_init = goya_early_init,
5602         .early_fini = goya_early_fini,
5603         .late_init = goya_late_init,
5604         .late_fini = goya_late_fini,
5605         .sw_init = goya_sw_init,
5606         .sw_fini = goya_sw_fini,
5607         .hw_init = goya_hw_init,
5608         .hw_fini = goya_hw_fini,
5609         .halt_engines = goya_halt_engines,
5610         .suspend = goya_suspend,
5611         .resume = goya_resume,
5612         .mmap = goya_mmap,
5613         .ring_doorbell = goya_ring_doorbell,
5614         .pqe_write = goya_pqe_write,
5615         .asic_dma_alloc_coherent = goya_dma_alloc_coherent,
5616         .asic_dma_free_coherent = goya_dma_free_coherent,
5617         .scrub_device_mem = goya_scrub_device_mem,
5618         .get_int_queue_base = goya_get_int_queue_base,
5619         .test_queues = goya_test_queues,
5620         .asic_dma_pool_zalloc = goya_dma_pool_zalloc,
5621         .asic_dma_pool_free = goya_dma_pool_free,
5622         .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
5623         .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
5624         .hl_dma_unmap_sg = goya_dma_unmap_sg,
5625         .cs_parser = goya_cs_parser,
5626         .asic_dma_map_sg = goya_dma_map_sg,
5627         .get_dma_desc_list_size = goya_get_dma_desc_list_size,
5628         .add_end_of_cb_packets = goya_add_end_of_cb_packets,
5629         .update_eq_ci = goya_update_eq_ci,
5630         .context_switch = goya_context_switch,
5631         .restore_phase_topology = goya_restore_phase_topology,
5632         .debugfs_read32 = goya_debugfs_read32,
5633         .debugfs_write32 = goya_debugfs_write32,
5634         .debugfs_read64 = goya_debugfs_read64,
5635         .debugfs_write64 = goya_debugfs_write64,
5636         .debugfs_read_dma = goya_debugfs_read_dma,
5637         .add_device_attr = goya_add_device_attr,
5638         .handle_eqe = goya_handle_eqe,
5639         .set_pll_profile = goya_set_pll_profile,
5640         .get_events_stat = goya_get_events_stat,
5641         .read_pte = goya_read_pte,
5642         .write_pte = goya_write_pte,
5643         .mmu_invalidate_cache = goya_mmu_invalidate_cache,
5644         .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
5645         .send_heartbeat = goya_send_heartbeat,
5646         .set_clock_gating = goya_set_clock_gating,
5647         .disable_clock_gating = goya_disable_clock_gating,
5648         .debug_coresight = goya_debug_coresight,
5649         .is_device_idle = goya_is_device_idle,
5650         .soft_reset_late_init = goya_soft_reset_late_init,
5651         .hw_queues_lock = goya_hw_queues_lock,
5652         .hw_queues_unlock = goya_hw_queues_unlock,
5653         .get_pci_id = goya_get_pci_id,
5654         .get_eeprom_data = goya_get_eeprom_data,
5655         .send_cpu_message = goya_send_cpu_message,
5656         .pci_bars_map = goya_pci_bars_map,
5657         .init_iatu = goya_init_iatu,
5658         .rreg = hl_rreg,
5659         .wreg = hl_wreg,
5660         .halt_coresight = goya_halt_coresight,
5661         .ctx_init = goya_ctx_init,
5662         .ctx_fini = goya_ctx_fini,
5663         .get_clk_rate = hl_get_clk_rate,
5664         .get_queue_id_for_cq = goya_get_queue_id_for_cq,
5665         .load_firmware_to_device = goya_load_firmware_to_device,
5666         .load_boot_fit_to_device = goya_load_boot_fit_to_device,
5667         .get_signal_cb_size = goya_get_signal_cb_size,
5668         .get_wait_cb_size = goya_get_wait_cb_size,
5669         .gen_signal_cb = goya_gen_signal_cb,
5670         .gen_wait_cb = goya_gen_wait_cb,
5671         .reset_sob = goya_reset_sob,
5672         .reset_sob_group = goya_reset_sob_group,
5673         .set_dma_mask_from_fw = goya_set_dma_mask_from_fw,
5674         .get_device_time = goya_get_device_time,
5675         .collective_wait_init_cs = goya_collective_wait_init_cs,
5676         .collective_wait_create_jobs = goya_collective_wait_create_jobs,
5677         .scramble_addr = hl_mmu_scramble_addr,
5678         .descramble_addr = hl_mmu_descramble_addr,
5679         .ack_protection_bits_errors = goya_ack_protection_bits_errors,
5680         .get_hw_block_id = goya_get_hw_block_id,
5681         .hw_block_mmap = goya_block_mmap,
5682         .enable_events_from_fw = goya_enable_events_from_fw,
5683         .map_pll_idx_to_fw_idx = goya_map_pll_idx_to_fw_idx,
5684         .init_firmware_loader = goya_init_firmware_loader,
5685         .init_cpu_scrambler_dram = goya_cpu_init_scrambler_dram,
5686         .state_dump_init = goya_state_dump_init,
5687         .get_sob_addr = &goya_get_sob_addr,
5688         .set_pci_memory_regions = goya_set_pci_memory_regions,
5689         .get_stream_master_qid_arr = goya_get_stream_master_qid_arr,
5690 };
5691
5692 /*
5693  * goya_set_asic_funcs - set Goya function pointers
5694  *
5695  * @*hdev: pointer to hl_device structure
5696  *
5697  */
5698 void goya_set_asic_funcs(struct hl_device *hdev)
5699 {
5700         hdev->asic_funcs = &goya_funcs;
5701 }