drivers/misc/habanalabs/goya/goya.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * Copyright 2016-2019 HabanaLabs, Ltd.
   5  * All Rights Reserved.
   6  */
   7
   8 #include "goyaP.h"
   9 #include "../include/hw_ip/mmu/mmu_general.h"
  10 #include "../include/hw_ip/mmu/mmu_v1_0.h"
  11 #include "../include/goya/asic_reg/goya_masks.h"
  12 #include "../include/goya/goya_reg_map.h"
  13
  14 #include <linux/pci.h>
  15 #include <linux/hwmon.h>
  16 #include <linux/iommu.h>
  17 #include <linux/seq_file.h>
  18
  19 /*
  20  * GOYA security scheme:
  21  *
  22  * 1. Host is protected by:
  23  *        - Range registers (When MMU is enabled, DMA RR does NOT protect host)
  24  *        - MMU
  25  *
  26  * 2. DRAM is protected by:
  27  *        - Range registers (protect the first 512MB)
  28  *        - MMU (isolation between users)
  29  *
  30  * 3. Configuration is protected by:
  31  *        - Range registers
  32  *        - Protection bits
  33  *
  34  * When MMU is disabled:
  35  *
  36  * QMAN DMA: PQ, CQ, CP, DMA are secured.
  37  * PQ, CB and the data are on the host.
  38  *
  39  * QMAN TPC/MME:
  40  * PQ, CQ and CP are not secured.
  41  * PQ, CB and the data are on the SRAM/DRAM.
  42  *
  43  * Since QMAN DMA is secured, the driver is parsing the DMA CB:
  44  *     - checks DMA pointer
  45  *     - WREG, MSG_PROT are not allowed.
  46  *     - MSG_LONG/SHORT are allowed.
  47  *
  48  * A read/write transaction by the QMAN to a protected area will succeed if
  49  * and only if the QMAN's CP is secured and MSG_PROT is used
  50  *
  51  *
  52  * When MMU is enabled:
  53  *
  54  * QMAN DMA: PQ, CQ and CP are secured.
  55  * MMU is set to bypass on the Secure props register of the QMAN.
  56  * The reasons we don't enable MMU for PQ, CQ and CP are:
  57  *     - PQ entry is in kernel address space and the driver doesn't map it.
  58  *     - CP writes to MSIX register and to kernel address space (completion
  59  *       queue).
  60  *
  61  * DMA is not secured but because CP is secured, the driver still needs to parse
  62  * the CB, but doesn't need to check the DMA addresses.
  63  *
  64  * For QMAN DMA 0, DMA is also secured because only the driver uses this DMA and
  65  * the driver doesn't map memory in MMU.
  66  *
  67  * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode)
  68  *
  69  * DMA RR does NOT protect host because DMA is not secured
  70  *
  71  */
  72
  73 #define GOYA_BOOT_FIT_FILE      "habanalabs/goya/goya-boot-fit.itb"
  74 #define GOYA_LINUX_FW_FILE      "habanalabs/goya/goya-fit.itb"
  75
  76 #define GOYA_MMU_REGS_NUM               63
  77
  78 #define GOYA_DMA_POOL_BLK_SIZE          0x100           /* 256 bytes */
  79
  80 #define GOYA_RESET_TIMEOUT_MSEC         500             /* 500ms */
  81 #define GOYA_PLDM_RESET_TIMEOUT_MSEC    20000           /* 20s */
  82 #define GOYA_RESET_WAIT_MSEC            1               /* 1ms */
  83 #define GOYA_CPU_RESET_WAIT_MSEC        100             /* 100ms */
  84 #define GOYA_PLDM_RESET_WAIT_MSEC       1000            /* 1s */
  85 #define GOYA_TEST_QUEUE_WAIT_USEC       100000          /* 100ms */
  86 #define GOYA_PLDM_MMU_TIMEOUT_USEC      (MMU_CONFIG_TIMEOUT_USEC * 100)
  87 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC    (HL_DEVICE_TIMEOUT_USEC * 30)
  88 #define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC  1000000         /* 1s */
  89 #define GOYA_MSG_TO_CPU_TIMEOUT_USEC    4000000         /* 4s */
  90
  91 #define GOYA_QMAN0_FENCE_VAL            0xD169B243
  92
  93 #define GOYA_MAX_STRING_LEN             20
  94
  95 #define GOYA_CB_POOL_CB_CNT             512
  96 #define GOYA_CB_POOL_CB_SIZE            0x20000         /* 128KB */
  97
  98 #define IS_QM_IDLE(engine, qm_glbl_sts0) \
  99         (((qm_glbl_sts0) & engine##_QM_IDLE_MASK) == engine##_QM_IDLE_MASK)
 100 #define IS_DMA_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(DMA, qm_glbl_sts0)
 101 #define IS_TPC_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(TPC, qm_glbl_sts0)
 102 #define IS_MME_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(MME, qm_glbl_sts0)
 103
 104 #define IS_CMDQ_IDLE(engine, cmdq_glbl_sts0) \
 105         (((cmdq_glbl_sts0) & engine##_CMDQ_IDLE_MASK) == \
 106                         engine##_CMDQ_IDLE_MASK)
 107 #define IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) \
 108         IS_CMDQ_IDLE(TPC, cmdq_glbl_sts0)
 109 #define IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) \
 110         IS_CMDQ_IDLE(MME, cmdq_glbl_sts0)
 111
 112 #define IS_DMA_IDLE(dma_core_sts0) \
 113         !((dma_core_sts0) & DMA_CH_0_STS0_DMA_BUSY_MASK)
 114
 115 #define IS_TPC_IDLE(tpc_cfg_sts) \
 116         (((tpc_cfg_sts) & TPC_CFG_IDLE_MASK) == TPC_CFG_IDLE_MASK)
 117
 118 #define IS_MME_IDLE(mme_arch_sts) \
 119         (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
 120
 121
 122 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
 123                 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
 124                 "goya cq 4", "goya cpu eq"
 125 };
 126
 127 static u16 goya_packet_sizes[MAX_PACKET_ID] = {
 128         [PACKET_WREG_32]        = sizeof(struct packet_wreg32),
 129         [PACKET_WREG_BULK]      = sizeof(struct packet_wreg_bulk),
 130         [PACKET_MSG_LONG]       = sizeof(struct packet_msg_long),
 131         [PACKET_MSG_SHORT]      = sizeof(struct packet_msg_short),
 132         [PACKET_CP_DMA]         = sizeof(struct packet_cp_dma),
 133         [PACKET_MSG_PROT]       = sizeof(struct packet_msg_prot),
 134         [PACKET_FENCE]          = sizeof(struct packet_fence),
 135         [PACKET_LIN_DMA]        = sizeof(struct packet_lin_dma),
 136         [PACKET_NOP]            = sizeof(struct packet_nop),
 137         [PACKET_STOP]           = sizeof(struct packet_stop)
 138 };
 139
 140 static inline bool validate_packet_id(enum packet_id id)
 141 {
 142         switch (id) {
 143         case PACKET_WREG_32:
 144         case PACKET_WREG_BULK:
 145         case PACKET_MSG_LONG:
 146         case PACKET_MSG_SHORT:
 147         case PACKET_CP_DMA:
 148         case PACKET_MSG_PROT:
 149         case PACKET_FENCE:
 150         case PACKET_LIN_DMA:
 151         case PACKET_NOP:
 152         case PACKET_STOP:
 153                 return true;
 154         default:
 155                 return false;
 156         }
 157 }
 158
 159 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
 160         mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
 161         mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
 162         mmDMA_QM_2_GLBL_NON_SECURE_PROPS,
 163         mmDMA_QM_3_GLBL_NON_SECURE_PROPS,
 164         mmDMA_QM_4_GLBL_NON_SECURE_PROPS,
 165         mmTPC0_QM_GLBL_SECURE_PROPS,
 166         mmTPC0_QM_GLBL_NON_SECURE_PROPS,
 167         mmTPC0_CMDQ_GLBL_SECURE_PROPS,
 168         mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS,
 169         mmTPC0_CFG_ARUSER,
 170         mmTPC0_CFG_AWUSER,
 171         mmTPC1_QM_GLBL_SECURE_PROPS,
 172         mmTPC1_QM_GLBL_NON_SECURE_PROPS,
 173         mmTPC1_CMDQ_GLBL_SECURE_PROPS,
 174         mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS,
 175         mmTPC1_CFG_ARUSER,
 176         mmTPC1_CFG_AWUSER,
 177         mmTPC2_QM_GLBL_SECURE_PROPS,
 178         mmTPC2_QM_GLBL_NON_SECURE_PROPS,
 179         mmTPC2_CMDQ_GLBL_SECURE_PROPS,
 180         mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS,
 181         mmTPC2_CFG_ARUSER,
 182         mmTPC2_CFG_AWUSER,
 183         mmTPC3_QM_GLBL_SECURE_PROPS,
 184         mmTPC3_QM_GLBL_NON_SECURE_PROPS,
 185         mmTPC3_CMDQ_GLBL_SECURE_PROPS,
 186         mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS,
 187         mmTPC3_CFG_ARUSER,
 188         mmTPC3_CFG_AWUSER,
 189         mmTPC4_QM_GLBL_SECURE_PROPS,
 190         mmTPC4_QM_GLBL_NON_SECURE_PROPS,
 191         mmTPC4_CMDQ_GLBL_SECURE_PROPS,
 192         mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS,
 193         mmTPC4_CFG_ARUSER,
 194         mmTPC4_CFG_AWUSER,
 195         mmTPC5_QM_GLBL_SECURE_PROPS,
 196         mmTPC5_QM_GLBL_NON_SECURE_PROPS,
 197         mmTPC5_CMDQ_GLBL_SECURE_PROPS,
 198         mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS,
 199         mmTPC5_CFG_ARUSER,
 200         mmTPC5_CFG_AWUSER,
 201         mmTPC6_QM_GLBL_SECURE_PROPS,
 202         mmTPC6_QM_GLBL_NON_SECURE_PROPS,
 203         mmTPC6_CMDQ_GLBL_SECURE_PROPS,
 204         mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS,
 205         mmTPC6_CFG_ARUSER,
 206         mmTPC6_CFG_AWUSER,
 207         mmTPC7_QM_GLBL_SECURE_PROPS,
 208         mmTPC7_QM_GLBL_NON_SECURE_PROPS,
 209         mmTPC7_CMDQ_GLBL_SECURE_PROPS,
 210         mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS,
 211         mmTPC7_CFG_ARUSER,
 212         mmTPC7_CFG_AWUSER,
 213         mmMME_QM_GLBL_SECURE_PROPS,
 214         mmMME_QM_GLBL_NON_SECURE_PROPS,
 215         mmMME_CMDQ_GLBL_SECURE_PROPS,
 216         mmMME_CMDQ_GLBL_NON_SECURE_PROPS,
 217         mmMME_SBA_CONTROL_DATA,
 218         mmMME_SBB_CONTROL_DATA,
 219         mmMME_SBC_CONTROL_DATA,
 220         mmMME_WBC_CONTROL_DATA,
 221         mmPCIE_WRAP_PSOC_ARUSER,
 222         mmPCIE_WRAP_PSOC_AWUSER
 223 };
 224
 225 static u32 goya_all_events[] = {
 226         GOYA_ASYNC_EVENT_ID_PCIE_IF,
 227         GOYA_ASYNC_EVENT_ID_TPC0_ECC,
 228         GOYA_ASYNC_EVENT_ID_TPC1_ECC,
 229         GOYA_ASYNC_EVENT_ID_TPC2_ECC,
 230         GOYA_ASYNC_EVENT_ID_TPC3_ECC,
 231         GOYA_ASYNC_EVENT_ID_TPC4_ECC,
 232         GOYA_ASYNC_EVENT_ID_TPC5_ECC,
 233         GOYA_ASYNC_EVENT_ID_TPC6_ECC,
 234         GOYA_ASYNC_EVENT_ID_TPC7_ECC,
 235         GOYA_ASYNC_EVENT_ID_MME_ECC,
 236         GOYA_ASYNC_EVENT_ID_MME_ECC_EXT,
 237         GOYA_ASYNC_EVENT_ID_MMU_ECC,
 238         GOYA_ASYNC_EVENT_ID_DMA_MACRO,
 239         GOYA_ASYNC_EVENT_ID_DMA_ECC,
 240         GOYA_ASYNC_EVENT_ID_CPU_IF_ECC,
 241         GOYA_ASYNC_EVENT_ID_PSOC_MEM,
 242         GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT,
 243         GOYA_ASYNC_EVENT_ID_SRAM0,
 244         GOYA_ASYNC_EVENT_ID_SRAM1,
 245         GOYA_ASYNC_EVENT_ID_SRAM2,
 246         GOYA_ASYNC_EVENT_ID_SRAM3,
 247         GOYA_ASYNC_EVENT_ID_SRAM4,
 248         GOYA_ASYNC_EVENT_ID_SRAM5,
 249         GOYA_ASYNC_EVENT_ID_SRAM6,
 250         GOYA_ASYNC_EVENT_ID_SRAM7,
 251         GOYA_ASYNC_EVENT_ID_SRAM8,
 252         GOYA_ASYNC_EVENT_ID_SRAM9,
 253         GOYA_ASYNC_EVENT_ID_SRAM10,
 254         GOYA_ASYNC_EVENT_ID_SRAM11,
 255         GOYA_ASYNC_EVENT_ID_SRAM12,
 256         GOYA_ASYNC_EVENT_ID_SRAM13,
 257         GOYA_ASYNC_EVENT_ID_SRAM14,
 258         GOYA_ASYNC_EVENT_ID_SRAM15,
 259         GOYA_ASYNC_EVENT_ID_SRAM16,
 260         GOYA_ASYNC_EVENT_ID_SRAM17,
 261         GOYA_ASYNC_EVENT_ID_SRAM18,
 262         GOYA_ASYNC_EVENT_ID_SRAM19,
 263         GOYA_ASYNC_EVENT_ID_SRAM20,
 264         GOYA_ASYNC_EVENT_ID_SRAM21,
 265         GOYA_ASYNC_EVENT_ID_SRAM22,
 266         GOYA_ASYNC_EVENT_ID_SRAM23,
 267         GOYA_ASYNC_EVENT_ID_SRAM24,
 268         GOYA_ASYNC_EVENT_ID_SRAM25,
 269         GOYA_ASYNC_EVENT_ID_SRAM26,
 270         GOYA_ASYNC_EVENT_ID_SRAM27,
 271         GOYA_ASYNC_EVENT_ID_SRAM28,
 272         GOYA_ASYNC_EVENT_ID_SRAM29,
 273         GOYA_ASYNC_EVENT_ID_GIC500,
 274         GOYA_ASYNC_EVENT_ID_PLL0,
 275         GOYA_ASYNC_EVENT_ID_PLL1,
 276         GOYA_ASYNC_EVENT_ID_PLL3,
 277         GOYA_ASYNC_EVENT_ID_PLL4,
 278         GOYA_ASYNC_EVENT_ID_PLL5,
 279         GOYA_ASYNC_EVENT_ID_PLL6,
 280         GOYA_ASYNC_EVENT_ID_AXI_ECC,
 281         GOYA_ASYNC_EVENT_ID_L2_RAM_ECC,
 282         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET,
 283         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT,
 284         GOYA_ASYNC_EVENT_ID_PCIE_DEC,
 285         GOYA_ASYNC_EVENT_ID_TPC0_DEC,
 286         GOYA_ASYNC_EVENT_ID_TPC1_DEC,
 287         GOYA_ASYNC_EVENT_ID_TPC2_DEC,
 288         GOYA_ASYNC_EVENT_ID_TPC3_DEC,
 289         GOYA_ASYNC_EVENT_ID_TPC4_DEC,
 290         GOYA_ASYNC_EVENT_ID_TPC5_DEC,
 291         GOYA_ASYNC_EVENT_ID_TPC6_DEC,
 292         GOYA_ASYNC_EVENT_ID_TPC7_DEC,
 293         GOYA_ASYNC_EVENT_ID_MME_WACS,
 294         GOYA_ASYNC_EVENT_ID_MME_WACSD,
 295         GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER,
 296         GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC,
 297         GOYA_ASYNC_EVENT_ID_PSOC,
 298         GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR,
 299         GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR,
 300         GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR,
 301         GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR,
 302         GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR,
 303         GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR,
 304         GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR,
 305         GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR,
 306         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ,
 307         GOYA_ASYNC_EVENT_ID_TPC1_CMDQ,
 308         GOYA_ASYNC_EVENT_ID_TPC2_CMDQ,
 309         GOYA_ASYNC_EVENT_ID_TPC3_CMDQ,
 310         GOYA_ASYNC_EVENT_ID_TPC4_CMDQ,
 311         GOYA_ASYNC_EVENT_ID_TPC5_CMDQ,
 312         GOYA_ASYNC_EVENT_ID_TPC6_CMDQ,
 313         GOYA_ASYNC_EVENT_ID_TPC7_CMDQ,
 314         GOYA_ASYNC_EVENT_ID_TPC0_QM,
 315         GOYA_ASYNC_EVENT_ID_TPC1_QM,
 316         GOYA_ASYNC_EVENT_ID_TPC2_QM,
 317         GOYA_ASYNC_EVENT_ID_TPC3_QM,
 318         GOYA_ASYNC_EVENT_ID_TPC4_QM,
 319         GOYA_ASYNC_EVENT_ID_TPC5_QM,
 320         GOYA_ASYNC_EVENT_ID_TPC6_QM,
 321         GOYA_ASYNC_EVENT_ID_TPC7_QM,
 322         GOYA_ASYNC_EVENT_ID_MME_QM,
 323         GOYA_ASYNC_EVENT_ID_MME_CMDQ,
 324         GOYA_ASYNC_EVENT_ID_DMA0_QM,
 325         GOYA_ASYNC_EVENT_ID_DMA1_QM,
 326         GOYA_ASYNC_EVENT_ID_DMA2_QM,
 327         GOYA_ASYNC_EVENT_ID_DMA3_QM,
 328         GOYA_ASYNC_EVENT_ID_DMA4_QM,
 329         GOYA_ASYNC_EVENT_ID_DMA0_CH,
 330         GOYA_ASYNC_EVENT_ID_DMA1_CH,
 331         GOYA_ASYNC_EVENT_ID_DMA2_CH,
 332         GOYA_ASYNC_EVENT_ID_DMA3_CH,
 333         GOYA_ASYNC_EVENT_ID_DMA4_CH,
 334         GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU,
 335         GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU,
 336         GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU,
 337         GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU,
 338         GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU,
 339         GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU,
 340         GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU,
 341         GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU,
 342         GOYA_ASYNC_EVENT_ID_DMA_BM_CH0,
 343         GOYA_ASYNC_EVENT_ID_DMA_BM_CH1,
 344         GOYA_ASYNC_EVENT_ID_DMA_BM_CH2,
 345         GOYA_ASYNC_EVENT_ID_DMA_BM_CH3,
 346         GOYA_ASYNC_EVENT_ID_DMA_BM_CH4,
 347         GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S,
 348         GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E,
 349         GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S,
 350         GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E
 351 };
 352
 353 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
 354 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
 355 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev);
 356 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
 357
 358 int goya_get_fixed_properties(struct hl_device *hdev)
 359 {
 360         struct asic_fixed_properties *prop = &hdev->asic_prop;
 361         int i;
 362
 363         prop->max_queues = GOYA_QUEUE_ID_SIZE;
 364         prop->hw_queues_props = kcalloc(prop->max_queues,
 365                         sizeof(struct hw_queue_properties),
 366                         GFP_KERNEL);
 367
 368         if (!prop->hw_queues_props)
 369                 return -ENOMEM;
 370
 371         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
 372                 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
 373                 prop->hw_queues_props[i].driver_only = 0;
 374                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
 375         }
 376
 377         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
 378                 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
 379                 prop->hw_queues_props[i].driver_only = 1;
 380                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
 381         }
 382
 383         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
 384                         NUMBER_OF_INT_HW_QUEUES; i++) {
 385                 prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
 386                 prop->hw_queues_props[i].driver_only = 0;
 387                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER;
 388         }
 389
 390         prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
 391
 392         prop->dram_base_address = DRAM_PHYS_BASE;
 393         prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
 394         prop->dram_end_address = prop->dram_base_address + prop->dram_size;
 395         prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
 396
 397         prop->sram_base_address = SRAM_BASE_ADDR;
 398         prop->sram_size = SRAM_SIZE;
 399         prop->sram_end_address = prop->sram_base_address + prop->sram_size;
 400         prop->sram_user_base_address = prop->sram_base_address +
 401                                                 SRAM_USER_BASE_OFFSET;
 402
 403         prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
 404         prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR;
 405         if (hdev->pldm)
 406                 prop->mmu_pgt_size = 0x800000; /* 8MB */
 407         else
 408                 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
 409         prop->mmu_pte_size = HL_PTE_SIZE;
 410         prop->mmu_hop_table_size = HOP_TABLE_SIZE;
 411         prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
 412         prop->dram_page_size = PAGE_SIZE_2MB;
 413         prop->dram_supports_virtual_memory = true;
 414
 415         prop->dmmu.hop0_shift = HOP0_SHIFT;
 416         prop->dmmu.hop1_shift = HOP1_SHIFT;
 417         prop->dmmu.hop2_shift = HOP2_SHIFT;
 418         prop->dmmu.hop3_shift = HOP3_SHIFT;
 419         prop->dmmu.hop4_shift = HOP4_SHIFT;
 420         prop->dmmu.hop0_mask = HOP0_MASK;
 421         prop->dmmu.hop1_mask = HOP1_MASK;
 422         prop->dmmu.hop2_mask = HOP2_MASK;
 423         prop->dmmu.hop3_mask = HOP3_MASK;
 424         prop->dmmu.hop4_mask = HOP4_MASK;
 425         prop->dmmu.start_addr = VA_DDR_SPACE_START;
 426         prop->dmmu.end_addr = VA_DDR_SPACE_END;
 427         prop->dmmu.page_size = PAGE_SIZE_2MB;
 428         prop->dmmu.num_hops = MMU_ARCH_5_HOPS;
 429
 430         /* shifts and masks are the same in PMMU and DMMU */
 431         memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu));
 432         prop->pmmu.start_addr = VA_HOST_SPACE_START;
 433         prop->pmmu.end_addr = VA_HOST_SPACE_END;
 434         prop->pmmu.page_size = PAGE_SIZE_4KB;
 435         prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
 436
 437         /* PMMU and HPMMU are the same except of page size */
 438         memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
 439         prop->pmmu_huge.page_size = PAGE_SIZE_2MB;
 440
 441         prop->dram_size_for_default_page_mapping = VA_DDR_SPACE_END;
 442         prop->cfg_size = CFG_SIZE;
 443         prop->max_asid = MAX_ASID;
 444         prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
 445         prop->high_pll = PLL_HIGH_DEFAULT;
 446         prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
 447         prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
 448         prop->max_power_default = MAX_POWER_DEFAULT;
 449         prop->tpc_enabled_mask = TPC_ENABLED_MASK;
 450         prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
 451         prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
 452
 453         strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
 454                 CARD_NAME_MAX_LEN);
 455
 456         prop->max_pending_cs = GOYA_MAX_PENDING_CS;
 457
 458         /* disable fw security for now, set it in a later stage */
 459         prop->fw_security_disabled = true;
 460         prop->fw_security_status_valid = false;
 461         prop->hard_reset_done_by_fw = false;
 462
 463         return 0;
 464 }
 465
 466 /*
 467  * goya_pci_bars_map - Map PCI BARS of Goya device
 468  *
 469  * @hdev: pointer to hl_device structure
 470  *
 471  * Request PCI regions and map them to kernel virtual addresses.
 472  * Returns 0 on success
 473  *
 474  */
 475 static int goya_pci_bars_map(struct hl_device *hdev)
 476 {
 477         static const char * const name[] = {"SRAM_CFG", "MSIX", "DDR"};
 478         bool is_wc[3] = {false, false, true};
 479         int rc;
 480
 481         rc = hl_pci_bars_map(hdev, name, is_wc);
 482         if (rc)
 483                 return rc;
 484
 485         hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
 486                         (CFG_BASE - SRAM_BASE_ADDR);
 487
 488         return 0;
 489 }
 490
 491 static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
 492 {
 493         struct goya_device *goya = hdev->asic_specific;
 494         struct hl_inbound_pci_region pci_region;
 495         u64 old_addr = addr;
 496         int rc;
 497
 498         if ((goya) && (goya->ddr_bar_cur_addr == addr))
 499                 return old_addr;
 500
 501         /* Inbound Region 1 - Bar 4 - Point to DDR */
 502         pci_region.mode = PCI_BAR_MATCH_MODE;
 503         pci_region.bar = DDR_BAR_ID;
 504         pci_region.addr = addr;
 505         rc = hl_pci_set_inbound_region(hdev, 1, &pci_region);
 506         if (rc)
 507                 return U64_MAX;
 508
 509         if (goya) {
 510                 old_addr = goya->ddr_bar_cur_addr;
 511                 goya->ddr_bar_cur_addr = addr;
 512         }
 513
 514         return old_addr;
 515 }
 516
 517 /*
 518  * goya_init_iatu - Initialize the iATU unit inside the PCI controller
 519  *
 520  * @hdev: pointer to hl_device structure
 521  *
 522  * This is needed in case the firmware doesn't initialize the iATU
 523  *
 524  */
 525 static int goya_init_iatu(struct hl_device *hdev)
 526 {
 527         struct hl_inbound_pci_region inbound_region;
 528         struct hl_outbound_pci_region outbound_region;
 529         int rc;
 530
 531         /* Inbound Region 0 - Bar 0 - Point to SRAM and CFG */
 532         inbound_region.mode = PCI_BAR_MATCH_MODE;
 533         inbound_region.bar = SRAM_CFG_BAR_ID;
 534         inbound_region.addr = SRAM_BASE_ADDR;
 535         rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
 536         if (rc)
 537                 goto done;
 538
 539         /* Inbound Region 1 - Bar 4 - Point to DDR */
 540         inbound_region.mode = PCI_BAR_MATCH_MODE;
 541         inbound_region.bar = DDR_BAR_ID;
 542         inbound_region.addr = DRAM_PHYS_BASE;
 543         rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
 544         if (rc)
 545                 goto done;
 546
 547         hdev->asic_funcs->set_dma_mask_from_fw(hdev);
 548
 549         /* Outbound Region 0 - Point to Host  */
 550         outbound_region.addr = HOST_PHYS_BASE;
 551         outbound_region.size = HOST_PHYS_SIZE;
 552         rc = hl_pci_set_outbound_region(hdev, &outbound_region);
 553
 554 done:
 555         return rc;
 556 }
 557
 558 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
 559 {
 560         return RREG32(mmHW_STATE);
 561 }
 562
 563 /*
 564  * goya_early_init - GOYA early initialization code
 565  *
 566  * @hdev: pointer to hl_device structure
 567  *
 568  * Verify PCI bars
 569  * Set DMA masks
 570  * PCI controller initialization
 571  * Map PCI bars
 572  *
 573  */
 574 static int goya_early_init(struct hl_device *hdev)
 575 {
 576         struct asic_fixed_properties *prop = &hdev->asic_prop;
 577         struct pci_dev *pdev = hdev->pdev;
 578         u32 val;
 579         int rc;
 580
 581         rc = goya_get_fixed_properties(hdev);
 582         if (rc) {
 583                 dev_err(hdev->dev, "Failed to get fixed properties\n");
 584                 return rc;
 585         }
 586
 587         /* Check BAR sizes */
 588         if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) {
 589                 dev_err(hdev->dev,
 590                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 591                         SRAM_CFG_BAR_ID,
 592                         (unsigned long long) pci_resource_len(pdev,
 593                                                         SRAM_CFG_BAR_ID),
 594                         CFG_BAR_SIZE);
 595                 rc = -ENODEV;
 596                 goto free_queue_props;
 597         }
 598
 599         if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) {
 600                 dev_err(hdev->dev,
 601                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 602                         MSIX_BAR_ID,
 603                         (unsigned long long) pci_resource_len(pdev,
 604                                                                 MSIX_BAR_ID),
 605                         MSIX_BAR_SIZE);
 606                 rc = -ENODEV;
 607                 goto free_queue_props;
 608         }
 609
 610         prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
 611
 612         rc = hl_pci_init(hdev);
 613         if (rc)
 614                 goto free_queue_props;
 615
 616         if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
 617                 dev_info(hdev->dev,
 618                         "H/W state is dirty, must reset before initializing\n");
 619                 hdev->asic_funcs->hw_fini(hdev, true);
 620         }
 621
 622         /* Before continuing in the initialization, we need to read the preboot
 623          * version to determine whether we run with a security-enabled firmware
 624          */
 625         rc = hl_fw_read_preboot_status(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS,
 626                         mmCPU_BOOT_DEV_STS0, mmCPU_BOOT_ERR0,
 627                         GOYA_BOOT_FIT_REQ_TIMEOUT_USEC);
 628         if (rc) {
 629                 if (hdev->reset_on_preboot_fail)
 630                         hdev->asic_funcs->hw_fini(hdev, true);
 631                 goto pci_fini;
 632         }
 633
 634         if (!hdev->pldm) {
 635                 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
 636                 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
 637                         dev_warn(hdev->dev,
 638                                 "PCI strap is not configured correctly, PCI bus errors may occur\n");
 639         }
 640
 641         return 0;
 642
 643 pci_fini:
 644         hl_pci_fini(hdev);
 645 free_queue_props:
 646         kfree(hdev->asic_prop.hw_queues_props);
 647         return rc;
 648 }
 649
 650 /*
 651  * goya_early_fini - GOYA early finalization code
 652  *
 653  * @hdev: pointer to hl_device structure
 654  *
 655  * Unmap PCI bars
 656  *
 657  */
 658 static int goya_early_fini(struct hl_device *hdev)
 659 {
 660         kfree(hdev->asic_prop.hw_queues_props);
 661         hl_pci_fini(hdev);
 662
 663         return 0;
 664 }
 665
 666 static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
 667 {
 668         /* mask to zero the MMBP and ASID bits */
 669         WREG32_AND(reg, ~0x7FF);
 670         WREG32_OR(reg, asid);
 671 }
 672
 673 static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
 674 {
 675         struct goya_device *goya = hdev->asic_specific;
 676
 677         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
 678                 return;
 679
 680         if (secure)
 681                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
 682         else
 683                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
 684
 685         RREG32(mmDMA_QM_0_GLBL_PROT);
 686 }
 687
 688 /*
 689  * goya_fetch_psoc_frequency - Fetch PSOC frequency values
 690  *
 691  * @hdev: pointer to hl_device structure
 692  *
 693  */
 694 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
 695 {
 696         struct asic_fixed_properties *prop = &hdev->asic_prop;
 697         u32 trace_freq = 0;
 698         u32 pll_clk = 0;
 699         u32 div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
 700         u32 div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);
 701         u32 nr = RREG32(mmPSOC_PCI_PLL_NR);
 702         u32 nf = RREG32(mmPSOC_PCI_PLL_NF);
 703         u32 od = RREG32(mmPSOC_PCI_PLL_OD);
 704
 705         if (div_sel == DIV_SEL_REF_CLK || div_sel == DIV_SEL_DIVIDED_REF) {
 706                 if (div_sel == DIV_SEL_REF_CLK)
 707                         trace_freq = PLL_REF_CLK;
 708                 else
 709                         trace_freq = PLL_REF_CLK / (div_fctr + 1);
 710         } else if (div_sel == DIV_SEL_PLL_CLK ||
 711                                         div_sel == DIV_SEL_DIVIDED_PLL) {
 712                 pll_clk = PLL_REF_CLK * (nf + 1) / ((nr + 1) * (od + 1));
 713                 if (div_sel == DIV_SEL_PLL_CLK)
 714                         trace_freq = pll_clk;
 715                 else
 716                         trace_freq = pll_clk / (div_fctr + 1);
 717         } else {
 718                 dev_warn(hdev->dev,
 719                         "Received invalid div select value: %d", div_sel);
 720         }
 721
 722         prop->psoc_timestamp_frequency = trace_freq;
 723         prop->psoc_pci_pll_nr = nr;
 724         prop->psoc_pci_pll_nf = nf;
 725         prop->psoc_pci_pll_od = od;
 726         prop->psoc_pci_pll_div_factor = div_fctr;
 727 }
 728
 729 int goya_late_init(struct hl_device *hdev)
 730 {
 731         struct asic_fixed_properties *prop = &hdev->asic_prop;
 732         int rc;
 733
 734         goya_fetch_psoc_frequency(hdev);
 735
 736         rc = goya_mmu_clear_pgt_range(hdev);
 737         if (rc) {
 738                 dev_err(hdev->dev,
 739                         "Failed to clear MMU page tables range %d\n", rc);
 740                 return rc;
 741         }
 742
 743         rc = goya_mmu_set_dram_default_page(hdev);
 744         if (rc) {
 745                 dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc);
 746                 return rc;
 747         }
 748
 749         rc = goya_mmu_add_mappings_for_device_cpu(hdev);
 750         if (rc)
 751                 return rc;
 752
 753         rc = goya_init_cpu_queues(hdev);
 754         if (rc)
 755                 return rc;
 756
 757         rc = goya_test_cpu_queue(hdev);
 758         if (rc)
 759                 return rc;
 760
 761         rc = goya_cpucp_info_get(hdev);
 762         if (rc) {
 763                 dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc);
 764                 return rc;
 765         }
 766
 767         /* Now that we have the DRAM size in ASIC prop, we need to check
 768          * its size and configure the DMA_IF DDR wrap protection (which is in
 769          * the MMU block) accordingly. The value is the log2 of the DRAM size
 770          */
 771         WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
 772
 773         rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS);
 774         if (rc) {
 775                 dev_err(hdev->dev,
 776                         "Failed to enable PCI access from CPU %d\n", rc);
 777                 return rc;
 778         }
 779
 780         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
 781                         GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
 782
 783         return 0;
 784 }
 785
 786 /*
 787  * goya_late_fini - GOYA late tear-down code
 788  *
 789  * @hdev: pointer to hl_device structure
 790  *
 791  * Free sensors allocated structures
 792  */
 793 void goya_late_fini(struct hl_device *hdev)
 794 {
 795         const struct hwmon_channel_info **channel_info_arr;
 796         int i = 0;
 797
 798         if (!hdev->hl_chip_info->info)
 799                 return;
 800
 801         channel_info_arr = hdev->hl_chip_info->info;
 802
 803         while (channel_info_arr[i]) {
 804                 kfree(channel_info_arr[i]->config);
 805                 kfree(channel_info_arr[i]);
 806                 i++;
 807         }
 808
 809         kfree(channel_info_arr);
 810
 811         hdev->hl_chip_info->info = NULL;
 812 }
 813
 814 /*
 815  * goya_sw_init - Goya software initialization code
 816  *
 817  * @hdev: pointer to hl_device structure
 818  *
 819  */
 820 static int goya_sw_init(struct hl_device *hdev)
 821 {
 822         struct goya_device *goya;
 823         int rc;
 824
 825         /* Allocate device structure */
 826         goya = kzalloc(sizeof(*goya), GFP_KERNEL);
 827         if (!goya)
 828                 return -ENOMEM;
 829
 830         /* according to goya_init_iatu */
 831         goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
 832
 833         goya->mme_clk = GOYA_PLL_FREQ_LOW;
 834         goya->tpc_clk = GOYA_PLL_FREQ_LOW;
 835         goya->ic_clk = GOYA_PLL_FREQ_LOW;
 836
 837         hdev->asic_specific = goya;
 838
 839         /* Create DMA pool for small allocations */
 840         hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
 841                         &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
 842         if (!hdev->dma_pool) {
 843                 dev_err(hdev->dev, "failed to create DMA pool\n");
 844                 rc = -ENOMEM;
 845                 goto free_goya_device;
 846         }
 847
 848         hdev->cpu_accessible_dma_mem =
 849                         hdev->asic_funcs->asic_dma_alloc_coherent(hdev,
 850                                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 851                                         &hdev->cpu_accessible_dma_address,
 852                                         GFP_KERNEL | __GFP_ZERO);
 853
 854         if (!hdev->cpu_accessible_dma_mem) {
 855                 rc = -ENOMEM;
 856                 goto free_dma_pool;
 857         }
 858
 859         dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n",
 860                 &hdev->cpu_accessible_dma_address);
 861
 862         hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
 863         if (!hdev->cpu_accessible_dma_pool) {
 864                 dev_err(hdev->dev,
 865                         "Failed to create CPU accessible DMA pool\n");
 866                 rc = -ENOMEM;
 867                 goto free_cpu_dma_mem;
 868         }
 869
 870         rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
 871                                 (uintptr_t) hdev->cpu_accessible_dma_mem,
 872                                 HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
 873         if (rc) {
 874                 dev_err(hdev->dev,
 875                         "Failed to add memory to CPU accessible DMA pool\n");
 876                 rc = -EFAULT;
 877                 goto free_cpu_accessible_dma_pool;
 878         }
 879
 880         spin_lock_init(&goya->hw_queues_lock);
 881         hdev->supports_coresight = true;
 882         hdev->supports_soft_reset = true;
 883
 884         return 0;
 885
 886 free_cpu_accessible_dma_pool:
 887         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 888 free_cpu_dma_mem:
 889         hdev->asic_funcs->asic_dma_free_coherent(hdev,
 890                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 891                         hdev->cpu_accessible_dma_mem,
 892                         hdev->cpu_accessible_dma_address);
 893 free_dma_pool:
 894         dma_pool_destroy(hdev->dma_pool);
 895 free_goya_device:
 896         kfree(goya);
 897
 898         return rc;
 899 }
 900
 901 /*
 902  * goya_sw_fini - Goya software tear-down code
 903  *
 904  * @hdev: pointer to hl_device structure
 905  *
 906  */
 907 static int goya_sw_fini(struct hl_device *hdev)
 908 {
 909         struct goya_device *goya = hdev->asic_specific;
 910
 911         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 912
 913         hdev->asic_funcs->asic_dma_free_coherent(hdev,
 914                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 915                         hdev->cpu_accessible_dma_mem,
 916                         hdev->cpu_accessible_dma_address);
 917
 918         dma_pool_destroy(hdev->dma_pool);
 919
 920         kfree(goya);
 921
 922         return 0;
 923 }
 924
 925 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
 926                 dma_addr_t bus_address)
 927 {
 928         struct goya_device *goya = hdev->asic_specific;
 929         u32 mtr_base_lo, mtr_base_hi;
 930         u32 so_base_lo, so_base_hi;
 931         u32 gic_base_lo, gic_base_hi;
 932         u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
 933         u32 dma_err_cfg = QMAN_DMA_ERR_MSG_EN;
 934
 935         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
 936         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
 937         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
 938         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
 939
 940         gic_base_lo =
 941                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 942         gic_base_hi =
 943                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 944
 945         WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
 946         WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
 947
 948         WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
 949         WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
 950         WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
 951
 952         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
 953         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
 954         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
 955         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
 956         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
 957         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
 958         WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
 959                         GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id);
 960
 961         /* PQ has buffer of 2 cache lines, while CQ has 8 lines */
 962         WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
 963         WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
 964
 965         if (goya->hw_cap_initialized & HW_CAP_MMU)
 966                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
 967         else
 968                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
 969
 970         if (hdev->stop_on_err)
 971                 dma_err_cfg |= 1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT;
 972
 973         WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
 974         WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
 975 }
 976
 977 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
 978 {
 979         u32 gic_base_lo, gic_base_hi;
 980         u64 sob_addr;
 981         u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
 982
 983         gic_base_lo =
 984                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 985         gic_base_hi =
 986                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 987
 988         WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
 989         WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
 990         WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
 991                         GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id);
 992
 993         if (dma_id)
 994                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
 995                                 (dma_id - 1) * 4;
 996         else
 997                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
 998
 999         WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
1000         WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1001 }
1002
1003 /*
1004  * goya_init_dma_qmans - Initialize QMAN DMA registers
1005  *
1006  * @hdev: pointer to hl_device structure
1007  *
1008  * Initialize the H/W registers of the QMAN DMA channels
1009  *
1010  */
1011 void goya_init_dma_qmans(struct hl_device *hdev)
1012 {
1013         struct goya_device *goya = hdev->asic_specific;
1014         struct hl_hw_queue *q;
1015         int i;
1016
1017         if (goya->hw_cap_initialized & HW_CAP_DMA)
1018                 return;
1019
1020         q = &hdev->kernel_queues[0];
1021
1022         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
1023                 q->cq_id = q->msi_vec = i;
1024                 goya_init_dma_qman(hdev, i, q->bus_address);
1025                 goya_init_dma_ch(hdev, i);
1026         }
1027
1028         goya->hw_cap_initialized |= HW_CAP_DMA;
1029 }
1030
1031 /*
1032  * goya_disable_external_queues - Disable external queues
1033  *
1034  * @hdev: pointer to hl_device structure
1035  *
1036  */
1037 static void goya_disable_external_queues(struct hl_device *hdev)
1038 {
1039         struct goya_device *goya = hdev->asic_specific;
1040
1041         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1042                 return;
1043
1044         WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1045         WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1046         WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1047         WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1048         WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1049 }
1050
1051 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
1052                                 u32 cp_sts_reg, u32 glbl_sts0_reg)
1053 {
1054         int rc;
1055         u32 status;
1056
1057         /* use the values of TPC0 as they are all the same*/
1058
1059         WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1060
1061         status = RREG32(cp_sts_reg);
1062         if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) {
1063                 rc = hl_poll_timeout(
1064                         hdev,
1065                         cp_sts_reg,
1066                         status,
1067                         !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK),
1068                         1000,
1069                         QMAN_FENCE_TIMEOUT_USEC);
1070
1071                 /* if QMAN is stuck in fence no need to check for stop */
1072                 if (rc)
1073                         return 0;
1074         }
1075
1076         rc = hl_poll_timeout(
1077                 hdev,
1078                 glbl_sts0_reg,
1079                 status,
1080                 (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK),
1081                 1000,
1082                 QMAN_STOP_TIMEOUT_USEC);
1083
1084         if (rc) {
1085                 dev_err(hdev->dev,
1086                         "Timeout while waiting for QMAN to stop\n");
1087                 return -EINVAL;
1088         }
1089
1090         return 0;
1091 }
1092
1093 /*
1094  * goya_stop_external_queues - Stop external queues
1095  *
1096  * @hdev: pointer to hl_device structure
1097  *
1098  * Returns 0 on success
1099  *
1100  */
1101 static int goya_stop_external_queues(struct hl_device *hdev)
1102 {
1103         int rc, retval = 0;
1104
1105         struct goya_device *goya = hdev->asic_specific;
1106
1107         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1108                 return retval;
1109
1110         rc = goya_stop_queue(hdev,
1111                         mmDMA_QM_0_GLBL_CFG1,
1112                         mmDMA_QM_0_CP_STS,
1113                         mmDMA_QM_0_GLBL_STS0);
1114
1115         if (rc) {
1116                 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
1117                 retval = -EIO;
1118         }
1119
1120         rc = goya_stop_queue(hdev,
1121                         mmDMA_QM_1_GLBL_CFG1,
1122                         mmDMA_QM_1_CP_STS,
1123                         mmDMA_QM_1_GLBL_STS0);
1124
1125         if (rc) {
1126                 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
1127                 retval = -EIO;
1128         }
1129
1130         rc = goya_stop_queue(hdev,
1131                         mmDMA_QM_2_GLBL_CFG1,
1132                         mmDMA_QM_2_CP_STS,
1133                         mmDMA_QM_2_GLBL_STS0);
1134
1135         if (rc) {
1136                 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
1137                 retval = -EIO;
1138         }
1139
1140         rc = goya_stop_queue(hdev,
1141                         mmDMA_QM_3_GLBL_CFG1,
1142                         mmDMA_QM_3_CP_STS,
1143                         mmDMA_QM_3_GLBL_STS0);
1144
1145         if (rc) {
1146                 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
1147                 retval = -EIO;
1148         }
1149
1150         rc = goya_stop_queue(hdev,
1151                         mmDMA_QM_4_GLBL_CFG1,
1152                         mmDMA_QM_4_CP_STS,
1153                         mmDMA_QM_4_GLBL_STS0);
1154
1155         if (rc) {
1156                 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
1157                 retval = -EIO;
1158         }
1159
1160         return retval;
1161 }
1162
1163 /*
1164  * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
1165  *
1166  * @hdev: pointer to hl_device structure
1167  *
1168  * Returns 0 on success
1169  *
1170  */
1171 int goya_init_cpu_queues(struct hl_device *hdev)
1172 {
1173         struct goya_device *goya = hdev->asic_specific;
1174         struct hl_eq *eq;
1175         u32 status;
1176         struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
1177         int err;
1178
1179         if (!hdev->cpu_queues_enable)
1180                 return 0;
1181
1182         if (goya->hw_cap_initialized & HW_CAP_CPU_Q)
1183                 return 0;
1184
1185         eq = &hdev->event_queue;
1186
1187         WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
1188         WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
1189
1190         WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
1191         WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
1192
1193         WREG32(mmCPU_CQ_BASE_ADDR_LOW,
1194                         lower_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1195         WREG32(mmCPU_CQ_BASE_ADDR_HIGH,
1196                         upper_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1197
1198         WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
1199         WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
1200         WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
1201
1202         /* Used for EQ CI */
1203         WREG32(mmCPU_EQ_CI, 0);
1204
1205         WREG32(mmCPU_IF_PF_PQ_PI, 0);
1206
1207         WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP);
1208
1209         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1210                         GOYA_ASYNC_EVENT_ID_PI_UPDATE);
1211
1212         err = hl_poll_timeout(
1213                 hdev,
1214                 mmCPU_PQ_INIT_STATUS,
1215                 status,
1216                 (status == PQ_INIT_STATUS_READY_FOR_HOST),
1217                 1000,
1218                 GOYA_CPU_TIMEOUT_USEC);
1219
1220         if (err) {
1221                 dev_err(hdev->dev,
1222                         "Failed to setup communication with device CPU\n");
1223                 return -EIO;
1224         }
1225
1226         goya->hw_cap_initialized |= HW_CAP_CPU_Q;
1227         return 0;
1228 }
1229
1230 static void goya_set_pll_refclk(struct hl_device *hdev)
1231 {
1232         WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1233         WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1234         WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1235         WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1236
1237         WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1238         WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1239         WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1240         WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1241
1242         WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1243         WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1244         WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1245         WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1246
1247         WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1248         WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1249         WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1250         WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1251
1252         WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1253         WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1254         WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1255         WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1256
1257         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1258         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1259         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1260         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1261
1262         WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1263         WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1264         WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1265         WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1266 }
1267
1268 static void goya_disable_clk_rlx(struct hl_device *hdev)
1269 {
1270         WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1271         WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1272 }
1273
1274 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1275 {
1276         u64 tpc_eml_address;
1277         u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1278         int err, slm_index;
1279
1280         tpc_offset = tpc_id * 0x40000;
1281         tpc_eml_offset = tpc_id * 0x200000;
1282         tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE);
1283         tpc_slm_offset = tpc_eml_address + 0x100000;
1284
1285         /*
1286          * Workaround for Bug H2 #2443 :
1287          * "TPC SB is not initialized on chip reset"
1288          */
1289
1290         val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1291         if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1292                 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1293                         tpc_id);
1294
1295         WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1296
1297         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1298         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1299         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1300         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1301         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1302         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1303         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1304         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1305         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1306         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1307
1308         WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1309                 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT);
1310
1311         err = hl_poll_timeout(
1312                 hdev,
1313                 mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1314                 val,
1315                 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1316                 1000,
1317                 HL_DEVICE_TIMEOUT_USEC);
1318
1319         if (err)
1320                 dev_err(hdev->dev,
1321                         "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id);
1322
1323         WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1324                 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT);
1325
1326         msleep(GOYA_RESET_WAIT_MSEC);
1327
1328         WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1329                 ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT));
1330
1331         msleep(GOYA_RESET_WAIT_MSEC);
1332
1333         for (slm_index = 0 ; slm_index < 256 ; slm_index++)
1334                 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1335
1336         val = RREG32(tpc_slm_offset);
1337 }
1338
1339 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1340 {
1341         struct goya_device *goya = hdev->asic_specific;
1342         int i;
1343
1344         if (hdev->pldm)
1345                 return;
1346
1347         if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST)
1348                 return;
1349
1350         /* Workaround for H2 #2443 */
1351
1352         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1353                 _goya_tpc_mbist_workaround(hdev, i);
1354
1355         goya->hw_cap_initialized |= HW_CAP_TPC_MBIST;
1356 }
1357
1358 /*
1359  * goya_init_golden_registers - Initialize golden registers
1360  *
1361  * @hdev: pointer to hl_device structure
1362  *
1363  * Initialize the H/W registers of the device
1364  *
1365  */
1366 static void goya_init_golden_registers(struct hl_device *hdev)
1367 {
1368         struct goya_device *goya = hdev->asic_specific;
1369         u32 polynom[10], tpc_intr_mask, offset;
1370         int i;
1371
1372         if (goya->hw_cap_initialized & HW_CAP_GOLDEN)
1373                 return;
1374
1375         polynom[0] = 0x00020080;
1376         polynom[1] = 0x00401000;
1377         polynom[2] = 0x00200800;
1378         polynom[3] = 0x00002000;
1379         polynom[4] = 0x00080200;
1380         polynom[5] = 0x00040100;
1381         polynom[6] = 0x00100400;
1382         polynom[7] = 0x00004000;
1383         polynom[8] = 0x00010000;
1384         polynom[9] = 0x00008000;
1385
1386         /* Mask all arithmetic interrupts from TPC */
1387         tpc_intr_mask = 0x7FFF;
1388
1389         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) {
1390                 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1391                 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1392                 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1393                 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1394                 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1395
1396                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1397                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1398                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1399                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1400                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1401
1402
1403                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1404                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1405                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1406                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1407                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1408
1409                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1410                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1411                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1412                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1413                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1414
1415                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1416                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1417                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1418                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1419                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1420
1421                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1422                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1423                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1424                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1425                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1426         }
1427
1428         WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1429         WREG32(mmMME_AGU, 0x0f0f0f10);
1430         WREG32(mmMME_SEI_MASK, ~0x0);
1431
1432         WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1433         WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1434         WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1435         WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1436         WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1437         WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1438         WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1439         WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1440         WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1441         WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1442         WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1443         WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1444         WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1445         WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1446         WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1447         WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1448         WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1449         WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1450         WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1451         WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1452         WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1453         WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1454         WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1455         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1456         WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1457         WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1458         WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1459         WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1460         WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1461         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1462         WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1463         WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1464         WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1465         WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1466         WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1467         WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1468         WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1469         WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1470         WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1471         WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1472         WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1473         WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1474         WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1475         WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1476         WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1477         WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1478         WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1479         WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1480         WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1481         WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1482         WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1483         WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1484         WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1485         WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1486         WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1487         WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1488         WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1489         WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1490         WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1491         WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1492         WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1493         WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1494         WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1495         WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1496         WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1497         WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1498         WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1499         WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1500         WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1501         WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1502         WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1503         WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1504         WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1505         WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1506         WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1507         WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1508         WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1509         WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1510         WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1511         WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1512         WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1513         WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1514         WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1515         WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1516
1517         WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1518         WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1519         WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1520         WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1521         WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1522         WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1523         WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1524         WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1525         WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1526         WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1527         WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1528         WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1529
1530         WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1531         WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1532         WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1533         WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1534         WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1535         WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1536         WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1537         WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1538         WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1539         WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1540         WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1541         WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1542
1543         WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1544         WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1545         WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1546         WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1547         WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1548         WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1549         WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1550         WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1551         WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1552         WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1553         WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1554         WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1555
1556         WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1557         WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1558         WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1559         WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1560         WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1561         WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1562         WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1563         WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1564         WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1565         WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1566         WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1567         WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1568
1569         WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1570         WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1571         WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1572         WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1573         WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1574         WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1575         WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1576         WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1577         WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1578         WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1579         WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1580         WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1581
1582         WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1583         WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1584         WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1585         WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1586         WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1587         WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1588         WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1589         WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1590         WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1591         WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1592         WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1593         WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1594
1595         for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) {
1596                 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1597                 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1598                 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1599                 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1600                 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1601                 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1602
1603                 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1604                 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1605                 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1606                 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1607                 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1608                 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1609                 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1610                 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1611
1612                 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1613                 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1614         }
1615
1616         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) {
1617                 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1618                                 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT);
1619                 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1620                                 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT);
1621         }
1622
1623         for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) {
1624                 /*
1625                  * Workaround for Bug H2 #2441 :
1626                  * "ST.NOP set trace event illegal opcode"
1627                  */
1628                 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1629
1630                 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1631                                 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
1632                 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1633                                 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1634
1635                 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset,
1636                                 ICACHE_FETCH_LINE_NUM, 2);
1637         }
1638
1639         WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1640         WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1641                         1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1642
1643         WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1644         WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1645                         1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1646
1647         /*
1648          * Workaround for H2 #HW-23 bug
1649          * Set DMA max outstanding read requests to 240 on DMA CH 1.
1650          * This limitation is still large enough to not affect Gen4 bandwidth.
1651          * We need to only limit that DMA channel because the user can only read
1652          * from Host using DMA CH 1
1653          */
1654         WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1655
1656         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1657
1658         goya->hw_cap_initialized |= HW_CAP_GOLDEN;
1659 }
1660
1661 static void goya_init_mme_qman(struct hl_device *hdev)
1662 {
1663         u32 mtr_base_lo, mtr_base_hi;
1664         u32 so_base_lo, so_base_hi;
1665         u32 gic_base_lo, gic_base_hi;
1666         u64 qman_base_addr;
1667
1668         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1669         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1670         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1671         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1672
1673         gic_base_lo =
1674                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1675         gic_base_hi =
1676                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1677
1678         qman_base_addr = hdev->asic_prop.sram_base_address +
1679                                 MME_QMAN_BASE_OFFSET;
1680
1681         WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1682         WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1683         WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1684         WREG32(mmMME_QM_PQ_PI, 0);
1685         WREG32(mmMME_QM_PQ_CI, 0);
1686         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1687         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1688         WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1689         WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1690
1691         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1692         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1693         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1694         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1695
1696         /* QMAN CQ has 8 cache lines */
1697         WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1698
1699         WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1700         WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1701
1702         WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1703
1704         WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1705
1706         WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1707
1708         WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1709 }
1710
1711 static void goya_init_mme_cmdq(struct hl_device *hdev)
1712 {
1713         u32 mtr_base_lo, mtr_base_hi;
1714         u32 so_base_lo, so_base_hi;
1715         u32 gic_base_lo, gic_base_hi;
1716
1717         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1718         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1719         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1720         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1721
1722         gic_base_lo =
1723                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1724         gic_base_hi =
1725                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1726
1727         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1728         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1729         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1730         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1731
1732         /* CMDQ CQ has 20 cache lines */
1733         WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1734
1735         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1736         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1737
1738         WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1739
1740         WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1741
1742         WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1743
1744         WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1745 }
1746
1747 void goya_init_mme_qmans(struct hl_device *hdev)
1748 {
1749         struct goya_device *goya = hdev->asic_specific;
1750         u32 so_base_lo, so_base_hi;
1751
1752         if (goya->hw_cap_initialized & HW_CAP_MME)
1753                 return;
1754
1755         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1756         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1757
1758         WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1759         WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1760
1761         goya_init_mme_qman(hdev);
1762         goya_init_mme_cmdq(hdev);
1763
1764         goya->hw_cap_initialized |= HW_CAP_MME;
1765 }
1766
1767 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1768 {
1769         u32 mtr_base_lo, mtr_base_hi;
1770         u32 so_base_lo, so_base_hi;
1771         u32 gic_base_lo, gic_base_hi;
1772         u64 qman_base_addr;
1773         u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
1774
1775         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1776         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1777         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1778         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1779
1780         gic_base_lo =
1781                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1782         gic_base_hi =
1783                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1784
1785         qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1786
1787         WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1788         WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1789         WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1790         WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1791         WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1792         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1793         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1794         WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1795         WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1796
1797         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1798         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1799         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1800         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1801
1802         WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1803
1804         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1805         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1806
1807         WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1808                         GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id);
1809
1810         WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1811
1812         WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1813
1814         WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1815 }
1816
1817 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
1818 {
1819         u32 mtr_base_lo, mtr_base_hi;
1820         u32 so_base_lo, so_base_hi;
1821         u32 gic_base_lo, gic_base_hi;
1822         u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
1823
1824         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1825         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1826         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1827         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1828
1829         gic_base_lo =
1830                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1831         gic_base_hi =
1832                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1833
1834         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1835         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1836         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1837         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1838
1839         WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
1840
1841         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1842         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1843
1844         WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
1845                         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id);
1846
1847         WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
1848
1849         WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
1850
1851         WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
1852 }
1853
1854 void goya_init_tpc_qmans(struct hl_device *hdev)
1855 {
1856         struct goya_device *goya = hdev->asic_specific;
1857         u32 so_base_lo, so_base_hi;
1858         u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW -
1859                         mmTPC0_CFG_SM_BASE_ADDRESS_LOW;
1860         int i;
1861
1862         if (goya->hw_cap_initialized & HW_CAP_TPC)
1863                 return;
1864
1865         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1866         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1867
1868         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
1869                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
1870                                 so_base_lo);
1871                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
1872                                 so_base_hi);
1873         }
1874
1875         goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
1876         goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
1877         goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
1878         goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
1879         goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
1880         goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
1881         goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
1882         goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
1883
1884         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1885                 goya_init_tpc_cmdq(hdev, i);
1886
1887         goya->hw_cap_initialized |= HW_CAP_TPC;
1888 }
1889
1890 /*
1891  * goya_disable_internal_queues - Disable internal queues
1892  *
1893  * @hdev: pointer to hl_device structure
1894  *
1895  */
1896 static void goya_disable_internal_queues(struct hl_device *hdev)
1897 {
1898         struct goya_device *goya = hdev->asic_specific;
1899
1900         if (!(goya->hw_cap_initialized & HW_CAP_MME))
1901                 goto disable_tpc;
1902
1903         WREG32(mmMME_QM_GLBL_CFG0, 0);
1904         WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
1905
1906 disable_tpc:
1907         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
1908                 return;
1909
1910         WREG32(mmTPC0_QM_GLBL_CFG0, 0);
1911         WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
1912
1913         WREG32(mmTPC1_QM_GLBL_CFG0, 0);
1914         WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
1915
1916         WREG32(mmTPC2_QM_GLBL_CFG0, 0);
1917         WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
1918
1919         WREG32(mmTPC3_QM_GLBL_CFG0, 0);
1920         WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
1921
1922         WREG32(mmTPC4_QM_GLBL_CFG0, 0);
1923         WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
1924
1925         WREG32(mmTPC5_QM_GLBL_CFG0, 0);
1926         WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
1927
1928         WREG32(mmTPC6_QM_GLBL_CFG0, 0);
1929         WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
1930
1931         WREG32(mmTPC7_QM_GLBL_CFG0, 0);
1932         WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
1933 }
1934
1935 /*
1936  * goya_stop_internal_queues - Stop internal queues
1937  *
1938  * @hdev: pointer to hl_device structure
1939  *
1940  * Returns 0 on success
1941  *
1942  */
1943 static int goya_stop_internal_queues(struct hl_device *hdev)
1944 {
1945         struct goya_device *goya = hdev->asic_specific;
1946         int rc, retval = 0;
1947
1948         if (!(goya->hw_cap_initialized & HW_CAP_MME))
1949                 goto stop_tpc;
1950
1951         /*
1952          * Each queue (QMAN) is a separate H/W logic. That means that each
1953          * QMAN can be stopped independently and failure to stop one does NOT
1954          * mandate we should not try to stop other QMANs
1955          */
1956
1957         rc = goya_stop_queue(hdev,
1958                         mmMME_QM_GLBL_CFG1,
1959                         mmMME_QM_CP_STS,
1960                         mmMME_QM_GLBL_STS0);
1961
1962         if (rc) {
1963                 dev_err(hdev->dev, "failed to stop MME QMAN\n");
1964                 retval = -EIO;
1965         }
1966
1967         rc = goya_stop_queue(hdev,
1968                         mmMME_CMDQ_GLBL_CFG1,
1969                         mmMME_CMDQ_CP_STS,
1970                         mmMME_CMDQ_GLBL_STS0);
1971
1972         if (rc) {
1973                 dev_err(hdev->dev, "failed to stop MME CMDQ\n");
1974                 retval = -EIO;
1975         }
1976
1977 stop_tpc:
1978         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
1979                 return retval;
1980
1981         rc = goya_stop_queue(hdev,
1982                         mmTPC0_QM_GLBL_CFG1,
1983                         mmTPC0_QM_CP_STS,
1984                         mmTPC0_QM_GLBL_STS0);
1985
1986         if (rc) {
1987                 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
1988                 retval = -EIO;
1989         }
1990
1991         rc = goya_stop_queue(hdev,
1992                         mmTPC0_CMDQ_GLBL_CFG1,
1993                         mmTPC0_CMDQ_CP_STS,
1994                         mmTPC0_CMDQ_GLBL_STS0);
1995
1996         if (rc) {
1997                 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
1998                 retval = -EIO;
1999         }
2000
2001         rc = goya_stop_queue(hdev,
2002                         mmTPC1_QM_GLBL_CFG1,
2003                         mmTPC1_QM_CP_STS,
2004                         mmTPC1_QM_GLBL_STS0);
2005
2006         if (rc) {
2007                 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
2008                 retval = -EIO;
2009         }
2010
2011         rc = goya_stop_queue(hdev,
2012                         mmTPC1_CMDQ_GLBL_CFG1,
2013                         mmTPC1_CMDQ_CP_STS,
2014                         mmTPC1_CMDQ_GLBL_STS0);
2015
2016         if (rc) {
2017                 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
2018                 retval = -EIO;
2019         }
2020
2021         rc = goya_stop_queue(hdev,
2022                         mmTPC2_QM_GLBL_CFG1,
2023                         mmTPC2_QM_CP_STS,
2024                         mmTPC2_QM_GLBL_STS0);
2025
2026         if (rc) {
2027                 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
2028                 retval = -EIO;
2029         }
2030
2031         rc = goya_stop_queue(hdev,
2032                         mmTPC2_CMDQ_GLBL_CFG1,
2033                         mmTPC2_CMDQ_CP_STS,
2034                         mmTPC2_CMDQ_GLBL_STS0);
2035
2036         if (rc) {
2037                 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
2038                 retval = -EIO;
2039         }
2040
2041         rc = goya_stop_queue(hdev,
2042                         mmTPC3_QM_GLBL_CFG1,
2043                         mmTPC3_QM_CP_STS,
2044                         mmTPC3_QM_GLBL_STS0);
2045
2046         if (rc) {
2047                 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
2048                 retval = -EIO;
2049         }
2050
2051         rc = goya_stop_queue(hdev,
2052                         mmTPC3_CMDQ_GLBL_CFG1,
2053                         mmTPC3_CMDQ_CP_STS,
2054                         mmTPC3_CMDQ_GLBL_STS0);
2055
2056         if (rc) {
2057                 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
2058                 retval = -EIO;
2059         }
2060
2061         rc = goya_stop_queue(hdev,
2062                         mmTPC4_QM_GLBL_CFG1,
2063                         mmTPC4_QM_CP_STS,
2064                         mmTPC4_QM_GLBL_STS0);
2065
2066         if (rc) {
2067                 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
2068                 retval = -EIO;
2069         }
2070
2071         rc = goya_stop_queue(hdev,
2072                         mmTPC4_CMDQ_GLBL_CFG1,
2073                         mmTPC4_CMDQ_CP_STS,
2074                         mmTPC4_CMDQ_GLBL_STS0);
2075
2076         if (rc) {
2077                 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
2078                 retval = -EIO;
2079         }
2080
2081         rc = goya_stop_queue(hdev,
2082                         mmTPC5_QM_GLBL_CFG1,
2083                         mmTPC5_QM_CP_STS,
2084                         mmTPC5_QM_GLBL_STS0);
2085
2086         if (rc) {
2087                 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
2088                 retval = -EIO;
2089         }
2090
2091         rc = goya_stop_queue(hdev,
2092                         mmTPC5_CMDQ_GLBL_CFG1,
2093                         mmTPC5_CMDQ_CP_STS,
2094                         mmTPC5_CMDQ_GLBL_STS0);
2095
2096         if (rc) {
2097                 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
2098                 retval = -EIO;
2099         }
2100
2101         rc = goya_stop_queue(hdev,
2102                         mmTPC6_QM_GLBL_CFG1,
2103                         mmTPC6_QM_CP_STS,
2104                         mmTPC6_QM_GLBL_STS0);
2105
2106         if (rc) {
2107                 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
2108                 retval = -EIO;
2109         }
2110
2111         rc = goya_stop_queue(hdev,
2112                         mmTPC6_CMDQ_GLBL_CFG1,
2113                         mmTPC6_CMDQ_CP_STS,
2114                         mmTPC6_CMDQ_GLBL_STS0);
2115
2116         if (rc) {
2117                 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
2118                 retval = -EIO;
2119         }
2120
2121         rc = goya_stop_queue(hdev,
2122                         mmTPC7_QM_GLBL_CFG1,
2123                         mmTPC7_QM_CP_STS,
2124                         mmTPC7_QM_GLBL_STS0);
2125
2126         if (rc) {
2127                 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
2128                 retval = -EIO;
2129         }
2130
2131         rc = goya_stop_queue(hdev,
2132                         mmTPC7_CMDQ_GLBL_CFG1,
2133                         mmTPC7_CMDQ_CP_STS,
2134                         mmTPC7_CMDQ_GLBL_STS0);
2135
2136         if (rc) {
2137                 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
2138                 retval = -EIO;
2139         }
2140
2141         return retval;
2142 }
2143
2144 static void goya_dma_stall(struct hl_device *hdev)
2145 {
2146         struct goya_device *goya = hdev->asic_specific;
2147
2148         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
2149                 return;
2150
2151         WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2152         WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2153         WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2154         WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2155         WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2156 }
2157
2158 static void goya_tpc_stall(struct hl_device *hdev)
2159 {
2160         struct goya_device *goya = hdev->asic_specific;
2161
2162         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2163                 return;
2164
2165         WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2166         WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2167         WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2168         WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2169         WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2170         WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2171         WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2172         WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2173 }
2174
2175 static void goya_mme_stall(struct hl_device *hdev)
2176 {
2177         struct goya_device *goya = hdev->asic_specific;
2178
2179         if (!(goya->hw_cap_initialized & HW_CAP_MME))
2180                 return;
2181
2182         WREG32(mmMME_STALL, 0xFFFFFFFF);
2183 }
2184
2185 static int goya_enable_msix(struct hl_device *hdev)
2186 {
2187         struct goya_device *goya = hdev->asic_specific;
2188         int cq_cnt = hdev->asic_prop.completion_queues_count;
2189         int rc, i, irq_cnt_init, irq;
2190
2191         if (goya->hw_cap_initialized & HW_CAP_MSIX)
2192                 return 0;
2193
2194         rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
2195                                 GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX);
2196         if (rc < 0) {
2197                 dev_err(hdev->dev,
2198                         "MSI-X: Failed to enable support -- %d/%d\n",
2199                         GOYA_MSIX_ENTRIES, rc);
2200                 return rc;
2201         }
2202
2203         for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
2204                 irq = pci_irq_vector(hdev->pdev, i);
2205                 rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i],
2206                                 &hdev->completion_queue[i]);
2207                 if (rc) {
2208                         dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2209                         goto free_irqs;
2210                 }
2211         }
2212
2213         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2214
2215         rc = request_irq(irq, hl_irq_handler_eq, 0,
2216                         goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX],
2217                         &hdev->event_queue);
2218         if (rc) {
2219                 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2220                 goto free_irqs;
2221         }
2222
2223         goya->hw_cap_initialized |= HW_CAP_MSIX;
2224         return 0;
2225
2226 free_irqs:
2227         for (i = 0 ; i < irq_cnt_init ; i++)
2228                 free_irq(pci_irq_vector(hdev->pdev, i),
2229                         &hdev->completion_queue[i]);
2230
2231         pci_free_irq_vectors(hdev->pdev);
2232         return rc;
2233 }
2234
2235 static void goya_sync_irqs(struct hl_device *hdev)
2236 {
2237         struct goya_device *goya = hdev->asic_specific;
2238         int i;
2239
2240         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2241                 return;
2242
2243         /* Wait for all pending IRQs to be finished */
2244         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2245                 synchronize_irq(pci_irq_vector(hdev->pdev, i));
2246
2247         synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
2248 }
2249
2250 static void goya_disable_msix(struct hl_device *hdev)
2251 {
2252         struct goya_device *goya = hdev->asic_specific;
2253         int i, irq;
2254
2255         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2256                 return;
2257
2258         goya_sync_irqs(hdev);
2259
2260         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2261         free_irq(irq, &hdev->event_queue);
2262
2263         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2264                 irq = pci_irq_vector(hdev->pdev, i);
2265                 free_irq(irq, &hdev->completion_queue[i]);
2266         }
2267
2268         pci_free_irq_vectors(hdev->pdev);
2269
2270         goya->hw_cap_initialized &= ~HW_CAP_MSIX;
2271 }
2272
2273 static void goya_enable_timestamp(struct hl_device *hdev)
2274 {
2275         /* Disable the timestamp counter */
2276         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2277
2278         /* Zero the lower/upper parts of the 64-bit counter */
2279         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
2280         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
2281
2282         /* Enable the counter */
2283         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
2284 }
2285
2286 static void goya_disable_timestamp(struct hl_device *hdev)
2287 {
2288         /* Disable the timestamp counter */
2289         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2290 }
2291
2292 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset)
2293 {
2294         u32 wait_timeout_ms;
2295
2296         dev_info(hdev->dev,
2297                 "Halting compute engines and disabling interrupts\n");
2298
2299         if (hdev->pldm)
2300                 wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2301         else
2302                 wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
2303
2304         goya_stop_external_queues(hdev);
2305         goya_stop_internal_queues(hdev);
2306
2307         msleep(wait_timeout_ms);
2308
2309         goya_dma_stall(hdev);
2310         goya_tpc_stall(hdev);
2311         goya_mme_stall(hdev);
2312
2313         msleep(wait_timeout_ms);
2314
2315         goya_disable_external_queues(hdev);
2316         goya_disable_internal_queues(hdev);
2317
2318         goya_disable_timestamp(hdev);
2319
2320         if (hard_reset) {
2321                 goya_disable_msix(hdev);
2322                 goya_mmu_remove_device_cpu_mappings(hdev);
2323         } else {
2324                 goya_sync_irqs(hdev);
2325         }
2326 }
2327
2328 /*
2329  * goya_load_firmware_to_device() - Load LINUX FW code to device.
2330  * @hdev: Pointer to hl_device structure.
2331  *
2332  * Copy LINUX fw code from firmware file to HBM BAR.
2333  *
2334  * Return: 0 on success, non-zero for failure.
2335  */
2336 static int goya_load_firmware_to_device(struct hl_device *hdev)
2337 {
2338         void __iomem *dst;
2339
2340         dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2341
2342         return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst, 0, 0);
2343 }
2344
2345 /*
2346  * goya_load_boot_fit_to_device() - Load boot fit to device.
2347  * @hdev: Pointer to hl_device structure.
2348  *
2349  * Copy boot fit file to SRAM BAR.
2350  *
2351  * Return: 0 on success, non-zero for failure.
2352  */
2353 static int goya_load_boot_fit_to_device(struct hl_device *hdev)
2354 {
2355         void __iomem *dst;
2356
2357         dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET;
2358
2359         return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst, 0, 0);
2360 }
2361
2362 /*
2363  * FW component passes an offset from SRAM_BASE_ADDR in SCRATCHPAD_xx.
2364  * The version string should be located by that offset.
2365  */
2366 static int goya_read_device_fw_version(struct hl_device *hdev,
2367                                         enum hl_fw_component fwc)
2368 {
2369         const char *name;
2370         u32 ver_off;
2371         char *dest;
2372
2373         switch (fwc) {
2374         case FW_COMP_UBOOT:
2375                 ver_off = RREG32(mmUBOOT_VER_OFFSET);
2376                 dest = hdev->asic_prop.uboot_ver;
2377                 name = "U-Boot";
2378                 break;
2379         case FW_COMP_PREBOOT:
2380                 ver_off = RREG32(mmPREBOOT_VER_OFFSET);
2381                 dest = hdev->asic_prop.preboot_ver;
2382                 name = "Preboot";
2383                 break;
2384         default:
2385                 dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc);
2386                 return -EIO;
2387         }
2388
2389         ver_off &= ~((u32)SRAM_BASE_ADDR);
2390
2391         if (ver_off < SRAM_SIZE - VERSION_MAX_LEN) {
2392                 memcpy_fromio(dest, hdev->pcie_bar[SRAM_CFG_BAR_ID] + ver_off,
2393                                                         VERSION_MAX_LEN);
2394         } else {
2395                 dev_err(hdev->dev, "%s version offset (0x%x) is above SRAM\n",
2396                                                                 name, ver_off);
2397                 strcpy(dest, "unavailable");
2398
2399                 return -EIO;
2400         }
2401
2402         return 0;
2403 }
2404
2405 static int goya_init_cpu(struct hl_device *hdev)
2406 {
2407         struct goya_device *goya = hdev->asic_specific;
2408         int rc;
2409
2410         if (!hdev->cpu_enable)
2411                 return 0;
2412
2413         if (goya->hw_cap_initialized & HW_CAP_CPU)
2414                 return 0;
2415
2416         /*
2417          * Before pushing u-boot/linux to device, need to set the ddr bar to
2418          * base address of dram
2419          */
2420         if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
2421                 dev_err(hdev->dev,
2422                         "failed to map DDR bar to DRAM base address\n");
2423                 return -EIO;
2424         }
2425
2426         rc = hl_fw_init_cpu(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS,
2427                         mmPSOC_GLOBAL_CONF_UBOOT_MAGIC,
2428                         mmCPU_CMD_STATUS_TO_HOST,
2429                         mmCPU_BOOT_DEV_STS0, mmCPU_BOOT_ERR0,
2430                         false, GOYA_CPU_TIMEOUT_USEC,
2431                         GOYA_BOOT_FIT_REQ_TIMEOUT_USEC);
2432
2433         if (rc)
2434                 return rc;
2435
2436         goya->hw_cap_initialized |= HW_CAP_CPU;
2437
2438         return 0;
2439 }
2440
2441 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
2442                                                 u64 phys_addr)
2443 {
2444         u32 status, timeout_usec;
2445         int rc;
2446
2447         if (hdev->pldm)
2448                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
2449         else
2450                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
2451
2452         WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2453         WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2454         WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2455
2456         rc = hl_poll_timeout(
2457                 hdev,
2458                 MMU_ASID_BUSY,
2459                 status,
2460                 !(status & 0x80000000),
2461                 1000,
2462                 timeout_usec);
2463
2464         if (rc) {
2465                 dev_err(hdev->dev,
2466                         "Timeout during MMU hop0 config of asid %d\n", asid);
2467                 return rc;
2468         }
2469
2470         return 0;
2471 }
2472
2473 int goya_mmu_init(struct hl_device *hdev)
2474 {
2475         struct asic_fixed_properties *prop = &hdev->asic_prop;
2476         struct goya_device *goya = hdev->asic_specific;
2477         u64 hop0_addr;
2478         int rc, i;
2479
2480         if (!hdev->mmu_enable)
2481                 return 0;
2482
2483         if (goya->hw_cap_initialized & HW_CAP_MMU)
2484                 return 0;
2485
2486         hdev->dram_default_page_mapping = true;
2487
2488         for (i = 0 ; i < prop->max_asid ; i++) {
2489                 hop0_addr = prop->mmu_pgt_addr +
2490                                 (i * prop->mmu_hop_table_size);
2491
2492                 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2493                 if (rc) {
2494                         dev_err(hdev->dev,
2495                                 "failed to set hop0 addr for asid %d\n", i);
2496                         goto err;
2497                 }
2498         }
2499
2500         goya->hw_cap_initialized |= HW_CAP_MMU;
2501
2502         /* init MMU cache manage page */
2503         WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2504                                 lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
2505         WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2506
2507         /* Remove follower feature due to performance bug */
2508         WREG32_AND(mmSTLB_STLB_FEATURE_EN,
2509                         (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
2510
2511         hdev->asic_funcs->mmu_invalidate_cache(hdev, true,
2512                                         VM_TYPE_USERPTR | VM_TYPE_PHYS_PACK);
2513
2514         WREG32(mmMMU_MMU_ENABLE, 1);
2515         WREG32(mmMMU_SPI_MASK, 0xF);
2516
2517         return 0;
2518
2519 err:
2520         return rc;
2521 }
2522
2523 /*
2524  * goya_hw_init - Goya hardware initialization code
2525  *
2526  * @hdev: pointer to hl_device structure
2527  *
2528  * Returns 0 on success
2529  *
2530  */
2531 static int goya_hw_init(struct hl_device *hdev)
2532 {
2533         struct asic_fixed_properties *prop = &hdev->asic_prop;
2534         int rc;
2535
2536         /* Perform read from the device to make sure device is up */
2537         RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2538
2539         /*
2540          * Let's mark in the H/W that we have reached this point. We check
2541          * this value in the reset_before_init function to understand whether
2542          * we need to reset the chip before doing H/W init. This register is
2543          * cleared by the H/W upon H/W reset
2544          */
2545         WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2546
2547         rc = goya_init_cpu(hdev);
2548         if (rc) {
2549                 dev_err(hdev->dev, "failed to initialize CPU\n");
2550                 return rc;
2551         }
2552
2553         goya_tpc_mbist_workaround(hdev);
2554
2555         goya_init_golden_registers(hdev);
2556
2557         /*
2558          * After CPU initialization is finished, change DDR bar mapping inside
2559          * iATU to point to the start address of the MMU page tables
2560          */
2561         if (goya_set_ddr_bar_base(hdev, (MMU_PAGE_TABLES_ADDR &
2562                         ~(prop->dram_pci_bar_size - 0x1ull))) == U64_MAX) {
2563                 dev_err(hdev->dev,
2564                         "failed to map DDR bar to MMU page tables\n");
2565                 return -EIO;
2566         }
2567
2568         rc = goya_mmu_init(hdev);
2569         if (rc)
2570                 return rc;
2571
2572         goya_init_security(hdev);
2573
2574         goya_init_dma_qmans(hdev);
2575
2576         goya_init_mme_qmans(hdev);
2577
2578         goya_init_tpc_qmans(hdev);
2579
2580         goya_enable_timestamp(hdev);
2581
2582         /* MSI-X must be enabled before CPU queues are initialized */
2583         rc = goya_enable_msix(hdev);
2584         if (rc)
2585                 goto disable_queues;
2586
2587         /* Perform read from the device to flush all MSI-X configuration */
2588         RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2589
2590         return 0;
2591
2592 disable_queues:
2593         goya_disable_internal_queues(hdev);
2594         goya_disable_external_queues(hdev);
2595
2596         return rc;
2597 }
2598
2599 /*
2600  * goya_hw_fini - Goya hardware tear-down code
2601  *
2602  * @hdev: pointer to hl_device structure
2603  * @hard_reset: should we do hard reset to all engines or just reset the
2604  *              compute/dma engines
2605  */
2606 static void goya_hw_fini(struct hl_device *hdev, bool hard_reset)
2607 {
2608         struct goya_device *goya = hdev->asic_specific;
2609         u32 reset_timeout_ms, cpu_timeout_ms, status;
2610
2611         if (hdev->pldm) {
2612                 reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
2613                 cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2614         } else {
2615                 reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
2616                 cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
2617         }
2618
2619         if (hard_reset) {
2620                 /* I don't know what is the state of the CPU so make sure it is
2621                  * stopped in any means necessary
2622                  */
2623                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2624                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2625                         GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
2626
2627                 msleep(cpu_timeout_ms);
2628
2629                 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2630                 goya_disable_clk_rlx(hdev);
2631                 goya_set_pll_refclk(hdev);
2632
2633                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2634                 dev_info(hdev->dev,
2635                         "Issued HARD reset command, going to wait %dms\n",
2636                         reset_timeout_ms);
2637         } else {
2638                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2639                 dev_info(hdev->dev,
2640                         "Issued SOFT reset command, going to wait %dms\n",
2641                         reset_timeout_ms);
2642         }
2643
2644         /*
2645          * After hard reset, we can't poll the BTM_FSM register because the PSOC
2646          * itself is in reset. In either reset we need to wait until the reset
2647          * is deasserted
2648          */
2649         msleep(reset_timeout_ms);
2650
2651         status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
2652         if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
2653                 dev_err(hdev->dev,
2654                         "Timeout while waiting for device to reset 0x%x\n",
2655                         status);
2656
2657         if (!hard_reset && goya) {
2658                 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
2659                                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2660                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2661                                 GOYA_ASYNC_EVENT_ID_SOFT_RESET);
2662                 return;
2663         }
2664
2665         /* Chicken bit to re-initiate boot sequencer flow */
2666         WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2667                 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT);
2668         /* Move boot manager FSM to pre boot sequencer init state */
2669         WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2670                         0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
2671
2672         if (goya) {
2673                 goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
2674                                 HW_CAP_DDR_0 | HW_CAP_DDR_1 |
2675                                 HW_CAP_DMA | HW_CAP_MME |
2676                                 HW_CAP_MMU | HW_CAP_TPC_MBIST |
2677                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2678
2679                 memset(goya->events_stat, 0, sizeof(goya->events_stat));
2680         }
2681 }
2682
2683 int goya_suspend(struct hl_device *hdev)
2684 {
2685         int rc;
2686
2687         rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS);
2688         if (rc)
2689                 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2690
2691         return rc;
2692 }
2693
2694 int goya_resume(struct hl_device *hdev)
2695 {
2696         return goya_init_iatu(hdev);
2697 }
2698
2699 static int goya_cb_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2700                         void *cpu_addr, dma_addr_t dma_addr, size_t size)
2701 {
2702         int rc;
2703
2704         vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
2705                         VM_DONTCOPY | VM_NORESERVE;
2706
2707         rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr, dma_addr, size);
2708         if (rc)
2709                 dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
2710
2711         return rc;
2712 }
2713
2714 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2715 {
2716         u32 db_reg_offset, db_value;
2717
2718         switch (hw_queue_id) {
2719         case GOYA_QUEUE_ID_DMA_0:
2720                 db_reg_offset = mmDMA_QM_0_PQ_PI;
2721                 break;
2722
2723         case GOYA_QUEUE_ID_DMA_1:
2724                 db_reg_offset = mmDMA_QM_1_PQ_PI;
2725                 break;
2726
2727         case GOYA_QUEUE_ID_DMA_2:
2728                 db_reg_offset = mmDMA_QM_2_PQ_PI;
2729                 break;
2730
2731         case GOYA_QUEUE_ID_DMA_3:
2732                 db_reg_offset = mmDMA_QM_3_PQ_PI;
2733                 break;
2734
2735         case GOYA_QUEUE_ID_DMA_4:
2736                 db_reg_offset = mmDMA_QM_4_PQ_PI;
2737                 break;
2738
2739         case GOYA_QUEUE_ID_CPU_PQ:
2740                 db_reg_offset = mmCPU_IF_PF_PQ_PI;
2741                 break;
2742
2743         case GOYA_QUEUE_ID_MME:
2744                 db_reg_offset = mmMME_QM_PQ_PI;
2745                 break;
2746
2747         case GOYA_QUEUE_ID_TPC0:
2748                 db_reg_offset = mmTPC0_QM_PQ_PI;
2749                 break;
2750
2751         case GOYA_QUEUE_ID_TPC1:
2752                 db_reg_offset = mmTPC1_QM_PQ_PI;
2753                 break;
2754
2755         case GOYA_QUEUE_ID_TPC2:
2756                 db_reg_offset = mmTPC2_QM_PQ_PI;
2757                 break;
2758
2759         case GOYA_QUEUE_ID_TPC3:
2760                 db_reg_offset = mmTPC3_QM_PQ_PI;
2761                 break;
2762
2763         case GOYA_QUEUE_ID_TPC4:
2764                 db_reg_offset = mmTPC4_QM_PQ_PI;
2765                 break;
2766
2767         case GOYA_QUEUE_ID_TPC5:
2768                 db_reg_offset = mmTPC5_QM_PQ_PI;
2769                 break;
2770
2771         case GOYA_QUEUE_ID_TPC6:
2772                 db_reg_offset = mmTPC6_QM_PQ_PI;
2773                 break;
2774
2775         case GOYA_QUEUE_ID_TPC7:
2776                 db_reg_offset = mmTPC7_QM_PQ_PI;
2777                 break;
2778
2779         default:
2780                 /* Should never get here */
2781                 dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n",
2782                         hw_queue_id);
2783                 return;
2784         }
2785
2786         db_value = pi;
2787
2788         /* ring the doorbell */
2789         WREG32(db_reg_offset, db_value);
2790
2791         if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ)
2792                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2793                                 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2794 }
2795
2796 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
2797 {
2798         /* The QMANs are on the SRAM so need to copy to IO space */
2799         memcpy_toio((void __iomem *) pqe, bd, sizeof(struct hl_bd));
2800 }
2801
2802 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2803                                         dma_addr_t *dma_handle, gfp_t flags)
2804 {
2805         void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
2806                                                 dma_handle, flags);
2807
2808         /* Shift to the device's base physical address of host memory */
2809         if (kernel_addr)
2810                 *dma_handle += HOST_PHYS_BASE;
2811
2812         return kernel_addr;
2813 }
2814
2815 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
2816                                         void *cpu_addr, dma_addr_t dma_handle)
2817 {
2818         /* Cancel the device's base physical address of host memory */
2819         dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE;
2820
2821         dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
2822 }
2823
2824 int goya_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size)
2825 {
2826         return 0;
2827 }
2828
2829 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
2830                                 dma_addr_t *dma_handle, u16 *queue_len)
2831 {
2832         void *base;
2833         u32 offset;
2834
2835         *dma_handle = hdev->asic_prop.sram_base_address;
2836
2837         base = (void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
2838
2839         switch (queue_id) {
2840         case GOYA_QUEUE_ID_MME:
2841                 offset = MME_QMAN_BASE_OFFSET;
2842                 *queue_len = MME_QMAN_LENGTH;
2843                 break;
2844         case GOYA_QUEUE_ID_TPC0:
2845                 offset = TPC0_QMAN_BASE_OFFSET;
2846                 *queue_len = TPC_QMAN_LENGTH;
2847                 break;
2848         case GOYA_QUEUE_ID_TPC1:
2849                 offset = TPC1_QMAN_BASE_OFFSET;
2850                 *queue_len = TPC_QMAN_LENGTH;
2851                 break;
2852         case GOYA_QUEUE_ID_TPC2:
2853                 offset = TPC2_QMAN_BASE_OFFSET;
2854                 *queue_len = TPC_QMAN_LENGTH;
2855                 break;
2856         case GOYA_QUEUE_ID_TPC3:
2857                 offset = TPC3_QMAN_BASE_OFFSET;
2858                 *queue_len = TPC_QMAN_LENGTH;
2859                 break;
2860         case GOYA_QUEUE_ID_TPC4:
2861                 offset = TPC4_QMAN_BASE_OFFSET;
2862                 *queue_len = TPC_QMAN_LENGTH;
2863                 break;
2864         case GOYA_QUEUE_ID_TPC5:
2865                 offset = TPC5_QMAN_BASE_OFFSET;
2866                 *queue_len = TPC_QMAN_LENGTH;
2867                 break;
2868         case GOYA_QUEUE_ID_TPC6:
2869                 offset = TPC6_QMAN_BASE_OFFSET;
2870                 *queue_len = TPC_QMAN_LENGTH;
2871                 break;
2872         case GOYA_QUEUE_ID_TPC7:
2873                 offset = TPC7_QMAN_BASE_OFFSET;
2874                 *queue_len = TPC_QMAN_LENGTH;
2875                 break;
2876         default:
2877                 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
2878                 return NULL;
2879         }
2880
2881         base += offset;
2882         *dma_handle += offset;
2883
2884         return base;
2885 }
2886
2887 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
2888 {
2889         struct packet_msg_prot *fence_pkt;
2890         u32 *fence_ptr;
2891         dma_addr_t fence_dma_addr;
2892         struct hl_cb *cb;
2893         u32 tmp, timeout;
2894         int rc;
2895
2896         if (hdev->pldm)
2897                 timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC;
2898         else
2899                 timeout = HL_DEVICE_TIMEOUT_USEC;
2900
2901         if (!hdev->asic_funcs->is_device_idle(hdev, NULL, NULL)) {
2902                 dev_err_ratelimited(hdev->dev,
2903                         "Can't send driver job on QMAN0 because the device is not idle\n");
2904                 return -EBUSY;
2905         }
2906
2907         fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
2908                                                         &fence_dma_addr);
2909         if (!fence_ptr) {
2910                 dev_err(hdev->dev,
2911                         "Failed to allocate fence memory for QMAN0\n");
2912                 return -ENOMEM;
2913         }
2914
2915         goya_qman0_set_security(hdev, true);
2916
2917         cb = job->patched_cb;
2918
2919         fence_pkt = cb->kernel_address +
2920                         job->job_cb_size - sizeof(struct packet_msg_prot);
2921
2922         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
2923                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
2924                         (1 << GOYA_PKT_CTL_MB_SHIFT);
2925         fence_pkt->ctl = cpu_to_le32(tmp);
2926         fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
2927         fence_pkt->addr = cpu_to_le64(fence_dma_addr);
2928
2929         rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
2930                                         job->job_cb_size, cb->bus_address);
2931         if (rc) {
2932                 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
2933                 goto free_fence_ptr;
2934         }
2935
2936         rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp,
2937                                 (tmp == GOYA_QMAN0_FENCE_VAL), 1000,
2938                                 timeout, true);
2939
2940         hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
2941
2942         if (rc == -ETIMEDOUT) {
2943                 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp);
2944                 goto free_fence_ptr;
2945         }
2946
2947 free_fence_ptr:
2948         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
2949                                         fence_dma_addr);
2950
2951         goya_qman0_set_security(hdev, false);
2952
2953         return rc;
2954 }
2955
2956 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
2957                                 u32 timeout, u64 *result)
2958 {
2959         struct goya_device *goya = hdev->asic_specific;
2960
2961         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) {
2962                 if (result)
2963                         *result = 0;
2964                 return 0;
2965         }
2966
2967         if (!timeout)
2968                 timeout = GOYA_MSG_TO_CPU_TIMEOUT_USEC;
2969
2970         return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len,
2971                                         timeout, result);
2972 }
2973
2974 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
2975 {
2976         struct packet_msg_prot *fence_pkt;
2977         dma_addr_t pkt_dma_addr;
2978         u32 fence_val, tmp;
2979         dma_addr_t fence_dma_addr;
2980         u32 *fence_ptr;
2981         int rc;
2982
2983         fence_val = GOYA_QMAN0_FENCE_VAL;
2984
2985         fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
2986                                                         &fence_dma_addr);
2987         if (!fence_ptr) {
2988                 dev_err(hdev->dev,
2989                         "Failed to allocate memory for H/W queue %d testing\n",
2990                         hw_queue_id);
2991                 return -ENOMEM;
2992         }
2993
2994         *fence_ptr = 0;
2995
2996         fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev,
2997                                         sizeof(struct packet_msg_prot),
2998                                         GFP_KERNEL, &pkt_dma_addr);
2999         if (!fence_pkt) {
3000                 dev_err(hdev->dev,
3001                         "Failed to allocate packet for H/W queue %d testing\n",
3002                         hw_queue_id);
3003                 rc = -ENOMEM;
3004                 goto free_fence_ptr;
3005         }
3006
3007         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3008                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3009                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3010         fence_pkt->ctl = cpu_to_le32(tmp);
3011         fence_pkt->value = cpu_to_le32(fence_val);
3012         fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3013
3014         rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
3015                                         sizeof(struct packet_msg_prot),
3016                                         pkt_dma_addr);
3017         if (rc) {
3018                 dev_err(hdev->dev,
3019                         "Failed to send fence packet to H/W queue %d\n",
3020                         hw_queue_id);
3021                 goto free_pkt;
3022         }
3023
3024         rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val),
3025                                         1000, GOYA_TEST_QUEUE_WAIT_USEC, true);
3026
3027         hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
3028
3029         if (rc == -ETIMEDOUT) {
3030                 dev_err(hdev->dev,
3031                         "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
3032                         hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
3033                 rc = -EIO;
3034         }
3035
3036 free_pkt:
3037         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt,
3038                                         pkt_dma_addr);
3039 free_fence_ptr:
3040         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
3041                                         fence_dma_addr);
3042         return rc;
3043 }
3044
3045 int goya_test_cpu_queue(struct hl_device *hdev)
3046 {
3047         struct goya_device *goya = hdev->asic_specific;
3048
3049         /*
3050          * check capability here as send_cpu_message() won't update the result
3051          * value if no capability
3052          */
3053         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
3054                 return 0;
3055
3056         return hl_fw_test_cpu_queue(hdev);
3057 }
3058
3059 int goya_test_queues(struct hl_device *hdev)
3060 {
3061         int i, rc, ret_val = 0;
3062
3063         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
3064                 rc = goya_test_queue(hdev, i);
3065                 if (rc)
3066                         ret_val = -EINVAL;
3067         }
3068
3069         return ret_val;
3070 }
3071
3072 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3073                                         gfp_t mem_flags, dma_addr_t *dma_handle)
3074 {
3075         void *kernel_addr;
3076
3077         if (size > GOYA_DMA_POOL_BLK_SIZE)
3078                 return NULL;
3079
3080         kernel_addr =  dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3081
3082         /* Shift to the device's base physical address of host memory */
3083         if (kernel_addr)
3084                 *dma_handle += HOST_PHYS_BASE;
3085
3086         return kernel_addr;
3087 }
3088
3089 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3090                                 dma_addr_t dma_addr)
3091 {
3092         /* Cancel the device's base physical address of host memory */
3093         dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE;
3094
3095         dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
3096 }
3097
3098 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
3099                                         dma_addr_t *dma_handle)
3100 {
3101         void *vaddr;
3102
3103         vaddr = hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
3104         *dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address +
3105                         VA_CPU_ACCESSIBLE_MEM_ADDR;
3106
3107         return vaddr;
3108 }
3109
3110 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
3111                                         void *vaddr)
3112 {
3113         hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
3114 }
3115
3116 static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sgl,
3117                                 int nents, enum dma_data_direction dir)
3118 {
3119         struct scatterlist *sg;
3120         int i;
3121
3122         if (!dma_map_sg(&hdev->pdev->dev, sgl, nents, dir))
3123                 return -ENOMEM;
3124
3125         /* Shift to the device's base physical address of host memory */
3126         for_each_sg(sgl, sg, nents, i)
3127                 sg->dma_address += HOST_PHYS_BASE;
3128
3129         return 0;
3130 }
3131
3132 static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sgl,
3133                                 int nents, enum dma_data_direction dir)
3134 {
3135         struct scatterlist *sg;
3136         int i;
3137
3138         /* Cancel the device's base physical address of host memory */
3139         for_each_sg(sgl, sg, nents, i)
3140                 sg->dma_address -= HOST_PHYS_BASE;
3141
3142         dma_unmap_sg(&hdev->pdev->dev, sgl, nents, dir);
3143 }
3144
3145 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3146 {
3147         struct scatterlist *sg, *sg_next_iter;
3148         u32 count, dma_desc_cnt;
3149         u64 len, len_next;
3150         dma_addr_t addr, addr_next;
3151
3152         dma_desc_cnt = 0;
3153
3154         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3155
3156                 len = sg_dma_len(sg);
3157                 addr = sg_dma_address(sg);
3158
3159                 if (len == 0)
3160                         break;
3161
3162                 while ((count + 1) < sgt->nents) {
3163                         sg_next_iter = sg_next(sg);
3164                         len_next = sg_dma_len(sg_next_iter);
3165                         addr_next = sg_dma_address(sg_next_iter);
3166
3167                         if (len_next == 0)
3168                                 break;
3169
3170                         if ((addr + len == addr_next) &&
3171                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3172                                 len += len_next;
3173                                 count++;
3174                                 sg = sg_next_iter;
3175                         } else {
3176                                 break;
3177                         }
3178                 }
3179
3180                 dma_desc_cnt++;
3181         }
3182
3183         return dma_desc_cnt * sizeof(struct packet_lin_dma);
3184 }
3185
3186 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3187                                 struct hl_cs_parser *parser,
3188                                 struct packet_lin_dma *user_dma_pkt,
3189                                 u64 addr, enum dma_data_direction dir)
3190 {
3191         struct hl_userptr *userptr;
3192         int rc;
3193
3194         if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3195                         parser->job_userptr_list, &userptr))
3196                 goto already_pinned;
3197
3198         userptr = kzalloc(sizeof(*userptr), GFP_ATOMIC);
3199         if (!userptr)
3200                 return -ENOMEM;
3201
3202         rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3203                                 userptr);
3204         if (rc)
3205                 goto free_userptr;
3206
3207         list_add_tail(&userptr->job_node, parser->job_userptr_list);
3208
3209         rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl,
3210                                         userptr->sgt->nents, dir);
3211         if (rc) {
3212                 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3213                 goto unpin_memory;
3214         }
3215
3216         userptr->dma_mapped = true;
3217         userptr->dir = dir;
3218
3219 already_pinned:
3220         parser->patched_cb_size +=
3221                         goya_get_dma_desc_list_size(hdev, userptr->sgt);
3222
3223         return 0;
3224
3225 unpin_memory:
3226         hl_unpin_host_memory(hdev, userptr);
3227 free_userptr:
3228         kfree(userptr);
3229         return rc;
3230 }
3231
3232 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3233                                 struct hl_cs_parser *parser,
3234                                 struct packet_lin_dma *user_dma_pkt)
3235 {
3236         u64 device_memory_addr, addr;
3237         enum dma_data_direction dir;
3238         enum goya_dma_direction user_dir;
3239         bool sram_addr = true;
3240         bool skip_host_mem_pin = false;
3241         bool user_memset;
3242         u32 ctl;
3243         int rc = 0;
3244
3245         ctl = le32_to_cpu(user_dma_pkt->ctl);
3246
3247         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3248                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3249
3250         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3251                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3252
3253         switch (user_dir) {
3254         case DMA_HOST_TO_DRAM:
3255                 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3256                 dir = DMA_TO_DEVICE;
3257                 sram_addr = false;
3258                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3259                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3260                 if (user_memset)
3261                         skip_host_mem_pin = true;
3262                 break;
3263
3264         case DMA_DRAM_TO_HOST:
3265                 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3266                 dir = DMA_FROM_DEVICE;
3267                 sram_addr = false;
3268                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3269                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3270                 break;
3271
3272         case DMA_HOST_TO_SRAM:
3273                 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3274                 dir = DMA_TO_DEVICE;
3275                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3276                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3277                 if (user_memset)
3278                         skip_host_mem_pin = true;
3279                 break;
3280
3281         case DMA_SRAM_TO_HOST:
3282                 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3283                 dir = DMA_FROM_DEVICE;
3284                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3285                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3286                 break;
3287         default:
3288                 dev_err(hdev->dev, "DMA direction is undefined\n");
3289                 return -EFAULT;
3290         }
3291
3292         if (sram_addr) {
3293                 if (!hl_mem_area_inside_range(device_memory_addr,
3294                                 le32_to_cpu(user_dma_pkt->tsize),
3295                                 hdev->asic_prop.sram_user_base_address,
3296                                 hdev->asic_prop.sram_end_address)) {
3297
3298                         dev_err(hdev->dev,
3299                                 "SRAM address 0x%llx + 0x%x is invalid\n",
3300                                 device_memory_addr,
3301                                 user_dma_pkt->tsize);
3302                         return -EFAULT;
3303                 }
3304         } else {
3305                 if (!hl_mem_area_inside_range(device_memory_addr,
3306                                 le32_to_cpu(user_dma_pkt->tsize),
3307                                 hdev->asic_prop.dram_user_base_address,
3308                                 hdev->asic_prop.dram_end_address)) {
3309
3310                         dev_err(hdev->dev,
3311                                 "DRAM address 0x%llx + 0x%x is invalid\n",
3312                                 device_memory_addr,
3313                                 user_dma_pkt->tsize);
3314                         return -EFAULT;
3315                 }
3316         }
3317
3318         if (skip_host_mem_pin)
3319                 parser->patched_cb_size += sizeof(*user_dma_pkt);
3320         else {
3321                 if ((dir == DMA_TO_DEVICE) &&
3322                                 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) {
3323                         dev_err(hdev->dev,
3324                                 "Can't DMA from host on queue other then 1\n");
3325                         return -EFAULT;
3326                 }
3327
3328                 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3329                                                 addr, dir);
3330         }
3331
3332         return rc;
3333 }
3334
3335 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3336                                 struct hl_cs_parser *parser,
3337                                 struct packet_lin_dma *user_dma_pkt)
3338 {
3339         u64 sram_memory_addr, dram_memory_addr;
3340         enum goya_dma_direction user_dir;
3341         u32 ctl;
3342
3343         ctl = le32_to_cpu(user_dma_pkt->ctl);
3344         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3345                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3346
3347         if (user_dir == DMA_DRAM_TO_SRAM) {
3348                 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3349                 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3350                 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3351         } else {
3352                 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3353                 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3354                 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3355         }
3356
3357         if (!hl_mem_area_inside_range(sram_memory_addr,
3358                                 le32_to_cpu(user_dma_pkt->tsize),
3359                                 hdev->asic_prop.sram_user_base_address,
3360                                 hdev->asic_prop.sram_end_address)) {
3361                 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3362                         sram_memory_addr, user_dma_pkt->tsize);
3363                 return -EFAULT;
3364         }
3365
3366         if (!hl_mem_area_inside_range(dram_memory_addr,
3367                                 le32_to_cpu(user_dma_pkt->tsize),
3368                                 hdev->asic_prop.dram_user_base_address,
3369                                 hdev->asic_prop.dram_end_address)) {
3370                 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3371                         dram_memory_addr, user_dma_pkt->tsize);
3372                 return -EFAULT;
3373         }
3374
3375         parser->patched_cb_size += sizeof(*user_dma_pkt);
3376
3377         return 0;
3378 }
3379
3380 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3381                                 struct hl_cs_parser *parser,
3382                                 struct packet_lin_dma *user_dma_pkt)
3383 {
3384         enum goya_dma_direction user_dir;
3385         u32 ctl;
3386         int rc;
3387
3388         dev_dbg(hdev->dev, "DMA packet details:\n");
3389         dev_dbg(hdev->dev, "source == 0x%llx\n",
3390                 le64_to_cpu(user_dma_pkt->src_addr));
3391         dev_dbg(hdev->dev, "destination == 0x%llx\n",
3392                 le64_to_cpu(user_dma_pkt->dst_addr));
3393         dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3394
3395         ctl = le32_to_cpu(user_dma_pkt->ctl);
3396         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3397                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3398
3399         /*
3400          * Special handling for DMA with size 0. The H/W has a bug where
3401          * this can cause the QMAN DMA to get stuck, so block it here.
3402          */
3403         if (user_dma_pkt->tsize == 0) {
3404                 dev_err(hdev->dev,
3405                         "Got DMA with size 0, might reset the device\n");
3406                 return -EINVAL;
3407         }
3408
3409         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM))
3410                 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3411         else
3412                 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3413
3414         return rc;
3415 }
3416
3417 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3418                                 struct hl_cs_parser *parser,
3419                                 struct packet_lin_dma *user_dma_pkt)
3420 {
3421         dev_dbg(hdev->dev, "DMA packet details:\n");
3422         dev_dbg(hdev->dev, "source == 0x%llx\n",
3423                 le64_to_cpu(user_dma_pkt->src_addr));
3424         dev_dbg(hdev->dev, "destination == 0x%llx\n",
3425                 le64_to_cpu(user_dma_pkt->dst_addr));
3426         dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3427
3428         /*
3429          * WA for HW-23.
3430          * We can't allow user to read from Host using QMANs other than 1.
3431          * PMMU and HPMMU addresses are equal, check only one of them.
3432          */
3433         if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 &&
3434                 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr),
3435                                 le32_to_cpu(user_dma_pkt->tsize),
3436                                 hdev->asic_prop.pmmu.start_addr,
3437                                 hdev->asic_prop.pmmu.end_addr)) {
3438                 dev_err(hdev->dev,
3439                         "Can't DMA from host on queue other then 1\n");
3440                 return -EFAULT;
3441         }
3442
3443         if (user_dma_pkt->tsize == 0) {
3444                 dev_err(hdev->dev,
3445                         "Got DMA with size 0, might reset the device\n");
3446                 return -EINVAL;
3447         }
3448
3449         parser->patched_cb_size += sizeof(*user_dma_pkt);
3450
3451         return 0;
3452 }
3453
3454 static int goya_validate_wreg32(struct hl_device *hdev,
3455                                 struct hl_cs_parser *parser,
3456                                 struct packet_wreg32 *wreg_pkt)
3457 {
3458         struct goya_device *goya = hdev->asic_specific;
3459         u32 sob_start_addr, sob_end_addr;
3460         u16 reg_offset;
3461
3462         reg_offset = le32_to_cpu(wreg_pkt->ctl) &
3463                         GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK;
3464
3465         dev_dbg(hdev->dev, "WREG32 packet details:\n");
3466         dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3467         dev_dbg(hdev->dev, "value      == 0x%x\n",
3468                 le32_to_cpu(wreg_pkt->value));
3469
3470         if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3471                 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3472                         reg_offset);
3473                 return -EPERM;
3474         }
3475
3476         /*
3477          * With MMU, DMA channels are not secured, so it doesn't matter where
3478          * the WR COMP will be written to because it will go out with
3479          * non-secured property
3480          */
3481         if (goya->hw_cap_initialized & HW_CAP_MMU)
3482                 return 0;
3483
3484         sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
3485         sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023);
3486
3487         if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) ||
3488                         (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) {
3489
3490                 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3491                         wreg_pkt->value);
3492                 return -EPERM;
3493         }
3494
3495         return 0;
3496 }
3497
3498 static int goya_validate_cb(struct hl_device *hdev,
3499                         struct hl_cs_parser *parser, bool is_mmu)
3500 {
3501         u32 cb_parsed_length = 0;
3502         int rc = 0;
3503
3504         parser->patched_cb_size = 0;
3505
3506         /* cb_user_size is more than 0 so loop will always be executed */
3507         while (cb_parsed_length < parser->user_cb_size) {
3508                 enum packet_id pkt_id;
3509                 u16 pkt_size;
3510                 struct goya_packet *user_pkt;
3511
3512                 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3513
3514                 pkt_id = (enum packet_id) (
3515                                 (le64_to_cpu(user_pkt->header) &
3516                                 PACKET_HEADER_PACKET_ID_MASK) >>
3517                                         PACKET_HEADER_PACKET_ID_SHIFT);
3518
3519                 if (!validate_packet_id(pkt_id)) {
3520                         dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3521                         rc = -EINVAL;
3522                         break;
3523                 }
3524
3525                 pkt_size = goya_packet_sizes[pkt_id];
3526                 cb_parsed_length += pkt_size;
3527                 if (cb_parsed_length > parser->user_cb_size) {
3528                         dev_err(hdev->dev,
3529                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3530                         rc = -EINVAL;
3531                         break;
3532                 }
3533
3534                 switch (pkt_id) {
3535                 case PACKET_WREG_32:
3536                         /*
3537                          * Although it is validated after copy in patch_cb(),
3538                          * need to validate here as well because patch_cb() is
3539                          * not called in MMU path while this function is called
3540                          */
3541                         rc = goya_validate_wreg32(hdev,
3542                                 parser, (struct packet_wreg32 *) user_pkt);
3543                         parser->patched_cb_size += pkt_size;
3544                         break;
3545
3546                 case PACKET_WREG_BULK:
3547                         dev_err(hdev->dev,
3548                                 "User not allowed to use WREG_BULK\n");
3549                         rc = -EPERM;
3550                         break;
3551
3552                 case PACKET_MSG_PROT:
3553                         dev_err(hdev->dev,
3554                                 "User not allowed to use MSG_PROT\n");
3555                         rc = -EPERM;
3556                         break;
3557
3558                 case PACKET_CP_DMA:
3559                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3560                         rc = -EPERM;
3561                         break;
3562
3563                 case PACKET_STOP:
3564                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3565                         rc = -EPERM;
3566                         break;
3567
3568                 case PACKET_LIN_DMA:
3569                         if (is_mmu)
3570                                 rc = goya_validate_dma_pkt_mmu(hdev, parser,
3571                                         (struct packet_lin_dma *) user_pkt);
3572                         else
3573                                 rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3574                                         (struct packet_lin_dma *) user_pkt);
3575                         break;
3576
3577                 case PACKET_MSG_LONG:
3578                 case PACKET_MSG_SHORT:
3579                 case PACKET_FENCE:
3580                 case PACKET_NOP:
3581                         parser->patched_cb_size += pkt_size;
3582                         break;
3583
3584                 default:
3585                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3586                                 pkt_id);
3587                         rc = -EINVAL;
3588                         break;
3589                 }
3590
3591                 if (rc)
3592                         break;
3593         }
3594
3595         /*
3596          * The new CB should have space at the end for two MSG_PROT packets:
3597          * 1. A packet that will act as a completion packet
3598          * 2. A packet that will generate MSI-X interrupt
3599          */
3600         parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
3601
3602         return rc;
3603 }
3604
3605 static int goya_patch_dma_packet(struct hl_device *hdev,
3606                                 struct hl_cs_parser *parser,
3607                                 struct packet_lin_dma *user_dma_pkt,
3608                                 struct packet_lin_dma *new_dma_pkt,
3609                                 u32 *new_dma_pkt_size)
3610 {
3611         struct hl_userptr *userptr;
3612         struct scatterlist *sg, *sg_next_iter;
3613         u32 count, dma_desc_cnt;
3614         u64 len, len_next;
3615         dma_addr_t dma_addr, dma_addr_next;
3616         enum goya_dma_direction user_dir;
3617         u64 device_memory_addr, addr;
3618         enum dma_data_direction dir;
3619         struct sg_table *sgt;
3620         bool skip_host_mem_pin = false;
3621         bool user_memset;
3622         u32 user_rdcomp_mask, user_wrcomp_mask, ctl;
3623
3624         ctl = le32_to_cpu(user_dma_pkt->ctl);
3625
3626         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3627                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3628
3629         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3630                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3631
3632         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) ||
3633                         (user_dma_pkt->tsize == 0)) {
3634                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
3635                 *new_dma_pkt_size = sizeof(*new_dma_pkt);
3636                 return 0;
3637         }
3638
3639         if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) {
3640                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3641                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3642                 dir = DMA_TO_DEVICE;
3643                 if (user_memset)
3644                         skip_host_mem_pin = true;
3645         } else {
3646                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3647                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3648                 dir = DMA_FROM_DEVICE;
3649         }
3650
3651         if ((!skip_host_mem_pin) &&
3652                 (hl_userptr_is_pinned(hdev, addr,
3653                         le32_to_cpu(user_dma_pkt->tsize),
3654                         parser->job_userptr_list, &userptr) == false)) {
3655                 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3656                                 addr, user_dma_pkt->tsize);
3657                 return -EFAULT;
3658         }
3659
3660         if ((user_memset) && (dir == DMA_TO_DEVICE)) {
3661                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
3662                 *new_dma_pkt_size = sizeof(*user_dma_pkt);
3663                 return 0;
3664         }
3665
3666         user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK;
3667
3668         user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK;
3669
3670         sgt = userptr->sgt;
3671         dma_desc_cnt = 0;
3672
3673         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3674                 len = sg_dma_len(sg);
3675                 dma_addr = sg_dma_address(sg);
3676
3677                 if (len == 0)
3678                         break;
3679
3680                 while ((count + 1) < sgt->nents) {
3681                         sg_next_iter = sg_next(sg);
3682                         len_next = sg_dma_len(sg_next_iter);
3683                         dma_addr_next = sg_dma_address(sg_next_iter);
3684
3685                         if (len_next == 0)
3686                                 break;
3687
3688                         if ((dma_addr + len == dma_addr_next) &&
3689                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3690                                 len += len_next;
3691                                 count++;
3692                                 sg = sg_next_iter;
3693                         } else {
3694                                 break;
3695                         }
3696                 }
3697
3698                 ctl = le32_to_cpu(user_dma_pkt->ctl);
3699                 if (likely(dma_desc_cnt))
3700                         ctl &= ~GOYA_PKT_CTL_EB_MASK;
3701                 ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK |
3702                                 GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK);
3703                 new_dma_pkt->ctl = cpu_to_le32(ctl);
3704                 new_dma_pkt->tsize = cpu_to_le32((u32) len);
3705
3706                 if (dir == DMA_TO_DEVICE) {
3707                         new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
3708                         new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
3709                 } else {
3710                         new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
3711                         new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
3712                 }
3713
3714                 if (!user_memset)
3715                         device_memory_addr += len;
3716                 dma_desc_cnt++;
3717                 new_dma_pkt++;
3718         }
3719
3720         if (!dma_desc_cnt) {
3721                 dev_err(hdev->dev,
3722                         "Error of 0 SG entries when patching DMA packet\n");
3723                 return -EFAULT;
3724         }
3725
3726         /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */
3727         new_dma_pkt--;
3728         new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask);
3729
3730         *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
3731
3732         return 0;
3733 }
3734
3735 static int goya_patch_cb(struct hl_device *hdev,
3736                                 struct hl_cs_parser *parser)
3737 {
3738         u32 cb_parsed_length = 0;
3739         u32 cb_patched_cur_length = 0;
3740         int rc = 0;
3741
3742         /* cb_user_size is more than 0 so loop will always be executed */
3743         while (cb_parsed_length < parser->user_cb_size) {
3744                 enum packet_id pkt_id;
3745                 u16 pkt_size;
3746                 u32 new_pkt_size = 0;
3747                 struct goya_packet *user_pkt, *kernel_pkt;
3748
3749                 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3750                 kernel_pkt = parser->patched_cb->kernel_address +
3751                                         cb_patched_cur_length;
3752
3753                 pkt_id = (enum packet_id) (
3754                                 (le64_to_cpu(user_pkt->header) &
3755                                 PACKET_HEADER_PACKET_ID_MASK) >>
3756                                         PACKET_HEADER_PACKET_ID_SHIFT);
3757
3758                 if (!validate_packet_id(pkt_id)) {
3759                         dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3760                         rc = -EINVAL;
3761                         break;
3762                 }
3763
3764                 pkt_size = goya_packet_sizes[pkt_id];
3765                 cb_parsed_length += pkt_size;
3766                 if (cb_parsed_length > parser->user_cb_size) {
3767                         dev_err(hdev->dev,
3768                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3769                         rc = -EINVAL;
3770                         break;
3771                 }
3772
3773                 switch (pkt_id) {
3774                 case PACKET_LIN_DMA:
3775                         rc = goya_patch_dma_packet(hdev, parser,
3776                                         (struct packet_lin_dma *) user_pkt,
3777                                         (struct packet_lin_dma *) kernel_pkt,
3778                                         &new_pkt_size);
3779                         cb_patched_cur_length += new_pkt_size;
3780                         break;
3781
3782                 case PACKET_WREG_32:
3783                         memcpy(kernel_pkt, user_pkt, pkt_size);
3784                         cb_patched_cur_length += pkt_size;
3785                         rc = goya_validate_wreg32(hdev, parser,
3786                                         (struct packet_wreg32 *) kernel_pkt);
3787                         break;
3788
3789                 case PACKET_WREG_BULK:
3790                         dev_err(hdev->dev,
3791                                 "User not allowed to use WREG_BULK\n");
3792                         rc = -EPERM;
3793                         break;
3794
3795                 case PACKET_MSG_PROT:
3796                         dev_err(hdev->dev,
3797                                 "User not allowed to use MSG_PROT\n");
3798                         rc = -EPERM;
3799                         break;
3800
3801                 case PACKET_CP_DMA:
3802                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3803                         rc = -EPERM;
3804                         break;
3805
3806                 case PACKET_STOP:
3807                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3808                         rc = -EPERM;
3809                         break;
3810
3811                 case PACKET_MSG_LONG:
3812                 case PACKET_MSG_SHORT:
3813                 case PACKET_FENCE:
3814                 case PACKET_NOP:
3815                         memcpy(kernel_pkt, user_pkt, pkt_size);
3816                         cb_patched_cur_length += pkt_size;
3817                         break;
3818
3819                 default:
3820                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3821                                 pkt_id);
3822                         rc = -EINVAL;
3823                         break;
3824                 }
3825
3826                 if (rc)
3827                         break;
3828         }
3829
3830         return rc;
3831 }
3832
3833 static int goya_parse_cb_mmu(struct hl_device *hdev,
3834                 struct hl_cs_parser *parser)
3835 {
3836         u64 patched_cb_handle;
3837         u32 patched_cb_size;
3838         struct hl_cb *user_cb;
3839         int rc;
3840
3841         /*
3842          * The new CB should have space at the end for two MSG_PROT pkt:
3843          * 1. A packet that will act as a completion packet
3844          * 2. A packet that will generate MSI-X interrupt
3845          */
3846         parser->patched_cb_size = parser->user_cb_size +
3847                         sizeof(struct packet_msg_prot) * 2;
3848
3849         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
3850                                 parser->patched_cb_size, false, false,
3851                                 &patched_cb_handle);
3852
3853         if (rc) {
3854                 dev_err(hdev->dev,
3855                         "Failed to allocate patched CB for DMA CS %d\n",
3856                         rc);
3857                 return rc;
3858         }
3859
3860         patched_cb_handle >>= PAGE_SHIFT;
3861         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
3862                                 (u32) patched_cb_handle);
3863         /* hl_cb_get should never fail here so use kernel WARN */
3864         WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
3865                         (u32) patched_cb_handle);
3866         if (!parser->patched_cb) {
3867                 rc = -EFAULT;
3868                 goto out;
3869         }
3870
3871         /*
3872          * The check that parser->user_cb_size <= parser->user_cb->size was done
3873          * in validate_queue_index().
3874          */
3875         memcpy(parser->patched_cb->kernel_address,
3876                 parser->user_cb->kernel_address,
3877                 parser->user_cb_size);
3878
3879         patched_cb_size = parser->patched_cb_size;
3880
3881         /* validate patched CB instead of user CB */
3882         user_cb = parser->user_cb;
3883         parser->user_cb = parser->patched_cb;
3884         rc = goya_validate_cb(hdev, parser, true);
3885         parser->user_cb = user_cb;
3886
3887         if (rc) {
3888                 hl_cb_put(parser->patched_cb);
3889                 goto out;
3890         }
3891
3892         if (patched_cb_size != parser->patched_cb_size) {
3893                 dev_err(hdev->dev, "user CB size mismatch\n");
3894                 hl_cb_put(parser->patched_cb);
3895                 rc = -EINVAL;
3896                 goto out;
3897         }
3898
3899 out:
3900         /*
3901          * Always call cb destroy here because we still have 1 reference
3902          * to it by calling cb_get earlier. After the job will be completed,
3903          * cb_put will release it, but here we want to remove it from the
3904          * idr
3905          */
3906         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
3907                                         patched_cb_handle << PAGE_SHIFT);
3908
3909         return rc;
3910 }
3911
3912 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
3913                                 struct hl_cs_parser *parser)
3914 {
3915         u64 patched_cb_handle;
3916         int rc;
3917
3918         rc = goya_validate_cb(hdev, parser, false);
3919
3920         if (rc)
3921                 goto free_userptr;
3922
3923         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
3924                                 parser->patched_cb_size, false, false,
3925                                 &patched_cb_handle);
3926         if (rc) {
3927                 dev_err(hdev->dev,
3928                         "Failed to allocate patched CB for DMA CS %d\n", rc);
3929                 goto free_userptr;
3930         }
3931
3932         patched_cb_handle >>= PAGE_SHIFT;
3933         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
3934                                 (u32) patched_cb_handle);
3935         /* hl_cb_get should never fail here so use kernel WARN */
3936         WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
3937                         (u32) patched_cb_handle);
3938         if (!parser->patched_cb) {
3939                 rc = -EFAULT;
3940                 goto out;
3941         }
3942
3943         rc = goya_patch_cb(hdev, parser);
3944
3945         if (rc)
3946                 hl_cb_put(parser->patched_cb);
3947
3948 out:
3949         /*
3950          * Always call cb destroy here because we still have 1 reference
3951          * to it by calling cb_get earlier. After the job will be completed,
3952          * cb_put will release it, but here we want to remove it from the
3953          * idr
3954          */
3955         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
3956                                 patched_cb_handle << PAGE_SHIFT);
3957
3958 free_userptr:
3959         if (rc)
3960                 hl_userptr_delete_list(hdev, parser->job_userptr_list);
3961         return rc;
3962 }
3963
3964 static int goya_parse_cb_no_ext_queue(struct hl_device *hdev,
3965                                         struct hl_cs_parser *parser)
3966 {
3967         struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
3968         struct goya_device *goya = hdev->asic_specific;
3969
3970         if (goya->hw_cap_initialized & HW_CAP_MMU)
3971                 return 0;
3972
3973         /* For internal queue jobs, just check if CB address is valid */
3974         if (hl_mem_area_inside_range(
3975                         (u64) (uintptr_t) parser->user_cb,
3976                         parser->user_cb_size,
3977                         asic_prop->sram_user_base_address,
3978                         asic_prop->sram_end_address))
3979                 return 0;
3980
3981         if (hl_mem_area_inside_range(
3982                         (u64) (uintptr_t) parser->user_cb,
3983                         parser->user_cb_size,
3984                         asic_prop->dram_user_base_address,
3985                         asic_prop->dram_end_address))
3986                 return 0;
3987
3988         dev_err(hdev->dev,
3989                 "Internal CB address 0x%px + 0x%x is not in SRAM nor in DRAM\n",
3990                 parser->user_cb, parser->user_cb_size);
3991
3992         return -EFAULT;
3993 }
3994
3995 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
3996 {
3997         struct goya_device *goya = hdev->asic_specific;
3998
3999         if (parser->queue_type == QUEUE_TYPE_INT)
4000                 return goya_parse_cb_no_ext_queue(hdev, parser);
4001
4002         if (goya->hw_cap_initialized & HW_CAP_MMU)
4003                 return goya_parse_cb_mmu(hdev, parser);
4004         else
4005                 return goya_parse_cb_no_mmu(hdev, parser);
4006 }
4007
4008 void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
4009                                 u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec,
4010                                 bool eb)
4011 {
4012         struct packet_msg_prot *cq_pkt;
4013         u32 tmp;
4014
4015         cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2);
4016
4017         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4018                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
4019                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4020         cq_pkt->ctl = cpu_to_le32(tmp);
4021         cq_pkt->value = cpu_to_le32(cq_val);
4022         cq_pkt->addr = cpu_to_le64(cq_addr);
4023
4024         cq_pkt++;
4025
4026         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4027                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4028         cq_pkt->ctl = cpu_to_le32(tmp);
4029         cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF);
4030         cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF);
4031 }
4032
4033 void goya_update_eq_ci(struct hl_device *hdev, u32 val)
4034 {
4035         WREG32(mmCPU_EQ_CI, val);
4036 }
4037
4038 void goya_restore_phase_topology(struct hl_device *hdev)
4039 {
4040
4041 }
4042
4043 static void goya_clear_sm_regs(struct hl_device *hdev)
4044 {
4045         int i, num_of_sob_in_longs, num_of_mon_in_longs;
4046
4047         num_of_sob_in_longs =
4048                 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4);
4049
4050         num_of_mon_in_longs =
4051                 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4);
4052
4053         for (i = 0 ; i < num_of_sob_in_longs ; i += 4)
4054                 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4055
4056         for (i = 0 ; i < num_of_mon_in_longs ; i += 4)
4057                 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4058
4059         /* Flush all WREG to prevent race */
4060         i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
4061 }
4062
4063 /*
4064  * goya_debugfs_read32 - read a 32bit value from a given device or a host mapped
4065  *                       address.
4066  *
4067  * @hdev:       pointer to hl_device structure
4068  * @addr:       device or host mapped address
4069  * @val:        returned value
4070  *
4071  * In case of DDR address that is not mapped into the default aperture that
4072  * the DDR bar exposes, the function will configure the iATU so that the DDR
4073  * bar will be positioned at a base address that allows reading from the
4074  * required address. Configuring the iATU during normal operation can
4075  * lead to undefined behavior and therefore, should be done with extreme care
4076  *
4077  */
4078 static int goya_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val)
4079 {
4080         struct asic_fixed_properties *prop = &hdev->asic_prop;
4081         u64 ddr_bar_addr;
4082         int rc = 0;
4083
4084         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4085                 *val = RREG32(addr - CFG_BASE);
4086
4087         } else if ((addr >= SRAM_BASE_ADDR) &&
4088                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4089
4090                 *val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4091                                 (addr - SRAM_BASE_ADDR));
4092
4093         } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
4094
4095                 u64 bar_base_addr = DRAM_PHYS_BASE +
4096                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4097
4098                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4099                 if (ddr_bar_addr != U64_MAX) {
4100                         *val = readl(hdev->pcie_bar[DDR_BAR_ID] +
4101                                                 (addr - bar_base_addr));
4102
4103                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4104                                                         ddr_bar_addr);
4105                 }
4106                 if (ddr_bar_addr == U64_MAX)
4107                         rc = -EIO;
4108
4109         } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
4110                 *val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);
4111
4112         } else {
4113                 rc = -EFAULT;
4114         }
4115
4116         return rc;
4117 }
4118
4119 /*
4120  * goya_debugfs_write32 - write a 32bit value to a given device or a host mapped
4121  *                        address.
4122  *
4123  * @hdev:       pointer to hl_device structure
4124  * @addr:       device or host mapped address
4125  * @val:        returned value
4126  *
4127  * In case of DDR address that is not mapped into the default aperture that
4128  * the DDR bar exposes, the function will configure the iATU so that the DDR
4129  * bar will be positioned at a base address that allows writing to the
4130  * required address. Configuring the iATU during normal operation can
4131  * lead to undefined behavior and therefore, should be done with extreme care
4132  *
4133  */
4134 static int goya_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val)
4135 {
4136         struct asic_fixed_properties *prop = &hdev->asic_prop;
4137         u64 ddr_bar_addr;
4138         int rc = 0;
4139
4140         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4141                 WREG32(addr - CFG_BASE, val);
4142
4143         } else if ((addr >= SRAM_BASE_ADDR) &&
4144                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4145
4146                 writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4147                                         (addr - SRAM_BASE_ADDR));
4148
4149         } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
4150
4151                 u64 bar_base_addr = DRAM_PHYS_BASE +
4152                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4153
4154                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4155                 if (ddr_bar_addr != U64_MAX) {
4156                         writel(val, hdev->pcie_bar[DDR_BAR_ID] +
4157                                                 (addr - bar_base_addr));
4158
4159                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4160                                                         ddr_bar_addr);
4161                 }
4162                 if (ddr_bar_addr == U64_MAX)
4163                         rc = -EIO;
4164
4165         } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
4166                 *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
4167
4168         } else {
4169                 rc = -EFAULT;
4170         }
4171
4172         return rc;
4173 }
4174
4175 static int goya_debugfs_read64(struct hl_device *hdev, u64 addr, u64 *val)
4176 {
4177         struct asic_fixed_properties *prop = &hdev->asic_prop;
4178         u64 ddr_bar_addr;
4179         int rc = 0;
4180
4181         if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
4182                 u32 val_l = RREG32(addr - CFG_BASE);
4183                 u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);
4184
4185                 *val = (((u64) val_h) << 32) | val_l;
4186
4187         } else if ((addr >= SRAM_BASE_ADDR) &&
4188                         (addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
4189
4190                 *val = readq(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4191                                 (addr - SRAM_BASE_ADDR));
4192
4193         } else if (addr <=
4194                    DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
4195
4196                 u64 bar_base_addr = DRAM_PHYS_BASE +
4197                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4198
4199                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4200                 if (ddr_bar_addr != U64_MAX) {
4201                         *val = readq(hdev->pcie_bar[DDR_BAR_ID] +
4202                                                 (addr - bar_base_addr));
4203
4204                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4205                                                         ddr_bar_addr);
4206                 }
4207                 if (ddr_bar_addr == U64_MAX)
4208                         rc = -EIO;
4209
4210         } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
4211                 *val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);
4212
4213         } else {
4214                 rc = -EFAULT;
4215         }
4216
4217         return rc;
4218 }
4219
4220 static int goya_debugfs_write64(struct hl_device *hdev, u64 addr, u64 val)
4221 {
4222         struct asic_fixed_properties *prop = &hdev->asic_prop;
4223         u64 ddr_bar_addr;
4224         int rc = 0;
4225
4226         if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
4227                 WREG32(addr - CFG_BASE, lower_32_bits(val));
4228                 WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));
4229
4230         } else if ((addr >= SRAM_BASE_ADDR) &&
4231                         (addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
4232
4233                 writeq(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4234                                         (addr - SRAM_BASE_ADDR));
4235
4236         } else if (addr <=
4237                    DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
4238
4239                 u64 bar_base_addr = DRAM_PHYS_BASE +
4240                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4241
4242                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4243                 if (ddr_bar_addr != U64_MAX) {
4244                         writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4245                                                 (addr - bar_base_addr));
4246
4247                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4248                                                         ddr_bar_addr);
4249                 }
4250                 if (ddr_bar_addr == U64_MAX)
4251                         rc = -EIO;
4252
4253         } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
4254                 *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
4255
4256         } else {
4257                 rc = -EFAULT;
4258         }
4259
4260         return rc;
4261 }
4262
4263 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4264 {
4265         struct goya_device *goya = hdev->asic_specific;
4266
4267         if (hdev->hard_reset_pending)
4268                 return U64_MAX;
4269
4270         return readq(hdev->pcie_bar[DDR_BAR_ID] +
4271                         (addr - goya->ddr_bar_cur_addr));
4272 }
4273
4274 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4275 {
4276         struct goya_device *goya = hdev->asic_specific;
4277
4278         if (hdev->hard_reset_pending)
4279                 return;
4280
4281         writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4282                         (addr - goya->ddr_bar_cur_addr));
4283 }
4284
4285 static const char *_goya_get_event_desc(u16 event_type)
4286 {
4287         switch (event_type) {
4288         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4289                 return "PCIe_if";
4290         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4291         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4292         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4293         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4294         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4295         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4296         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4297         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4298                 return "TPC%d_ecc";
4299         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4300                 return "MME_ecc";
4301         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4302                 return "MME_ecc_ext";
4303         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4304                 return "MMU_ecc";
4305         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4306                 return "DMA_macro";
4307         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4308                 return "DMA_ecc";
4309         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4310                 return "CPU_if_ecc";
4311         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4312                 return "PSOC_mem";
4313         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4314                 return "PSOC_coresight";
4315         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4316                 return "SRAM%d";
4317         case GOYA_ASYNC_EVENT_ID_GIC500:
4318                 return "GIC500";
4319         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4320                 return "PLL%d";
4321         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4322                 return "AXI_ecc";
4323         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4324                 return "L2_ram_ecc";
4325         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4326                 return "PSOC_gpio_05_sw_reset";
4327         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4328                 return "PSOC_gpio_10_vrhot_icrit";
4329         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4330                 return "PCIe_dec";
4331         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4332         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4333         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4334         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4335         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4336         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4337         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4338         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4339                 return "TPC%d_dec";
4340         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4341                 return "MME_wacs";
4342         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4343                 return "MME_wacsd";
4344         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4345                 return "CPU_axi_splitter";
4346         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4347                 return "PSOC_axi_dec";
4348         case GOYA_ASYNC_EVENT_ID_PSOC:
4349                 return "PSOC";
4350         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4351         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4352         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4353         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4354         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4355         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4356         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4357         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4358                 return "TPC%d_krn_err";
4359         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4360                 return "TPC%d_cq";
4361         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4362                 return "TPC%d_qm";
4363         case GOYA_ASYNC_EVENT_ID_MME_QM:
4364                 return "MME_qm";
4365         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4366                 return "MME_cq";
4367         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4368                 return "DMA%d_qm";
4369         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4370                 return "DMA%d_ch";
4371         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4372         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4373         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4374         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4375         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4376         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4377         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4378         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4379                 return "TPC%d_bmon_spmu";
4380         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4381                 return "DMA_bm_ch%d";
4382         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4383                 return "POWER_ENV_S";
4384         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4385                 return "POWER_ENV_E";
4386         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4387                 return "THERMAL_ENV_S";
4388         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4389                 return "THERMAL_ENV_E";
4390         default:
4391                 return "N/A";
4392         }
4393 }
4394
4395 static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
4396 {
4397         u8 index;
4398
4399         switch (event_type) {
4400         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4401         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4402         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4403         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4404         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4405         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4406         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4407         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4408                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_ECC) / 3;
4409                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4410                 break;
4411         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4412                 index = event_type - GOYA_ASYNC_EVENT_ID_SRAM0;
4413                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4414                 break;
4415         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4416                 index = event_type - GOYA_ASYNC_EVENT_ID_PLL0;
4417                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4418                 break;
4419         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4420         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4421         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4422         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4423         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4424         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4425         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4426         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4427                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3;
4428                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4429                 break;
4430         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4431         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4432         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4433         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4434         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4435         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4436         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4437         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4438                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10;
4439                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4440                 break;
4441         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4442                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ;
4443                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4444                 break;
4445         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4446                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM;
4447                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4448                 break;
4449         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4450                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM;
4451                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4452                 break;
4453         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4454                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH;
4455                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4456                 break;
4457         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4458         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4459         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4460         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4461         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4462         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4463         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4464         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4465                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU) / 10;
4466                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4467                 break;
4468         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4469                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0;
4470                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4471                 break;
4472         default:
4473                 snprintf(desc, size, _goya_get_event_desc(event_type));
4474                 break;
4475         }
4476 }
4477
4478 static void goya_print_razwi_info(struct hl_device *hdev)
4479 {
4480         if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {
4481                 dev_err_ratelimited(hdev->dev, "Illegal write to LBW\n");
4482                 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4483         }
4484
4485         if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {
4486                 dev_err_ratelimited(hdev->dev, "Illegal read from LBW\n");
4487                 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4488         }
4489
4490         if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {
4491                 dev_err_ratelimited(hdev->dev, "Illegal write to HBW\n");
4492                 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4493         }
4494
4495         if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {
4496                 dev_err_ratelimited(hdev->dev, "Illegal read from HBW\n");
4497                 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4498         }
4499 }
4500
4501 static void goya_print_mmu_error_info(struct hl_device *hdev)
4502 {
4503         struct goya_device *goya = hdev->asic_specific;
4504         u64 addr;
4505         u32 val;
4506
4507         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4508                 return;
4509
4510         val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4511         if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4512                 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4513                 addr <<= 32;
4514                 addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);
4515
4516                 dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n",
4517                                         addr);
4518
4519                 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4520         }
4521 }
4522
4523 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type,
4524                                 bool razwi)
4525 {
4526         char desc[20] = "";
4527
4528         goya_get_event_desc(event_type, desc, sizeof(desc));
4529         dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4530                 event_type, desc);
4531
4532         if (razwi) {
4533                 goya_print_razwi_info(hdev);
4534                 goya_print_mmu_error_info(hdev);
4535         }
4536 }
4537
4538 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4539                 size_t irq_arr_size)
4540 {
4541         struct cpucp_unmask_irq_arr_packet *pkt;
4542         size_t total_pkt_size;
4543         u64 result;
4544         int rc;
4545         int irq_num_entries, irq_arr_index;
4546         __le32 *goya_irq_arr;
4547
4548         total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) +
4549                         irq_arr_size;
4550
4551         /* data should be aligned to 8 bytes in order to CPU-CP to copy it */
4552         total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
4553
4554         /* total_pkt_size is casted to u16 later on */
4555         if (total_pkt_size > USHRT_MAX) {
4556                 dev_err(hdev->dev, "too many elements in IRQ array\n");
4557                 return -EINVAL;
4558         }
4559
4560         pkt = kzalloc(total_pkt_size, GFP_KERNEL);
4561         if (!pkt)
4562                 return -ENOMEM;
4563
4564         irq_num_entries = irq_arr_size / sizeof(irq_arr[0]);
4565         pkt->length = cpu_to_le32(irq_num_entries);
4566
4567         /* We must perform any necessary endianness conversation on the irq
4568          * array being passed to the goya hardware
4569          */
4570         for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs;
4571                         irq_arr_index < irq_num_entries ; irq_arr_index++)
4572                 goya_irq_arr[irq_arr_index] =
4573                                 cpu_to_le32(irq_arr[irq_arr_index]);
4574
4575         pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4576                                                 CPUCP_PKT_CTL_OPCODE_SHIFT);
4577
4578         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
4579                                                 total_pkt_size, 0, &result);
4580
4581         if (rc)
4582                 dev_err(hdev->dev, "failed to unmask IRQ array\n");
4583
4584         kfree(pkt);
4585
4586         return rc;
4587 }
4588
4589 static int goya_soft_reset_late_init(struct hl_device *hdev)
4590 {
4591         /*
4592          * Unmask all IRQs since some could have been received
4593          * during the soft reset
4594          */
4595         return goya_unmask_irq_arr(hdev, goya_all_events,
4596                                         sizeof(goya_all_events));
4597 }
4598
4599 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4600 {
4601         struct cpucp_packet pkt;
4602         u64 result;
4603         int rc;
4604
4605         memset(&pkt, 0, sizeof(pkt));
4606
4607         pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ <<
4608                                 CPUCP_PKT_CTL_OPCODE_SHIFT);
4609         pkt.value = cpu_to_le64(event_type);
4610
4611         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4612                                                 0, &result);
4613
4614         if (rc)
4615                 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4616
4617         return rc;
4618 }
4619
4620 static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type)
4621 {
4622         switch (event_type) {
4623         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4624                 hdev->clk_throttling_reason |= HL_CLK_THROTTLE_POWER;
4625                 dev_info_ratelimited(hdev->dev,
4626                         "Clock throttling due to power consumption\n");
4627                 break;
4628         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4629                 hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_POWER;
4630                 dev_info_ratelimited(hdev->dev,
4631                         "Power envelop is safe, back to optimal clock\n");
4632                 break;
4633         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4634                 hdev->clk_throttling_reason |= HL_CLK_THROTTLE_THERMAL;
4635                 dev_info_ratelimited(hdev->dev,
4636                         "Clock throttling due to overheating\n");
4637                 break;
4638         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4639                 hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_THERMAL;
4640                 dev_info_ratelimited(hdev->dev,
4641                         "Thermal envelop is safe, back to optimal clock\n");
4642                 break;
4643
4644         default:
4645                 dev_err(hdev->dev, "Received invalid clock change event %d\n",
4646                         event_type);
4647                 break;
4648         }
4649 }
4650
4651 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4652 {
4653         u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
4654         u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
4655                                 >> EQ_CTL_EVENT_TYPE_SHIFT);
4656         struct goya_device *goya = hdev->asic_specific;
4657
4658         goya->events_stat[event_type]++;
4659         goya->events_stat_aggregate[event_type]++;
4660
4661         switch (event_type) {
4662         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4663         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4664         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4665         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4666         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4667         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4668         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4669         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4670         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4671         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4672         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4673         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4674         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4675         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4676         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4677         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4678         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4679         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4680         case GOYA_ASYNC_EVENT_ID_GIC500:
4681         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4682         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4683         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4684         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4685                 goya_print_irq_info(hdev, event_type, false);
4686                 if (hdev->hard_reset_on_fw_events)
4687                         hl_device_reset(hdev, true, false);
4688                 break;
4689
4690         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4691         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4692         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4693         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4694         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4695         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4696         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4697         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4698         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4699         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4700         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4701         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4702         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4703         case GOYA_ASYNC_EVENT_ID_PSOC:
4704         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4705         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4706         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4707         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4708         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4709         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4710         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4711         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4712         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4713         case GOYA_ASYNC_EVENT_ID_MME_QM:
4714         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4715         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4716         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4717                 goya_print_irq_info(hdev, event_type, true);
4718                 goya_unmask_irq(hdev, event_type);
4719                 break;
4720
4721         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4722         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4723         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4724         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4725         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4726         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4727         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4728         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4729         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4730         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4731                 goya_print_irq_info(hdev, event_type, false);
4732                 goya_unmask_irq(hdev, event_type);
4733                 break;
4734
4735         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4736         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4737         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4738         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4739                 goya_print_clk_change_info(hdev, event_type);
4740                 goya_unmask_irq(hdev, event_type);
4741                 break;
4742
4743         default:
4744                 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
4745                                 event_type);
4746                 break;
4747         }
4748 }
4749
4750 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size)
4751 {
4752         struct goya_device *goya = hdev->asic_specific;
4753
4754         if (aggregate) {
4755                 *size = (u32) sizeof(goya->events_stat_aggregate);
4756                 return goya->events_stat_aggregate;
4757         }
4758
4759         *size = (u32) sizeof(goya->events_stat);
4760         return goya->events_stat;
4761 }
4762
4763 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
4764                                 u64 val, bool is_dram)
4765 {
4766         struct packet_lin_dma *lin_dma_pkt;
4767         struct hl_cs_job *job;
4768         u32 cb_size, ctl;
4769         struct hl_cb *cb;
4770         int rc, lin_dma_pkts_cnt;
4771
4772         lin_dma_pkts_cnt = DIV_ROUND_UP_ULL(size, SZ_2G);
4773         cb_size = lin_dma_pkts_cnt * sizeof(struct packet_lin_dma) +
4774                                                 sizeof(struct packet_msg_prot);
4775         cb = hl_cb_kernel_create(hdev, cb_size, false);
4776         if (!cb)
4777                 return -ENOMEM;
4778
4779         lin_dma_pkt = cb->kernel_address;
4780
4781         do {
4782                 memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
4783
4784                 ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) |
4785                                 (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |
4786                                 (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
4787                                 (1 << GOYA_PKT_CTL_RB_SHIFT) |
4788                                 (1 << GOYA_PKT_CTL_MB_SHIFT));
4789                 ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) <<
4790                                 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
4791                 lin_dma_pkt->ctl = cpu_to_le32(ctl);
4792
4793                 lin_dma_pkt->src_addr = cpu_to_le64(val);
4794                 lin_dma_pkt->dst_addr = cpu_to_le64(addr);
4795                 if (lin_dma_pkts_cnt > 1)
4796                         lin_dma_pkt->tsize = cpu_to_le32(SZ_2G);
4797                 else
4798                         lin_dma_pkt->tsize = cpu_to_le32(size);
4799
4800                 size -= SZ_2G;
4801                 addr += SZ_2G;
4802                 lin_dma_pkt++;
4803         } while (--lin_dma_pkts_cnt);
4804
4805         job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
4806         if (!job) {
4807                 dev_err(hdev->dev, "Failed to allocate a new job\n");
4808                 rc = -ENOMEM;
4809                 goto release_cb;
4810         }
4811
4812         job->id = 0;
4813         job->user_cb = cb;
4814         atomic_inc(&job->user_cb->cs_cnt);
4815         job->user_cb_size = cb_size;
4816         job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
4817         job->patched_cb = job->user_cb;
4818         job->job_cb_size = job->user_cb_size;
4819
4820         hl_debugfs_add_job(hdev, job);
4821
4822         rc = goya_send_job_on_qman0(hdev, job);
4823
4824         hl_debugfs_remove_job(hdev, job);
4825         kfree(job);
4826         atomic_dec(&cb->cs_cnt);
4827
4828 release_cb:
4829         hl_cb_put(cb);
4830         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
4831
4832         return rc;
4833 }
4834
4835 int goya_context_switch(struct hl_device *hdev, u32 asid)
4836 {
4837         struct asic_fixed_properties *prop = &hdev->asic_prop;
4838         u64 addr = prop->sram_base_address, sob_addr;
4839         u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
4840         u64 val = 0x7777777777777777ull;
4841         int rc, dma_id;
4842         u32 channel_off = mmDMA_CH_1_WR_COMP_ADDR_LO -
4843                                         mmDMA_CH_0_WR_COMP_ADDR_LO;
4844
4845         rc = goya_memset_device_memory(hdev, addr, size, val, false);
4846         if (rc) {
4847                 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
4848                 return rc;
4849         }
4850
4851         /* we need to reset registers that the user is allowed to change */
4852         sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
4853         WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr));
4854
4855         for (dma_id = 1 ; dma_id < NUMBER_OF_EXT_HW_QUEUES ; dma_id++) {
4856                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
4857                                                         (dma_id - 1) * 4;
4858                 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id,
4859                                                 lower_32_bits(sob_addr));
4860         }
4861
4862         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
4863
4864         goya_mmu_prepare(hdev, asid);
4865
4866         goya_clear_sm_regs(hdev);
4867
4868         return 0;
4869 }
4870
4871 static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
4872 {
4873         struct asic_fixed_properties *prop = &hdev->asic_prop;
4874         struct goya_device *goya = hdev->asic_specific;
4875         u64 addr = prop->mmu_pgt_addr;
4876         u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE +
4877                         MMU_CACHE_MNG_SIZE;
4878
4879         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4880                 return 0;
4881
4882         return goya_memset_device_memory(hdev, addr, size, 0, true);
4883 }
4884
4885 static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
4886 {
4887         struct goya_device *goya = hdev->asic_specific;
4888         u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
4889         u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE;
4890         u64 val = 0x9999999999999999ull;
4891
4892         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4893                 return 0;
4894
4895         return goya_memset_device_memory(hdev, addr, size, val, true);
4896 }
4897
4898 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
4899 {
4900         struct asic_fixed_properties *prop = &hdev->asic_prop;
4901         struct goya_device *goya = hdev->asic_specific;
4902         s64 off, cpu_off;
4903         int rc;
4904
4905         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4906                 return 0;
4907
4908         for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB) {
4909                 rc = hl_mmu_map_page(hdev->kernel_ctx,
4910                         prop->dram_base_address + off,
4911                         prop->dram_base_address + off, PAGE_SIZE_2MB,
4912                         (off + PAGE_SIZE_2MB) == CPU_FW_IMAGE_SIZE);
4913                 if (rc) {
4914                         dev_err(hdev->dev, "Map failed for address 0x%llx\n",
4915                                 prop->dram_base_address + off);
4916                         goto unmap;
4917                 }
4918         }
4919
4920         if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
4921                 rc = hl_mmu_map_page(hdev->kernel_ctx,
4922                         VA_CPU_ACCESSIBLE_MEM_ADDR,
4923                         hdev->cpu_accessible_dma_address,
4924                         PAGE_SIZE_2MB, true);
4925
4926                 if (rc) {
4927                         dev_err(hdev->dev,
4928                                 "Map failed for CPU accessible memory\n");
4929                         off -= PAGE_SIZE_2MB;
4930                         goto unmap;
4931                 }
4932         } else {
4933                 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB) {
4934                         rc = hl_mmu_map_page(hdev->kernel_ctx,
4935                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
4936                                 hdev->cpu_accessible_dma_address + cpu_off,
4937                                 PAGE_SIZE_4KB, true);
4938                         if (rc) {
4939                                 dev_err(hdev->dev,
4940                                         "Map failed for CPU accessible memory\n");
4941                                 cpu_off -= PAGE_SIZE_4KB;
4942                                 goto unmap_cpu;
4943                         }
4944                 }
4945         }
4946
4947         goya_mmu_prepare_reg(hdev, mmCPU_IF_ARUSER_OVR, HL_KERNEL_ASID_ID);
4948         goya_mmu_prepare_reg(hdev, mmCPU_IF_AWUSER_OVR, HL_KERNEL_ASID_ID);
4949         WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF);
4950         WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF);
4951
4952         /* Make sure configuration is flushed to device */
4953         RREG32(mmCPU_IF_AWUSER_OVR_EN);
4954
4955         goya->device_cpu_mmu_mappings_done = true;
4956
4957         return 0;
4958
4959 unmap_cpu:
4960         for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB)
4961                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
4962                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
4963                                 PAGE_SIZE_4KB, true))
4964                         dev_warn_ratelimited(hdev->dev,
4965                                 "failed to unmap address 0x%llx\n",
4966                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
4967 unmap:
4968         for (; off >= 0 ; off -= PAGE_SIZE_2MB)
4969                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
4970                                 prop->dram_base_address + off, PAGE_SIZE_2MB,
4971                                 true))
4972                         dev_warn_ratelimited(hdev->dev,
4973                                 "failed to unmap address 0x%llx\n",
4974                                 prop->dram_base_address + off);
4975
4976         return rc;
4977 }
4978
4979 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev)
4980 {
4981         struct asic_fixed_properties *prop = &hdev->asic_prop;
4982         struct goya_device *goya = hdev->asic_specific;
4983         u32 off, cpu_off;
4984
4985         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4986                 return;
4987
4988         if (!goya->device_cpu_mmu_mappings_done)
4989                 return;
4990
4991         WREG32(mmCPU_IF_ARUSER_OVR_EN, 0);
4992         WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
4993
4994         if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
4995                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
4996                                 VA_CPU_ACCESSIBLE_MEM_ADDR,
4997                                 PAGE_SIZE_2MB, true))
4998                         dev_warn(hdev->dev,
4999                                 "Failed to unmap CPU accessible memory\n");
5000         } else {
5001                 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB)
5002                         if (hl_mmu_unmap_page(hdev->kernel_ctx,
5003                                         VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5004                                         PAGE_SIZE_4KB,
5005                                         (cpu_off + PAGE_SIZE_4KB) >= SZ_2M))
5006                                 dev_warn_ratelimited(hdev->dev,
5007                                         "failed to unmap address 0x%llx\n",
5008                                         VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
5009         }
5010
5011         for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB)
5012                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5013                                 prop->dram_base_address + off, PAGE_SIZE_2MB,
5014                                 (off + PAGE_SIZE_2MB) >= CPU_FW_IMAGE_SIZE))
5015                         dev_warn_ratelimited(hdev->dev,
5016                                         "Failed to unmap address 0x%llx\n",
5017                                         prop->dram_base_address + off);
5018
5019         goya->device_cpu_mmu_mappings_done = false;
5020 }
5021
5022 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
5023 {
5024         struct goya_device *goya = hdev->asic_specific;
5025         int i;
5026
5027         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5028                 return;
5029
5030         if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
5031                 WARN(1, "asid %u is too big\n", asid);
5032                 return;
5033         }
5034
5035         /* zero the MMBP and ASID bits and then set the ASID */
5036         for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++)
5037                 goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
5038 }
5039
5040 static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
5041                                         u32 flags)
5042 {
5043         struct goya_device *goya = hdev->asic_specific;
5044         u32 status, timeout_usec;
5045         int rc;
5046
5047         if (!(goya->hw_cap_initialized & HW_CAP_MMU) ||
5048                 hdev->hard_reset_pending)
5049                 return 0;
5050
5051         /* no need in L1 only invalidation in Goya */
5052         if (!is_hard)
5053                 return 0;
5054
5055         if (hdev->pldm)
5056                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
5057         else
5058                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
5059
5060         mutex_lock(&hdev->mmu_cache_lock);
5061
5062         /* L0 & L1 invalidation */
5063         WREG32(mmSTLB_INV_ALL_START, 1);
5064
5065         rc = hl_poll_timeout(
5066                 hdev,
5067                 mmSTLB_INV_ALL_START,
5068                 status,
5069                 !status,
5070                 1000,
5071                 timeout_usec);
5072
5073         mutex_unlock(&hdev->mmu_cache_lock);
5074
5075         if (rc) {
5076                 dev_err_ratelimited(hdev->dev,
5077                                         "MMU cache invalidation timeout\n");
5078                 hl_device_reset(hdev, true, false);
5079         }
5080
5081         return rc;
5082 }
5083
5084 static int goya_mmu_invalidate_cache_range(struct hl_device *hdev,
5085                                 bool is_hard, u32 asid, u64 va, u64 size)
5086 {
5087         struct goya_device *goya = hdev->asic_specific;
5088         u32 status, timeout_usec, inv_data, pi;
5089         int rc;
5090
5091         if (!(goya->hw_cap_initialized & HW_CAP_MMU) ||
5092                 hdev->hard_reset_pending)
5093                 return 0;
5094
5095         /* no need in L1 only invalidation in Goya */
5096         if (!is_hard)
5097                 return 0;
5098
5099         if (hdev->pldm)
5100                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
5101         else
5102                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
5103
5104         mutex_lock(&hdev->mmu_cache_lock);
5105
5106         /*
5107          * TODO: currently invalidate entire L0 & L1 as in regular hard
5108          * invalidation. Need to apply invalidation of specific cache lines with
5109          * mask of ASID & VA & size.
5110          * Note that L1 with be flushed entirely in any case.
5111          */
5112
5113         /* L0 & L1 invalidation */
5114         inv_data = RREG32(mmSTLB_CACHE_INV);
5115         /* PI is 8 bit */
5116         pi = ((inv_data & STLB_CACHE_INV_PRODUCER_INDEX_MASK) + 1) & 0xFF;
5117         WREG32(mmSTLB_CACHE_INV,
5118                         (inv_data & STLB_CACHE_INV_INDEX_MASK_MASK) | pi);
5119
5120         rc = hl_poll_timeout(
5121                 hdev,
5122                 mmSTLB_INV_CONSUMER_INDEX,
5123                 status,
5124                 status == pi,
5125                 1000,
5126                 timeout_usec);
5127
5128         mutex_unlock(&hdev->mmu_cache_lock);
5129
5130         if (rc) {
5131                 dev_err_ratelimited(hdev->dev,
5132                                         "MMU cache invalidation timeout\n");
5133                 hl_device_reset(hdev, true, false);
5134         }
5135
5136         return rc;
5137 }
5138
5139 int goya_send_heartbeat(struct hl_device *hdev)
5140 {
5141         struct goya_device *goya = hdev->asic_specific;
5142
5143         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5144                 return 0;
5145
5146         return hl_fw_send_heartbeat(hdev);
5147 }
5148
5149 int goya_cpucp_info_get(struct hl_device *hdev)
5150 {
5151         struct goya_device *goya = hdev->asic_specific;
5152         struct asic_fixed_properties *prop = &hdev->asic_prop;
5153         u64 dram_size;
5154         int rc;
5155
5156         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5157                 return 0;
5158
5159         rc = hl_fw_cpucp_info_get(hdev, mmCPU_BOOT_DEV_STS0);
5160         if (rc)
5161                 return rc;
5162
5163         dram_size = le64_to_cpu(prop->cpucp_info.dram_size);
5164         if (dram_size) {
5165                 if ((!is_power_of_2(dram_size)) ||
5166                                 (dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
5167                         dev_err(hdev->dev,
5168                                 "F/W reported invalid DRAM size %llu. Trying to use default size\n",
5169                                 dram_size);
5170                         dram_size = DRAM_PHYS_DEFAULT_SIZE;
5171                 }
5172
5173                 prop->dram_size = dram_size;
5174                 prop->dram_end_address = prop->dram_base_address + dram_size;
5175         }
5176
5177         if (!strlen(prop->cpucp_info.card_name))
5178                 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
5179                                 CARD_NAME_MAX_LEN);
5180
5181         return 0;
5182 }
5183
5184 static void goya_set_clock_gating(struct hl_device *hdev)
5185 {
5186         /* clock gating not supported in Goya */
5187 }
5188
5189 static void goya_disable_clock_gating(struct hl_device *hdev)
5190 {
5191         /* clock gating not supported in Goya */
5192 }
5193
5194 static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask,
5195                                 struct seq_file *s)
5196 {
5197         const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n";
5198         const char *dma_fmt = "%-5d%-9s%#-14x%#x\n";
5199         u32 qm_glbl_sts0, cmdq_glbl_sts0, dma_core_sts0, tpc_cfg_sts,
5200                 mme_arch_sts;
5201         bool is_idle = true, is_eng_idle;
5202         u64 offset;
5203         int i;
5204
5205         if (s)
5206                 seq_puts(s, "\nDMA  is_idle  QM_GLBL_STS0  DMA_CORE_STS0\n"
5207                                 "---  -------  ------------  -------------\n");
5208
5209         offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
5210
5211         for (i = 0 ; i < DMA_MAX_NUM ; i++) {
5212                 qm_glbl_sts0 = RREG32(mmDMA_QM_0_GLBL_STS0 + i * offset);
5213                 dma_core_sts0 = RREG32(mmDMA_CH_0_STS0 + i * offset);
5214                 is_eng_idle = IS_DMA_QM_IDLE(qm_glbl_sts0) &&
5215                                 IS_DMA_IDLE(dma_core_sts0);
5216                 is_idle &= is_eng_idle;
5217
5218                 if (mask)
5219                         *mask |= ((u64) !is_eng_idle) <<
5220                                                 (GOYA_ENGINE_ID_DMA_0 + i);
5221                 if (s)
5222                         seq_printf(s, dma_fmt, i, is_eng_idle ? "Y" : "N",
5223                                         qm_glbl_sts0, dma_core_sts0);
5224         }
5225
5226         if (s)
5227                 seq_puts(s,
5228                         "\nTPC  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  CFG_STATUS\n"
5229                         "---  -------  ------------  --------------  ----------\n");
5230
5231         offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
5232
5233         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
5234                 qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + i * offset);
5235                 cmdq_glbl_sts0 = RREG32(mmTPC0_CMDQ_GLBL_STS0 + i * offset);
5236                 tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + i * offset);
5237                 is_eng_idle = IS_TPC_QM_IDLE(qm_glbl_sts0) &&
5238                                 IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) &&
5239                                 IS_TPC_IDLE(tpc_cfg_sts);
5240                 is_idle &= is_eng_idle;
5241
5242                 if (mask)
5243                         *mask |= ((u64) !is_eng_idle) <<
5244                                                 (GOYA_ENGINE_ID_TPC_0 + i);
5245                 if (s)
5246                         seq_printf(s, fmt, i, is_eng_idle ? "Y" : "N",
5247                                 qm_glbl_sts0, cmdq_glbl_sts0, tpc_cfg_sts);
5248         }
5249
5250         if (s)
5251                 seq_puts(s,
5252                         "\nMME  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  ARCH_STATUS\n"
5253                         "---  -------  ------------  --------------  -----------\n");
5254
5255         qm_glbl_sts0 = RREG32(mmMME_QM_GLBL_STS0);
5256         cmdq_glbl_sts0 = RREG32(mmMME_CMDQ_GLBL_STS0);
5257         mme_arch_sts = RREG32(mmMME_ARCH_STATUS);
5258         is_eng_idle = IS_MME_QM_IDLE(qm_glbl_sts0) &&
5259                         IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) &&
5260                         IS_MME_IDLE(mme_arch_sts);
5261         is_idle &= is_eng_idle;
5262
5263         if (mask)
5264                 *mask |= ((u64) !is_eng_idle) << GOYA_ENGINE_ID_MME_0;
5265         if (s) {
5266                 seq_printf(s, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0,
5267                                 cmdq_glbl_sts0, mme_arch_sts);
5268                 seq_puts(s, "\n");
5269         }
5270
5271         return is_idle;
5272 }
5273
5274 static void goya_hw_queues_lock(struct hl_device *hdev)
5275         __acquires(&goya->hw_queues_lock)
5276 {
5277         struct goya_device *goya = hdev->asic_specific;
5278
5279         spin_lock(&goya->hw_queues_lock);
5280 }
5281
5282 static void goya_hw_queues_unlock(struct hl_device *hdev)
5283         __releases(&goya->hw_queues_lock)
5284 {
5285         struct goya_device *goya = hdev->asic_specific;
5286
5287         spin_unlock(&goya->hw_queues_lock);
5288 }
5289
5290 static u32 goya_get_pci_id(struct hl_device *hdev)
5291 {
5292         return hdev->pdev->device;
5293 }
5294
5295 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
5296                                 size_t max_size)
5297 {
5298         struct goya_device *goya = hdev->asic_specific;
5299
5300         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5301                 return 0;
5302
5303         return hl_fw_get_eeprom_data(hdev, data, max_size);
5304 }
5305
5306 static int goya_ctx_init(struct hl_ctx *ctx)
5307 {
5308         return 0;
5309 }
5310
5311 u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
5312 {
5313         return cq_idx;
5314 }
5315
5316 static u32 goya_get_signal_cb_size(struct hl_device *hdev)
5317 {
5318         return 0;
5319 }
5320
5321 static u32 goya_get_wait_cb_size(struct hl_device *hdev)
5322 {
5323         return 0;
5324 }
5325
5326 static u32 goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
5327                 u32 size)
5328 {
5329         return 0;
5330 }
5331
5332 static u32 goya_gen_wait_cb(struct hl_device *hdev,
5333                 struct hl_gen_wait_properties *prop)
5334 {
5335         return 0;
5336 }
5337
5338 static void goya_reset_sob(struct hl_device *hdev, void *data)
5339 {
5340
5341 }
5342
5343 static void goya_reset_sob_group(struct hl_device *hdev, u16 sob_group)
5344 {
5345
5346 }
5347
5348 static void goya_set_dma_mask_from_fw(struct hl_device *hdev)
5349 {
5350         if (RREG32(mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0) ==
5351                                                         HL_POWER9_HOST_MAGIC) {
5352                 dev_dbg(hdev->dev, "Working in 64-bit DMA mode\n");
5353                 hdev->power9_64bit_dma_enable = 1;
5354                 hdev->dma_mask = 64;
5355         } else {
5356                 dev_dbg(hdev->dev, "Working in 48-bit DMA mode\n");
5357                 hdev->power9_64bit_dma_enable = 0;
5358                 hdev->dma_mask = 48;
5359         }
5360 }
5361
5362 u64 goya_get_device_time(struct hl_device *hdev)
5363 {
5364         u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;
5365
5366         return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);
5367 }
5368
5369 static void goya_collective_wait_init_cs(struct hl_cs *cs)
5370 {
5371
5372 }
5373
5374 static int goya_collective_wait_create_jobs(struct hl_device *hdev,
5375                 struct hl_ctx *ctx, struct hl_cs *cs, u32 wait_queue_id,
5376                 u32 collective_engine_id)
5377 {
5378         return -EINVAL;
5379 }
5380
5381 static void goya_ctx_fini(struct hl_ctx *ctx)
5382 {
5383
5384 }
5385
5386 static const struct hl_asic_funcs goya_funcs = {
5387         .early_init = goya_early_init,
5388         .early_fini = goya_early_fini,
5389         .late_init = goya_late_init,
5390         .late_fini = goya_late_fini,
5391         .sw_init = goya_sw_init,
5392         .sw_fini = goya_sw_fini,
5393         .hw_init = goya_hw_init,
5394         .hw_fini = goya_hw_fini,
5395         .halt_engines = goya_halt_engines,
5396         .suspend = goya_suspend,
5397         .resume = goya_resume,
5398         .cb_mmap = goya_cb_mmap,
5399         .ring_doorbell = goya_ring_doorbell,
5400         .pqe_write = goya_pqe_write,
5401         .asic_dma_alloc_coherent = goya_dma_alloc_coherent,
5402         .asic_dma_free_coherent = goya_dma_free_coherent,
5403         .scrub_device_mem = goya_scrub_device_mem,
5404         .get_int_queue_base = goya_get_int_queue_base,
5405         .test_queues = goya_test_queues,
5406         .asic_dma_pool_zalloc = goya_dma_pool_zalloc,
5407         .asic_dma_pool_free = goya_dma_pool_free,
5408         .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
5409         .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
5410         .hl_dma_unmap_sg = goya_dma_unmap_sg,
5411         .cs_parser = goya_cs_parser,
5412         .asic_dma_map_sg = goya_dma_map_sg,
5413         .get_dma_desc_list_size = goya_get_dma_desc_list_size,
5414         .add_end_of_cb_packets = goya_add_end_of_cb_packets,
5415         .update_eq_ci = goya_update_eq_ci,
5416         .context_switch = goya_context_switch,
5417         .restore_phase_topology = goya_restore_phase_topology,
5418         .debugfs_read32 = goya_debugfs_read32,
5419         .debugfs_write32 = goya_debugfs_write32,
5420         .debugfs_read64 = goya_debugfs_read64,
5421         .debugfs_write64 = goya_debugfs_write64,
5422         .add_device_attr = goya_add_device_attr,
5423         .handle_eqe = goya_handle_eqe,
5424         .set_pll_profile = goya_set_pll_profile,
5425         .get_events_stat = goya_get_events_stat,
5426         .read_pte = goya_read_pte,
5427         .write_pte = goya_write_pte,
5428         .mmu_invalidate_cache = goya_mmu_invalidate_cache,
5429         .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
5430         .send_heartbeat = goya_send_heartbeat,
5431         .set_clock_gating = goya_set_clock_gating,
5432         .disable_clock_gating = goya_disable_clock_gating,
5433         .debug_coresight = goya_debug_coresight,
5434         .is_device_idle = goya_is_device_idle,
5435         .soft_reset_late_init = goya_soft_reset_late_init,
5436         .hw_queues_lock = goya_hw_queues_lock,
5437         .hw_queues_unlock = goya_hw_queues_unlock,
5438         .get_pci_id = goya_get_pci_id,
5439         .get_eeprom_data = goya_get_eeprom_data,
5440         .send_cpu_message = goya_send_cpu_message,
5441         .pci_bars_map = goya_pci_bars_map,
5442         .init_iatu = goya_init_iatu,
5443         .rreg = hl_rreg,
5444         .wreg = hl_wreg,
5445         .halt_coresight = goya_halt_coresight,
5446         .ctx_init = goya_ctx_init,
5447         .ctx_fini = goya_ctx_fini,
5448         .get_clk_rate = goya_get_clk_rate,
5449         .get_queue_id_for_cq = goya_get_queue_id_for_cq,
5450         .read_device_fw_version = goya_read_device_fw_version,
5451         .load_firmware_to_device = goya_load_firmware_to_device,
5452         .load_boot_fit_to_device = goya_load_boot_fit_to_device,
5453         .get_signal_cb_size = goya_get_signal_cb_size,
5454         .get_wait_cb_size = goya_get_wait_cb_size,
5455         .gen_signal_cb = goya_gen_signal_cb,
5456         .gen_wait_cb = goya_gen_wait_cb,
5457         .reset_sob = goya_reset_sob,
5458         .reset_sob_group = goya_reset_sob_group,
5459         .set_dma_mask_from_fw = goya_set_dma_mask_from_fw,
5460         .get_device_time = goya_get_device_time,
5461         .collective_wait_init_cs = goya_collective_wait_init_cs,
5462         .collective_wait_create_jobs = goya_collective_wait_create_jobs
5463 };
5464
5465 /*
5466  * goya_set_asic_funcs - set Goya function pointers
5467  *
5468  * @*hdev: pointer to hl_device structure
5469  *
5470  */
5471 void goya_set_asic_funcs(struct hl_device *hdev)
5472 {
5473         hdev->asic_funcs = &goya_funcs;
5474 }