1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
8 #include "habanalabs.h"
9 #include "../include/hw_ip/pci/pci_general.h"
11 #include <linux/pci.h>
13 #define HL_PLDM_PCI_ELBI_TIMEOUT_MSEC (HL_PCI_ELBI_TIMEOUT_MSEC * 10)
15 #define IATU_REGION_CTRL_REGION_EN_MASK BIT(31)
16 #define IATU_REGION_CTRL_MATCH_MODE_MASK BIT(30)
17 #define IATU_REGION_CTRL_NUM_MATCH_EN_MASK BIT(19)
18 #define IATU_REGION_CTRL_BAR_NUM_MASK GENMASK(10, 8)
21 * hl_pci_bars_map() - Map PCI BARs.
22 * @hdev: Pointer to hl_device structure.
23 * @name: Array of BAR names.
24 * @is_wc: Array with flag per BAR whether a write-combined mapping is needed.
26 * Request PCI regions and map them to kernel virtual addresses.
28 * Return: 0 on success, non-zero for failure.
30 int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
33 struct pci_dev *pdev = hdev->pdev;
36 rc = pci_request_regions(pdev, HL_NAME);
38 dev_err(hdev->dev, "Cannot obtain PCI resources\n");
42 for (i = 0 ; i < 3 ; i++) {
43 bar = i * 2; /* 64-bit BARs */
44 hdev->pcie_bar[bar] = is_wc[i] ?
45 pci_ioremap_wc_bar(pdev, bar) :
46 pci_ioremap_bar(pdev, bar);
47 if (!hdev->pcie_bar[bar]) {
48 dev_err(hdev->dev, "pci_ioremap%s_bar failed for %s\n",
49 is_wc[i] ? "_wc" : "", name[i]);
58 for (i = 2 ; i >= 0 ; i--) {
59 bar = i * 2; /* 64-bit BARs */
60 if (hdev->pcie_bar[bar])
61 iounmap(hdev->pcie_bar[bar]);
64 pci_release_regions(pdev);
70 * hl_pci_bars_unmap() - Unmap PCI BARS.
71 * @hdev: Pointer to hl_device structure.
73 * Release all PCI BARs and unmap their virtual addresses.
75 static void hl_pci_bars_unmap(struct hl_device *hdev)
77 struct pci_dev *pdev = hdev->pdev;
80 for (i = 2 ; i >= 0 ; i--) {
81 bar = i * 2; /* 64-bit BARs */
82 iounmap(hdev->pcie_bar[bar]);
85 pci_release_regions(pdev);
89 * hl_pci_elbi_write() - Write through the ELBI interface.
90 * @hdev: Pointer to hl_device structure.
91 * @addr: Address to write to
92 * @data: Data to write
94 * Return: 0 on success, negative value for failure.
96 static int hl_pci_elbi_write(struct hl_device *hdev, u64 addr, u32 data)
98 struct pci_dev *pdev = hdev->pdev;
104 msec = HL_PLDM_PCI_ELBI_TIMEOUT_MSEC;
106 msec = HL_PCI_ELBI_TIMEOUT_MSEC;
108 /* Clear previous status */
109 pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0);
111 pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr);
112 pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data);
113 pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL,
114 PCI_CONFIG_ELBI_CTRL_WRITE);
116 timeout = ktime_add_ms(ktime_get(), msec);
118 pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val);
119 if (val & PCI_CONFIG_ELBI_STS_MASK)
121 if (ktime_compare(ktime_get(), timeout) > 0) {
122 pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS,
127 usleep_range(300, 500);
130 if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE)
133 if (val & PCI_CONFIG_ELBI_STS_ERR) {
134 dev_err(hdev->dev, "Error writing to ELBI\n");
138 if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
139 dev_err(hdev->dev, "ELBI write didn't finish in time\n");
143 dev_err(hdev->dev, "ELBI write has undefined bits in status\n");
148 * hl_pci_iatu_write() - iatu write routine.
149 * @hdev: Pointer to hl_device structure.
150 * @addr: Address to write to
151 * @data: Data to write
153 * Return: 0 on success, negative value for failure.
155 int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data)
157 struct asic_fixed_properties *prop = &hdev->asic_prop;
161 dbi_offset = addr & 0xFFF;
163 rc = hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000);
164 rc |= hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset,
174 * hl_pci_reset_link_through_bridge() - Reset PCI link.
175 * @hdev: Pointer to hl_device structure.
177 static void hl_pci_reset_link_through_bridge(struct hl_device *hdev)
179 struct pci_dev *pdev = hdev->pdev;
180 struct pci_dev *parent_port;
183 parent_port = pdev->bus->self;
184 pci_read_config_word(parent_port, PCI_BRIDGE_CONTROL, &val);
185 val |= PCI_BRIDGE_CTL_BUS_RESET;
186 pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
189 val &= ~(PCI_BRIDGE_CTL_BUS_RESET);
190 pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
195 * hl_pci_set_inbound_region() - Configure inbound region
196 * @hdev: Pointer to hl_device structure.
197 * @region: Inbound region number.
198 * @pci_region: Inbound region parameters.
200 * Configure the iATU inbound region.
202 * Return: 0 on success, negative value for failure.
204 int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region,
205 struct hl_inbound_pci_region *pci_region)
207 struct asic_fixed_properties *prop = &hdev->asic_prop;
208 u64 bar_phys_base, region_base, region_end_address;
209 u32 offset, ctrl_reg_val;
213 offset = (0x200 * region) + 0x100;
215 if (pci_region->mode == PCI_ADDRESS_MATCH_MODE) {
216 bar_phys_base = hdev->pcie_bar_phys[pci_region->bar];
217 region_base = bar_phys_base + pci_region->offset_in_bar;
218 region_end_address = region_base + pci_region->size - 1;
220 rc |= hl_pci_iatu_write(hdev, offset + 0x8,
221 lower_32_bits(region_base));
222 rc |= hl_pci_iatu_write(hdev, offset + 0xC,
223 upper_32_bits(region_base));
224 rc |= hl_pci_iatu_write(hdev, offset + 0x10,
225 lower_32_bits(region_end_address));
228 /* Point to the specified address */
229 rc |= hl_pci_iatu_write(hdev, offset + 0x14,
230 lower_32_bits(pci_region->addr));
231 rc |= hl_pci_iatu_write(hdev, offset + 0x18,
232 upper_32_bits(pci_region->addr));
233 rc |= hl_pci_iatu_write(hdev, offset + 0x0, 0);
235 /* Enable + bar/address match + match enable + bar number */
236 ctrl_reg_val = FIELD_PREP(IATU_REGION_CTRL_REGION_EN_MASK, 1);
237 ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_MATCH_MODE_MASK,
239 ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_NUM_MATCH_EN_MASK, 1);
241 if (pci_region->mode == PCI_BAR_MATCH_MODE)
242 ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_BAR_NUM_MASK,
245 rc |= hl_pci_iatu_write(hdev, offset + 0x4, ctrl_reg_val);
247 /* Return the DBI window to the default location */
248 rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
249 rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0);
252 dev_err(hdev->dev, "failed to map bar %u to 0x%08llx\n",
253 pci_region->bar, pci_region->addr);
259 * hl_pci_set_outbound_region() - Configure outbound region 0
260 * @hdev: Pointer to hl_device structure.
261 * @pci_region: Outbound region parameters.
263 * Configure the iATU outbound region 0.
265 * Return: 0 on success, negative value for failure.
267 int hl_pci_set_outbound_region(struct hl_device *hdev,
268 struct hl_outbound_pci_region *pci_region)
270 struct asic_fixed_properties *prop = &hdev->asic_prop;
271 u64 outbound_region_end_address;
274 /* Outbound Region 0 */
275 outbound_region_end_address =
276 pci_region->addr + pci_region->size - 1;
277 rc |= hl_pci_iatu_write(hdev, 0x008,
278 lower_32_bits(pci_region->addr));
279 rc |= hl_pci_iatu_write(hdev, 0x00C,
280 upper_32_bits(pci_region->addr));
281 rc |= hl_pci_iatu_write(hdev, 0x010,
282 lower_32_bits(outbound_region_end_address));
283 rc |= hl_pci_iatu_write(hdev, 0x014, 0);
285 if ((hdev->power9_64bit_dma_enable) && (hdev->dma_mask == 64))
286 rc |= hl_pci_iatu_write(hdev, 0x018, 0x08000000);
288 rc |= hl_pci_iatu_write(hdev, 0x018, 0);
290 rc |= hl_pci_iatu_write(hdev, 0x020,
291 upper_32_bits(outbound_region_end_address));
292 /* Increase region size */
293 rc |= hl_pci_iatu_write(hdev, 0x000, 0x00002000);
295 rc |= hl_pci_iatu_write(hdev, 0x004, 0x80000000);
297 /* Return the DBI window to the default location */
298 rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
299 rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0);
305 * hl_pci_set_dma_mask() - Set DMA masks for the device.
306 * @hdev: Pointer to hl_device structure.
308 * This function sets the DMA masks (regular and consistent) for a specified
309 * value. If it doesn't succeed, it tries to set it to a fall-back value
311 * Return: 0 on success, non-zero for failure.
313 static int hl_pci_set_dma_mask(struct hl_device *hdev)
315 struct pci_dev *pdev = hdev->pdev;
319 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(hdev->dma_mask));
322 "Failed to set pci dma mask to %d bits, error %d\n",
327 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(hdev->dma_mask));
330 "Failed to set pci consistent dma mask to %d bits, error %d\n",
339 * hl_pci_init() - PCI initialization code.
340 * @hdev: Pointer to hl_device structure.
341 * @cpu_boot_status_reg: status register of the device's CPU
342 * @boot_err0_reg: boot error register of the device's CPU
343 * @preboot_ver_timeout: how much to wait before bailing out on reading
344 * the preboot version
346 * Set DMA masks, initialize the PCI controller and map the PCI BARs.
348 * Return: 0 on success, non-zero for failure.
350 int hl_pci_init(struct hl_device *hdev, u32 cpu_boot_status_reg,
351 u32 boot_err0_reg, u32 preboot_ver_timeout)
353 struct pci_dev *pdev = hdev->pdev;
356 if (hdev->reset_pcilink)
357 hl_pci_reset_link_through_bridge(hdev);
359 rc = pci_enable_device_mem(pdev);
361 dev_err(hdev->dev, "can't enable PCI device\n");
365 pci_set_master(pdev);
367 rc = hdev->asic_funcs->pci_bars_map(hdev);
369 dev_err(hdev->dev, "Failed to initialize PCI BARs\n");
373 rc = hdev->asic_funcs->init_iatu(hdev);
375 dev_err(hdev->dev, "Failed to initialize iATU\n");
379 rc = hl_pci_set_dma_mask(hdev);
383 /* Before continuing in the initialization, we need to read the preboot
384 * version to determine whether we run with a security-enabled firmware
385 * The check will be done in each ASIC's specific code
387 rc = hl_fw_read_preboot_ver(hdev, cpu_boot_status_reg, boot_err0_reg,
388 preboot_ver_timeout);
395 hl_pci_bars_unmap(hdev);
397 pci_clear_master(pdev);
398 pci_disable_device(pdev);
404 * hl_fw_fini() - PCI finalization code.
405 * @hdev: Pointer to hl_device structure
407 * Unmap PCI bars and disable PCI device.
409 void hl_pci_fini(struct hl_device *hdev)
411 hl_pci_bars_unmap(hdev);
413 pci_clear_master(hdev->pdev);
414 pci_disable_device(hdev->pdev);