1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
8 #include "../habanalabs.h"
9 #include "../../include/hw_ip/pci/pci_general.h"
11 #include <linux/pci.h>
13 #define HL_PLDM_PCI_ELBI_TIMEOUT_MSEC (HL_PCI_ELBI_TIMEOUT_MSEC * 100)
15 #define IATU_REGION_CTRL_REGION_EN_MASK BIT(31)
16 #define IATU_REGION_CTRL_MATCH_MODE_MASK BIT(30)
17 #define IATU_REGION_CTRL_NUM_MATCH_EN_MASK BIT(19)
18 #define IATU_REGION_CTRL_BAR_NUM_MASK GENMASK(10, 8)
21 * hl_pci_bars_map() - Map PCI BARs.
22 * @hdev: Pointer to hl_device structure.
23 * @name: Array of BAR names.
24 * @is_wc: Array with flag per BAR whether a write-combined mapping is needed.
26 * Request PCI regions and map them to kernel virtual addresses.
28 * Return: 0 on success, non-zero for failure.
30 int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
33 struct pci_dev *pdev = hdev->pdev;
36 rc = pci_request_regions(pdev, HL_NAME);
38 dev_err(hdev->dev, "Cannot obtain PCI resources\n");
42 for (i = 0 ; i < 3 ; i++) {
43 bar = i * 2; /* 64-bit BARs */
44 hdev->pcie_bar[bar] = is_wc[i] ?
45 pci_ioremap_wc_bar(pdev, bar) :
46 pci_ioremap_bar(pdev, bar);
47 if (!hdev->pcie_bar[bar]) {
48 dev_err(hdev->dev, "pci_ioremap%s_bar failed for %s\n",
49 is_wc[i] ? "_wc" : "", name[i]);
58 for (i = 2 ; i >= 0 ; i--) {
59 bar = i * 2; /* 64-bit BARs */
60 if (hdev->pcie_bar[bar])
61 iounmap(hdev->pcie_bar[bar]);
64 pci_release_regions(pdev);
70 * hl_pci_bars_unmap() - Unmap PCI BARS.
71 * @hdev: Pointer to hl_device structure.
73 * Release all PCI BARs and unmap their virtual addresses.
75 static void hl_pci_bars_unmap(struct hl_device *hdev)
77 struct pci_dev *pdev = hdev->pdev;
80 for (i = 2 ; i >= 0 ; i--) {
81 bar = i * 2; /* 64-bit BARs */
82 iounmap(hdev->pcie_bar[bar]);
85 pci_release_regions(pdev);
88 int hl_pci_elbi_read(struct hl_device *hdev, u64 addr, u32 *data)
90 struct pci_dev *pdev = hdev->pdev;
96 msec = HL_PLDM_PCI_ELBI_TIMEOUT_MSEC;
98 msec = HL_PCI_ELBI_TIMEOUT_MSEC;
100 /* Clear previous status */
101 pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0);
103 pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr);
104 pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL, 0);
106 timeout = ktime_add_ms(ktime_get(), msec);
108 pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val);
109 if (val & PCI_CONFIG_ELBI_STS_MASK)
111 if (ktime_compare(ktime_get(), timeout) > 0) {
112 pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS,
117 usleep_range(300, 500);
120 if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE) {
121 pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data);
126 if (val & PCI_CONFIG_ELBI_STS_ERR) {
127 dev_err(hdev->dev, "Error reading from ELBI\n");
131 if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
132 dev_err(hdev->dev, "ELBI read didn't finish in time\n");
136 dev_err(hdev->dev, "ELBI read has undefined bits in status\n");
141 * hl_pci_elbi_write() - Write through the ELBI interface.
142 * @hdev: Pointer to hl_device structure.
143 * @addr: Address to write to
144 * @data: Data to write
146 * Return: 0 on success, negative value for failure.
148 static int hl_pci_elbi_write(struct hl_device *hdev, u64 addr, u32 data)
150 struct pci_dev *pdev = hdev->pdev;
156 msec = HL_PLDM_PCI_ELBI_TIMEOUT_MSEC;
158 msec = HL_PCI_ELBI_TIMEOUT_MSEC;
160 /* Clear previous status */
161 pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0);
163 pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr);
164 pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data);
165 pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL,
166 PCI_CONFIG_ELBI_CTRL_WRITE);
168 timeout = ktime_add_ms(ktime_get(), msec);
170 pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val);
171 if (val & PCI_CONFIG_ELBI_STS_MASK)
173 if (ktime_compare(ktime_get(), timeout) > 0) {
174 pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS,
179 usleep_range(300, 500);
182 if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE)
185 if (val & PCI_CONFIG_ELBI_STS_ERR)
188 if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
189 dev_err(hdev->dev, "ELBI write didn't finish in time\n");
193 dev_err(hdev->dev, "ELBI write has undefined bits in status\n");
198 * hl_pci_iatu_write() - iatu write routine.
199 * @hdev: Pointer to hl_device structure.
200 * @addr: Address to write to
201 * @data: Data to write
203 * Return: 0 on success, negative value for failure.
205 int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data)
207 struct asic_fixed_properties *prop = &hdev->asic_prop;
211 dbi_offset = addr & 0xFFF;
213 /* Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
214 * in case the firmware security is enabled
216 hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000);
218 rc = hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset,
228 * hl_pci_reset_link_through_bridge() - Reset PCI link.
229 * @hdev: Pointer to hl_device structure.
231 static void hl_pci_reset_link_through_bridge(struct hl_device *hdev)
233 struct pci_dev *pdev = hdev->pdev;
234 struct pci_dev *parent_port;
237 parent_port = pdev->bus->self;
238 pci_read_config_word(parent_port, PCI_BRIDGE_CONTROL, &val);
239 val |= PCI_BRIDGE_CTL_BUS_RESET;
240 pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
243 val &= ~(PCI_BRIDGE_CTL_BUS_RESET);
244 pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
249 * hl_pci_set_inbound_region() - Configure inbound region
250 * @hdev: Pointer to hl_device structure.
251 * @region: Inbound region number.
252 * @pci_region: Inbound region parameters.
254 * Configure the iATU inbound region.
256 * Return: 0 on success, negative value for failure.
258 int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region,
259 struct hl_inbound_pci_region *pci_region)
261 struct asic_fixed_properties *prop = &hdev->asic_prop;
262 u64 bar_phys_base, region_base, region_end_address;
263 u32 offset, ctrl_reg_val;
267 offset = (0x200 * region) + 0x100;
269 if (pci_region->mode == PCI_ADDRESS_MATCH_MODE) {
270 bar_phys_base = hdev->pcie_bar_phys[pci_region->bar];
271 region_base = bar_phys_base + pci_region->offset_in_bar;
272 region_end_address = region_base + pci_region->size - 1;
274 rc |= hl_pci_iatu_write(hdev, offset + 0x8,
275 lower_32_bits(region_base));
276 rc |= hl_pci_iatu_write(hdev, offset + 0xC,
277 upper_32_bits(region_base));
278 rc |= hl_pci_iatu_write(hdev, offset + 0x10,
279 lower_32_bits(region_end_address));
282 /* Point to the specified address */
283 rc |= hl_pci_iatu_write(hdev, offset + 0x14,
284 lower_32_bits(pci_region->addr));
285 rc |= hl_pci_iatu_write(hdev, offset + 0x18,
286 upper_32_bits(pci_region->addr));
287 rc |= hl_pci_iatu_write(hdev, offset + 0x0, 0);
289 /* Enable + bar/address match + match enable + bar number */
290 ctrl_reg_val = FIELD_PREP(IATU_REGION_CTRL_REGION_EN_MASK, 1);
291 ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_MATCH_MODE_MASK,
293 ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_NUM_MATCH_EN_MASK, 1);
295 if (pci_region->mode == PCI_BAR_MATCH_MODE)
296 ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_BAR_NUM_MASK,
299 rc |= hl_pci_iatu_write(hdev, offset + 0x4, ctrl_reg_val);
301 /* Return the DBI window to the default location
302 * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
303 * in case the firmware security is enabled
305 hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
308 dev_err(hdev->dev, "failed to map bar %u to 0x%08llx\n",
309 pci_region->bar, pci_region->addr);
315 * hl_pci_set_outbound_region() - Configure outbound region 0
316 * @hdev: Pointer to hl_device structure.
317 * @pci_region: Outbound region parameters.
319 * Configure the iATU outbound region 0.
321 * Return: 0 on success, negative value for failure.
323 int hl_pci_set_outbound_region(struct hl_device *hdev,
324 struct hl_outbound_pci_region *pci_region)
326 struct asic_fixed_properties *prop = &hdev->asic_prop;
327 u64 outbound_region_end_address;
330 /* Outbound Region 0 */
331 outbound_region_end_address =
332 pci_region->addr + pci_region->size - 1;
333 rc |= hl_pci_iatu_write(hdev, 0x008,
334 lower_32_bits(pci_region->addr));
335 rc |= hl_pci_iatu_write(hdev, 0x00C,
336 upper_32_bits(pci_region->addr));
337 rc |= hl_pci_iatu_write(hdev, 0x010,
338 lower_32_bits(outbound_region_end_address));
339 rc |= hl_pci_iatu_write(hdev, 0x014, 0);
341 if ((hdev->power9_64bit_dma_enable) && (hdev->dma_mask == 64))
342 rc |= hl_pci_iatu_write(hdev, 0x018, 0x08000000);
344 rc |= hl_pci_iatu_write(hdev, 0x018, 0);
346 rc |= hl_pci_iatu_write(hdev, 0x020,
347 upper_32_bits(outbound_region_end_address));
348 /* Increase region size */
349 rc |= hl_pci_iatu_write(hdev, 0x000, 0x00002000);
351 rc |= hl_pci_iatu_write(hdev, 0x004, 0x80000000);
353 /* Return the DBI window to the default location
354 * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
355 * in case the firmware security is enabled
357 hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
363 * hl_get_pci_memory_region() - get PCI region for given address
364 * @hdev: Pointer to hl_device structure.
365 * @addr: device address
367 * @return region index on success, otherwise PCI_REGION_NUMBER (invalid
370 enum pci_region hl_get_pci_memory_region(struct hl_device *hdev, u64 addr)
374 for (i = 0 ; i < PCI_REGION_NUMBER ; i++) {
375 struct pci_mem_region *region = &hdev->pci_mem_region[i];
380 if ((addr >= region->region_base) &&
381 (addr < region->region_base + region->region_size))
385 return PCI_REGION_NUMBER;
389 * hl_pci_init() - PCI initialization code.
390 * @hdev: Pointer to hl_device structure.
392 * Set DMA masks, initialize the PCI controller and map the PCI BARs.
394 * Return: 0 on success, non-zero for failure.
396 int hl_pci_init(struct hl_device *hdev)
398 struct pci_dev *pdev = hdev->pdev;
401 if (hdev->reset_pcilink)
402 hl_pci_reset_link_through_bridge(hdev);
404 rc = pci_enable_device_mem(pdev);
406 dev_err(hdev->dev, "can't enable PCI device\n");
410 pci_set_master(pdev);
412 rc = hdev->asic_funcs->pci_bars_map(hdev);
414 dev_err(hdev->dev, "Failed to initialize PCI BARs\n");
418 rc = hdev->asic_funcs->init_iatu(hdev);
420 dev_err(hdev->dev, "Failed to initialize iATU\n");
424 /* Driver must sleep in order for FW to finish the iATU configuration */
425 if (hdev->asic_prop.iatu_done_by_fw) {
426 usleep_range(2000, 3000);
427 hdev->asic_funcs->set_dma_mask_from_fw(hdev);
430 rc = dma_set_mask_and_coherent(&pdev->dev,
431 DMA_BIT_MASK(hdev->dma_mask));
434 "Failed to set dma mask to %d bits, error %d\n",
439 dma_set_max_seg_size(&pdev->dev, U32_MAX);
444 hl_pci_bars_unmap(hdev);
446 pci_clear_master(pdev);
447 pci_disable_device(pdev);
453 * hl_fw_fini() - PCI finalization code.
454 * @hdev: Pointer to hl_device structure
456 * Unmap PCI bars and disable PCI device.
458 void hl_pci_fini(struct hl_device *hdev)
460 hl_pci_bars_unmap(hdev);
462 pci_clear_master(hdev->pdev);
463 pci_disable_device(hdev->pdev);