drivers/misc/cardreader/rts5260.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Driver for Realtek PCI-Express card reader
   3  *
   4  * Copyright(c) 2016-2017 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Steven FENG <steven_feng@realsil.com.cn>
   8  *   Rui FENG <rui_feng@realsil.com.cn>
   9  *   Wei WANG <wei_wang@realsil.com.cn>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/delay.h>
  14 #include <linux/rtsx_pci.h>
  15
  16 #include "rts5260.h"
  17 #include "rtsx_pcr.h"
  18
  19 static u8 rts5260_get_ic_version(struct rtsx_pcr *pcr)
  20 {
  21         u8 val;
  22
  23         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  24         return val & IC_VERSION_MASK;
  25 }
  26
  27 static void rts5260_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  28 {
  29         u8 driving_3v3[6][3] = {
  30                 {0x94, 0x94, 0x94},
  31                 {0x11, 0x11, 0x18},
  32                 {0x55, 0x55, 0x5C},
  33                 {0x94, 0x94, 0x94},
  34                 {0x94, 0x94, 0x94},
  35                 {0xFF, 0xFF, 0xFF},
  36         };
  37         u8 driving_1v8[6][3] = {
  38                 {0x9A, 0x89, 0x89},
  39                 {0xC4, 0xC4, 0xC4},
  40                 {0x3C, 0x3C, 0x3C},
  41                 {0x9B, 0x99, 0x99},
  42                 {0x9A, 0x89, 0x89},
  43                 {0xFE, 0xFE, 0xFE},
  44         };
  45         u8 (*driving)[3], drive_sel;
  46
  47         if (voltage == OUTPUT_3V3) {
  48                 driving = driving_3v3;
  49                 drive_sel = pcr->sd30_drive_sel_3v3;
  50         } else {
  51                 driving = driving_1v8;
  52                 drive_sel = pcr->sd30_drive_sel_1v8;
  53         }
  54
  55         rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
  56                          0xFF, driving[drive_sel][0]);
  57
  58         rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
  59                          0xFF, driving[drive_sel][1]);
  60
  61         rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
  62                          0xFF, driving[drive_sel][2]);
  63 }
  64
  65 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
  66 {
  67         u32 reg;
  68
  69         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  70         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  71
  72         if (!rtsx_vendor_setting_valid(reg)) {
  73                 pcr_dbg(pcr, "skip fetch vendor setting\n");
  74                 return;
  75         }
  76
  77         pcr->aspm_en = rtsx_reg_to_aspm(reg);
  78         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  79         pcr->card_drive_sel &= 0x3F;
  80         pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  81
  82         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  83         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  84         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  85         if (rtsx_reg_check_reverse_socket(reg))
  86                 pcr->flags |= PCR_REVERSE_SOCKET;
  87 }
  88
  89 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  90 {
  91         /* Set relink_time to 0 */
  92         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
  93         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
  94         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
  95                                 RELINK_TIME_MASK, 0);
  96
  97         if (pm_state == HOST_ENTER_S3)
  98                 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
  99                                         D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
 100
 101         rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
 102 }
 103
 104 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
 105 {
 106         return rtsx_pci_write_register(pcr, OLT_LED_CTL,
 107                 LED_SHINE_MASK, LED_SHINE_EN);
 108 }
 109
 110 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
 111 {
 112         return rtsx_pci_write_register(pcr, OLT_LED_CTL,
 113                 LED_SHINE_MASK, LED_SHINE_DISABLE);
 114 }
 115
 116 static int rts5260_turn_on_led(struct rtsx_pcr *pcr)
 117 {
 118         return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
 119                 RTS5260_REG_GPIO_MASK, RTS5260_REG_GPIO_ON);
 120 }
 121
 122 static int rts5260_turn_off_led(struct rtsx_pcr *pcr)
 123 {
 124         return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
 125                 RTS5260_REG_GPIO_MASK, RTS5260_REG_GPIO_OFF);
 126 }
 127
 128 /* SD Pull Control Enable:
 129  *     SD_DAT[3:0] ==> pull up
 130  *     SD_CD       ==> pull up
 131  *     SD_WP       ==> pull up
 132  *     SD_CMD      ==> pull up
 133  *     SD_CLK      ==> pull down
 134  */
 135 static const u32 rts5260_sd_pull_ctl_enable_tbl[] = {
 136         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 137         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 138         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 139         RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
 140         0,
 141 };
 142
 143 /* SD Pull Control Disable:
 144  *     SD_DAT[3:0] ==> pull down
 145  *     SD_CD       ==> pull up
 146  *     SD_WP       ==> pull down
 147  *     SD_CMD      ==> pull down
 148  *     SD_CLK      ==> pull down
 149  */
 150 static const u32 rts5260_sd_pull_ctl_disable_tbl[] = {
 151         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 152         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 153         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 154         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 155         0,
 156 };
 157
 158 /* MS Pull Control Enable:
 159  *     MS CD       ==> pull up
 160  *     others      ==> pull down
 161  */
 162 static const u32 rts5260_ms_pull_ctl_enable_tbl[] = {
 163         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 164         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 165         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 166         0,
 167 };
 168
 169 /* MS Pull Control Disable:
 170  *     MS CD       ==> pull up
 171  *     others      ==> pull down
 172  */
 173 static const u32 rts5260_ms_pull_ctl_disable_tbl[] = {
 174         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 175         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 176         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 177         0,
 178 };
 179
 180 static int sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
 181 {
 182         rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
 183                 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 184         rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
 185         rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
 186                         CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 187         rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 188
 189         return 0;
 190 }
 191
 192 static int rts5260_card_power_on(struct rtsx_pcr *pcr, int card)
 193 {
 194         struct rtsx_cr_option *option = &pcr->option;
 195
 196         if (option->ocp_en)
 197                 rtsx_pci_enable_ocp(pcr);
 198
 199
 200         rtsx_pci_write_register(pcr, LDO_CONFIG2, DV331812_VDD1, DV331812_VDD1);
 201         rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
 202                          RTS5260_DVCC_TUNE_MASK, RTS5260_DVCC_33);
 203
 204         rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_POW_SDVDD1_MASK,
 205                         LDO_POW_SDVDD1_ON);
 206
 207         rtsx_pci_write_register(pcr, LDO_CONFIG2,
 208                          DV331812_POWERON, DV331812_POWERON);
 209         msleep(20);
 210
 211         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
 212             pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
 213                 sd_set_sample_push_timing_sd30(pcr);
 214
 215         /* Initialize SD_CFG1 register */
 216         rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
 217                                 SD_CLK_DIVIDE_128 | SD_20_MODE);
 218
 219         rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
 220                                 0xFF, SD20_RX_POS_EDGE);
 221         rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
 222         rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
 223                                 SD_STOP | SD_CLR_ERR);
 224
 225         /* Reset SD_CFG3 register */
 226         rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
 227         rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
 228                         SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
 229                         SD30_CLK_STOP_CFG0, 0);
 230
 231         rtsx_pci_write_register(pcr, REG_PRE_RW_MODE, EN_INFINITE_MODE, 0);
 232
 233         return 0;
 234 }
 235
 236 static int rts5260_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 237 {
 238         switch (voltage) {
 239         case OUTPUT_3V3:
 240                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 241                                         DV331812_VDD1, DV331812_VDD1);
 242                 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
 243                                         DV331812_MASK, DV331812_33);
 244                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
 245                 break;
 246         case OUTPUT_1V8:
 247                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 248                                         DV331812_VDD1, DV331812_VDD1);
 249                 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
 250                                         DV331812_MASK, DV331812_17);
 251                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
 252                                         SD_IO_USING_1V8);
 253                 break;
 254         default:
 255                 return -EINVAL;
 256         }
 257
 258         /* set pad drive */
 259         rts5260_fill_driving(pcr, voltage);
 260
 261         return 0;
 262 }
 263
 264 static void rts5260_stop_cmd(struct rtsx_pcr *pcr)
 265 {
 266         rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
 267         rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
 268         rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
 269                                 RTS5260_DMA_RST | RTS5260_ADMA3_RST,
 270                                 RTS5260_DMA_RST | RTS5260_ADMA3_RST);
 271         rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
 272 }
 273
 274 static void rts5260_card_before_power_off(struct rtsx_pcr *pcr)
 275 {
 276         rts5260_stop_cmd(pcr);
 277         rts5260_switch_output_voltage(pcr, OUTPUT_3V3);
 278
 279 }
 280
 281 static int rts5260_card_power_off(struct rtsx_pcr *pcr, int card)
 282 {
 283         int err = 0;
 284
 285         rts5260_card_before_power_off(pcr);
 286         err = rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 287                          LDO_POW_SDVDD1_MASK, LDO_POW_SDVDD1_OFF);
 288         err = rtsx_pci_write_register(pcr, LDO_CONFIG2,
 289                          DV331812_POWERON, DV331812_POWEROFF);
 290         if (pcr->option.ocp_en)
 291                 rtsx_pci_disable_ocp(pcr);
 292
 293         return err;
 294 }
 295
 296 static void rts5260_init_ocp(struct rtsx_pcr *pcr)
 297 {
 298         struct rtsx_cr_option *option = &pcr->option;
 299
 300         if (option->ocp_en) {
 301                 u8 mask, val;
 302
 303
 304                 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
 305                                 RTS5260_DVCC_OCP_THD_MASK,
 306                                 option->sd_800mA_ocp_thd);
 307
 308                 rtsx_pci_write_register(pcr, RTS5260_DV331812_CFG,
 309                                 RTS5260_DV331812_OCP_THD_MASK,
 310                                 RTS5260_DV331812_OCP_THD_270);
 311
 312                 mask = SD_OCP_GLITCH_MASK;
 313                 val = pcr->hw_param.ocp_glitch;
 314                 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
 315                 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
 316                                         RTS5260_DVCC_OCP_EN |
 317                                         RTS5260_DVCC_OCP_CL_EN,
 318                                         RTS5260_DVCC_OCP_EN |
 319                                         RTS5260_DVCC_OCP_CL_EN);
 320
 321                 rtsx_pci_enable_ocp(pcr);
 322         } else {
 323                 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
 324                                         RTS5260_DVCC_OCP_EN |
 325                                         RTS5260_DVCC_OCP_CL_EN, 0);
 326         }
 327 }
 328
 329 static void rts5260_enable_ocp(struct rtsx_pcr *pcr)
 330 {
 331         u8 val = 0;
 332
 333         val = SD_OCP_INT_EN | SD_DETECT_EN;
 334         rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
 335
 336 }
 337
 338 static void rts5260_disable_ocp(struct rtsx_pcr *pcr)
 339 {
 340         u8 mask = 0;
 341
 342         mask = SD_OCP_INT_EN | SD_DETECT_EN;
 343         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
 344
 345 }
 346
 347
 348 static int rts5260_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
 349 {
 350         return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
 351 }
 352
 353 static int rts5260_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val)
 354 {
 355         return rtsx_pci_read_register(pcr, REG_DV3318_OCPSTAT, val);
 356 }
 357
 358 static void rts5260_clear_ocpstat(struct rtsx_pcr *pcr)
 359 {
 360         u8 mask = 0;
 361         u8 val = 0;
 362
 363         mask = SD_OCP_INT_CLR | SD_OC_CLR;
 364         val = SD_OCP_INT_CLR | SD_OC_CLR;
 365
 366         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
 367         rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
 368                                 DV3318_OCP_INT_CLR | DV3318_OCP_CLR,
 369                                 DV3318_OCP_INT_CLR | DV3318_OCP_CLR);
 370         udelay(10);
 371         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
 372         rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
 373                                 DV3318_OCP_INT_CLR | DV3318_OCP_CLR, 0);
 374 }
 375
 376 static void rts5260_process_ocp(struct rtsx_pcr *pcr)
 377 {
 378         if (!pcr->option.ocp_en)
 379                 return;
 380
 381         rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
 382         rts5260_get_ocpstat2(pcr, &pcr->ocp_stat2);
 383
 384         if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) ||
 385                 (pcr->ocp_stat2 & (DV3318_OCP_NOW | DV3318_OCP_EVER))) {
 386                 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 387                 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
 388                 rtsx_pci_clear_ocpstat(pcr);
 389                 pcr->ocp_stat = 0;
 390                 pcr->ocp_stat2 = 0;
 391         }
 392
 393 }
 394
 395 static int rts5260_init_hw(struct rtsx_pcr *pcr)
 396 {
 397         int err;
 398
 399         rtsx_pci_init_cmd(pcr);
 400
 401         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG1,
 402                          AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
 403         /* Rest L1SUB Config */
 404         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
 405         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CLK_FORCE_CTL,
 406                          CLK_PM_EN, CLK_PM_EN);
 407         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWD_SUSPEND_EN, 0xFF, 0xFF);
 408         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 409                          PWR_GATE_EN, PWR_GATE_EN);
 410         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, REG_VREF,
 411                          PWD_SUSPND_EN, PWD_SUSPND_EN);
 412         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RBCTL,
 413                          U_AUTO_DMA_EN_MASK, U_AUTO_DMA_DISABLE);
 414
 415         if (pcr->flags & PCR_REVERSE_SOCKET)
 416                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
 417         else
 418                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
 419
 420         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG,
 421                          OBFF_EN_MASK, OBFF_DISABLE);
 422
 423         err = rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
 424         if (err < 0)
 425                 return err;
 426
 427         rtsx_pci_init_ocp(pcr);
 428
 429         return 0;
 430 }
 431
 432 static void rts5260_pwr_saving_setting(struct rtsx_pcr *pcr)
 433 {
 434         int lss_l1_1, lss_l1_2;
 435
 436         lss_l1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN)
 437                         | rtsx_check_dev_flag(pcr, PM_L1_1_EN);
 438         lss_l1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN)
 439                         | rtsx_check_dev_flag(pcr, PM_L1_2_EN);
 440
 441         rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
 442         if (lss_l1_2) {
 443                 pcr_dbg(pcr, "Set parameters for L1.2.");
 444                 rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
 445                                         0xFF, PCIE_L1_2_EN);
 446                 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
 447                                         RTS5260_DVCC_OCP_EN |
 448                                         RTS5260_DVCC_OCP_CL_EN,
 449                                         RTS5260_DVCC_OCP_EN |
 450                                         RTS5260_DVCC_OCP_CL_EN);
 451
 452                 rtsx_pci_write_register(pcr, PWR_FE_CTL,
 453                                         0xFF, PCIE_L1_2_PD_FE_EN);
 454         } else if (lss_l1_1) {
 455                 pcr_dbg(pcr, "Set parameters for L1.1.");
 456                 rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
 457                                         0xFF, PCIE_L1_1_EN);
 458                 rtsx_pci_write_register(pcr, PWR_FE_CTL,
 459                                         0xFF, PCIE_L1_1_PD_FE_EN);
 460         } else {
 461                 pcr_dbg(pcr, "Set parameters for L1.");
 462                 rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
 463                                         0xFF, PCIE_L1_0_EN);
 464                 rtsx_pci_write_register(pcr, PWR_FE_CTL,
 465                                         0xFF, PCIE_L1_0_PD_FE_EN);
 466         }
 467
 468         rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_DPHY_RET_VALUE,
 469                                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
 470         rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_MAC_RET_VALUE,
 471                                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
 472         rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD30_RET_VALUE,
 473                                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
 474         rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD40_RET_VALUE,
 475                                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
 476         rtsx_pci_write_register(pcr, CFG_L1_0_SYS_RET_VALUE,
 477                                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
 478         /*Option cut APHY*/
 479         rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_0,
 480                                 0xFF, CFG_PCIE_APHY_OFF_0_DEFAULT);
 481         rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_1,
 482                                 0xFF, CFG_PCIE_APHY_OFF_1_DEFAULT);
 483         rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_2,
 484                                 0xFF, CFG_PCIE_APHY_OFF_2_DEFAULT);
 485         rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_3,
 486                                 0xFF, CFG_PCIE_APHY_OFF_3_DEFAULT);
 487         /*CDR DEC*/
 488         rtsx_pci_write_register(pcr, PWC_CDR, 0xFF, PWC_CDR_DEFAULT);
 489         /*PWMPFM*/
 490         rtsx_pci_write_register(pcr, CFG_LP_FPWM_VALUE,
 491                                 0xFF, CFG_LP_FPWM_VALUE_DEFAULT);
 492         /*No Power Saving WA*/
 493         rtsx_pci_write_register(pcr, CFG_L1_0_CRC_MISC_RET_VALUE,
 494                                 0xFF, CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT);
 495 }
 496
 497 static void rts5260_init_from_cfg(struct rtsx_pcr *pcr)
 498 {
 499         struct rtsx_cr_option *option = &pcr->option;
 500         u32 lval;
 501
 502         rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_5260, &lval);
 503
 504         if (lval & ASPM_L1_1_EN_MASK)
 505                 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
 506
 507         if (lval & ASPM_L1_2_EN_MASK)
 508                 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
 509
 510         if (lval & PM_L1_1_EN_MASK)
 511                 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
 512
 513         if (lval & PM_L1_2_EN_MASK)
 514                 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
 515
 516         rts5260_pwr_saving_setting(pcr);
 517
 518         if (option->ltr_en) {
 519                 u16 val;
 520
 521                 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
 522                 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
 523                         option->ltr_enabled = true;
 524                         option->ltr_active = true;
 525                         rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
 526                 } else {
 527                         option->ltr_enabled = false;
 528                 }
 529         }
 530
 531         if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
 532                                 | PM_L1_1_EN | PM_L1_2_EN))
 533                 option->force_clkreq_0 = false;
 534         else
 535                 option->force_clkreq_0 = true;
 536 }
 537
 538 static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
 539 {
 540         struct rtsx_cr_option *option = &pcr->option;
 541
 542         /* Set mcu_cnt to 7 to ensure data can be sampled properly */
 543         rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07);
 544         rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D);
 545
 546         rts5260_init_from_cfg(pcr);
 547
 548         /* force no MDIO*/
 549         rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
 550                                 0xFF, RTS5260_MIMO_DISABLE);
 551         /*Modify SDVCC Tune Default Parameters!*/
 552         rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
 553                                 RTS5260_DVCC_TUNE_MASK, RTS5260_DVCC_33);
 554
 555         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 556
 557         rts5260_init_hw(pcr);
 558
 559         /*
 560          * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
 561          * to drive low, and we forcibly request clock.
 562          */
 563         if (option->force_clkreq_0)
 564                 rtsx_pci_write_register(pcr, PETXCFG,
 565                                  FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
 566         else
 567                 rtsx_pci_write_register(pcr, PETXCFG,
 568                                  FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
 569
 570         return 0;
 571 }
 572
 573 static void rts5260_set_aspm(struct rtsx_pcr *pcr, bool enable)
 574 {
 575         struct rtsx_cr_option *option = &pcr->option;
 576         u8 val = 0;
 577
 578         if (pcr->aspm_enabled == enable)
 579                 return;
 580
 581         if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
 582                 if (enable)
 583                         val = pcr->aspm_en;
 584                 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
 585                                          ASPM_MASK_NEG, val);
 586         } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
 587                 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
 588
 589                 if (!enable)
 590                         val = FORCE_ASPM_CTL0;
 591                 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
 592         }
 593
 594         pcr->aspm_enabled = enable;
 595 }
 596
 597 static void rts5260_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
 598 {
 599         struct rtsx_cr_option *option = &pcr->option;
 600         u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
 601         int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
 602         int aspm_L1_1, aspm_L1_2;
 603         u8 val = 0;
 604
 605         aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
 606         aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
 607
 608         if (active) {
 609                 /* run, latency: 60us */
 610                 if (aspm_L1_1)
 611                         val = option->ltr_l1off_snooze_sspwrgate;
 612         } else {
 613                 /* l1off, latency: 300us */
 614                 if (aspm_L1_2)
 615                         val = option->ltr_l1off_sspwrgate;
 616         }
 617
 618         if (aspm_L1_1 || aspm_L1_2) {
 619                 if (rtsx_check_dev_flag(pcr,
 620                                         LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
 621                         if (card_exist)
 622                                 val &= ~L1OFF_MBIAS2_EN_5250;
 623                         else
 624                                 val |= L1OFF_MBIAS2_EN_5250;
 625                 }
 626         }
 627         rtsx_set_l1off_sub(pcr, val);
 628 }
 629
 630 static const struct pcr_ops rts5260_pcr_ops = {
 631         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 632         .turn_on_led = rts5260_turn_on_led,
 633         .turn_off_led = rts5260_turn_off_led,
 634         .extra_init_hw = rts5260_extra_init_hw,
 635         .enable_auto_blink = rtsx_base_enable_auto_blink,
 636         .disable_auto_blink = rtsx_base_disable_auto_blink,
 637         .card_power_on = rts5260_card_power_on,
 638         .card_power_off = rts5260_card_power_off,
 639         .switch_output_voltage = rts5260_switch_output_voltage,
 640         .force_power_down = rtsx_base_force_power_down,
 641         .stop_cmd = rts5260_stop_cmd,
 642         .set_aspm = rts5260_set_aspm,
 643         .set_l1off_cfg_sub_d0 = rts5260_set_l1off_cfg_sub_d0,
 644         .enable_ocp = rts5260_enable_ocp,
 645         .disable_ocp = rts5260_disable_ocp,
 646         .init_ocp = rts5260_init_ocp,
 647         .process_ocp = rts5260_process_ocp,
 648         .get_ocpstat = rts5260_get_ocpstat,
 649         .clear_ocpstat = rts5260_clear_ocpstat,
 650 };
 651
 652 void rts5260_init_params(struct rtsx_pcr *pcr)
 653 {
 654         struct rtsx_cr_option *option = &pcr->option;
 655         struct rtsx_hw_param *hw_param = &pcr->hw_param;
 656
 657         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 658         pcr->num_slots = 2;
 659
 660         pcr->flags = 0;
 661         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 662         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 663         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 664         pcr->aspm_en = ASPM_L1_EN;
 665         pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
 666         pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
 667
 668         pcr->ic_version = rts5260_get_ic_version(pcr);
 669         pcr->sd_pull_ctl_enable_tbl = rts5260_sd_pull_ctl_enable_tbl;
 670         pcr->sd_pull_ctl_disable_tbl = rts5260_sd_pull_ctl_disable_tbl;
 671         pcr->ms_pull_ctl_enable_tbl = rts5260_ms_pull_ctl_enable_tbl;
 672         pcr->ms_pull_ctl_disable_tbl = rts5260_ms_pull_ctl_disable_tbl;
 673
 674         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 675
 676         pcr->ops = &rts5260_pcr_ops;
 677
 678         option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
 679                                 | LTR_L1SS_PWR_GATE_EN);
 680         option->ltr_en = true;
 681
 682         /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
 683         option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
 684         option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
 685         option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
 686         option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
 687         option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
 688         option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 689         option->ltr_l1off_snooze_sspwrgate =
 690                 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
 691
 692         option->ocp_en = 1;
 693         if (option->ocp_en)
 694                 hw_param->interrupt_en |= SD_OC_INT_EN;
 695         hw_param->ocp_glitch =  SD_OCP_GLITCH_100U | SDVIO_OCP_GLITCH_800U;
 696         option->sd_400mA_ocp_thd = RTS5260_DVCC_OCP_THD_550;
 697         option->sd_800mA_ocp_thd = RTS5260_DVCC_OCP_THD_970;
 698 }