drivers/misc/cardreader/rts5249.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Driver for Realtek PCI-Express card reader
   3  *
   4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Wei WANG <wei_wang@realsil.com.cn>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/delay.h>
  12 #include <linux/rtsx_pci.h>
  13
  14 #include "rtsx_pcr.h"
  15
  16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  17 {
  18         u8 val;
  19
  20         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  21         return val & 0x0F;
  22 }
  23
  24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  25 {
  26         u8 driving_3v3[4][3] = {
  27                 {0x11, 0x11, 0x18},
  28                 {0x55, 0x55, 0x5C},
  29                 {0xFF, 0xFF, 0xFF},
  30                 {0x96, 0x96, 0x96},
  31         };
  32         u8 driving_1v8[4][3] = {
  33                 {0xC4, 0xC4, 0xC4},
  34                 {0x3C, 0x3C, 0x3C},
  35                 {0xFE, 0xFE, 0xFE},
  36                 {0xB3, 0xB3, 0xB3},
  37         };
  38         u8 (*driving)[3], drive_sel;
  39
  40         if (voltage == OUTPUT_3V3) {
  41                 driving = driving_3v3;
  42                 drive_sel = pcr->sd30_drive_sel_3v3;
  43         } else {
  44                 driving = driving_1v8;
  45                 drive_sel = pcr->sd30_drive_sel_1v8;
  46         }
  47
  48         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  49                         0xFF, driving[drive_sel][0]);
  50         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  51                         0xFF, driving[drive_sel][1]);
  52         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  53                         0xFF, driving[drive_sel][2]);
  54 }
  55
  56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
  57 {
  58         struct pci_dev *pdev = pcr->pci;
  59         u32 reg;
  60
  61         pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  62         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  63
  64         if (!rtsx_vendor_setting_valid(reg)) {
  65                 pcr_dbg(pcr, "skip fetch vendor setting\n");
  66                 return;
  67         }
  68
  69         pcr->aspm_en = rtsx_reg_to_aspm(reg);
  70         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  71         pcr->card_drive_sel &= 0x3F;
  72         pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  73
  74         pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  75         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  76         if (rtsx_check_mmc_support(reg))
  77                 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  78         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  79         if (rtsx_reg_check_reverse_socket(reg))
  80                 pcr->flags |= PCR_REVERSE_SOCKET;
  81 }
  82
  83 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
  84 {
  85         struct pci_dev *pdev = pcr->pci;
  86         int l1ss;
  87         struct rtsx_cr_option *option = &(pcr->option);
  88         u32 lval;
  89
  90         l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
  91         if (!l1ss)
  92                 return;
  93
  94         pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
  95
  96         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
  97                 if (0 == (lval & 0x0F))
  98                         rtsx_pci_enable_oobs_polling(pcr);
  99                 else
 100                         rtsx_pci_disable_oobs_polling(pcr);
 101         }
 102
 103
 104         if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
 105                 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
 106
 107         if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
 108                 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
 109
 110         if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
 111                 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
 112
 113         if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
 114                 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
 115
 116         if (option->ltr_en) {
 117                 u16 val;
 118
 119                 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
 120                 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
 121                         option->ltr_enabled = true;
 122                         option->ltr_active = true;
 123                         rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
 124                 } else {
 125                         option->ltr_enabled = false;
 126                 }
 127         }
 128 }
 129
 130 static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
 131 {
 132         struct rtsx_cr_option *option = &(pcr->option);
 133
 134         if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
 135                                 | PM_L1_1_EN | PM_L1_2_EN))
 136                 option->force_clkreq_0 = false;
 137         else
 138                 option->force_clkreq_0 = true;
 139
 140         return 0;
 141 }
 142
 143 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
 144 {
 145         u8 cnt, sv;
 146         u16 j = 0;
 147         u8 tmp;
 148         u8 val;
 149         int i;
 150
 151         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 152                                 REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR);
 153         udelay(1);
 154
 155         pcr_dbg(pcr, "Enable efuse por!");
 156         pcr_dbg(pcr, "save efuse to autoload");
 157
 158         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
 159         rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
 160                                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
 161         /* Wait transfer end */
 162         for (j = 0; j < 1024; j++) {
 163                 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
 164                 if ((tmp & 0x80) == 0)
 165                         break;
 166         }
 167         rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
 168         cnt = val & 0x0F;
 169         sv = val & 0x10;
 170
 171         if (sv) {
 172                 for (i = 0; i < 4; i++) {
 173                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
 174                                 REG_EFUSE_ADD_MASK, 0x04 + i);
 175                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
 176                                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
 177                         /* Wait transfer end */
 178                         for (j = 0; j < 1024; j++) {
 179                                 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
 180                                 if ((tmp & 0x80) == 0)
 181                                         break;
 182                         }
 183                         rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
 184                         rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
 185                 }
 186         } else {
 187                 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
 188                 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
 189                 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
 190                 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
 191         }
 192
 193         for (i = 0; i < cnt * 4; i++) {
 194                 if (sv)
 195                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
 196                                 REG_EFUSE_ADD_MASK, 0x08 + i);
 197                 else
 198                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
 199                                 REG_EFUSE_ADD_MASK, 0x04 + i);
 200                 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
 201                                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
 202                 /* Wait transfer end */
 203                 for (j = 0; j < 1024; j++) {
 204                         rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
 205                         if ((tmp & 0x80) == 0)
 206                                 break;
 207                 }
 208                 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
 209                 rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
 210         }
 211         rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
 212         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 213                 REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS);
 214         pcr_dbg(pcr, "Disable efuse por!");
 215 }
 216
 217 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
 218 {
 219         u8 val;
 220
 221         rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
 222         if (val & 0x02) {
 223                 rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
 224                 if (val & RTS525A_LOAD_BIOS_FLAG) {
 225                         rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
 226                                 RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG);
 227
 228                         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 229                                 REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON);
 230
 231                         pcr_dbg(pcr, "Power ON efuse!");
 232                         mdelay(1);
 233                         rts52xa_save_content_from_efuse(pcr);
 234                 } else {
 235                         rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
 236                         if (!(val & 0x08))
 237                                 rts52xa_save_content_from_efuse(pcr);
 238                 }
 239         } else {
 240                 pcr_dbg(pcr, "Load from autoload");
 241                 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
 242                 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
 243                 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
 244                 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
 245                 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
 246         }
 247 }
 248
 249 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
 250 {
 251         struct rtsx_cr_option *option = &(pcr->option);
 252
 253         rts5249_init_from_cfg(pcr);
 254         rts5249_init_from_hw(pcr);
 255
 256         rtsx_pci_init_cmd(pcr);
 257
 258         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
 259                 rts52xa_save_content_to_autoload_space(pcr);
 260
 261         /* Rest L1SUB Config */
 262         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
 263         /* Configure GPIO as output */
 264         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
 265         /* Reset ASPM state to default value */
 266         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 267         /* Switch LDO3318 source from DV33 to card_3v3 */
 268         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
 269         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
 270         /* LED shine disabled, set initial shine cycle period */
 271         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
 272         /* Configure driving */
 273         rts5249_fill_driving(pcr, OUTPUT_3V3);
 274         if (pcr->flags & PCR_REVERSE_SOCKET)
 275                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
 276         else
 277                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
 278
 279         rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
 280
 281         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
 282                 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
 283                 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
 284                 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
 285         } else {
 286                 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
 287                 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
 288         }
 289
 290         /*
 291          * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
 292          * to drive low, and we forcibly request clock.
 293          */
 294         if (option->force_clkreq_0)
 295                 rtsx_pci_write_register(pcr, PETXCFG,
 296                         FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
 297         else
 298                 rtsx_pci_write_register(pcr, PETXCFG,
 299                         FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
 300
 301         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
 302         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
 303                 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 304                                 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
 305                 pcr_dbg(pcr, "Power OFF efuse!");
 306         }
 307
 308         return 0;
 309 }
 310
 311 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
 312 {
 313         int err;
 314
 315         err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
 316         if (err < 0)
 317                 return err;
 318
 319         err = rtsx_pci_write_phy_register(pcr, PHY_REV,
 320                         PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
 321                         PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
 322                         PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
 323                         PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
 324                         PHY_REV_STOP_CLKWR);
 325         if (err < 0)
 326                 return err;
 327
 328         msleep(1);
 329
 330         err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
 331                         PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
 332                         PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
 333         if (err < 0)
 334                 return err;
 335
 336         err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
 337                         PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
 338                         PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
 339                         PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
 340         if (err < 0)
 341                 return err;
 342
 343         err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
 344                         PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
 345                         PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
 346                         PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
 347         if (err < 0)
 348                 return err;
 349
 350         err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
 351                         PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
 352                         PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
 353                         PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
 354                         PHY_FLD4_BER_CHK_EN);
 355         if (err < 0)
 356                 return err;
 357         err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
 358                         PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
 359         if (err < 0)
 360                 return err;
 361         err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
 362                         PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
 363         if (err < 0)
 364                 return err;
 365         err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
 366                         PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
 367                         PHY_FLD3_RXDELINK);
 368         if (err < 0)
 369                 return err;
 370
 371         return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
 372                         PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
 373                         PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
 374                         PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
 375 }
 376
 377 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
 378 {
 379         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
 380 }
 381
 382 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
 383 {
 384         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
 385 }
 386
 387 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
 388 {
 389         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
 390 }
 391
 392 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
 393 {
 394         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
 395 }
 396
 397 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
 398 {
 399         int err;
 400         struct rtsx_cr_option *option = &pcr->option;
 401
 402         if (option->ocp_en)
 403                 rtsx_pci_enable_ocp(pcr);
 404
 405         rtsx_pci_init_cmd(pcr);
 406         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 407                         SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
 408         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 409                         LDO3318_PWR_MASK, 0x02);
 410         err = rtsx_pci_send_cmd(pcr, 100);
 411         if (err < 0)
 412                 return err;
 413
 414         msleep(5);
 415
 416         rtsx_pci_init_cmd(pcr);
 417         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 418                         SD_POWER_MASK, SD_VCC_POWER_ON);
 419         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 420                         LDO3318_PWR_MASK, 0x06);
 421         return rtsx_pci_send_cmd(pcr, 100);
 422 }
 423
 424 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
 425 {
 426         struct rtsx_cr_option *option = &pcr->option;
 427
 428         if (option->ocp_en)
 429                 rtsx_pci_disable_ocp(pcr);
 430
 431         rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
 432
 433         rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
 434         return 0;
 435 }
 436
 437 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 438 {
 439         int err;
 440         u16 append;
 441
 442         switch (voltage) {
 443         case OUTPUT_3V3:
 444                 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
 445                         PHY_TUNE_VOLTAGE_3V3);
 446                 if (err < 0)
 447                         return err;
 448                 break;
 449         case OUTPUT_1V8:
 450                 append = PHY_TUNE_D18_1V8;
 451                 if (CHK_PCI_PID(pcr, 0x5249)) {
 452                         err = rtsx_pci_update_phy(pcr, PHY_BACR,
 453                                 PHY_BACR_BASIC_MASK, 0);
 454                         if (err < 0)
 455                                 return err;
 456                         append = PHY_TUNE_D18_1V7;
 457                 }
 458
 459                 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
 460                         append);
 461                 if (err < 0)
 462                         return err;
 463                 break;
 464         default:
 465                 pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
 466                 return -EINVAL;
 467         }
 468
 469         /* set pad drive */
 470         rtsx_pci_init_cmd(pcr);
 471         rts5249_fill_driving(pcr, voltage);
 472         return rtsx_pci_send_cmd(pcr, 100);
 473 }
 474
 475 static const struct pcr_ops rts5249_pcr_ops = {
 476         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 477         .extra_init_hw = rts5249_extra_init_hw,
 478         .optimize_phy = rts5249_optimize_phy,
 479         .turn_on_led = rtsx_base_turn_on_led,
 480         .turn_off_led = rtsx_base_turn_off_led,
 481         .enable_auto_blink = rtsx_base_enable_auto_blink,
 482         .disable_auto_blink = rtsx_base_disable_auto_blink,
 483         .card_power_on = rtsx_base_card_power_on,
 484         .card_power_off = rtsx_base_card_power_off,
 485         .switch_output_voltage = rtsx_base_switch_output_voltage,
 486 };
 487
 488 /* SD Pull Control Enable:
 489  *     SD_DAT[3:0] ==> pull up
 490  *     SD_CD       ==> pull up
 491  *     SD_WP       ==> pull up
 492  *     SD_CMD      ==> pull up
 493  *     SD_CLK      ==> pull down
 494  */
 495 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
 496         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 497         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 498         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 499         RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
 500         0,
 501 };
 502
 503 /* SD Pull Control Disable:
 504  *     SD_DAT[3:0] ==> pull down
 505  *     SD_CD       ==> pull up
 506  *     SD_WP       ==> pull down
 507  *     SD_CMD      ==> pull down
 508  *     SD_CLK      ==> pull down
 509  */
 510 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
 511         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 512         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 513         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 514         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 515         0,
 516 };
 517
 518 /* MS Pull Control Enable:
 519  *     MS CD       ==> pull up
 520  *     others      ==> pull down
 521  */
 522 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
 523         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 524         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 525         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 526         0,
 527 };
 528
 529 /* MS Pull Control Disable:
 530  *     MS CD       ==> pull up
 531  *     others      ==> pull down
 532  */
 533 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
 534         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 535         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 536         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 537         0,
 538 };
 539
 540 void rts5249_init_params(struct rtsx_pcr *pcr)
 541 {
 542         struct rtsx_cr_option *option = &(pcr->option);
 543
 544         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 545         pcr->num_slots = 2;
 546         pcr->ops = &rts5249_pcr_ops;
 547
 548         pcr->flags = 0;
 549         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 550         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 551         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 552         pcr->aspm_en = ASPM_L1_EN;
 553         pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
 554         pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
 555
 556         pcr->ic_version = rts5249_get_ic_version(pcr);
 557         pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
 558         pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
 559         pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
 560         pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
 561
 562         pcr->reg_pm_ctrl3 = PM_CTRL3;
 563
 564         option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
 565                                 | LTR_L1SS_PWR_GATE_EN);
 566         option->ltr_en = true;
 567
 568         /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
 569         option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
 570         option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
 571         option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
 572         option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
 573         option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
 574         option->ltr_l1off_snooze_sspwrgate =
 575                 LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
 576 }
 577
 578 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
 579 {
 580         addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
 581
 582         return __rtsx_pci_write_phy_register(pcr, addr, val);
 583 }
 584
 585 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 586 {
 587         addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
 588
 589         return __rtsx_pci_read_phy_register(pcr, addr, val);
 590 }
 591
 592 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
 593 {
 594         int err;
 595
 596         err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 597                 D3_DELINK_MODE_EN, 0x00);
 598         if (err < 0)
 599                 return err;
 600
 601         rtsx_pci_write_phy_register(pcr, PHY_PCR,
 602                 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
 603                 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
 604         rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
 605                 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
 606
 607         if (is_version(pcr, 0x524A, IC_VER_A)) {
 608                 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
 609                         PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
 610                 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
 611                         PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
 612                         PHY_SSCCR2_TIME2_WIDTH);
 613                 rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
 614                         PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
 615                         PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
 616                 rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
 617                         PHY_ANA1D_DEBUG_ADDR);
 618                 rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
 619                         PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
 620                         PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
 621                         PHY_DIG1E_RCLK_TX_EN_KEEP |
 622                         PHY_DIG1E_RCLK_TX_TERM_KEEP |
 623                         PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
 624                         PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
 625                         PHY_DIG1E_RX_EN_KEEP);
 626         }
 627
 628         rtsx_pci_write_phy_register(pcr, PHY_ANA08,
 629                 PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
 630                 PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
 631
 632         return 0;
 633 }
 634
 635 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
 636 {
 637         rts5249_extra_init_hw(pcr);
 638
 639         rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
 640                 FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
 641         rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
 642         rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
 643                 LDO_VCC_LMT_EN);
 644         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 645         if (is_version(pcr, 0x524A, IC_VER_A)) {
 646                 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
 647                         LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
 648                 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 649                         LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
 650                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 651                         LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
 652                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 653                         LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
 654                 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
 655                         LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
 656                 rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
 657                         SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
 658         }
 659
 660         return 0;
 661 }
 662
 663 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
 664 {
 665         struct rtsx_cr_option *option = &(pcr->option);
 666
 667         u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
 668         int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
 669         int aspm_L1_1, aspm_L1_2;
 670         u8 val = 0;
 671
 672         aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
 673         aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
 674
 675         if (active) {
 676                 /* Run, latency: 60us */
 677                 if (aspm_L1_1)
 678                         val = option->ltr_l1off_snooze_sspwrgate;
 679         } else {
 680                 /* L1off, latency: 300us */
 681                 if (aspm_L1_2)
 682                         val = option->ltr_l1off_sspwrgate;
 683         }
 684
 685         if (aspm_L1_1 || aspm_L1_2) {
 686                 if (rtsx_check_dev_flag(pcr,
 687                                         LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
 688                         if (card_exist)
 689                                 val &= ~L1OFF_MBIAS2_EN_5250;
 690                         else
 691                                 val |= L1OFF_MBIAS2_EN_5250;
 692                 }
 693         }
 694         rtsx_set_l1off_sub(pcr, val);
 695 }
 696
 697 static const struct pcr_ops rts524a_pcr_ops = {
 698         .write_phy = rts524a_write_phy,
 699         .read_phy = rts524a_read_phy,
 700         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 701         .extra_init_hw = rts524a_extra_init_hw,
 702         .optimize_phy = rts524a_optimize_phy,
 703         .turn_on_led = rtsx_base_turn_on_led,
 704         .turn_off_led = rtsx_base_turn_off_led,
 705         .enable_auto_blink = rtsx_base_enable_auto_blink,
 706         .disable_auto_blink = rtsx_base_disable_auto_blink,
 707         .card_power_on = rtsx_base_card_power_on,
 708         .card_power_off = rtsx_base_card_power_off,
 709         .switch_output_voltage = rtsx_base_switch_output_voltage,
 710         .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
 711 };
 712
 713 void rts524a_init_params(struct rtsx_pcr *pcr)
 714 {
 715         rts5249_init_params(pcr);
 716         pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
 717         pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 718         pcr->option.ltr_l1off_snooze_sspwrgate =
 719                 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
 720
 721         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 722         pcr->ops = &rts524a_pcr_ops;
 723
 724         pcr->option.ocp_en = 1;
 725         if (pcr->option.ocp_en)
 726                 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
 727         pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
 728         pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
 729
 730 }
 731
 732 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
 733 {
 734         rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 735                 LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
 736         return rtsx_base_card_power_on(pcr, card);
 737 }
 738
 739 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 740 {
 741         switch (voltage) {
 742         case OUTPUT_3V3:
 743                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 744                         LDO_D3318_MASK, LDO_D3318_33V);
 745                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
 746                 break;
 747         case OUTPUT_1V8:
 748                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 749                         LDO_D3318_MASK, LDO_D3318_18V);
 750                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
 751                         SD_IO_USING_1V8);
 752                 break;
 753         default:
 754                 return -EINVAL;
 755         }
 756
 757         rtsx_pci_init_cmd(pcr);
 758         rts5249_fill_driving(pcr, voltage);
 759         return rtsx_pci_send_cmd(pcr, 100);
 760 }
 761
 762 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
 763 {
 764         int err;
 765
 766         err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 767                 D3_DELINK_MODE_EN, 0x00);
 768         if (err < 0)
 769                 return err;
 770
 771         rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
 772                 _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
 773                 _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
 774                 _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
 775
 776         rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
 777                 _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
 778                 _PHY_CMU_DEBUG_EN);
 779
 780         if (is_version(pcr, 0x525A, IC_VER_A))
 781                 rtsx_pci_write_phy_register(pcr, _PHY_REV0,
 782                         _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
 783                         _PHY_REV0_CDR_RX_IDLE_BYPASS);
 784
 785         return 0;
 786 }
 787
 788 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
 789 {
 790         rts5249_extra_init_hw(pcr);
 791
 792         rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
 793
 794         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 795         if (is_version(pcr, 0x525A, IC_VER_A)) {
 796                 rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
 797                         L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
 798                 rtsx_pci_write_register(pcr, RREF_CFG,
 799                         RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
 800                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 801                         LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
 802                 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
 803                         LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
 804                 rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
 805                         LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
 806                 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
 807                         LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
 808                 rtsx_pci_write_register(pcr, OOBS_CONFIG,
 809                         OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
 810         }
 811
 812         return 0;
 813 }
 814
 815 static const struct pcr_ops rts525a_pcr_ops = {
 816         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 817         .extra_init_hw = rts525a_extra_init_hw,
 818         .optimize_phy = rts525a_optimize_phy,
 819         .turn_on_led = rtsx_base_turn_on_led,
 820         .turn_off_led = rtsx_base_turn_off_led,
 821         .enable_auto_blink = rtsx_base_enable_auto_blink,
 822         .disable_auto_blink = rtsx_base_disable_auto_blink,
 823         .card_power_on = rts525a_card_power_on,
 824         .card_power_off = rtsx_base_card_power_off,
 825         .switch_output_voltage = rts525a_switch_output_voltage,
 826         .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
 827 };
 828
 829 void rts525a_init_params(struct rtsx_pcr *pcr)
 830 {
 831         rts5249_init_params(pcr);
 832         pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
 833         pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 834         pcr->option.ltr_l1off_snooze_sspwrgate =
 835                 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
 836
 837         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 838         pcr->ops = &rts525a_pcr_ops;
 839
 840         pcr->option.ocp_en = 1;
 841         if (pcr->option.ocp_en)
 842                 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
 843         pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
 844         pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;
 845 }