drivers/misc/cardreader/rts5249.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Driver for Realtek PCI-Express card reader
   3  *
   4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Wei WANG <wei_wang@realsil.com.cn>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/delay.h>
  12 #include <linux/rtsx_pci.h>
  13
  14 #include "rtsx_pcr.h"
  15
  16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  17 {
  18         u8 val;
  19
  20         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  21         return val & 0x0F;
  22 }
  23
  24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  25 {
  26         u8 driving_3v3[4][3] = {
  27                 {0x11, 0x11, 0x18},
  28                 {0x55, 0x55, 0x5C},
  29                 {0xFF, 0xFF, 0xFF},
  30                 {0x96, 0x96, 0x96},
  31         };
  32         u8 driving_1v8[4][3] = {
  33                 {0xC4, 0xC4, 0xC4},
  34                 {0x3C, 0x3C, 0x3C},
  35                 {0xFE, 0xFE, 0xFE},
  36                 {0xB3, 0xB3, 0xB3},
  37         };
  38         u8 (*driving)[3], drive_sel;
  39
  40         if (voltage == OUTPUT_3V3) {
  41                 driving = driving_3v3;
  42                 drive_sel = pcr->sd30_drive_sel_3v3;
  43         } else {
  44                 driving = driving_1v8;
  45                 drive_sel = pcr->sd30_drive_sel_1v8;
  46         }
  47
  48         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  49                         0xFF, driving[drive_sel][0]);
  50         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  51                         0xFF, driving[drive_sel][1]);
  52         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  53                         0xFF, driving[drive_sel][2]);
  54 }
  55
  56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
  57 {
  58         struct pci_dev *pdev = pcr->pci;
  59         u32 reg;
  60
  61         pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  62         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  63
  64         if (!rtsx_vendor_setting_valid(reg)) {
  65                 pcr_dbg(pcr, "skip fetch vendor setting\n");
  66                 return;
  67         }
  68
  69         pcr->aspm_en = rtsx_reg_to_aspm(reg);
  70         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  71         pcr->card_drive_sel &= 0x3F;
  72         pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  73
  74         pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  75         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  76         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  77         if (rtsx_reg_check_reverse_socket(reg))
  78                 pcr->flags |= PCR_REVERSE_SOCKET;
  79 }
  80
  81 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  82 {
  83         /* Set relink_time to 0 */
  84         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
  85         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
  86         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
  87
  88         if (pm_state == HOST_ENTER_S3)
  89                 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
  90                         D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
  91
  92         rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
  93 }
  94
  95 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
  96 {
  97         struct pci_dev *pdev = pcr->pci;
  98         int l1ss;
  99         struct rtsx_cr_option *option = &(pcr->option);
 100         u32 lval;
 101
 102         l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
 103         if (!l1ss)
 104                 return;
 105
 106         pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
 107
 108         if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
 109                 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
 110
 111         if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
 112                 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
 113
 114         if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
 115                 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
 116
 117         if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
 118                 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
 119
 120         if (option->ltr_en) {
 121                 u16 val;
 122
 123                 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
 124                 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
 125                         option->ltr_enabled = true;
 126                         option->ltr_active = true;
 127                         rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
 128                 } else {
 129                         option->ltr_enabled = false;
 130                 }
 131         }
 132 }
 133
 134 static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
 135 {
 136         struct rtsx_cr_option *option = &(pcr->option);
 137
 138         if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
 139                                 | PM_L1_1_EN | PM_L1_2_EN))
 140                 option->force_clkreq_0 = false;
 141         else
 142                 option->force_clkreq_0 = true;
 143
 144         return 0;
 145 }
 146
 147 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
 148 {
 149         struct rtsx_cr_option *option = &(pcr->option);
 150
 151         rts5249_init_from_cfg(pcr);
 152         rts5249_init_from_hw(pcr);
 153
 154         rtsx_pci_init_cmd(pcr);
 155
 156         /* Rest L1SUB Config */
 157         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
 158         /* Configure GPIO as output */
 159         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
 160         /* Reset ASPM state to default value */
 161         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 162         /* Switch LDO3318 source from DV33 to card_3v3 */
 163         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
 164         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
 165         /* LED shine disabled, set initial shine cycle period */
 166         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
 167         /* Configure driving */
 168         rts5249_fill_driving(pcr, OUTPUT_3V3);
 169         if (pcr->flags & PCR_REVERSE_SOCKET)
 170                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
 171         else
 172                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
 173
 174         /*
 175          * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
 176          * to drive low, and we forcibly request clock.
 177          */
 178         if (option->force_clkreq_0)
 179                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
 180                         FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
 181         else
 182                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
 183                         FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
 184
 185         return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
 186 }
 187
 188 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
 189 {
 190         int err;
 191
 192         err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
 193         if (err < 0)
 194                 return err;
 195
 196         err = rtsx_pci_write_phy_register(pcr, PHY_REV,
 197                         PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
 198                         PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
 199                         PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
 200                         PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
 201                         PHY_REV_STOP_CLKWR);
 202         if (err < 0)
 203                 return err;
 204
 205         msleep(1);
 206
 207         err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
 208                         PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
 209                         PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
 210         if (err < 0)
 211                 return err;
 212
 213         err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
 214                         PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
 215                         PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
 216                         PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
 217         if (err < 0)
 218                 return err;
 219
 220         err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
 221                         PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
 222                         PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
 223                         PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
 224         if (err < 0)
 225                 return err;
 226
 227         err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
 228                         PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
 229                         PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
 230                         PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
 231                         PHY_FLD4_BER_CHK_EN);
 232         if (err < 0)
 233                 return err;
 234         err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
 235                         PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
 236         if (err < 0)
 237                 return err;
 238         err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
 239                         PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
 240         if (err < 0)
 241                 return err;
 242         err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
 243                         PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
 244                         PHY_FLD3_RXDELINK);
 245         if (err < 0)
 246                 return err;
 247
 248         return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
 249                         PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
 250                         PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
 251                         PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
 252 }
 253
 254 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
 255 {
 256         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
 257 }
 258
 259 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
 260 {
 261         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
 262 }
 263
 264 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
 265 {
 266         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
 267 }
 268
 269 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
 270 {
 271         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
 272 }
 273
 274 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
 275 {
 276         int err;
 277         struct rtsx_cr_option *option = &pcr->option;
 278
 279         if (option->ocp_en)
 280                 rtsx_pci_enable_ocp(pcr);
 281
 282         rtsx_pci_init_cmd(pcr);
 283         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 284                         SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
 285         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 286                         LDO3318_PWR_MASK, 0x02);
 287         err = rtsx_pci_send_cmd(pcr, 100);
 288         if (err < 0)
 289                 return err;
 290
 291         msleep(5);
 292
 293         rtsx_pci_init_cmd(pcr);
 294         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 295                         SD_POWER_MASK, SD_VCC_POWER_ON);
 296         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 297                         LDO3318_PWR_MASK, 0x06);
 298         return rtsx_pci_send_cmd(pcr, 100);
 299 }
 300
 301 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
 302 {
 303         struct rtsx_cr_option *option = &pcr->option;
 304
 305         if (option->ocp_en)
 306                 rtsx_pci_disable_ocp(pcr);
 307
 308         rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
 309
 310         rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
 311         return 0;
 312 }
 313
 314 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 315 {
 316         int err;
 317         u16 append;
 318
 319         switch (voltage) {
 320         case OUTPUT_3V3:
 321                 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
 322                         PHY_TUNE_VOLTAGE_3V3);
 323                 if (err < 0)
 324                         return err;
 325                 break;
 326         case OUTPUT_1V8:
 327                 append = PHY_TUNE_D18_1V8;
 328                 if (CHK_PCI_PID(pcr, 0x5249)) {
 329                         err = rtsx_pci_update_phy(pcr, PHY_BACR,
 330                                 PHY_BACR_BASIC_MASK, 0);
 331                         if (err < 0)
 332                                 return err;
 333                         append = PHY_TUNE_D18_1V7;
 334                 }
 335
 336                 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
 337                         append);
 338                 if (err < 0)
 339                         return err;
 340                 break;
 341         default:
 342                 pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
 343                 return -EINVAL;
 344         }
 345
 346         /* set pad drive */
 347         rtsx_pci_init_cmd(pcr);
 348         rts5249_fill_driving(pcr, voltage);
 349         return rtsx_pci_send_cmd(pcr, 100);
 350 }
 351
 352 static const struct pcr_ops rts5249_pcr_ops = {
 353         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 354         .extra_init_hw = rts5249_extra_init_hw,
 355         .optimize_phy = rts5249_optimize_phy,
 356         .turn_on_led = rtsx_base_turn_on_led,
 357         .turn_off_led = rtsx_base_turn_off_led,
 358         .enable_auto_blink = rtsx_base_enable_auto_blink,
 359         .disable_auto_blink = rtsx_base_disable_auto_blink,
 360         .card_power_on = rtsx_base_card_power_on,
 361         .card_power_off = rtsx_base_card_power_off,
 362         .switch_output_voltage = rtsx_base_switch_output_voltage,
 363         .force_power_down = rtsx_base_force_power_down,
 364 };
 365
 366 /* SD Pull Control Enable:
 367  *     SD_DAT[3:0] ==> pull up
 368  *     SD_CD       ==> pull up
 369  *     SD_WP       ==> pull up
 370  *     SD_CMD      ==> pull up
 371  *     SD_CLK      ==> pull down
 372  */
 373 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
 374         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 375         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 376         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 377         RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
 378         0,
 379 };
 380
 381 /* SD Pull Control Disable:
 382  *     SD_DAT[3:0] ==> pull down
 383  *     SD_CD       ==> pull up
 384  *     SD_WP       ==> pull down
 385  *     SD_CMD      ==> pull down
 386  *     SD_CLK      ==> pull down
 387  */
 388 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
 389         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 390         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 391         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 392         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 393         0,
 394 };
 395
 396 /* MS Pull Control Enable:
 397  *     MS CD       ==> pull up
 398  *     others      ==> pull down
 399  */
 400 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
 401         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 402         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 403         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 404         0,
 405 };
 406
 407 /* MS Pull Control Disable:
 408  *     MS CD       ==> pull up
 409  *     others      ==> pull down
 410  */
 411 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
 412         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 413         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 414         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 415         0,
 416 };
 417
 418 void rts5249_init_params(struct rtsx_pcr *pcr)
 419 {
 420         struct rtsx_cr_option *option = &(pcr->option);
 421
 422         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 423         pcr->num_slots = 2;
 424         pcr->ops = &rts5249_pcr_ops;
 425
 426         pcr->flags = 0;
 427         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 428         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 429         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 430         pcr->aspm_en = ASPM_L1_EN;
 431         pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
 432         pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
 433
 434         pcr->ic_version = rts5249_get_ic_version(pcr);
 435         pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
 436         pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
 437         pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
 438         pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
 439
 440         pcr->reg_pm_ctrl3 = PM_CTRL3;
 441
 442         option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
 443                                 | LTR_L1SS_PWR_GATE_EN);
 444         option->ltr_en = true;
 445
 446         /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
 447         option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
 448         option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
 449         option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
 450         option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
 451         option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
 452         option->ltr_l1off_snooze_sspwrgate =
 453                 LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
 454 }
 455
 456 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
 457 {
 458         addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
 459
 460         return __rtsx_pci_write_phy_register(pcr, addr, val);
 461 }
 462
 463 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 464 {
 465         addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
 466
 467         return __rtsx_pci_read_phy_register(pcr, addr, val);
 468 }
 469
 470 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
 471 {
 472         int err;
 473
 474         err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 475                 D3_DELINK_MODE_EN, 0x00);
 476         if (err < 0)
 477                 return err;
 478
 479         rtsx_pci_write_phy_register(pcr, PHY_PCR,
 480                 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
 481                 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
 482         rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
 483                 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
 484
 485         if (is_version(pcr, 0x524A, IC_VER_A)) {
 486                 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
 487                         PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
 488                 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
 489                         PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
 490                         PHY_SSCCR2_TIME2_WIDTH);
 491                 rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
 492                         PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
 493                         PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
 494                 rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
 495                         PHY_ANA1D_DEBUG_ADDR);
 496                 rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
 497                         PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
 498                         PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
 499                         PHY_DIG1E_RCLK_TX_EN_KEEP |
 500                         PHY_DIG1E_RCLK_TX_TERM_KEEP |
 501                         PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
 502                         PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
 503                         PHY_DIG1E_RX_EN_KEEP);
 504         }
 505
 506         rtsx_pci_write_phy_register(pcr, PHY_ANA08,
 507                 PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
 508                 PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
 509
 510         return 0;
 511 }
 512
 513 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
 514 {
 515         rts5249_extra_init_hw(pcr);
 516
 517         rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
 518                 FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
 519         rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
 520         rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
 521                 LDO_VCC_LMT_EN);
 522         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 523         if (is_version(pcr, 0x524A, IC_VER_A)) {
 524                 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
 525                         LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
 526                 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 527                         LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
 528                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 529                         LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
 530                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 531                         LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
 532                 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
 533                         LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
 534                 rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
 535                         SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
 536         }
 537
 538         return 0;
 539 }
 540
 541 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
 542 {
 543         struct rtsx_cr_option *option = &(pcr->option);
 544
 545         u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
 546         int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
 547         int aspm_L1_1, aspm_L1_2;
 548         u8 val = 0;
 549
 550         aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
 551         aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
 552
 553         if (active) {
 554                 /* Run, latency: 60us */
 555                 if (aspm_L1_1)
 556                         val = option->ltr_l1off_snooze_sspwrgate;
 557         } else {
 558                 /* L1off, latency: 300us */
 559                 if (aspm_L1_2)
 560                         val = option->ltr_l1off_sspwrgate;
 561         }
 562
 563         if (aspm_L1_1 || aspm_L1_2) {
 564                 if (rtsx_check_dev_flag(pcr,
 565                                         LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
 566                         if (card_exist)
 567                                 val &= ~L1OFF_MBIAS2_EN_5250;
 568                         else
 569                                 val |= L1OFF_MBIAS2_EN_5250;
 570                 }
 571         }
 572         rtsx_set_l1off_sub(pcr, val);
 573 }
 574
 575 static const struct pcr_ops rts524a_pcr_ops = {
 576         .write_phy = rts524a_write_phy,
 577         .read_phy = rts524a_read_phy,
 578         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 579         .extra_init_hw = rts524a_extra_init_hw,
 580         .optimize_phy = rts524a_optimize_phy,
 581         .turn_on_led = rtsx_base_turn_on_led,
 582         .turn_off_led = rtsx_base_turn_off_led,
 583         .enable_auto_blink = rtsx_base_enable_auto_blink,
 584         .disable_auto_blink = rtsx_base_disable_auto_blink,
 585         .card_power_on = rtsx_base_card_power_on,
 586         .card_power_off = rtsx_base_card_power_off,
 587         .switch_output_voltage = rtsx_base_switch_output_voltage,
 588         .force_power_down = rtsx_base_force_power_down,
 589         .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
 590 };
 591
 592 void rts524a_init_params(struct rtsx_pcr *pcr)
 593 {
 594         rts5249_init_params(pcr);
 595         pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
 596         pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 597         pcr->option.ltr_l1off_snooze_sspwrgate =
 598                 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
 599
 600         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 601         pcr->ops = &rts524a_pcr_ops;
 602
 603         pcr->option.ocp_en = 1;
 604         if (pcr->option.ocp_en)
 605                 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
 606         pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
 607         pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
 608
 609 }
 610
 611 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
 612 {
 613         rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 614                 LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
 615         return rtsx_base_card_power_on(pcr, card);
 616 }
 617
 618 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 619 {
 620         switch (voltage) {
 621         case OUTPUT_3V3:
 622                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 623                         LDO_D3318_MASK, LDO_D3318_33V);
 624                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
 625                 break;
 626         case OUTPUT_1V8:
 627                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 628                         LDO_D3318_MASK, LDO_D3318_18V);
 629                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
 630                         SD_IO_USING_1V8);
 631                 break;
 632         default:
 633                 return -EINVAL;
 634         }
 635
 636         rtsx_pci_init_cmd(pcr);
 637         rts5249_fill_driving(pcr, voltage);
 638         return rtsx_pci_send_cmd(pcr, 100);
 639 }
 640
 641 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
 642 {
 643         int err;
 644
 645         err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 646                 D3_DELINK_MODE_EN, 0x00);
 647         if (err < 0)
 648                 return err;
 649
 650         rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
 651                 _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
 652                 _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
 653                 _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
 654
 655         rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
 656                 _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
 657                 _PHY_CMU_DEBUG_EN);
 658
 659         if (is_version(pcr, 0x525A, IC_VER_A))
 660                 rtsx_pci_write_phy_register(pcr, _PHY_REV0,
 661                         _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
 662                         _PHY_REV0_CDR_RX_IDLE_BYPASS);
 663
 664         return 0;
 665 }
 666
 667 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
 668 {
 669         rts5249_extra_init_hw(pcr);
 670
 671         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 672         if (is_version(pcr, 0x525A, IC_VER_A)) {
 673                 rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
 674                         L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
 675                 rtsx_pci_write_register(pcr, RREF_CFG,
 676                         RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
 677                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 678                         LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
 679                 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
 680                         LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
 681                 rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
 682                         LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
 683                 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
 684                         LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
 685                 rtsx_pci_write_register(pcr, OOBS_CONFIG,
 686                         OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
 687         }
 688
 689         return 0;
 690 }
 691
 692 static const struct pcr_ops rts525a_pcr_ops = {
 693         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 694         .extra_init_hw = rts525a_extra_init_hw,
 695         .optimize_phy = rts525a_optimize_phy,
 696         .turn_on_led = rtsx_base_turn_on_led,
 697         .turn_off_led = rtsx_base_turn_off_led,
 698         .enable_auto_blink = rtsx_base_enable_auto_blink,
 699         .disable_auto_blink = rtsx_base_disable_auto_blink,
 700         .card_power_on = rts525a_card_power_on,
 701         .card_power_off = rtsx_base_card_power_off,
 702         .switch_output_voltage = rts525a_switch_output_voltage,
 703         .force_power_down = rtsx_base_force_power_down,
 704         .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
 705 };
 706
 707 void rts525a_init_params(struct rtsx_pcr *pcr)
 708 {
 709         rts5249_init_params(pcr);
 710         pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
 711         pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 712         pcr->option.ltr_l1off_snooze_sspwrgate =
 713                 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
 714
 715         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 716         pcr->ops = &rts525a_pcr_ops;
 717
 718         pcr->option.ocp_en = 1;
 719         if (pcr->option.ocp_en)
 720                 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
 721         pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
 722         pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;
 723 }