drivers/misc/cardreader/rts5249.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Driver for Realtek PCI-Express card reader
   3  *
   4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Wei WANG <wei_wang@realsil.com.cn>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/delay.h>
  12 #include <linux/rtsx_pci.h>
  13
  14 #include "rtsx_pcr.h"
  15
  16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  17 {
  18         u8 val;
  19
  20         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  21         return val & 0x0F;
  22 }
  23
  24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  25 {
  26         u8 driving_3v3[4][3] = {
  27                 {0x11, 0x11, 0x18},
  28                 {0x55, 0x55, 0x5C},
  29                 {0xFF, 0xFF, 0xFF},
  30                 {0x96, 0x96, 0x96},
  31         };
  32         u8 driving_1v8[4][3] = {
  33                 {0xC4, 0xC4, 0xC4},
  34                 {0x3C, 0x3C, 0x3C},
  35                 {0xFE, 0xFE, 0xFE},
  36                 {0xB3, 0xB3, 0xB3},
  37         };
  38         u8 (*driving)[3], drive_sel;
  39
  40         if (voltage == OUTPUT_3V3) {
  41                 driving = driving_3v3;
  42                 drive_sel = pcr->sd30_drive_sel_3v3;
  43         } else {
  44                 driving = driving_1v8;
  45                 drive_sel = pcr->sd30_drive_sel_1v8;
  46         }
  47
  48         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  49                         0xFF, driving[drive_sel][0]);
  50         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  51                         0xFF, driving[drive_sel][1]);
  52         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  53                         0xFF, driving[drive_sel][2]);
  54 }
  55
  56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
  57 {
  58         struct pci_dev *pdev = pcr->pci;
  59         u32 reg;
  60
  61         pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  62         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  63
  64         if (!rtsx_vendor_setting_valid(reg)) {
  65                 pcr_dbg(pcr, "skip fetch vendor setting\n");
  66                 return;
  67         }
  68
  69         pcr->aspm_en = rtsx_reg_to_aspm(reg);
  70         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  71         pcr->card_drive_sel &= 0x3F;
  72         pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  73
  74         pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  75         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  76
  77         pcr->rtd3_en = rtsx_reg_to_rtd3_uhsii(reg);
  78
  79         if (rtsx_check_mmc_support(reg))
  80                 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  81         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  82         if (rtsx_reg_check_reverse_socket(reg))
  83                 pcr->flags |= PCR_REVERSE_SOCKET;
  84 }
  85
  86 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
  87 {
  88         struct pci_dev *pdev = pcr->pci;
  89         int l1ss;
  90         struct rtsx_cr_option *option = &(pcr->option);
  91         u32 lval;
  92
  93         l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
  94         if (!l1ss)
  95                 return;
  96
  97         pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
  98
  99         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
 100                 if (0 == (lval & 0x0F))
 101                         rtsx_pci_enable_oobs_polling(pcr);
 102                 else
 103                         rtsx_pci_disable_oobs_polling(pcr);
 104         }
 105
 106
 107         if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
 108                 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
 109
 110         if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
 111                 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
 112
 113         if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
 114                 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
 115
 116         if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
 117                 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
 118
 119         if (option->ltr_en) {
 120                 u16 val;
 121
 122                 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
 123                 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
 124                         option->ltr_enabled = true;
 125                         option->ltr_active = true;
 126                         rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
 127                 } else {
 128                         option->ltr_enabled = false;
 129                 }
 130         }
 131 }
 132
 133 static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
 134 {
 135         struct rtsx_cr_option *option = &(pcr->option);
 136
 137         if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
 138                                 | PM_L1_1_EN | PM_L1_2_EN))
 139                 option->force_clkreq_0 = false;
 140         else
 141                 option->force_clkreq_0 = true;
 142
 143         return 0;
 144 }
 145
 146 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
 147 {
 148         u8 cnt, sv;
 149         u16 j = 0;
 150         u8 tmp;
 151         u8 val;
 152         int i;
 153
 154         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 155                                 REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR);
 156         udelay(1);
 157
 158         pcr_dbg(pcr, "Enable efuse por!");
 159         pcr_dbg(pcr, "save efuse to autoload");
 160
 161         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
 162         rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
 163                                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
 164         /* Wait transfer end */
 165         for (j = 0; j < 1024; j++) {
 166                 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
 167                 if ((tmp & 0x80) == 0)
 168                         break;
 169         }
 170         rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
 171         cnt = val & 0x0F;
 172         sv = val & 0x10;
 173
 174         if (sv) {
 175                 for (i = 0; i < 4; i++) {
 176                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
 177                                 REG_EFUSE_ADD_MASK, 0x04 + i);
 178                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
 179                                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
 180                         /* Wait transfer end */
 181                         for (j = 0; j < 1024; j++) {
 182                                 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
 183                                 if ((tmp & 0x80) == 0)
 184                                         break;
 185                         }
 186                         rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
 187                         rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
 188                 }
 189         } else {
 190                 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
 191                 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
 192                 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
 193                 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
 194         }
 195
 196         for (i = 0; i < cnt * 4; i++) {
 197                 if (sv)
 198                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
 199                                 REG_EFUSE_ADD_MASK, 0x08 + i);
 200                 else
 201                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
 202                                 REG_EFUSE_ADD_MASK, 0x04 + i);
 203                 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
 204                                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
 205                 /* Wait transfer end */
 206                 for (j = 0; j < 1024; j++) {
 207                         rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
 208                         if ((tmp & 0x80) == 0)
 209                                 break;
 210                 }
 211                 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
 212                 rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
 213         }
 214         rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
 215         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 216                 REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS);
 217         pcr_dbg(pcr, "Disable efuse por!");
 218 }
 219
 220 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
 221 {
 222         u8 val;
 223
 224         rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
 225         if (val & 0x02) {
 226                 rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
 227                 if (val & RTS525A_LOAD_BIOS_FLAG) {
 228                         rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
 229                                 RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG);
 230
 231                         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 232                                 REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON);
 233
 234                         pcr_dbg(pcr, "Power ON efuse!");
 235                         mdelay(1);
 236                         rts52xa_save_content_from_efuse(pcr);
 237                 } else {
 238                         rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
 239                         if (!(val & 0x08))
 240                                 rts52xa_save_content_from_efuse(pcr);
 241                 }
 242         } else {
 243                 pcr_dbg(pcr, "Load from autoload");
 244                 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
 245                 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
 246                 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
 247                 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
 248                 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
 249         }
 250 }
 251
 252 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
 253 {
 254         struct rtsx_cr_option *option = &(pcr->option);
 255
 256         rts5249_init_from_cfg(pcr);
 257         rts5249_init_from_hw(pcr);
 258
 259         rtsx_pci_init_cmd(pcr);
 260
 261         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
 262                 rts52xa_save_content_to_autoload_space(pcr);
 263
 264         /* Rest L1SUB Config */
 265         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
 266         /* Configure GPIO as output */
 267         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
 268         /* Reset ASPM state to default value */
 269         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 270         /* Switch LDO3318 source from DV33 to card_3v3 */
 271         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
 272         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
 273         /* LED shine disabled, set initial shine cycle period */
 274         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
 275         /* Configure driving */
 276         rts5249_fill_driving(pcr, OUTPUT_3V3);
 277         if (pcr->flags & PCR_REVERSE_SOCKET)
 278                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
 279         else
 280                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
 281
 282         rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
 283
 284         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
 285                 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
 286
 287         if (pcr->rtd3_en) {
 288                 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
 289                         rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x01);
 290                         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x30);
 291                 } else {
 292                         rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x01);
 293                         rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x33);
 294                 }
 295         } else {
 296                 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
 297                         rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
 298                         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
 299                 } else {
 300                         rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
 301                         rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
 302                 }
 303         }
 304
 305
 306         /*
 307          * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
 308          * to drive low, and we forcibly request clock.
 309          */
 310         if (option->force_clkreq_0)
 311                 rtsx_pci_write_register(pcr, PETXCFG,
 312                         FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
 313         else
 314                 rtsx_pci_write_register(pcr, PETXCFG,
 315                         FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
 316
 317         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
 318         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
 319                 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 320                                 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
 321                 pcr_dbg(pcr, "Power OFF efuse!");
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
 328 {
 329         int err;
 330
 331         err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
 332         if (err < 0)
 333                 return err;
 334
 335         err = rtsx_pci_write_phy_register(pcr, PHY_REV,
 336                         PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
 337                         PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
 338                         PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
 339                         PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
 340                         PHY_REV_STOP_CLKWR);
 341         if (err < 0)
 342                 return err;
 343
 344         msleep(1);
 345
 346         err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
 347                         PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
 348                         PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
 349         if (err < 0)
 350                 return err;
 351
 352         err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
 353                         PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
 354                         PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
 355                         PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
 356         if (err < 0)
 357                 return err;
 358
 359         err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
 360                         PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
 361                         PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
 362                         PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
 363         if (err < 0)
 364                 return err;
 365
 366         err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
 367                         PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
 368                         PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
 369                         PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
 370                         PHY_FLD4_BER_CHK_EN);
 371         if (err < 0)
 372                 return err;
 373         err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
 374                         PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
 375         if (err < 0)
 376                 return err;
 377         err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
 378                         PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
 379         if (err < 0)
 380                 return err;
 381         err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
 382                         PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
 383                         PHY_FLD3_RXDELINK);
 384         if (err < 0)
 385                 return err;
 386
 387         return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
 388                         PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
 389                         PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
 390                         PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
 391 }
 392
 393 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
 394 {
 395         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
 396 }
 397
 398 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
 399 {
 400         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
 401 }
 402
 403 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
 404 {
 405         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
 406 }
 407
 408 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
 409 {
 410         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
 411 }
 412
 413 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
 414 {
 415         int err;
 416         struct rtsx_cr_option *option = &pcr->option;
 417
 418         if (option->ocp_en)
 419                 rtsx_pci_enable_ocp(pcr);
 420
 421         rtsx_pci_init_cmd(pcr);
 422         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 423                         SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
 424         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 425                         LDO3318_PWR_MASK, 0x02);
 426         err = rtsx_pci_send_cmd(pcr, 100);
 427         if (err < 0)
 428                 return err;
 429
 430         msleep(5);
 431
 432         rtsx_pci_init_cmd(pcr);
 433         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 434                         SD_POWER_MASK, SD_VCC_POWER_ON);
 435         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 436                         LDO3318_PWR_MASK, 0x06);
 437         return rtsx_pci_send_cmd(pcr, 100);
 438 }
 439
 440 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
 441 {
 442         struct rtsx_cr_option *option = &pcr->option;
 443
 444         if (option->ocp_en)
 445                 rtsx_pci_disable_ocp(pcr);
 446
 447         rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
 448
 449         rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
 450         return 0;
 451 }
 452
 453 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 454 {
 455         int err;
 456         u16 append;
 457
 458         switch (voltage) {
 459         case OUTPUT_3V3:
 460                 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
 461                         PHY_TUNE_VOLTAGE_3V3);
 462                 if (err < 0)
 463                         return err;
 464                 break;
 465         case OUTPUT_1V8:
 466                 append = PHY_TUNE_D18_1V8;
 467                 if (CHK_PCI_PID(pcr, 0x5249)) {
 468                         err = rtsx_pci_update_phy(pcr, PHY_BACR,
 469                                 PHY_BACR_BASIC_MASK, 0);
 470                         if (err < 0)
 471                                 return err;
 472                         append = PHY_TUNE_D18_1V7;
 473                 }
 474
 475                 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
 476                         append);
 477                 if (err < 0)
 478                         return err;
 479                 break;
 480         default:
 481                 pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
 482                 return -EINVAL;
 483         }
 484
 485         /* set pad drive */
 486         rtsx_pci_init_cmd(pcr);
 487         rts5249_fill_driving(pcr, voltage);
 488         return rtsx_pci_send_cmd(pcr, 100);
 489 }
 490
 491 static const struct pcr_ops rts5249_pcr_ops = {
 492         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 493         .extra_init_hw = rts5249_extra_init_hw,
 494         .optimize_phy = rts5249_optimize_phy,
 495         .turn_on_led = rtsx_base_turn_on_led,
 496         .turn_off_led = rtsx_base_turn_off_led,
 497         .enable_auto_blink = rtsx_base_enable_auto_blink,
 498         .disable_auto_blink = rtsx_base_disable_auto_blink,
 499         .card_power_on = rtsx_base_card_power_on,
 500         .card_power_off = rtsx_base_card_power_off,
 501         .switch_output_voltage = rtsx_base_switch_output_voltage,
 502 };
 503
 504 /* SD Pull Control Enable:
 505  *     SD_DAT[3:0] ==> pull up
 506  *     SD_CD       ==> pull up
 507  *     SD_WP       ==> pull up
 508  *     SD_CMD      ==> pull up
 509  *     SD_CLK      ==> pull down
 510  */
 511 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
 512         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 513         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 514         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 515         RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
 516         0,
 517 };
 518
 519 /* SD Pull Control Disable:
 520  *     SD_DAT[3:0] ==> pull down
 521  *     SD_CD       ==> pull up
 522  *     SD_WP       ==> pull down
 523  *     SD_CMD      ==> pull down
 524  *     SD_CLK      ==> pull down
 525  */
 526 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
 527         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 528         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 529         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 530         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 531         0,
 532 };
 533
 534 /* MS Pull Control Enable:
 535  *     MS CD       ==> pull up
 536  *     others      ==> pull down
 537  */
 538 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
 539         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 540         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 541         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 542         0,
 543 };
 544
 545 /* MS Pull Control Disable:
 546  *     MS CD       ==> pull up
 547  *     others      ==> pull down
 548  */
 549 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
 550         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 551         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 552         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 553         0,
 554 };
 555
 556 void rts5249_init_params(struct rtsx_pcr *pcr)
 557 {
 558         struct rtsx_cr_option *option = &(pcr->option);
 559
 560         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 561         pcr->num_slots = 2;
 562         pcr->ops = &rts5249_pcr_ops;
 563
 564         pcr->flags = 0;
 565         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 566         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 567         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 568         pcr->aspm_en = ASPM_L1_EN;
 569         pcr->aspm_mode = ASPM_MODE_CFG;
 570         pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
 571         pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
 572
 573         pcr->ic_version = rts5249_get_ic_version(pcr);
 574         pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
 575         pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
 576         pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
 577         pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
 578
 579         pcr->reg_pm_ctrl3 = PM_CTRL3;
 580
 581         option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
 582                                 | LTR_L1SS_PWR_GATE_EN);
 583         option->ltr_en = true;
 584
 585         /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
 586         option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
 587         option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
 588         option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
 589         option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
 590         option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
 591         option->ltr_l1off_snooze_sspwrgate =
 592                 LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
 593 }
 594
 595 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
 596 {
 597         addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
 598
 599         return __rtsx_pci_write_phy_register(pcr, addr, val);
 600 }
 601
 602 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 603 {
 604         addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
 605
 606         return __rtsx_pci_read_phy_register(pcr, addr, val);
 607 }
 608
 609 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
 610 {
 611         int err;
 612
 613         err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 614                 D3_DELINK_MODE_EN, 0x00);
 615         if (err < 0)
 616                 return err;
 617
 618         rtsx_pci_write_phy_register(pcr, PHY_PCR,
 619                 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
 620                 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
 621         rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
 622                 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
 623
 624         if (is_version(pcr, 0x524A, IC_VER_A)) {
 625                 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
 626                         PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
 627                 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
 628                         PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
 629                         PHY_SSCCR2_TIME2_WIDTH);
 630                 rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
 631                         PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
 632                         PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
 633                 rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
 634                         PHY_ANA1D_DEBUG_ADDR);
 635                 rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
 636                         PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
 637                         PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
 638                         PHY_DIG1E_RCLK_TX_EN_KEEP |
 639                         PHY_DIG1E_RCLK_TX_TERM_KEEP |
 640                         PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
 641                         PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
 642                         PHY_DIG1E_RX_EN_KEEP);
 643         }
 644
 645         rtsx_pci_write_phy_register(pcr, PHY_ANA08,
 646                 PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
 647                 PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
 648
 649         return 0;
 650 }
 651
 652 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
 653 {
 654         rts5249_extra_init_hw(pcr);
 655
 656         rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
 657                 FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
 658         rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
 659         rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
 660                 LDO_VCC_LMT_EN);
 661         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 662         if (is_version(pcr, 0x524A, IC_VER_A)) {
 663                 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
 664                         LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
 665                 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 666                         LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
 667                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 668                         LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
 669                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 670                         LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
 671                 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
 672                         LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
 673                 rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
 674                         SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
 675         }
 676
 677         return 0;
 678 }
 679
 680 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
 681 {
 682         struct rtsx_cr_option *option = &(pcr->option);
 683
 684         u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
 685         int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
 686         int aspm_L1_1, aspm_L1_2;
 687         u8 val = 0;
 688
 689         aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
 690         aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
 691
 692         if (active) {
 693                 /* Run, latency: 60us */
 694                 if (aspm_L1_1)
 695                         val = option->ltr_l1off_snooze_sspwrgate;
 696         } else {
 697                 /* L1off, latency: 300us */
 698                 if (aspm_L1_2)
 699                         val = option->ltr_l1off_sspwrgate;
 700         }
 701
 702         if (aspm_L1_1 || aspm_L1_2) {
 703                 if (rtsx_check_dev_flag(pcr,
 704                                         LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
 705                         if (card_exist)
 706                                 val &= ~L1OFF_MBIAS2_EN_5250;
 707                         else
 708                                 val |= L1OFF_MBIAS2_EN_5250;
 709                 }
 710         }
 711         rtsx_set_l1off_sub(pcr, val);
 712 }
 713
 714 static const struct pcr_ops rts524a_pcr_ops = {
 715         .write_phy = rts524a_write_phy,
 716         .read_phy = rts524a_read_phy,
 717         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 718         .extra_init_hw = rts524a_extra_init_hw,
 719         .optimize_phy = rts524a_optimize_phy,
 720         .turn_on_led = rtsx_base_turn_on_led,
 721         .turn_off_led = rtsx_base_turn_off_led,
 722         .enable_auto_blink = rtsx_base_enable_auto_blink,
 723         .disable_auto_blink = rtsx_base_disable_auto_blink,
 724         .card_power_on = rtsx_base_card_power_on,
 725         .card_power_off = rtsx_base_card_power_off,
 726         .switch_output_voltage = rtsx_base_switch_output_voltage,
 727         .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
 728 };
 729
 730 void rts524a_init_params(struct rtsx_pcr *pcr)
 731 {
 732         rts5249_init_params(pcr);
 733         pcr->aspm_mode = ASPM_MODE_REG;
 734         pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
 735         pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 736         pcr->option.ltr_l1off_snooze_sspwrgate =
 737                 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
 738
 739         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 740         pcr->ops = &rts524a_pcr_ops;
 741
 742         pcr->option.ocp_en = 1;
 743         if (pcr->option.ocp_en)
 744                 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
 745         pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
 746         pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
 747
 748 }
 749
 750 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
 751 {
 752         rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 753                 LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
 754         return rtsx_base_card_power_on(pcr, card);
 755 }
 756
 757 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 758 {
 759         switch (voltage) {
 760         case OUTPUT_3V3:
 761                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 762                         LDO_D3318_MASK, LDO_D3318_33V);
 763                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
 764                 break;
 765         case OUTPUT_1V8:
 766                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 767                         LDO_D3318_MASK, LDO_D3318_18V);
 768                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
 769                         SD_IO_USING_1V8);
 770                 break;
 771         default:
 772                 return -EINVAL;
 773         }
 774
 775         rtsx_pci_init_cmd(pcr);
 776         rts5249_fill_driving(pcr, voltage);
 777         return rtsx_pci_send_cmd(pcr, 100);
 778 }
 779
 780 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
 781 {
 782         int err;
 783
 784         err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 785                 D3_DELINK_MODE_EN, 0x00);
 786         if (err < 0)
 787                 return err;
 788
 789         rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
 790                 _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
 791                 _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
 792                 _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
 793
 794         rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
 795                 _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
 796                 _PHY_CMU_DEBUG_EN);
 797
 798         if (is_version(pcr, 0x525A, IC_VER_A))
 799                 rtsx_pci_write_phy_register(pcr, _PHY_REV0,
 800                         _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
 801                         _PHY_REV0_CDR_RX_IDLE_BYPASS);
 802
 803         return 0;
 804 }
 805
 806 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
 807 {
 808         rts5249_extra_init_hw(pcr);
 809
 810         rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
 811
 812         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 813         if (is_version(pcr, 0x525A, IC_VER_A)) {
 814                 rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
 815                         L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
 816                 rtsx_pci_write_register(pcr, RREF_CFG,
 817                         RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
 818                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 819                         LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
 820                 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
 821                         LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
 822                 rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
 823                         LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
 824                 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
 825                         LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
 826                 rtsx_pci_write_register(pcr, OOBS_CONFIG,
 827                         OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
 828         }
 829
 830         return 0;
 831 }
 832
 833 static const struct pcr_ops rts525a_pcr_ops = {
 834         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 835         .extra_init_hw = rts525a_extra_init_hw,
 836         .optimize_phy = rts525a_optimize_phy,
 837         .turn_on_led = rtsx_base_turn_on_led,
 838         .turn_off_led = rtsx_base_turn_off_led,
 839         .enable_auto_blink = rtsx_base_enable_auto_blink,
 840         .disable_auto_blink = rtsx_base_disable_auto_blink,
 841         .card_power_on = rts525a_card_power_on,
 842         .card_power_off = rtsx_base_card_power_off,
 843         .switch_output_voltage = rts525a_switch_output_voltage,
 844         .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
 845 };
 846
 847 void rts525a_init_params(struct rtsx_pcr *pcr)
 848 {
 849         rts5249_init_params(pcr);
 850         pcr->aspm_mode = ASPM_MODE_REG;
 851         pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
 852         pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 853         pcr->option.ltr_l1off_snooze_sspwrgate =
 854                 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
 855
 856         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 857         pcr->ops = &rts525a_pcr_ops;
 858
 859         pcr->option.ocp_en = 1;
 860         if (pcr->option.ocp_en)
 861                 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
 862         pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
 863         pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;
 864 }