2 * Toshiba TC6393XB SoC support
4 * Copyright(c) 2005-2006 Chris Humbert
5 * Copyright(c) 2005 Dirk Opfer
6 * Copyright(c) 2005 Ian Molton <spyro@f2s.com>
7 * Copyright(c) 2007 Dmitry Baryshkov
9 * Based on code written by Sharp/Lineo for 2.4 kernels
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/mfd/core.h>
25 #include <linux/mfd/tmio.h>
26 #include <linux/mfd/tc6393xb.h>
27 #include <linux/gpio/driver.h>
28 #include <linux/slab.h>
30 #define SCR_REVID 0x08 /* b Revision ID */
31 #define SCR_ISR 0x50 /* b Interrupt Status */
32 #define SCR_IMR 0x52 /* b Interrupt Mask */
33 #define SCR_IRR 0x54 /* b Interrupt Routing */
34 #define SCR_GPER 0x60 /* w GP Enable */
35 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
36 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
37 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
38 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
39 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
40 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
41 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
42 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
43 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
44 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
45 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
46 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
47 #define SCR_CCR 0x98 /* w Clock Control */
48 #define SCR_PLL2CR 0x9a /* w PLL2 Control */
49 #define SCR_PLL1CR 0x9c /* l PLL1 Control */
50 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
51 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
52 #define SCR_FER 0xe0 /* b Function Enable */
53 #define SCR_MCR 0xe4 /* w Mode Control */
54 #define SCR_CONFIG 0xfc /* b Configuration Control */
55 #define SCR_DEBUG 0xff /* b Debug */
57 #define SCR_CCR_CK32K BIT(0)
58 #define SCR_CCR_USBCK BIT(1)
59 #define SCR_CCR_UNK1 BIT(4)
60 #define SCR_CCR_MCLK_MASK (7 << 8)
61 #define SCR_CCR_MCLK_OFF (0 << 8)
62 #define SCR_CCR_MCLK_12 (1 << 8)
63 #define SCR_CCR_MCLK_24 (2 << 8)
64 #define SCR_CCR_MCLK_48 (3 << 8)
65 #define SCR_CCR_HCLK_MASK (3 << 12)
66 #define SCR_CCR_HCLK_24 (0 << 12)
67 #define SCR_CCR_HCLK_48 (1 << 12)
69 #define SCR_FER_USBEN BIT(0) /* USB host enable */
70 #define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
71 #define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
73 #define SCR_MCR_RDY_MASK (3 << 0)
74 #define SCR_MCR_RDY_OPENDRAIN (0 << 0)
75 #define SCR_MCR_RDY_TRISTATE (1 << 0)
76 #define SCR_MCR_RDY_PUSHPULL (2 << 0)
77 #define SCR_MCR_RDY_UNK BIT(2)
78 #define SCR_MCR_RDY_EN BIT(3)
79 #define SCR_MCR_INT_MASK (3 << 4)
80 #define SCR_MCR_INT_OPENDRAIN (0 << 4)
81 #define SCR_MCR_INT_TRISTATE (1 << 4)
82 #define SCR_MCR_INT_PUSHPULL (2 << 4)
83 #define SCR_MCR_INT_UNK BIT(6)
84 #define SCR_MCR_INT_EN BIT(7)
85 /* bits 8 - 16 are unknown */
87 #define TC_GPIO_BIT(i) (1 << (i & 0x7))
89 /*--------------------------------------------------------------------------*/
94 struct gpio_chip gpio;
96 struct clk *clk; /* 3,6 Mhz */
98 raw_spinlock_t lock; /* protects RMW cycles */
108 struct resource rscr;
109 struct resource *iomem;
121 /*--------------------------------------------------------------------------*/
123 static int tc6393xb_nand_enable(struct platform_device *nand)
125 struct tc6393xb *tc6393xb = dev_get_drvdata(nand->dev.parent);
128 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
131 dev_dbg(nand->dev.parent, "SMD buffer on\n");
132 tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));
134 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
139 static struct resource tc6393xb_nand_resources[] = {
143 .flags = IORESOURCE_MEM,
148 .flags = IORESOURCE_MEM,
151 .start = IRQ_TC6393_NAND,
152 .end = IRQ_TC6393_NAND,
153 .flags = IORESOURCE_IRQ,
157 static struct resource tc6393xb_mmc_resources[] = {
161 .flags = IORESOURCE_MEM,
164 .start = IRQ_TC6393_MMC,
165 .end = IRQ_TC6393_MMC,
166 .flags = IORESOURCE_IRQ,
170 static const struct resource tc6393xb_ohci_resources[] = {
174 .flags = IORESOURCE_MEM,
179 .flags = IORESOURCE_MEM,
184 .flags = IORESOURCE_MEM,
189 .flags = IORESOURCE_MEM,
192 .start = IRQ_TC6393_OHCI,
193 .end = IRQ_TC6393_OHCI,
194 .flags = IORESOURCE_IRQ,
198 static struct resource tc6393xb_fb_resources[] = {
202 .flags = IORESOURCE_MEM,
207 .flags = IORESOURCE_MEM,
212 .flags = IORESOURCE_MEM,
215 .start = IRQ_TC6393_FB,
216 .end = IRQ_TC6393_FB,
217 .flags = IORESOURCE_IRQ,
221 static int tc6393xb_ohci_enable(struct platform_device *dev)
223 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
228 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
230 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
231 ccr |= SCR_CCR_USBCK;
232 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
234 fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
235 fer |= SCR_FER_USBEN;
236 tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
238 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
243 static int tc6393xb_ohci_disable(struct platform_device *dev)
245 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
250 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
252 fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
253 fer &= ~SCR_FER_USBEN;
254 tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
256 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
257 ccr &= ~SCR_CCR_USBCK;
258 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
260 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
265 static int tc6393xb_ohci_suspend(struct platform_device *dev)
267 struct tc6393xb_platform_data *tcpd = dev_get_platdata(dev->dev.parent);
269 /* We can't properly store/restore OHCI state, so fail here */
270 if (tcpd->resume_restore)
273 return tc6393xb_ohci_disable(dev);
276 static int tc6393xb_fb_enable(struct platform_device *dev)
278 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
282 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
284 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
285 ccr &= ~SCR_CCR_MCLK_MASK;
286 ccr |= SCR_CCR_MCLK_48;
287 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
289 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
294 static int tc6393xb_fb_disable(struct platform_device *dev)
296 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
300 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
302 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
303 ccr &= ~SCR_CCR_MCLK_MASK;
304 ccr |= SCR_CCR_MCLK_OFF;
305 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
307 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
312 int tc6393xb_lcd_set_power(struct platform_device *fb, bool on)
314 struct tc6393xb *tc6393xb = dev_get_drvdata(fb->dev.parent);
318 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
320 fer = ioread8(tc6393xb->scr + SCR_FER);
322 fer |= SCR_FER_SLCDEN;
324 fer &= ~SCR_FER_SLCDEN;
325 iowrite8(fer, tc6393xb->scr + SCR_FER);
327 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
331 EXPORT_SYMBOL(tc6393xb_lcd_set_power);
333 int tc6393xb_lcd_mode(struct platform_device *fb,
334 const struct fb_videomode *mode) {
335 struct tc6393xb *tc6393xb = dev_get_drvdata(fb->dev.parent);
338 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
340 iowrite16(mode->pixclock, tc6393xb->scr + SCR_PLL1CR + 0);
341 iowrite16(mode->pixclock >> 16, tc6393xb->scr + SCR_PLL1CR + 2);
343 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
347 EXPORT_SYMBOL(tc6393xb_lcd_mode);
349 static int tc6393xb_mmc_enable(struct platform_device *mmc)
351 struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
353 tmio_core_mmc_enable(tc6393xb->scr + 0x200, 0,
354 tc6393xb_mmc_resources[0].start & 0xfffe);
359 static int tc6393xb_mmc_resume(struct platform_device *mmc)
361 struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
363 tmio_core_mmc_resume(tc6393xb->scr + 0x200, 0,
364 tc6393xb_mmc_resources[0].start & 0xfffe);
369 static void tc6393xb_mmc_pwr(struct platform_device *mmc, int state)
371 struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
373 tmio_core_mmc_pwr(tc6393xb->scr + 0x200, 0, state);
376 static void tc6393xb_mmc_clk_div(struct platform_device *mmc, int state)
378 struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
380 tmio_core_mmc_clk_div(tc6393xb->scr + 0x200, 0, state);
383 static struct tmio_mmc_data tc6393xb_mmc_data = {
385 .set_pwr = tc6393xb_mmc_pwr,
386 .set_clk_div = tc6393xb_mmc_clk_div,
389 static struct mfd_cell tc6393xb_cells[] = {
390 [TC6393XB_CELL_NAND] = {
392 .enable = tc6393xb_nand_enable,
393 .num_resources = ARRAY_SIZE(tc6393xb_nand_resources),
394 .resources = tc6393xb_nand_resources,
396 [TC6393XB_CELL_MMC] = {
398 .enable = tc6393xb_mmc_enable,
399 .resume = tc6393xb_mmc_resume,
400 .platform_data = &tc6393xb_mmc_data,
401 .pdata_size = sizeof(tc6393xb_mmc_data),
402 .num_resources = ARRAY_SIZE(tc6393xb_mmc_resources),
403 .resources = tc6393xb_mmc_resources,
405 [TC6393XB_CELL_OHCI] = {
407 .num_resources = ARRAY_SIZE(tc6393xb_ohci_resources),
408 .resources = tc6393xb_ohci_resources,
409 .enable = tc6393xb_ohci_enable,
410 .suspend = tc6393xb_ohci_suspend,
411 .resume = tc6393xb_ohci_enable,
412 .disable = tc6393xb_ohci_disable,
414 [TC6393XB_CELL_FB] = {
416 .num_resources = ARRAY_SIZE(tc6393xb_fb_resources),
417 .resources = tc6393xb_fb_resources,
418 .enable = tc6393xb_fb_enable,
419 .suspend = tc6393xb_fb_disable,
420 .resume = tc6393xb_fb_enable,
421 .disable = tc6393xb_fb_disable,
425 /*--------------------------------------------------------------------------*/
427 static int tc6393xb_gpio_get(struct gpio_chip *chip,
430 struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
432 /* XXX: does dsr also represent inputs? */
433 return !!(tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
434 & TC_GPIO_BIT(offset));
437 static void __tc6393xb_gpio_set(struct gpio_chip *chip,
438 unsigned offset, int value)
440 struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
443 dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
445 dsr |= TC_GPIO_BIT(offset);
447 dsr &= ~TC_GPIO_BIT(offset);
449 tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
452 static void tc6393xb_gpio_set(struct gpio_chip *chip,
453 unsigned offset, int value)
455 struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
458 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
460 __tc6393xb_gpio_set(chip, offset, value);
462 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
465 static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
468 struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
472 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
474 doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
475 doecr &= ~TC_GPIO_BIT(offset);
476 tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
478 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
483 static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
484 unsigned offset, int value)
486 struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
490 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
492 __tc6393xb_gpio_set(chip, offset, value);
494 doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
495 doecr |= TC_GPIO_BIT(offset);
496 tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
498 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
503 static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base)
505 tc6393xb->gpio.label = "tc6393xb";
506 tc6393xb->gpio.base = gpio_base;
507 tc6393xb->gpio.ngpio = 16;
508 tc6393xb->gpio.set = tc6393xb_gpio_set;
509 tc6393xb->gpio.get = tc6393xb_gpio_get;
510 tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input;
511 tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output;
513 return gpiochip_add_data(&tc6393xb->gpio, tc6393xb);
516 /*--------------------------------------------------------------------------*/
518 static void tc6393xb_irq(struct irq_desc *desc)
520 struct tc6393xb *tc6393xb = irq_desc_get_handler_data(desc);
522 unsigned int i, irq_base;
524 irq_base = tc6393xb->irq_base;
526 while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) &
527 ~tmio_ioread8(tc6393xb->scr + SCR_IMR)))
528 for (i = 0; i < TC6393XB_NR_IRQS; i++) {
530 generic_handle_irq(irq_base + i);
534 static void tc6393xb_irq_ack(struct irq_data *data)
538 static void tc6393xb_irq_mask(struct irq_data *data)
540 struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
544 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
545 imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
546 imr |= 1 << (data->irq - tc6393xb->irq_base);
547 tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
548 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
551 static void tc6393xb_irq_unmask(struct irq_data *data)
553 struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
557 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
558 imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
559 imr &= ~(1 << (data->irq - tc6393xb->irq_base));
560 tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
561 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
564 static struct irq_chip tc6393xb_chip = {
566 .irq_ack = tc6393xb_irq_ack,
567 .irq_mask = tc6393xb_irq_mask,
568 .irq_unmask = tc6393xb_irq_unmask,
571 static void tc6393xb_attach_irq(struct platform_device *dev)
573 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
574 unsigned int irq, irq_base;
576 irq_base = tc6393xb->irq_base;
578 for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
579 irq_set_chip_and_handler(irq, &tc6393xb_chip, handle_edge_irq);
580 irq_set_chip_data(irq, tc6393xb);
581 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
584 irq_set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
585 irq_set_chained_handler_and_data(tc6393xb->irq, tc6393xb_irq,
589 static void tc6393xb_detach_irq(struct platform_device *dev)
591 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
592 unsigned int irq, irq_base;
594 irq_set_chained_handler_and_data(tc6393xb->irq, NULL, NULL);
596 irq_base = tc6393xb->irq_base;
598 for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
599 irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
600 irq_set_chip(irq, NULL);
601 irq_set_chip_data(irq, NULL);
605 /*--------------------------------------------------------------------------*/
607 static int tc6393xb_probe(struct platform_device *dev)
609 struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
610 struct tc6393xb *tc6393xb;
611 struct resource *iomem, *rscr;
614 iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
618 tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
624 raw_spin_lock_init(&tc6393xb->lock);
626 platform_set_drvdata(dev, tc6393xb);
628 ret = platform_get_irq(dev, 0);
634 tc6393xb->iomem = iomem;
635 tc6393xb->irq_base = tcpd->irq_base;
637 tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI");
638 if (IS_ERR(tc6393xb->clk)) {
639 ret = PTR_ERR(tc6393xb->clk);
643 rscr = &tc6393xb->rscr;
644 rscr->name = "tc6393xb-core";
645 rscr->start = iomem->start;
646 rscr->end = iomem->start + 0xff;
647 rscr->flags = IORESOURCE_MEM;
649 ret = request_resource(iomem, rscr);
651 goto err_request_scr;
653 tc6393xb->scr = ioremap(rscr->start, resource_size(rscr));
654 if (!tc6393xb->scr) {
659 ret = clk_prepare_enable(tc6393xb->clk);
663 ret = tcpd->enable(dev);
667 iowrite8(0, tc6393xb->scr + SCR_FER);
668 iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
669 iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48,
670 tc6393xb->scr + SCR_CCR);
671 iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
672 SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
673 BIT(15), tc6393xb->scr + SCR_MCR);
674 iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
675 iowrite8(0, tc6393xb->scr + SCR_IRR);
676 iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
678 printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
679 tmio_ioread8(tc6393xb->scr + SCR_REVID),
680 (unsigned long) iomem->start, tc6393xb->irq);
682 tc6393xb->gpio.base = -1;
684 if (tcpd->gpio_base >= 0) {
685 ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
690 tc6393xb_attach_irq(dev);
693 ret = tcpd->setup(dev);
698 tc6393xb_cells[TC6393XB_CELL_NAND].platform_data = tcpd->nand_data;
699 tc6393xb_cells[TC6393XB_CELL_NAND].pdata_size =
700 sizeof(*tcpd->nand_data);
701 tc6393xb_cells[TC6393XB_CELL_FB].platform_data = tcpd->fb_data;
702 tc6393xb_cells[TC6393XB_CELL_FB].pdata_size = sizeof(*tcpd->fb_data);
704 ret = mfd_add_devices(&dev->dev, dev->id,
705 tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
706 iomem, tcpd->irq_base, NULL);
715 tc6393xb_detach_irq(dev);
718 if (tc6393xb->gpio.base != -1)
719 gpiochip_remove(&tc6393xb->gpio);
722 clk_disable_unprepare(tc6393xb->clk);
724 iounmap(tc6393xb->scr);
726 release_resource(&tc6393xb->rscr);
728 clk_put(tc6393xb->clk);
736 static int tc6393xb_remove(struct platform_device *dev)
738 struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
739 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
742 mfd_remove_devices(&dev->dev);
747 tc6393xb_detach_irq(dev);
749 if (tc6393xb->gpio.base != -1)
750 gpiochip_remove(&tc6393xb->gpio);
752 ret = tcpd->disable(dev);
753 clk_disable_unprepare(tc6393xb->clk);
754 iounmap(tc6393xb->scr);
755 release_resource(&tc6393xb->rscr);
756 clk_put(tc6393xb->clk);
763 static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
765 struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
766 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
769 tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
770 tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);
772 for (i = 0; i < 3; i++) {
773 tc6393xb->suspend_state.gpo_dsr[i] =
774 ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
775 tc6393xb->suspend_state.gpo_doecr[i] =
776 ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
777 tc6393xb->suspend_state.gpi_bcr[i] =
778 ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
780 ret = tcpd->suspend(dev);
781 clk_disable_unprepare(tc6393xb->clk);
786 static int tc6393xb_resume(struct platform_device *dev)
788 struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
789 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
793 ret = clk_prepare_enable(tc6393xb->clk);
797 ret = tcpd->resume(dev);
801 if (!tcpd->resume_restore)
804 iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER);
805 iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
806 iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR);
807 iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
808 SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
809 BIT(15), tc6393xb->scr + SCR_MCR);
810 iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
811 iowrite8(0, tc6393xb->scr + SCR_IRR);
812 iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
814 for (i = 0; i < 3; i++) {
815 iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
816 tc6393xb->scr + SCR_GPO_DSR(i));
817 iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
818 tc6393xb->scr + SCR_GPO_DOECR(i));
819 iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
820 tc6393xb->scr + SCR_GPI_BCR(i));
826 #define tc6393xb_suspend NULL
827 #define tc6393xb_resume NULL
830 static struct platform_driver tc6393xb_driver = {
831 .probe = tc6393xb_probe,
832 .remove = tc6393xb_remove,
833 .suspend = tc6393xb_suspend,
834 .resume = tc6393xb_resume,
841 static int __init tc6393xb_init(void)
843 return platform_driver_register(&tc6393xb_driver);
846 static void __exit tc6393xb_exit(void)
848 platform_driver_unregister(&tc6393xb_driver);
851 subsys_initcall(tc6393xb_init);
852 module_exit(tc6393xb_exit);
854 MODULE_LICENSE("GPL v2");
855 MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
856 MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
857 MODULE_ALIAS("platform:tc6393xb");