drivers/mfd/sm501.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* linux/drivers/mfd/sm501.c
   3  *
   4  * Copyright (C) 2006 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      Vincent Sanders <vince@simtec.co.uk>
   7  *
   8  * SM501 MFD driver
   9 */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/delay.h>
  14 #include <linux/init.h>
  15 #include <linux/list.h>
  16 #include <linux/device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pci.h>
  19 #include <linux/platform_data/i2c-gpio.h>
  20 #include <linux/gpio/driver.h>
  21 #include <linux/gpio/machine.h>
  22 #include <linux/slab.h>
  23
  24 #include <linux/sm501.h>
  25 #include <linux/sm501-regs.h>
  26 #include <linux/serial_8250.h>
  27
  28 #include <linux/io.h>
  29
  30 struct sm501_device {
  31         struct list_head                list;
  32         struct platform_device          pdev;
  33 };
  34
  35 struct sm501_gpio;
  36
  37 #ifdef CONFIG_MFD_SM501_GPIO
  38 #include <linux/gpio.h>
  39
  40 struct sm501_gpio_chip {
  41         struct gpio_chip        gpio;
  42         struct sm501_gpio       *ourgpio;       /* to get back to parent. */
  43         void __iomem            *regbase;
  44         void __iomem            *control;       /* address of control reg. */
  45 };
  46
  47 struct sm501_gpio {
  48         struct sm501_gpio_chip  low;
  49         struct sm501_gpio_chip  high;
  50         spinlock_t              lock;
  51
  52         unsigned int             registered : 1;
  53         void __iomem            *regs;
  54         struct resource         *regs_res;
  55 };
  56 #else
  57 struct sm501_gpio {
  58         /* no gpio support, empty definition for sm501_devdata. */
  59 };
  60 #endif
  61
  62 struct sm501_devdata {
  63         spinlock_t                       reg_lock;
  64         struct mutex                     clock_lock;
  65         struct list_head                 devices;
  66         struct sm501_gpio                gpio;
  67
  68         struct device                   *dev;
  69         struct resource                 *io_res;
  70         struct resource                 *mem_res;
  71         struct resource                 *regs_claim;
  72         struct sm501_platdata           *platdata;
  73
  74
  75         unsigned int                     in_suspend;
  76         unsigned long                    pm_misc;
  77
  78         int                              unit_power[20];
  79         unsigned int                     pdev_id;
  80         unsigned int                     irq;
  81         void __iomem                    *regs;
  82         unsigned int                     rev;
  83 };
  84
  85
  86 #define MHZ (1000 * 1000)
  87
  88 #ifdef DEBUG
  89 static const unsigned int div_tab[] = {
  90         [0]             = 1,
  91         [1]             = 2,
  92         [2]             = 4,
  93         [3]             = 8,
  94         [4]             = 16,
  95         [5]             = 32,
  96         [6]             = 64,
  97         [7]             = 128,
  98         [8]             = 3,
  99         [9]             = 6,
 100         [10]            = 12,
 101         [11]            = 24,
 102         [12]            = 48,
 103         [13]            = 96,
 104         [14]            = 192,
 105         [15]            = 384,
 106         [16]            = 5,
 107         [17]            = 10,
 108         [18]            = 20,
 109         [19]            = 40,
 110         [20]            = 80,
 111         [21]            = 160,
 112         [22]            = 320,
 113         [23]            = 604,
 114 };
 115
 116 static unsigned long decode_div(unsigned long pll2, unsigned long val,
 117                                 unsigned int lshft, unsigned int selbit,
 118                                 unsigned long mask)
 119 {
 120         if (val & selbit)
 121                 pll2 = 288 * MHZ;
 122
 123         return pll2 / div_tab[(val >> lshft) & mask];
 124 }
 125
 126 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
 127
 128 /* sm501_dump_clk
 129  *
 130  * Print out the current clock configuration for the device
 131 */
 132
 133 static void sm501_dump_clk(struct sm501_devdata *sm)
 134 {
 135         unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
 136         unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
 137         unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
 138         unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 139         unsigned long sdclk0, sdclk1;
 140         unsigned long pll2 = 0;
 141
 142         switch (misct & 0x30) {
 143         case 0x00:
 144                 pll2 = 336 * MHZ;
 145                 break;
 146         case 0x10:
 147                 pll2 = 288 * MHZ;
 148                 break;
 149         case 0x20:
 150                 pll2 = 240 * MHZ;
 151                 break;
 152         case 0x30:
 153                 pll2 = 192 * MHZ;
 154                 break;
 155         }
 156
 157         sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
 158         sdclk0 /= div_tab[((misct >> 8) & 0xf)];
 159
 160         sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
 161         sdclk1 /= div_tab[((misct >> 16) & 0xf)];
 162
 163         dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
 164                 misct, pm0, pm1);
 165
 166         dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
 167                 fmt_freq(pll2), sdclk0, sdclk1);
 168
 169         dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
 170
 171         dev_dbg(sm->dev, "PM0[%c]: "
 172                  "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
 173                  "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
 174                  (pmc & 3 ) == 0 ? '*' : '-',
 175                  fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
 176                  fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
 177                  fmt_freq(decode_div(pll2, pm0, 8,  1<<12, 15)),
 178                  fmt_freq(decode_div(pll2, pm0, 0,  1<<4,  15)));
 179
 180         dev_dbg(sm->dev, "PM1[%c]: "
 181                 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
 182                 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
 183                 (pmc & 3 ) == 1 ? '*' : '-',
 184                 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
 185                 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
 186                 fmt_freq(decode_div(pll2, pm1, 8,  1<<12, 15)),
 187                 fmt_freq(decode_div(pll2, pm1, 0,  1<<4,  15)));
 188 }
 189
 190 static void sm501_dump_regs(struct sm501_devdata *sm)
 191 {
 192         void __iomem *regs = sm->regs;
 193
 194         dev_info(sm->dev, "System Control   %08x\n",
 195                         smc501_readl(regs + SM501_SYSTEM_CONTROL));
 196         dev_info(sm->dev, "Misc Control     %08x\n",
 197                         smc501_readl(regs + SM501_MISC_CONTROL));
 198         dev_info(sm->dev, "GPIO Control Low %08x\n",
 199                         smc501_readl(regs + SM501_GPIO31_0_CONTROL));
 200         dev_info(sm->dev, "GPIO Control Hi  %08x\n",
 201                         smc501_readl(regs + SM501_GPIO63_32_CONTROL));
 202         dev_info(sm->dev, "DRAM Control     %08x\n",
 203                         smc501_readl(regs + SM501_DRAM_CONTROL));
 204         dev_info(sm->dev, "Arbitration Ctrl %08x\n",
 205                         smc501_readl(regs + SM501_ARBTRTN_CONTROL));
 206         dev_info(sm->dev, "Misc Timing      %08x\n",
 207                         smc501_readl(regs + SM501_MISC_TIMING));
 208 }
 209
 210 static void sm501_dump_gate(struct sm501_devdata *sm)
 211 {
 212         dev_info(sm->dev, "CurrentGate      %08x\n",
 213                         smc501_readl(sm->regs + SM501_CURRENT_GATE));
 214         dev_info(sm->dev, "CurrentClock     %08x\n",
 215                         smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
 216         dev_info(sm->dev, "PowerModeControl %08x\n",
 217                         smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
 218 }
 219
 220 #else
 221 static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
 222 static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
 223 static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
 224 #endif
 225
 226 /* sm501_sync_regs
 227  *
 228  * ensure the
 229 */
 230
 231 static void sm501_sync_regs(struct sm501_devdata *sm)
 232 {
 233         smc501_readl(sm->regs);
 234 }
 235
 236 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
 237 {
 238         /* during suspend/resume, we are currently not allowed to sleep,
 239          * so change to using mdelay() instead of msleep() if we
 240          * are in one of these paths */
 241
 242         if (sm->in_suspend)
 243                 mdelay(delay);
 244         else
 245                 msleep(delay);
 246 }
 247
 248 /* sm501_misc_control
 249  *
 250  * alters the miscellaneous control parameters
 251 */
 252
 253 int sm501_misc_control(struct device *dev,
 254                        unsigned long set, unsigned long clear)
 255 {
 256         struct sm501_devdata *sm = dev_get_drvdata(dev);
 257         unsigned long misc;
 258         unsigned long save;
 259         unsigned long to;
 260
 261         spin_lock_irqsave(&sm->reg_lock, save);
 262
 263         misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
 264         to = (misc & ~clear) | set;
 265
 266         if (to != misc) {
 267                 smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
 268                 sm501_sync_regs(sm);
 269
 270                 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
 271         }
 272
 273         spin_unlock_irqrestore(&sm->reg_lock, save);
 274         return to;
 275 }
 276
 277 EXPORT_SYMBOL_GPL(sm501_misc_control);
 278
 279 /* sm501_modify_reg
 280  *
 281  * Modify a register in the SM501 which may be shared with other
 282  * drivers.
 283 */
 284
 285 unsigned long sm501_modify_reg(struct device *dev,
 286                                unsigned long reg,
 287                                unsigned long set,
 288                                unsigned long clear)
 289 {
 290         struct sm501_devdata *sm = dev_get_drvdata(dev);
 291         unsigned long data;
 292         unsigned long save;
 293
 294         spin_lock_irqsave(&sm->reg_lock, save);
 295
 296         data = smc501_readl(sm->regs + reg);
 297         data |= set;
 298         data &= ~clear;
 299
 300         smc501_writel(data, sm->regs + reg);
 301         sm501_sync_regs(sm);
 302
 303         spin_unlock_irqrestore(&sm->reg_lock, save);
 304
 305         return data;
 306 }
 307
 308 EXPORT_SYMBOL_GPL(sm501_modify_reg);
 309
 310 /* sm501_unit_power
 311  *
 312  * alters the power active gate to set specific units on or off
 313  */
 314
 315 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
 316 {
 317         struct sm501_devdata *sm = dev_get_drvdata(dev);
 318         unsigned long mode;
 319         unsigned long gate;
 320         unsigned long clock;
 321
 322         mutex_lock(&sm->clock_lock);
 323
 324         mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 325         gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
 326         clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
 327
 328         mode &= 3;              /* get current power mode */
 329
 330         if (unit >= ARRAY_SIZE(sm->unit_power)) {
 331                 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
 332                 goto already;
 333         }
 334
 335         dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
 336                 sm->unit_power[unit], to);
 337
 338         if (to == 0 && sm->unit_power[unit] == 0) {
 339                 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
 340                 goto already;
 341         }
 342
 343         sm->unit_power[unit] += to ? 1 : -1;
 344         to = sm->unit_power[unit] ? 1 : 0;
 345
 346         if (to) {
 347                 if (gate & (1 << unit))
 348                         goto already;
 349                 gate |= (1 << unit);
 350         } else {
 351                 if (!(gate & (1 << unit)))
 352                         goto already;
 353                 gate &= ~(1 << unit);
 354         }
 355
 356         switch (mode) {
 357         case 1:
 358                 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
 359                 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
 360                 mode = 0;
 361                 break;
 362         case 2:
 363         case 0:
 364                 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
 365                 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
 366                 mode = 1;
 367                 break;
 368
 369         default:
 370                 gate = -1;
 371                 goto already;
 372         }
 373
 374         smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
 375         sm501_sync_regs(sm);
 376
 377         dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
 378                 gate, clock, mode);
 379
 380         sm501_mdelay(sm, 16);
 381
 382  already:
 383         mutex_unlock(&sm->clock_lock);
 384         return gate;
 385 }
 386
 387 EXPORT_SYMBOL_GPL(sm501_unit_power);
 388
 389 /* clock value structure. */
 390 struct sm501_clock {
 391         unsigned long mclk;
 392         int divider;
 393         int shift;
 394         unsigned int m, n, k;
 395 };
 396
 397 /* sm501_calc_clock
 398  *
 399  * Calculates the nearest discrete clock frequency that
 400  * can be achieved with the specified input clock.
 401  *   the maximum divisor is 3 or 5
 402  */
 403
 404 static int sm501_calc_clock(unsigned long freq,
 405                             struct sm501_clock *clock,
 406                             int max_div,
 407                             unsigned long mclk,
 408                             long *best_diff)
 409 {
 410         int ret = 0;
 411         int divider;
 412         int shift;
 413         long diff;
 414
 415         /* try dividers 1 and 3 for CRT and for panel,
 416            try divider 5 for panel only.*/
 417
 418         for (divider = 1; divider <= max_div; divider += 2) {
 419                 /* try all 8 shift values.*/
 420                 for (shift = 0; shift < 8; shift++) {
 421                         /* Calculate difference to requested clock */
 422                         diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
 423                         if (diff < 0)
 424                                 diff = -diff;
 425
 426                         /* If it is less than the current, use it */
 427                         if (diff < *best_diff) {
 428                                 *best_diff = diff;
 429
 430                                 clock->mclk = mclk;
 431                                 clock->divider = divider;
 432                                 clock->shift = shift;
 433                                 ret = 1;
 434                         }
 435                 }
 436         }
 437
 438         return ret;
 439 }
 440
 441 /* sm501_calc_pll
 442  *
 443  * Calculates the nearest discrete clock frequency that can be
 444  * achieved using the programmable PLL.
 445  *   the maximum divisor is 3 or 5
 446  */
 447
 448 static unsigned long sm501_calc_pll(unsigned long freq,
 449                                         struct sm501_clock *clock,
 450                                         int max_div)
 451 {
 452         unsigned long mclk;
 453         unsigned int m, n, k;
 454         long best_diff = 999999999;
 455
 456         /*
 457          * The SM502 datasheet doesn't specify the min/max values for M and N.
 458          * N = 1 at least doesn't work in practice.
 459          */
 460         for (m = 2; m <= 255; m++) {
 461                 for (n = 2; n <= 127; n++) {
 462                         for (k = 0; k <= 1; k++) {
 463                                 mclk = (24000000UL * m / n) >> k;
 464
 465                                 if (sm501_calc_clock(freq, clock, max_div,
 466                                                      mclk, &best_diff)) {
 467                                         clock->m = m;
 468                                         clock->n = n;
 469                                         clock->k = k;
 470                                 }
 471                         }
 472                 }
 473         }
 474
 475         /* Return best clock. */
 476         return clock->mclk / (clock->divider << clock->shift);
 477 }
 478
 479 /* sm501_select_clock
 480  *
 481  * Calculates the nearest discrete clock frequency that can be
 482  * achieved using the 288MHz and 336MHz PLLs.
 483  *   the maximum divisor is 3 or 5
 484  */
 485
 486 static unsigned long sm501_select_clock(unsigned long freq,
 487                                         struct sm501_clock *clock,
 488                                         int max_div)
 489 {
 490         unsigned long mclk;
 491         long best_diff = 999999999;
 492
 493         /* Try 288MHz and 336MHz clocks. */
 494         for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
 495                 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
 496         }
 497
 498         /* Return best clock. */
 499         return clock->mclk / (clock->divider << clock->shift);
 500 }
 501
 502 /* sm501_set_clock
 503  *
 504  * set one of the four clock sources to the closest available frequency to
 505  *  the one specified
 506 */
 507
 508 unsigned long sm501_set_clock(struct device *dev,
 509                               int clksrc,
 510                               unsigned long req_freq)
 511 {
 512         struct sm501_devdata *sm = dev_get_drvdata(dev);
 513         unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 514         unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
 515         unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
 516         unsigned int pll_reg = 0;
 517         unsigned long sm501_freq; /* the actual frequency achieved */
 518         u64 reg;
 519
 520         struct sm501_clock to;
 521
 522         /* find achivable discrete frequency and setup register value
 523          * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
 524          * has an extra bit for the divider */
 525
 526         switch (clksrc) {
 527         case SM501_CLOCK_P2XCLK:
 528                 /* This clock is divided in half so to achieve the
 529                  * requested frequency the value must be multiplied by
 530                  * 2. This clock also has an additional pre divisor */
 531
 532                 if (sm->rev >= 0xC0) {
 533                         /* SM502 -> use the programmable PLL */
 534                         sm501_freq = (sm501_calc_pll(2 * req_freq,
 535                                                      &to, 5) / 2);
 536                         reg = to.shift & 0x07;/* bottom 3 bits are shift */
 537                         if (to.divider == 3)
 538                                 reg |= 0x08; /* /3 divider required */
 539                         else if (to.divider == 5)
 540                                 reg |= 0x10; /* /5 divider required */
 541                         reg |= 0x40; /* select the programmable PLL */
 542                         pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
 543                 } else {
 544                         sm501_freq = (sm501_select_clock(2 * req_freq,
 545                                                          &to, 5) / 2);
 546                         reg = to.shift & 0x07;/* bottom 3 bits are shift */
 547                         if (to.divider == 3)
 548                                 reg |= 0x08; /* /3 divider required */
 549                         else if (to.divider == 5)
 550                                 reg |= 0x10; /* /5 divider required */
 551                         if (to.mclk != 288000000)
 552                                 reg |= 0x20; /* which mclk pll is source */
 553                 }
 554                 break;
 555
 556         case SM501_CLOCK_V2XCLK:
 557                 /* This clock is divided in half so to achieve the
 558                  * requested frequency the value must be multiplied by 2. */
 559
 560                 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
 561                 reg=to.shift & 0x07;    /* bottom 3 bits are shift */
 562                 if (to.divider == 3)
 563                         reg |= 0x08;    /* /3 divider required */
 564                 if (to.mclk != 288000000)
 565                         reg |= 0x10;    /* which mclk pll is source */
 566                 break;
 567
 568         case SM501_CLOCK_MCLK:
 569         case SM501_CLOCK_M1XCLK:
 570                 /* These clocks are the same and not further divided */
 571
 572                 sm501_freq = sm501_select_clock( req_freq, &to, 3);
 573                 reg=to.shift & 0x07;    /* bottom 3 bits are shift */
 574                 if (to.divider == 3)
 575                         reg |= 0x08;    /* /3 divider required */
 576                 if (to.mclk != 288000000)
 577                         reg |= 0x10;    /* which mclk pll is source */
 578                 break;
 579
 580         default:
 581                 return 0; /* this is bad */
 582         }
 583
 584         mutex_lock(&sm->clock_lock);
 585
 586         mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 587         gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
 588         clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
 589
 590         clock = clock & ~(0xFF << clksrc);
 591         clock |= reg<<clksrc;
 592
 593         mode &= 3;      /* find current mode */
 594
 595         switch (mode) {
 596         case 1:
 597                 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
 598                 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
 599                 mode = 0;
 600                 break;
 601         case 2:
 602         case 0:
 603                 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
 604                 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
 605                 mode = 1;
 606                 break;
 607
 608         default:
 609                 mutex_unlock(&sm->clock_lock);
 610                 return -1;
 611         }
 612
 613         smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
 614
 615         if (pll_reg)
 616                 smc501_writel(pll_reg,
 617                                 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
 618
 619         sm501_sync_regs(sm);
 620
 621         dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
 622                 gate, clock, mode);
 623
 624         sm501_mdelay(sm, 16);
 625         mutex_unlock(&sm->clock_lock);
 626
 627         sm501_dump_clk(sm);
 628
 629         return sm501_freq;
 630 }
 631
 632 EXPORT_SYMBOL_GPL(sm501_set_clock);
 633
 634 /* sm501_find_clock
 635  *
 636  * finds the closest available frequency for a given clock
 637 */
 638
 639 unsigned long sm501_find_clock(struct device *dev,
 640                                int clksrc,
 641                                unsigned long req_freq)
 642 {
 643         struct sm501_devdata *sm = dev_get_drvdata(dev);
 644         unsigned long sm501_freq; /* the frequency achieveable by the 501 */
 645         struct sm501_clock to;
 646
 647         switch (clksrc) {
 648         case SM501_CLOCK_P2XCLK:
 649                 if (sm->rev >= 0xC0) {
 650                         /* SM502 -> use the programmable PLL */
 651                         sm501_freq = (sm501_calc_pll(2 * req_freq,
 652                                                      &to, 5) / 2);
 653                 } else {
 654                         sm501_freq = (sm501_select_clock(2 * req_freq,
 655                                                          &to, 5) / 2);
 656                 }
 657                 break;
 658
 659         case SM501_CLOCK_V2XCLK:
 660                 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
 661                 break;
 662
 663         case SM501_CLOCK_MCLK:
 664         case SM501_CLOCK_M1XCLK:
 665                 sm501_freq = sm501_select_clock(req_freq, &to, 3);
 666                 break;
 667
 668         default:
 669                 sm501_freq = 0;         /* error */
 670         }
 671
 672         return sm501_freq;
 673 }
 674
 675 EXPORT_SYMBOL_GPL(sm501_find_clock);
 676
 677 static struct sm501_device *to_sm_device(struct platform_device *pdev)
 678 {
 679         return container_of(pdev, struct sm501_device, pdev);
 680 }
 681
 682 /* sm501_device_release
 683  *
 684  * A release function for the platform devices we create to allow us to
 685  * free any items we allocated
 686 */
 687
 688 static void sm501_device_release(struct device *dev)
 689 {
 690         kfree(to_sm_device(to_platform_device(dev)));
 691 }
 692
 693 /* sm501_create_subdev
 694  *
 695  * Create a skeleton platform device with resources for passing to a
 696  * sub-driver
 697 */
 698
 699 static struct platform_device *
 700 sm501_create_subdev(struct sm501_devdata *sm, char *name,
 701                     unsigned int res_count, unsigned int platform_data_size)
 702 {
 703         struct sm501_device *smdev;
 704
 705         smdev = kzalloc(sizeof(struct sm501_device) +
 706                         (sizeof(struct resource) * res_count) +
 707                         platform_data_size, GFP_KERNEL);
 708         if (!smdev)
 709                 return NULL;
 710
 711         smdev->pdev.dev.release = sm501_device_release;
 712
 713         smdev->pdev.name = name;
 714         smdev->pdev.id = sm->pdev_id;
 715         smdev->pdev.dev.parent = sm->dev;
 716         smdev->pdev.dev.coherent_dma_mask = 0xffffffff;
 717
 718         if (res_count) {
 719                 smdev->pdev.resource = (struct resource *)(smdev+1);
 720                 smdev->pdev.num_resources = res_count;
 721         }
 722         if (platform_data_size)
 723                 smdev->pdev.dev.platform_data = (void *)(smdev+1);
 724
 725         return &smdev->pdev;
 726 }
 727
 728 /* sm501_register_device
 729  *
 730  * Register a platform device created with sm501_create_subdev()
 731 */
 732
 733 static int sm501_register_device(struct sm501_devdata *sm,
 734                                  struct platform_device *pdev)
 735 {
 736         struct sm501_device *smdev = to_sm_device(pdev);
 737         int ptr;
 738         int ret;
 739
 740         for (ptr = 0; ptr < pdev->num_resources; ptr++) {
 741                 printk(KERN_DEBUG "%s[%d] %pR\n",
 742                        pdev->name, ptr, &pdev->resource[ptr]);
 743         }
 744
 745         ret = platform_device_register(pdev);
 746
 747         if (ret >= 0) {
 748                 dev_dbg(sm->dev, "registered %s\n", pdev->name);
 749                 list_add_tail(&smdev->list, &sm->devices);
 750         } else
 751                 dev_err(sm->dev, "error registering %s (%d)\n",
 752                         pdev->name, ret);
 753
 754         return ret;
 755 }
 756
 757 /* sm501_create_subio
 758  *
 759  * Fill in an IO resource for a sub device
 760 */
 761
 762 static void sm501_create_subio(struct sm501_devdata *sm,
 763                                struct resource *res,
 764                                resource_size_t offs,
 765                                resource_size_t size)
 766 {
 767         res->flags = IORESOURCE_MEM;
 768         res->parent = sm->io_res;
 769         res->start = sm->io_res->start + offs;
 770         res->end = res->start + size - 1;
 771 }
 772
 773 /* sm501_create_mem
 774  *
 775  * Fill in an MEM resource for a sub device
 776 */
 777
 778 static void sm501_create_mem(struct sm501_devdata *sm,
 779                              struct resource *res,
 780                              resource_size_t *offs,
 781                              resource_size_t size)
 782 {
 783         *offs -= size;          /* adjust memory size */
 784
 785         res->flags = IORESOURCE_MEM;
 786         res->parent = sm->mem_res;
 787         res->start = sm->mem_res->start + *offs;
 788         res->end = res->start + size - 1;
 789 }
 790
 791 /* sm501_create_irq
 792  *
 793  * Fill in an IRQ resource for a sub device
 794 */
 795
 796 static void sm501_create_irq(struct sm501_devdata *sm,
 797                              struct resource *res)
 798 {
 799         res->flags = IORESOURCE_IRQ;
 800         res->parent = NULL;
 801         res->start = res->end = sm->irq;
 802 }
 803
 804 static int sm501_register_usbhost(struct sm501_devdata *sm,
 805                                   resource_size_t *mem_avail)
 806 {
 807         struct platform_device *pdev;
 808
 809         pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
 810         if (!pdev)
 811                 return -ENOMEM;
 812
 813         sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
 814         sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
 815         sm501_create_irq(sm, &pdev->resource[2]);
 816
 817         return sm501_register_device(sm, pdev);
 818 }
 819
 820 static void sm501_setup_uart_data(struct sm501_devdata *sm,
 821                                   struct plat_serial8250_port *uart_data,
 822                                   unsigned int offset)
 823 {
 824         uart_data->membase = sm->regs + offset;
 825         uart_data->mapbase = sm->io_res->start + offset;
 826         uart_data->iotype = UPIO_MEM;
 827         uart_data->irq = sm->irq;
 828         uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
 829         uart_data->regshift = 2;
 830         uart_data->uartclk = (9600 * 16);
 831 }
 832
 833 static int sm501_register_uart(struct sm501_devdata *sm, int devices)
 834 {
 835         struct platform_device *pdev;
 836         struct plat_serial8250_port *uart_data;
 837
 838         pdev = sm501_create_subdev(sm, "serial8250", 0,
 839                                    sizeof(struct plat_serial8250_port) * 3);
 840         if (!pdev)
 841                 return -ENOMEM;
 842
 843         uart_data = dev_get_platdata(&pdev->dev);
 844
 845         if (devices & SM501_USE_UART0) {
 846                 sm501_setup_uart_data(sm, uart_data++, 0x30000);
 847                 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
 848                 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
 849                 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
 850         }
 851         if (devices & SM501_USE_UART1) {
 852                 sm501_setup_uart_data(sm, uart_data++, 0x30020);
 853                 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
 854                 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
 855                 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
 856         }
 857
 858         pdev->id = PLAT8250_DEV_SM501;
 859
 860         return sm501_register_device(sm, pdev);
 861 }
 862
 863 static int sm501_register_display(struct sm501_devdata *sm,
 864                                   resource_size_t *mem_avail)
 865 {
 866         struct platform_device *pdev;
 867
 868         pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
 869         if (!pdev)
 870                 return -ENOMEM;
 871
 872         sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
 873         sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
 874         sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
 875         sm501_create_irq(sm, &pdev->resource[3]);
 876
 877         return sm501_register_device(sm, pdev);
 878 }
 879
 880 #ifdef CONFIG_MFD_SM501_GPIO
 881
 882 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
 883 {
 884         return container_of(gpio, struct sm501_devdata, gpio);
 885 }
 886
 887 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
 888
 889 {
 890         struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip);
 891         unsigned long result;
 892
 893         result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
 894         result >>= offset;
 895
 896         return result & 1UL;
 897 }
 898
 899 static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
 900                                    unsigned long bit)
 901 {
 902         unsigned long ctrl;
 903
 904         /* check and modify if this pin is not set as gpio. */
 905
 906         if (smc501_readl(smchip->control) & bit) {
 907                 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
 908                          "changing mode of gpio, bit %08lx\n", bit);
 909
 910                 ctrl = smc501_readl(smchip->control);
 911                 ctrl &= ~bit;
 912                 smc501_writel(ctrl, smchip->control);
 913
 914                 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
 915         }
 916 }
 917
 918 static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 919
 920 {
 921         struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
 922         struct sm501_gpio *smgpio = smchip->ourgpio;
 923         unsigned long bit = 1 << offset;
 924         void __iomem *regs = smchip->regbase;
 925         unsigned long save;
 926         unsigned long val;
 927
 928         dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
 929                 __func__, chip, offset);
 930
 931         spin_lock_irqsave(&smgpio->lock, save);
 932
 933         val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
 934         if (value)
 935                 val |= bit;
 936         smc501_writel(val, regs);
 937
 938         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 939         sm501_gpio_ensure_gpio(smchip, bit);
 940
 941         spin_unlock_irqrestore(&smgpio->lock, save);
 942 }
 943
 944 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
 945 {
 946         struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
 947         struct sm501_gpio *smgpio = smchip->ourgpio;
 948         void __iomem *regs = smchip->regbase;
 949         unsigned long bit = 1 << offset;
 950         unsigned long save;
 951         unsigned long ddr;
 952
 953         dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
 954                 __func__, chip, offset);
 955
 956         spin_lock_irqsave(&smgpio->lock, save);
 957
 958         ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
 959         smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
 960
 961         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 962         sm501_gpio_ensure_gpio(smchip, bit);
 963
 964         spin_unlock_irqrestore(&smgpio->lock, save);
 965
 966         return 0;
 967 }
 968
 969 static int sm501_gpio_output(struct gpio_chip *chip,
 970                              unsigned offset, int value)
 971 {
 972         struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
 973         struct sm501_gpio *smgpio = smchip->ourgpio;
 974         unsigned long bit = 1 << offset;
 975         void __iomem *regs = smchip->regbase;
 976         unsigned long save;
 977         unsigned long val;
 978         unsigned long ddr;
 979
 980         dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
 981                 __func__, chip, offset, value);
 982
 983         spin_lock_irqsave(&smgpio->lock, save);
 984
 985         val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
 986         if (value)
 987                 val |= bit;
 988         else
 989                 val &= ~bit;
 990         smc501_writel(val, regs);
 991
 992         ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
 993         smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
 994
 995         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 996         smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
 997
 998         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 999         spin_unlock_irqrestore(&smgpio->lock, save);
1000
1001         return 0;
1002 }
1003
1004 static const struct gpio_chip gpio_chip_template = {
1005         .ngpio                  = 32,
1006         .direction_input        = sm501_gpio_input,
1007         .direction_output       = sm501_gpio_output,
1008         .set                    = sm501_gpio_set,
1009         .get                    = sm501_gpio_get,
1010 };
1011
1012 static int sm501_gpio_register_chip(struct sm501_devdata *sm,
1013                                               struct sm501_gpio *gpio,
1014                                               struct sm501_gpio_chip *chip)
1015 {
1016         struct sm501_platdata *pdata = sm->platdata;
1017         struct gpio_chip *gchip = &chip->gpio;
1018         int base = pdata->gpio_base;
1019
1020         chip->gpio = gpio_chip_template;
1021
1022         if (chip == &gpio->high) {
1023                 if (base > 0)
1024                         base += 32;
1025                 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1026                 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
1027                 gchip->label  = "SM501-HIGH";
1028         } else {
1029                 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1030                 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
1031                 gchip->label  = "SM501-LOW";
1032         }
1033
1034         gchip->base   = base;
1035         chip->ourgpio = gpio;
1036
1037         return gpiochip_add_data(gchip, chip);
1038 }
1039
1040 static int sm501_register_gpio(struct sm501_devdata *sm)
1041 {
1042         struct sm501_gpio *gpio = &sm->gpio;
1043         resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1044         int ret;
1045
1046         dev_dbg(sm->dev, "registering gpio block %08llx\n",
1047                 (unsigned long long)iobase);
1048
1049         spin_lock_init(&gpio->lock);
1050
1051         gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1052         if (!gpio->regs_res) {
1053                 dev_err(sm->dev, "gpio: failed to request region\n");
1054                 return -ENXIO;
1055         }
1056
1057         gpio->regs = ioremap(iobase, 0x20);
1058         if (!gpio->regs) {
1059                 dev_err(sm->dev, "gpio: failed to remap registers\n");
1060                 ret = -ENXIO;
1061                 goto err_claimed;
1062         }
1063
1064         /* Register both our chips. */
1065
1066         ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1067         if (ret) {
1068                 dev_err(sm->dev, "failed to add low chip\n");
1069                 goto err_mapped;
1070         }
1071
1072         ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1073         if (ret) {
1074                 dev_err(sm->dev, "failed to add high chip\n");
1075                 goto err_low_chip;
1076         }
1077
1078         gpio->registered = 1;
1079
1080         return 0;
1081
1082  err_low_chip:
1083         gpiochip_remove(&gpio->low.gpio);
1084
1085  err_mapped:
1086         iounmap(gpio->regs);
1087
1088  err_claimed:
1089         release_mem_region(iobase, 0x20);
1090
1091         return ret;
1092 }
1093
1094 static void sm501_gpio_remove(struct sm501_devdata *sm)
1095 {
1096         struct sm501_gpio *gpio = &sm->gpio;
1097         resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1098
1099         if (!sm->gpio.registered)
1100                 return;
1101
1102         gpiochip_remove(&gpio->low.gpio);
1103         gpiochip_remove(&gpio->high.gpio);
1104
1105         iounmap(gpio->regs);
1106         release_mem_region(iobase, 0x20);
1107 }
1108
1109 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1110 {
1111         return sm->gpio.registered;
1112 }
1113 #else
1114 static inline int sm501_register_gpio(struct sm501_devdata *sm)
1115 {
1116         return 0;
1117 }
1118
1119 static inline void sm501_gpio_remove(struct sm501_devdata *sm)
1120 {
1121 }
1122
1123 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1124 {
1125         return 0;
1126 }
1127 #endif
1128
1129 static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1130                                             struct sm501_platdata_gpio_i2c *iic)
1131 {
1132         struct i2c_gpio_platform_data *icd;
1133         struct platform_device *pdev;
1134         struct gpiod_lookup_table *lookup;
1135
1136         pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1137                                    sizeof(struct i2c_gpio_platform_data));
1138         if (!pdev)
1139                 return -ENOMEM;
1140
1141         /* Create a gpiod lookup using gpiochip-local offsets */
1142         lookup = devm_kzalloc(&pdev->dev, struct_size(lookup, table, 3),
1143                               GFP_KERNEL);
1144         if (!lookup)
1145                 return -ENOMEM;
1146
1147         lookup->dev_id = "i2c-gpio";
1148         lookup->table[0] = (struct gpiod_lookup)
1149                 GPIO_LOOKUP_IDX(iic->pin_sda < 32 ? "SM501-LOW" : "SM501-HIGH",
1150                                 iic->pin_sda % 32, NULL, 0,
1151                                 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN);
1152         lookup->table[1] = (struct gpiod_lookup)
1153                 GPIO_LOOKUP_IDX(iic->pin_scl < 32 ? "SM501-LOW" : "SM501-HIGH",
1154                                 iic->pin_scl % 32, NULL, 1,
1155                                 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN);
1156         gpiod_add_lookup_table(lookup);
1157
1158         icd = dev_get_platdata(&pdev->dev);
1159         icd->timeout = iic->timeout;
1160         icd->udelay = iic->udelay;
1161
1162         /* note, we can't use either of the pin numbers, as the i2c-gpio
1163          * driver uses the platform.id field to generate the bus number
1164          * to register with the i2c core; The i2c core doesn't have enough
1165          * entries to deal with anything we currently use.
1166         */
1167
1168         pdev->id = iic->bus_num;
1169
1170         dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n",
1171                  iic->bus_num,
1172                  iic->pin_sda, iic->pin_scl);
1173
1174         return sm501_register_device(sm, pdev);
1175 }
1176
1177 static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1178                                    struct sm501_platdata *pdata)
1179 {
1180         struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1181         int index;
1182         int ret;
1183
1184         for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1185                 ret = sm501_register_gpio_i2c_instance(sm, iic);
1186                 if (ret < 0)
1187                         return ret;
1188         }
1189
1190         return 0;
1191 }
1192
1193 /* dbg_regs_show
1194  *
1195  * Debug attribute to attach to parent device to show core registers
1196 */
1197
1198 static ssize_t dbg_regs_show(struct device *dev,
1199                              struct device_attribute *attr, char *buff)
1200 {
1201         struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1202         unsigned int reg;
1203         char *ptr = buff;
1204         int ret;
1205
1206         for (reg = 0x00; reg < 0x70; reg += 4) {
1207                 ret = sprintf(ptr, "%08x = %08x\n",
1208                               reg, smc501_readl(sm->regs + reg));
1209                 ptr += ret;
1210         }
1211
1212         return ptr - buff;
1213 }
1214
1215
1216 static DEVICE_ATTR_RO(dbg_regs);
1217
1218 /* sm501_init_reg
1219  *
1220  * Helper function for the init code to setup a register
1221  *
1222  * clear the bits which are set in r->mask, and then set
1223  * the bits set in r->set.
1224 */
1225
1226 static inline void sm501_init_reg(struct sm501_devdata *sm,
1227                                   unsigned long reg,
1228                                   struct sm501_reg_init *r)
1229 {
1230         unsigned long tmp;
1231
1232         tmp = smc501_readl(sm->regs + reg);
1233         tmp &= ~r->mask;
1234         tmp |= r->set;
1235         smc501_writel(tmp, sm->regs + reg);
1236 }
1237
1238 /* sm501_init_regs
1239  *
1240  * Setup core register values
1241 */
1242
1243 static void sm501_init_regs(struct sm501_devdata *sm,
1244                             struct sm501_initdata *init)
1245 {
1246         sm501_misc_control(sm->dev,
1247                            init->misc_control.set,
1248                            init->misc_control.mask);
1249
1250         sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1251         sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1252         sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1253
1254         if (init->m1xclk) {
1255                 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1256                 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1257         }
1258
1259         if (init->mclk) {
1260                 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1261                 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1262         }
1263
1264 }
1265
1266 /* Check the PLL sources for the M1CLK and M1XCLK
1267  *
1268  * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1269  * there is a risk (see errata AB-5) that the SM501 will cease proper
1270  * function. If this happens, then it is likely the SM501 will
1271  * hang the system.
1272 */
1273
1274 static int sm501_check_clocks(struct sm501_devdata *sm)
1275 {
1276         unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
1277         unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1278         unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1279
1280         return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1281 }
1282
1283 static unsigned int sm501_mem_local[] = {
1284         [0]     = 4*1024*1024,
1285         [1]     = 8*1024*1024,
1286         [2]     = 16*1024*1024,
1287         [3]     = 32*1024*1024,
1288         [4]     = 64*1024*1024,
1289         [5]     = 2*1024*1024,
1290 };
1291
1292 /* sm501_init_dev
1293  *
1294  * Common init code for an SM501
1295 */
1296
1297 static int sm501_init_dev(struct sm501_devdata *sm)
1298 {
1299         struct sm501_initdata *idata;
1300         struct sm501_platdata *pdata;
1301         resource_size_t mem_avail;
1302         unsigned long dramctrl;
1303         unsigned long devid;
1304         int ret;
1305
1306         mutex_init(&sm->clock_lock);
1307         spin_lock_init(&sm->reg_lock);
1308
1309         INIT_LIST_HEAD(&sm->devices);
1310
1311         devid = smc501_readl(sm->regs + SM501_DEVICEID);
1312
1313         if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1314                 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1315                 return -EINVAL;
1316         }
1317
1318         /* disable irqs */
1319         smc501_writel(0, sm->regs + SM501_IRQ_MASK);
1320
1321         dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
1322         mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1323
1324         dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1325                  sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1326
1327         sm->rev = devid & SM501_DEVICEID_REVMASK;
1328
1329         sm501_dump_gate(sm);
1330
1331         ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1332         if (ret)
1333                 dev_err(sm->dev, "failed to create debug regs file\n");
1334
1335         sm501_dump_clk(sm);
1336
1337         /* check to see if we have some device initialisation */
1338
1339         pdata = sm->platdata;
1340         idata = pdata ? pdata->init : NULL;
1341
1342         if (idata) {
1343                 sm501_init_regs(sm, idata);
1344
1345                 if (idata->devices & SM501_USE_USB_HOST)
1346                         sm501_register_usbhost(sm, &mem_avail);
1347                 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1348                         sm501_register_uart(sm, idata->devices);
1349                 if (idata->devices & SM501_USE_GPIO)
1350                         sm501_register_gpio(sm);
1351         }
1352
1353         if (pdata && pdata->gpio_i2c && pdata->gpio_i2c_nr > 0) {
1354                 if (!sm501_gpio_isregistered(sm))
1355                         dev_err(sm->dev, "no gpio available for i2c gpio.\n");
1356                 else
1357                         sm501_register_gpio_i2c(sm, pdata);
1358         }
1359
1360         ret = sm501_check_clocks(sm);
1361         if (ret) {
1362                 dev_err(sm->dev, "M1X and M clocks sourced from different "
1363                                         "PLLs\n");
1364                 return -EINVAL;
1365         }
1366
1367         /* always create a framebuffer */
1368         sm501_register_display(sm, &mem_avail);
1369
1370         return 0;
1371 }
1372
1373 static int sm501_plat_probe(struct platform_device *dev)
1374 {
1375         struct sm501_devdata *sm;
1376         int ret;
1377
1378         sm = kzalloc(sizeof(*sm), GFP_KERNEL);
1379         if (!sm) {
1380                 ret = -ENOMEM;
1381                 goto err1;
1382         }
1383
1384         sm->dev = &dev->dev;
1385         sm->pdev_id = dev->id;
1386         sm->platdata = dev_get_platdata(&dev->dev);
1387
1388         ret = platform_get_irq(dev, 0);
1389         if (ret < 0)
1390                 goto err_res;
1391         sm->irq = ret;
1392
1393         sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1394         sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1395         if (!sm->io_res || !sm->mem_res) {
1396                 dev_err(&dev->dev, "failed to get IO resource\n");
1397                 ret = -ENOENT;
1398                 goto err_res;
1399         }
1400
1401         sm->regs_claim = request_mem_region(sm->io_res->start,
1402                                             0x100, "sm501");
1403         if (!sm->regs_claim) {
1404                 dev_err(&dev->dev, "cannot claim registers\n");
1405                 ret = -EBUSY;
1406                 goto err_res;
1407         }
1408
1409         platform_set_drvdata(dev, sm);
1410
1411         sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
1412         if (!sm->regs) {
1413                 dev_err(&dev->dev, "cannot remap registers\n");
1414                 ret = -EIO;
1415                 goto err_claim;
1416         }
1417
1418         ret = sm501_init_dev(sm);
1419         if (ret)
1420                 goto err_unmap;
1421
1422         return 0;
1423
1424  err_unmap:
1425         iounmap(sm->regs);
1426  err_claim:
1427         release_mem_region(sm->io_res->start, 0x100);
1428  err_res:
1429         kfree(sm);
1430  err1:
1431         return ret;
1432
1433 }
1434
1435 #ifdef CONFIG_PM
1436
1437 /* power management support */
1438
1439 static void sm501_set_power(struct sm501_devdata *sm, int on)
1440 {
1441         struct sm501_platdata *pd = sm->platdata;
1442
1443         if (!pd)
1444                 return;
1445
1446         if (pd->get_power) {
1447                 if (pd->get_power(sm->dev) == on) {
1448                         dev_dbg(sm->dev, "is already %d\n", on);
1449                         return;
1450                 }
1451         }
1452
1453         if (pd->set_power) {
1454                 dev_dbg(sm->dev, "setting power to %d\n", on);
1455
1456                 pd->set_power(sm->dev, on);
1457                 sm501_mdelay(sm, 10);
1458         }
1459 }
1460
1461 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1462 {
1463         struct sm501_devdata *sm = platform_get_drvdata(pdev);
1464
1465         sm->in_suspend = 1;
1466         sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
1467
1468         sm501_dump_regs(sm);
1469
1470         if (sm->platdata) {
1471                 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1472                         sm501_set_power(sm, 0);
1473         }
1474
1475         return 0;
1476 }
1477
1478 static int sm501_plat_resume(struct platform_device *pdev)
1479 {
1480         struct sm501_devdata *sm = platform_get_drvdata(pdev);
1481
1482         sm501_set_power(sm, 1);
1483
1484         sm501_dump_regs(sm);
1485         sm501_dump_gate(sm);
1486         sm501_dump_clk(sm);
1487
1488         /* check to see if we are in the same state as when suspended */
1489
1490         if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1491                 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1492                 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1493
1494                 /* our suspend causes the controller state to change,
1495                  * either by something attempting setup, power loss,
1496                  * or an external reset event on power change */
1497
1498                 if (sm->platdata && sm->platdata->init) {
1499                         sm501_init_regs(sm, sm->platdata->init);
1500                 }
1501         }
1502
1503         /* dump our state from resume */
1504
1505         sm501_dump_regs(sm);
1506         sm501_dump_clk(sm);
1507
1508         sm->in_suspend = 0;
1509
1510         return 0;
1511 }
1512 #else
1513 #define sm501_plat_suspend NULL
1514 #define sm501_plat_resume NULL
1515 #endif
1516
1517 /* Initialisation data for PCI devices */
1518
1519 static struct sm501_initdata sm501_pci_initdata = {
1520         .gpio_high      = {
1521                 .set    = 0x3F000000,           /* 24bit panel */
1522                 .mask   = 0x0,
1523         },
1524         .misc_timing    = {
1525                 .set    = 0x010100,             /* SDRAM timing */
1526                 .mask   = 0x1F1F00,
1527         },
1528         .misc_control   = {
1529                 .set    = SM501_MISC_PNL_24BIT,
1530                 .mask   = 0,
1531         },
1532
1533         .devices        = SM501_USE_ALL,
1534
1535         /* Errata AB-3 says that 72MHz is the fastest available
1536          * for 33MHZ PCI with proper bus-mastering operation */
1537
1538         .mclk           = 72 * MHZ,
1539         .m1xclk         = 144 * MHZ,
1540 };
1541
1542 static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1543         .flags          = (SM501FB_FLAG_USE_INIT_MODE |
1544                            SM501FB_FLAG_USE_HWCURSOR |
1545                            SM501FB_FLAG_USE_HWACCEL |
1546                            SM501FB_FLAG_DISABLE_AT_EXIT),
1547 };
1548
1549 static struct sm501_platdata_fb sm501_fb_pdata = {
1550         .fb_route       = SM501_FB_OWN,
1551         .fb_crt         = &sm501_pdata_fbsub,
1552         .fb_pnl         = &sm501_pdata_fbsub,
1553 };
1554
1555 static struct sm501_platdata sm501_pci_platdata = {
1556         .init           = &sm501_pci_initdata,
1557         .fb             = &sm501_fb_pdata,
1558         .gpio_base      = -1,
1559 };
1560
1561 static int sm501_pci_probe(struct pci_dev *dev,
1562                                      const struct pci_device_id *id)
1563 {
1564         struct sm501_devdata *sm;
1565         int err;
1566
1567         sm = kzalloc(sizeof(*sm), GFP_KERNEL);
1568         if (!sm) {
1569                 err = -ENOMEM;
1570                 goto err1;
1571         }
1572
1573         /* set a default set of platform data */
1574         dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1575
1576         /* set a hopefully unique id for our child platform devices */
1577         sm->pdev_id = 32 + dev->devfn;
1578
1579         pci_set_drvdata(dev, sm);
1580
1581         err = pci_enable_device(dev);
1582         if (err) {
1583                 dev_err(&dev->dev, "cannot enable device\n");
1584                 goto err2;
1585         }
1586
1587         sm->dev = &dev->dev;
1588         sm->irq = dev->irq;
1589
1590 #ifdef __BIG_ENDIAN
1591         /* if the system is big-endian, we most probably have a
1592          * translation in the IO layer making the PCI bus little endian
1593          * so make the framebuffer swapped pixels */
1594
1595         sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1596 #endif
1597
1598         /* check our resources */
1599
1600         if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1601                 dev_err(&dev->dev, "region #0 is not memory?\n");
1602                 err = -EINVAL;
1603                 goto err3;
1604         }
1605
1606         if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1607                 dev_err(&dev->dev, "region #1 is not memory?\n");
1608                 err = -EINVAL;
1609                 goto err3;
1610         }
1611
1612         /* make our resources ready for sharing */
1613
1614         sm->io_res = &dev->resource[1];
1615         sm->mem_res = &dev->resource[0];
1616
1617         sm->regs_claim = request_mem_region(sm->io_res->start,
1618                                             0x100, "sm501");
1619         if (!sm->regs_claim) {
1620                 dev_err(&dev->dev, "cannot claim registers\n");
1621                 err= -EBUSY;
1622                 goto err3;
1623         }
1624
1625         sm->regs = pci_ioremap_bar(dev, 1);
1626         if (!sm->regs) {
1627                 dev_err(&dev->dev, "cannot remap registers\n");
1628                 err = -EIO;
1629                 goto err4;
1630         }
1631
1632         sm501_init_dev(sm);
1633         return 0;
1634
1635  err4:
1636         release_mem_region(sm->io_res->start, 0x100);
1637  err3:
1638         pci_disable_device(dev);
1639  err2:
1640         kfree(sm);
1641  err1:
1642         return err;
1643 }
1644
1645 static void sm501_remove_sub(struct sm501_devdata *sm,
1646                              struct sm501_device *smdev)
1647 {
1648         list_del(&smdev->list);
1649         platform_device_unregister(&smdev->pdev);
1650 }
1651
1652 static void sm501_dev_remove(struct sm501_devdata *sm)
1653 {
1654         struct sm501_device *smdev, *tmp;
1655
1656         list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1657                 sm501_remove_sub(sm, smdev);
1658
1659         device_remove_file(sm->dev, &dev_attr_dbg_regs);
1660
1661         sm501_gpio_remove(sm);
1662 }
1663
1664 static void sm501_pci_remove(struct pci_dev *dev)
1665 {
1666         struct sm501_devdata *sm = pci_get_drvdata(dev);
1667
1668         sm501_dev_remove(sm);
1669         iounmap(sm->regs);
1670
1671         release_mem_region(sm->io_res->start, 0x100);
1672
1673         pci_disable_device(dev);
1674 }
1675
1676 static int sm501_plat_remove(struct platform_device *dev)
1677 {
1678         struct sm501_devdata *sm = platform_get_drvdata(dev);
1679
1680         sm501_dev_remove(sm);
1681         iounmap(sm->regs);
1682
1683         release_mem_region(sm->io_res->start, 0x100);
1684
1685         return 0;
1686 }
1687
1688 static const struct pci_device_id sm501_pci_tbl[] = {
1689         { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1690         { 0, },
1691 };
1692
1693 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1694
1695 static struct pci_driver sm501_pci_driver = {
1696         .name           = "sm501",
1697         .id_table       = sm501_pci_tbl,
1698         .probe          = sm501_pci_probe,
1699         .remove         = sm501_pci_remove,
1700 };
1701
1702 MODULE_ALIAS("platform:sm501");
1703
1704 static const struct of_device_id of_sm501_match_tbl[] = {
1705         { .compatible = "smi,sm501", },
1706         { /* end */ }
1707 };
1708 MODULE_DEVICE_TABLE(of, of_sm501_match_tbl);
1709
1710 static struct platform_driver sm501_plat_driver = {
1711         .driver         = {
1712                 .name   = "sm501",
1713                 .of_match_table = of_sm501_match_tbl,
1714         },
1715         .probe          = sm501_plat_probe,
1716         .remove         = sm501_plat_remove,
1717         .suspend        = sm501_plat_suspend,
1718         .resume         = sm501_plat_resume,
1719 };
1720
1721 static int __init sm501_base_init(void)
1722 {
1723         platform_driver_register(&sm501_plat_driver);
1724         return pci_register_driver(&sm501_pci_driver);
1725 }
1726
1727 static void __exit sm501_base_exit(void)
1728 {
1729         platform_driver_unregister(&sm501_plat_driver);
1730         pci_unregister_driver(&sm501_pci_driver);
1731 }
1732
1733 module_init(sm501_base_init);
1734 module_exit(sm501_base_exit);
1735
1736 MODULE_DESCRIPTION("SM501 Core Driver");
1737 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1738 MODULE_LICENSE("GPL v2");