2 * Core driver access RC5T583 power management chip.
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * Author: Laxman dewangan <ldewangan@nvidia.com>
8 * Copyright (C) 2011 RICOH COMPANY,LTD
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/err.h>
29 #include <linux/slab.h>
30 #include <linux/i2c.h>
31 #include <linux/mfd/core.h>
32 #include <linux/mfd/rc5t583.h>
33 #include <linux/regmap.h>
35 #define RICOH_ONOFFSEL_REG 0x10
36 #define RICOH_SWCTL_REG 0x5E
38 struct deepsleep_control_data {
43 #define DEEPSLEEP_INIT(_id, _reg, _pos) \
45 .reg_add = RC5T583_##_reg, \
49 static struct deepsleep_control_data deepsleep_data[] = {
50 DEEPSLEEP_INIT(DC0, SLPSEQ1, 0),
51 DEEPSLEEP_INIT(DC1, SLPSEQ1, 4),
52 DEEPSLEEP_INIT(DC2, SLPSEQ2, 0),
53 DEEPSLEEP_INIT(DC3, SLPSEQ2, 4),
54 DEEPSLEEP_INIT(LDO0, SLPSEQ3, 0),
55 DEEPSLEEP_INIT(LDO1, SLPSEQ3, 4),
56 DEEPSLEEP_INIT(LDO2, SLPSEQ4, 0),
57 DEEPSLEEP_INIT(LDO3, SLPSEQ4, 4),
58 DEEPSLEEP_INIT(LDO4, SLPSEQ5, 0),
59 DEEPSLEEP_INIT(LDO5, SLPSEQ5, 4),
60 DEEPSLEEP_INIT(LDO6, SLPSEQ6, 0),
61 DEEPSLEEP_INIT(LDO7, SLPSEQ6, 4),
62 DEEPSLEEP_INIT(LDO8, SLPSEQ7, 0),
63 DEEPSLEEP_INIT(LDO9, SLPSEQ7, 4),
64 DEEPSLEEP_INIT(PSO0, SLPSEQ8, 0),
65 DEEPSLEEP_INIT(PSO1, SLPSEQ8, 4),
66 DEEPSLEEP_INIT(PSO2, SLPSEQ9, 0),
67 DEEPSLEEP_INIT(PSO3, SLPSEQ9, 4),
68 DEEPSLEEP_INIT(PSO4, SLPSEQ10, 0),
69 DEEPSLEEP_INIT(PSO5, SLPSEQ10, 4),
70 DEEPSLEEP_INIT(PSO6, SLPSEQ11, 0),
71 DEEPSLEEP_INIT(PSO7, SLPSEQ11, 4),
75 (RC5T583_EXT_PWRREQ1_CONTROL | RC5T583_EXT_PWRREQ2_CONTROL)
77 static struct mfd_cell rc5t583_subdevs[] = {
78 {.name = "rc5t583-regulator",},
79 {.name = "rc5t583-rtc", },
80 {.name = "rc5t583-key", }
83 static int __rc5t583_set_ext_pwrreq1_control(struct device *dev,
84 int id, int ext_pwr, int slots)
89 unsigned int slot_bit;
91 if (id == RC5T583_DS_DC0) {
92 dev_err(dev, "PWRREQ1 is invalid control for rail %d\n", id);
96 en_bit = deepsleep_data[id].ds_pos_bit;
97 slot_bit = en_bit + 1;
98 ret = rc5t583_read(dev, deepsleep_data[id].reg_add, &sleepseq_val);
100 dev_err(dev, "Error in reading reg 0x%x\n",
101 deepsleep_data[id].reg_add);
105 sleepseq_val &= ~(0xF << en_bit);
106 sleepseq_val |= BIT(en_bit);
107 sleepseq_val |= ((slots & 0x7) << slot_bit);
108 ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(1));
110 dev_err(dev, "Error in updating the 0x%02x register\n",
115 ret = rc5t583_write(dev, deepsleep_data[id].reg_add, sleepseq_val);
117 dev_err(dev, "Error in writing reg 0x%x\n",
118 deepsleep_data[id].reg_add);
122 if (id == RC5T583_DS_LDO4) {
123 ret = rc5t583_write(dev, RICOH_SWCTL_REG, 0x1);
125 dev_err(dev, "Error in writing reg 0x%x\n",
131 static int __rc5t583_set_ext_pwrreq2_control(struct device *dev,
136 if (id != RC5T583_DS_DC0) {
137 dev_err(dev, "PWRREQ2 is invalid control for rail %d\n", id);
141 ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(2));
143 dev_err(dev, "Error in updating the ONOFFSEL 0x10 register\n");
147 int rc5t583_ext_power_req_config(struct device *dev, int ds_id,
148 int ext_pwr_req, int deepsleep_slot_nr)
150 if ((ext_pwr_req & EXT_PWR_REQ) == EXT_PWR_REQ)
153 if (ext_pwr_req & RC5T583_EXT_PWRREQ1_CONTROL)
154 return __rc5t583_set_ext_pwrreq1_control(dev, ds_id,
155 ext_pwr_req, deepsleep_slot_nr);
157 if (ext_pwr_req & RC5T583_EXT_PWRREQ2_CONTROL)
158 return __rc5t583_set_ext_pwrreq2_control(dev,
162 EXPORT_SYMBOL(rc5t583_ext_power_req_config);
164 static int rc5t583_clear_ext_power_req(struct rc5t583 *rc5t583,
165 struct rc5t583_platform_data *pdata)
169 uint8_t on_off_val = 0;
171 /* Clear ONOFFSEL register */
172 if (pdata->enable_shutdown)
175 ret = rc5t583_write(rc5t583->dev, RICOH_ONOFFSEL_REG, on_off_val);
177 dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
178 RICOH_ONOFFSEL_REG, ret);
180 ret = rc5t583_write(rc5t583->dev, RICOH_SWCTL_REG, 0x0);
182 dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
183 RICOH_SWCTL_REG, ret);
185 /* Clear sleep sequence register */
186 for (i = RC5T583_SLPSEQ1; i <= RC5T583_SLPSEQ11; ++i) {
187 ret = rc5t583_write(rc5t583->dev, i, 0x0);
189 dev_warn(rc5t583->dev,
190 "Error in writing reg 0x%02x error: %d\n",
196 static bool volatile_reg(struct device *dev, unsigned int reg)
198 /* Enable caching in interrupt registers */
200 case RC5T583_INT_EN_SYS1:
201 case RC5T583_INT_EN_SYS2:
202 case RC5T583_INT_EN_DCDC:
203 case RC5T583_INT_EN_RTC:
204 case RC5T583_INT_EN_ADC1:
205 case RC5T583_INT_EN_ADC2:
206 case RC5T583_INT_EN_ADC3:
207 case RC5T583_GPIO_GPEDGE1:
208 case RC5T583_GPIO_GPEDGE2:
209 case RC5T583_GPIO_EN_INT:
212 case RC5T583_GPIO_MON_IOIN:
213 /* This is gpio input register */
217 /* Enable caching in gpio registers */
218 if ((reg >= RC5T583_GPIO_IOSEL) &&
219 (reg <= RC5T583_GPIO_GPOFUNC))
222 /* Enable caching in sleep seq registers */
223 if ((reg >= RC5T583_SLPSEQ1) && (reg <= RC5T583_SLPSEQ11))
226 /* Enable caching of regulator registers */
227 if ((reg >= RC5T583_REG_DC0CTL) && (reg <= RC5T583_REG_SR3CTL))
229 if ((reg >= RC5T583_REG_LDOEN1) &&
230 (reg <= RC5T583_REG_LDO9DAC_DS))
239 static const struct regmap_config rc5t583_regmap_config = {
242 .volatile_reg = volatile_reg,
243 .max_register = RC5T583_MAX_REGS,
244 .num_reg_defaults_raw = RC5T583_MAX_REGS,
245 .cache_type = REGCACHE_RBTREE,
248 static int __devinit rc5t583_i2c_probe(struct i2c_client *i2c,
249 const struct i2c_device_id *id)
251 struct rc5t583 *rc5t583;
252 struct rc5t583_platform_data *pdata = i2c->dev.platform_data;
254 bool irq_init_success = false;
257 dev_err(&i2c->dev, "Err: Platform data not found\n");
261 rc5t583 = devm_kzalloc(&i2c->dev, sizeof(struct rc5t583), GFP_KERNEL);
263 dev_err(&i2c->dev, "Memory allocation failed\n");
267 rc5t583->dev = &i2c->dev;
268 i2c_set_clientdata(i2c, rc5t583);
270 rc5t583->regmap = regmap_init_i2c(i2c, &rc5t583_regmap_config);
271 if (IS_ERR(rc5t583->regmap)) {
272 ret = PTR_ERR(rc5t583->regmap);
273 dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
277 ret = rc5t583_clear_ext_power_req(rc5t583, pdata);
282 ret = rc5t583_irq_init(rc5t583, i2c->irq, pdata->irq_base);
283 /* Still continue with waring if irq init fails */
285 dev_warn(&i2c->dev, "IRQ init failed: %d\n", ret);
287 irq_init_success = true;
290 ret = mfd_add_devices(rc5t583->dev, -1, rc5t583_subdevs,
291 ARRAY_SIZE(rc5t583_subdevs), NULL, 0);
293 dev_err(&i2c->dev, "add mfd devices failed: %d\n", ret);
300 if (irq_init_success)
301 rc5t583_irq_exit(rc5t583);
303 regmap_exit(rc5t583->regmap);
307 static int __devexit rc5t583_i2c_remove(struct i2c_client *i2c)
309 struct rc5t583 *rc5t583 = i2c_get_clientdata(i2c);
311 mfd_remove_devices(rc5t583->dev);
312 rc5t583_irq_exit(rc5t583);
313 regmap_exit(rc5t583->regmap);
317 static const struct i2c_device_id rc5t583_i2c_id[] = {
318 {.name = "rc5t583", .driver_data = 0},
322 MODULE_DEVICE_TABLE(i2c, rc5t583_i2c_id);
324 static struct i2c_driver rc5t583_i2c_driver = {
327 .owner = THIS_MODULE,
329 .probe = rc5t583_i2c_probe,
330 .remove = __devexit_p(rc5t583_i2c_remove),
331 .id_table = rc5t583_i2c_id,
334 static int __init rc5t583_i2c_init(void)
336 return i2c_add_driver(&rc5t583_i2c_driver);
338 subsys_initcall(rc5t583_i2c_init);
340 static void __exit rc5t583_i2c_exit(void)
342 i2c_del_driver(&rc5t583_i2c_driver);
345 module_exit(rc5t583_i2c_exit);
347 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
348 MODULE_DESCRIPTION("RICOH RC5T583 power management system device driver");
349 MODULE_LICENSE("GPL v2");