drivers/mfd/qcom-pm8008.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/i2c.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/irq.h>
  10 #include <linux/irqdomain.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/pinctrl/consumer.h>
  15 #include <linux/regmap.h>
  16 #include <linux/slab.h>
  17
  18 #include <dt-bindings/mfd/qcom-pm8008.h>
  19
  20 #define I2C_INTR_STATUS_BASE            0x0550
  21 #define INT_RT_STS_OFFSET               0x10
  22 #define INT_SET_TYPE_OFFSET             0x11
  23 #define INT_POL_HIGH_OFFSET             0x12
  24 #define INT_POL_LOW_OFFSET              0x13
  25 #define INT_LATCHED_CLR_OFFSET          0x14
  26 #define INT_EN_SET_OFFSET               0x15
  27 #define INT_EN_CLR_OFFSET               0x16
  28 #define INT_LATCHED_STS_OFFSET          0x18
  29
  30 enum {
  31         PM8008_MISC,
  32         PM8008_TEMP_ALARM,
  33         PM8008_GPIO1,
  34         PM8008_GPIO2,
  35         PM8008_NUM_PERIPHS,
  36 };
  37
  38 #define PM8008_PERIPH_0_BASE    0x900
  39 #define PM8008_PERIPH_1_BASE    0x2400
  40 #define PM8008_PERIPH_2_BASE    0xC000
  41 #define PM8008_PERIPH_3_BASE    0xC100
  42
  43 #define PM8008_TEMP_ALARM_ADDR  PM8008_PERIPH_1_BASE
  44 #define PM8008_GPIO1_ADDR       PM8008_PERIPH_2_BASE
  45 #define PM8008_GPIO2_ADDR       PM8008_PERIPH_3_BASE
  46
  47 #define PM8008_STATUS_BASE      (PM8008_PERIPH_0_BASE | INT_LATCHED_STS_OFFSET)
  48 #define PM8008_MASK_BASE        (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET)
  49 #define PM8008_UNMASK_BASE      (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET)
  50 #define PM8008_TYPE_BASE        (PM8008_PERIPH_0_BASE | INT_SET_TYPE_OFFSET)
  51 #define PM8008_ACK_BASE         (PM8008_PERIPH_0_BASE | INT_LATCHED_CLR_OFFSET)
  52 #define PM8008_POLARITY_HI_BASE (PM8008_PERIPH_0_BASE | INT_POL_HIGH_OFFSET)
  53 #define PM8008_POLARITY_LO_BASE (PM8008_PERIPH_0_BASE | INT_POL_LOW_OFFSET)
  54
  55 #define PM8008_PERIPH_OFFSET(paddr)     (paddr - PM8008_PERIPH_0_BASE)
  56
  57 static unsigned int p0_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_0_BASE)};
  58 static unsigned int p1_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_1_BASE)};
  59 static unsigned int p2_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_2_BASE)};
  60 static unsigned int p3_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_3_BASE)};
  61
  62 static struct regmap_irq_sub_irq_map pm8008_sub_reg_offsets[] = {
  63         REGMAP_IRQ_MAIN_REG_OFFSET(p0_offs),
  64         REGMAP_IRQ_MAIN_REG_OFFSET(p1_offs),
  65         REGMAP_IRQ_MAIN_REG_OFFSET(p2_offs),
  66         REGMAP_IRQ_MAIN_REG_OFFSET(p3_offs),
  67 };
  68
  69 static unsigned int pm8008_virt_regs[] = {
  70         PM8008_POLARITY_HI_BASE,
  71         PM8008_POLARITY_LO_BASE,
  72 };
  73
  74 enum {
  75         POLARITY_HI_INDEX,
  76         POLARITY_LO_INDEX,
  77         PM8008_NUM_VIRT_REGS,
  78 };
  79
  80 static struct regmap_irq pm8008_irqs[] = {
  81         REGMAP_IRQ_REG(PM8008_IRQ_MISC_UVLO,    PM8008_MISC,    BIT(0)),
  82         REGMAP_IRQ_REG(PM8008_IRQ_MISC_OVLO,    PM8008_MISC,    BIT(1)),
  83         REGMAP_IRQ_REG(PM8008_IRQ_MISC_OTST2,   PM8008_MISC,    BIT(2)),
  84         REGMAP_IRQ_REG(PM8008_IRQ_MISC_OTST3,   PM8008_MISC,    BIT(3)),
  85         REGMAP_IRQ_REG(PM8008_IRQ_MISC_LDO_OCP, PM8008_MISC,    BIT(4)),
  86         REGMAP_IRQ_REG(PM8008_IRQ_TEMP_ALARM,   PM8008_TEMP_ALARM, BIT(0)),
  87         REGMAP_IRQ_REG(PM8008_IRQ_GPIO1,        PM8008_GPIO1,   BIT(0)),
  88         REGMAP_IRQ_REG(PM8008_IRQ_GPIO2,        PM8008_GPIO2,   BIT(0)),
  89 };
  90
  91 static int pm8008_set_type_virt(unsigned int **virt_buf,
  92                                       unsigned int type, unsigned long hwirq,
  93                                       int reg)
  94 {
  95         switch (type) {
  96         case IRQ_TYPE_EDGE_FALLING:
  97         case IRQ_TYPE_LEVEL_LOW:
  98                 virt_buf[POLARITY_HI_INDEX][reg] &= ~pm8008_irqs[hwirq].mask;
  99                 virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask;
 100                 break;
 101
 102         case IRQ_TYPE_EDGE_RISING:
 103         case IRQ_TYPE_LEVEL_HIGH:
 104                 virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask;
 105                 virt_buf[POLARITY_LO_INDEX][reg] &= ~pm8008_irqs[hwirq].mask;
 106                 break;
 107
 108         case IRQ_TYPE_EDGE_BOTH:
 109                 virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask;
 110                 virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask;
 111                 break;
 112
 113         default:
 114                 return -EINVAL;
 115         }
 116
 117         return 0;
 118 }
 119
 120 static struct regmap_irq_chip pm8008_irq_chip = {
 121         .name                   = "pm8008_irq",
 122         .main_status            = I2C_INTR_STATUS_BASE,
 123         .num_main_regs          = 1,
 124         .num_virt_regs          = PM8008_NUM_VIRT_REGS,
 125         .irqs                   = pm8008_irqs,
 126         .num_irqs               = ARRAY_SIZE(pm8008_irqs),
 127         .num_regs               = PM8008_NUM_PERIPHS,
 128         .not_fixed_stride       = true,
 129         .sub_reg_offsets        = pm8008_sub_reg_offsets,
 130         .set_type_virt          = pm8008_set_type_virt,
 131         .status_base            = PM8008_STATUS_BASE,
 132         .mask_base              = PM8008_MASK_BASE,
 133         .unmask_base            = PM8008_UNMASK_BASE,
 134         .type_base              = PM8008_TYPE_BASE,
 135         .ack_base               = PM8008_ACK_BASE,
 136         .virt_reg_base          = pm8008_virt_regs,
 137         .num_type_reg           = PM8008_NUM_PERIPHS,
 138 };
 139
 140 static struct regmap_config qcom_mfd_regmap_cfg = {
 141         .reg_bits       = 16,
 142         .val_bits       = 8,
 143         .max_register   = 0xFFFF,
 144 };
 145
 146 static int pm8008_init(struct regmap *regmap)
 147 {
 148         int rc;
 149
 150         /*
 151          * Set TEMP_ALARM peripheral's TYPE so that the regmap-irq framework
 152          * reads this as the default value instead of zero, the HW default.
 153          * This is required to enable the writing of TYPE registers in
 154          * regmap_irq_sync_unlock().
 155          */
 156         rc = regmap_write(regmap, (PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
 157         if (rc)
 158                 return rc;
 159
 160         /* Do the same for GPIO1 and GPIO2 peripherals */
 161         rc = regmap_write(regmap, (PM8008_GPIO1_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
 162         if (rc)
 163                 return rc;
 164
 165         rc = regmap_write(regmap, (PM8008_GPIO2_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
 166
 167         return rc;
 168 }
 169
 170 static int pm8008_probe_irq_peripherals(struct device *dev,
 171                                         struct regmap *regmap,
 172                                         int client_irq)
 173 {
 174         int rc, i;
 175         struct regmap_irq_type *type;
 176         struct regmap_irq_chip_data *irq_data;
 177
 178         rc = pm8008_init(regmap);
 179         if (rc) {
 180                 dev_err(dev, "Init failed: %d\n", rc);
 181                 return rc;
 182         }
 183
 184         for (i = 0; i < ARRAY_SIZE(pm8008_irqs); i++) {
 185                 type = &pm8008_irqs[i].type;
 186
 187                 type->type_reg_offset     = pm8008_irqs[i].reg_offset;
 188                 type->type_rising_val     = pm8008_irqs[i].mask;
 189                 type->type_falling_val    = pm8008_irqs[i].mask;
 190                 type->type_level_high_val = 0;
 191                 type->type_level_low_val  = 0;
 192
 193                 if (type->type_reg_offset == PM8008_MISC)
 194                         type->types_supported = IRQ_TYPE_EDGE_RISING;
 195                 else
 196                         type->types_supported = (IRQ_TYPE_EDGE_BOTH |
 197                                 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW);
 198         }
 199
 200         rc = devm_regmap_add_irq_chip(dev, regmap, client_irq,
 201                         IRQF_SHARED, 0, &pm8008_irq_chip, &irq_data);
 202         if (rc) {
 203                 dev_err(dev, "Failed to add IRQ chip: %d\n", rc);
 204                 return rc;
 205         }
 206
 207         return 0;
 208 }
 209
 210 static int pm8008_probe(struct i2c_client *client)
 211 {
 212         int rc;
 213         struct device *dev;
 214         struct regmap *regmap;
 215
 216         dev = &client->dev;
 217         regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg);
 218         if (IS_ERR(regmap))
 219                 return PTR_ERR(regmap);
 220
 221         i2c_set_clientdata(client, regmap);
 222
 223         if (of_property_read_bool(dev->of_node, "interrupt-controller")) {
 224                 rc = pm8008_probe_irq_peripherals(dev, regmap, client->irq);
 225                 if (rc)
 226                         dev_err(dev, "Failed to probe irq periphs: %d\n", rc);
 227         }
 228
 229         return devm_of_platform_populate(dev);
 230 }
 231
 232 static const struct of_device_id pm8008_match[] = {
 233         { .compatible = "qcom,pm8008", },
 234         { },
 235 };
 236
 237 static struct i2c_driver pm8008_mfd_driver = {
 238         .driver = {
 239                 .name = "pm8008",
 240                 .of_match_table = pm8008_match,
 241         },
 242         .probe_new = pm8008_probe,
 243 };
 244 module_i2c_driver(pm8008_mfd_driver);
 245
 246 MODULE_LICENSE("GPL v2");
 247 MODULE_ALIAS("i2c:qcom-pm8008");