1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2012 Texas Instruments Inc.
7 * Author: Graeme Gregory <gg@slimlogic.co.uk>
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/regmap.h>
18 #include <linux/err.h>
19 #include <linux/mfd/core.h>
20 #include <linux/mfd/palmas.h>
21 #include <linux/of_device.h>
23 static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
27 .max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
28 PALMAS_PRIMARY_SECONDARY_PAD3),
33 .max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
34 PALMAS_GPADC_SMPS_VSEL_MONITORING),
39 .max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
44 static const struct regmap_irq tps65917_irqs[] = {
46 [TPS65917_RESERVED1] = {
47 .mask = TPS65917_RESERVED,
49 [TPS65917_PWRON_IRQ] = {
50 .mask = TPS65917_INT1_STATUS_PWRON,
52 [TPS65917_LONG_PRESS_KEY_IRQ] = {
53 .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
55 [TPS65917_RESERVED2] = {
56 .mask = TPS65917_RESERVED,
58 [TPS65917_PWRDOWN_IRQ] = {
59 .mask = TPS65917_INT1_STATUS_PWRDOWN,
61 [TPS65917_HOTDIE_IRQ] = {
62 .mask = TPS65917_INT1_STATUS_HOTDIE,
64 [TPS65917_VSYS_MON_IRQ] = {
65 .mask = TPS65917_INT1_STATUS_VSYS_MON,
67 [TPS65917_RESERVED3] = {
68 .mask = TPS65917_RESERVED,
71 [TPS65917_RESERVED4] = {
72 .mask = TPS65917_RESERVED,
75 [TPS65917_OTP_ERROR_IRQ] = {
76 .mask = TPS65917_INT2_STATUS_OTP_ERROR,
79 [TPS65917_WDT_IRQ] = {
80 .mask = TPS65917_INT2_STATUS_WDT,
83 [TPS65917_RESERVED5] = {
84 .mask = TPS65917_RESERVED,
87 [TPS65917_RESET_IN_IRQ] = {
88 .mask = TPS65917_INT2_STATUS_RESET_IN,
91 [TPS65917_FSD_IRQ] = {
92 .mask = TPS65917_INT2_STATUS_FSD,
95 [TPS65917_SHORT_IRQ] = {
96 .mask = TPS65917_INT2_STATUS_SHORT,
99 [TPS65917_RESERVED6] = {
100 .mask = TPS65917_RESERVED,
104 [TPS65917_GPADC_AUTO_0_IRQ] = {
105 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
108 [TPS65917_GPADC_AUTO_1_IRQ] = {
109 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
112 [TPS65917_GPADC_EOC_SW_IRQ] = {
113 .mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
116 [TPS65917_RESREVED6] = {
117 .mask = TPS65917_RESERVED6,
120 [TPS65917_RESERVED7] = {
121 .mask = TPS65917_RESERVED,
124 [TPS65917_RESERVED8] = {
125 .mask = TPS65917_RESERVED,
128 [TPS65917_RESERVED9] = {
129 .mask = TPS65917_RESERVED,
132 [TPS65917_VBUS_IRQ] = {
133 .mask = TPS65917_INT3_STATUS_VBUS,
137 [TPS65917_GPIO_0_IRQ] = {
138 .mask = TPS65917_INT4_STATUS_GPIO_0,
141 [TPS65917_GPIO_1_IRQ] = {
142 .mask = TPS65917_INT4_STATUS_GPIO_1,
145 [TPS65917_GPIO_2_IRQ] = {
146 .mask = TPS65917_INT4_STATUS_GPIO_2,
149 [TPS65917_GPIO_3_IRQ] = {
150 .mask = TPS65917_INT4_STATUS_GPIO_3,
153 [TPS65917_GPIO_4_IRQ] = {
154 .mask = TPS65917_INT4_STATUS_GPIO_4,
157 [TPS65917_GPIO_5_IRQ] = {
158 .mask = TPS65917_INT4_STATUS_GPIO_5,
161 [TPS65917_GPIO_6_IRQ] = {
162 .mask = TPS65917_INT4_STATUS_GPIO_6,
165 [TPS65917_RESERVED10] = {
166 .mask = TPS65917_RESERVED10,
171 static const struct regmap_irq palmas_irqs[] = {
173 [PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
174 .mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
176 [PALMAS_PWRON_IRQ] = {
177 .mask = PALMAS_INT1_STATUS_PWRON,
179 [PALMAS_LONG_PRESS_KEY_IRQ] = {
180 .mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
182 [PALMAS_RPWRON_IRQ] = {
183 .mask = PALMAS_INT1_STATUS_RPWRON,
185 [PALMAS_PWRDOWN_IRQ] = {
186 .mask = PALMAS_INT1_STATUS_PWRDOWN,
188 [PALMAS_HOTDIE_IRQ] = {
189 .mask = PALMAS_INT1_STATUS_HOTDIE,
191 [PALMAS_VSYS_MON_IRQ] = {
192 .mask = PALMAS_INT1_STATUS_VSYS_MON,
194 [PALMAS_VBAT_MON_IRQ] = {
195 .mask = PALMAS_INT1_STATUS_VBAT_MON,
198 [PALMAS_RTC_ALARM_IRQ] = {
199 .mask = PALMAS_INT2_STATUS_RTC_ALARM,
202 [PALMAS_RTC_TIMER_IRQ] = {
203 .mask = PALMAS_INT2_STATUS_RTC_TIMER,
207 .mask = PALMAS_INT2_STATUS_WDT,
210 [PALMAS_BATREMOVAL_IRQ] = {
211 .mask = PALMAS_INT2_STATUS_BATREMOVAL,
214 [PALMAS_RESET_IN_IRQ] = {
215 .mask = PALMAS_INT2_STATUS_RESET_IN,
218 [PALMAS_FBI_BB_IRQ] = {
219 .mask = PALMAS_INT2_STATUS_FBI_BB,
222 [PALMAS_SHORT_IRQ] = {
223 .mask = PALMAS_INT2_STATUS_SHORT,
226 [PALMAS_VAC_ACOK_IRQ] = {
227 .mask = PALMAS_INT2_STATUS_VAC_ACOK,
231 [PALMAS_GPADC_AUTO_0_IRQ] = {
232 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_0,
235 [PALMAS_GPADC_AUTO_1_IRQ] = {
236 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_1,
239 [PALMAS_GPADC_EOC_SW_IRQ] = {
240 .mask = PALMAS_INT3_STATUS_GPADC_EOC_SW,
243 [PALMAS_GPADC_EOC_RT_IRQ] = {
244 .mask = PALMAS_INT3_STATUS_GPADC_EOC_RT,
247 [PALMAS_ID_OTG_IRQ] = {
248 .mask = PALMAS_INT3_STATUS_ID_OTG,
252 .mask = PALMAS_INT3_STATUS_ID,
255 [PALMAS_VBUS_OTG_IRQ] = {
256 .mask = PALMAS_INT3_STATUS_VBUS_OTG,
259 [PALMAS_VBUS_IRQ] = {
260 .mask = PALMAS_INT3_STATUS_VBUS,
264 [PALMAS_GPIO_0_IRQ] = {
265 .mask = PALMAS_INT4_STATUS_GPIO_0,
268 [PALMAS_GPIO_1_IRQ] = {
269 .mask = PALMAS_INT4_STATUS_GPIO_1,
272 [PALMAS_GPIO_2_IRQ] = {
273 .mask = PALMAS_INT4_STATUS_GPIO_2,
276 [PALMAS_GPIO_3_IRQ] = {
277 .mask = PALMAS_INT4_STATUS_GPIO_3,
280 [PALMAS_GPIO_4_IRQ] = {
281 .mask = PALMAS_INT4_STATUS_GPIO_4,
284 [PALMAS_GPIO_5_IRQ] = {
285 .mask = PALMAS_INT4_STATUS_GPIO_5,
288 [PALMAS_GPIO_6_IRQ] = {
289 .mask = PALMAS_INT4_STATUS_GPIO_6,
292 [PALMAS_GPIO_7_IRQ] = {
293 .mask = PALMAS_INT4_STATUS_GPIO_7,
298 static struct regmap_irq_chip palmas_irq_chip = {
301 .num_irqs = ARRAY_SIZE(palmas_irqs),
305 .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
307 .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
311 static struct regmap_irq_chip tps65917_irq_chip = {
313 .irqs = tps65917_irqs,
314 .num_irqs = ARRAY_SIZE(tps65917_irqs),
318 .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
320 .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
324 int palmas_ext_control_req_config(struct palmas *palmas,
325 enum palmas_external_requestor_id id, int ext_ctrl, bool enable)
327 struct palmas_pmic_driver_data *pmic_ddata = palmas->pmic_ddata;
328 int preq_mask_bit = 0;
332 if (!(ext_ctrl & PALMAS_EXT_REQ))
335 if (id >= PALMAS_EXTERNAL_REQSTR_ID_MAX)
338 if (ext_ctrl & PALMAS_EXT_CONTROL_NSLEEP) {
339 reg_add = PALMAS_NSLEEP_RES_ASSIGN;
341 } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE1) {
342 reg_add = PALMAS_ENABLE1_RES_ASSIGN;
344 } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE2) {
345 reg_add = PALMAS_ENABLE2_RES_ASSIGN;
349 bit_pos = pmic_ddata->sleep_req_info[id].bit_pos;
350 reg_add += pmic_ddata->sleep_req_info[id].reg_offset;
352 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
353 reg_add, BIT(bit_pos), BIT(bit_pos));
355 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
356 reg_add, BIT(bit_pos), 0);
358 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
363 /* Unmask the PREQ */
364 ret = palmas_update_bits(palmas, PALMAS_PMU_CONTROL_BASE,
365 PALMAS_POWER_CTRL, BIT(preq_mask_bit), 0);
367 dev_err(palmas->dev, "POWER_CTRL register update failed %d\n",
373 EXPORT_SYMBOL_GPL(palmas_ext_control_req_config);
375 static int palmas_set_pdata_irq_flag(struct i2c_client *i2c,
376 struct palmas_platform_data *pdata)
378 struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
380 dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
384 pdata->irq_flags = irqd_get_trigger_type(irq_data);
385 dev_info(&i2c->dev, "Irq flag is 0x%08x\n", pdata->irq_flags);
389 static void palmas_dt_to_pdata(struct i2c_client *i2c,
390 struct palmas_platform_data *pdata)
392 struct device_node *node = i2c->dev.of_node;
396 ret = of_property_read_u32(node, "ti,mux-pad1", &prop);
398 pdata->mux_from_pdata = 1;
402 ret = of_property_read_u32(node, "ti,mux-pad2", &prop);
404 pdata->mux_from_pdata = 1;
408 /* The default for this register is all masked */
409 ret = of_property_read_u32(node, "ti,power-ctrl", &prop);
411 pdata->power_ctrl = prop;
413 pdata->power_ctrl = PALMAS_POWER_CTRL_NSLEEP_MASK |
414 PALMAS_POWER_CTRL_ENABLE1_MASK |
415 PALMAS_POWER_CTRL_ENABLE2_MASK;
417 palmas_set_pdata_irq_flag(i2c, pdata);
419 pdata->pm_off = of_property_read_bool(node,
420 "ti,system-power-controller");
423 static struct palmas *palmas_dev;
424 static void palmas_power_off(void)
429 struct device_node *np = palmas_dev->dev->of_node;
431 if (of_property_read_bool(np, "ti,palmas-override-powerhold")) {
432 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
433 PALMAS_PRIMARY_SECONDARY_PAD2);
434 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
436 if (of_device_is_compatible(np, "ti,tps65917"))
438 TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK;
441 PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK;
443 ret = regmap_update_bits(palmas_dev->regmap[slave], addr,
446 dev_err(palmas_dev->dev,
447 "Unable to write PRIMARY_SECONDARY_PAD2 %d\n",
451 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
452 addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_DEV_CTRL);
454 ret = regmap_update_bits(
455 palmas_dev->regmap[slave],
457 PALMAS_DEV_CTRL_DEV_ON,
461 pr_err("%s: Unable to write to DEV_CTRL_DEV_ON: %d\n",
465 static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST;
466 static unsigned int tps659038_features;
468 struct palmas_driver_data {
469 unsigned int *features;
470 struct regmap_irq_chip *irq_chip;
473 static struct palmas_driver_data palmas_data = {
474 .features = &palmas_features,
475 .irq_chip = &palmas_irq_chip,
478 static struct palmas_driver_data tps659038_data = {
479 .features = &tps659038_features,
480 .irq_chip = &palmas_irq_chip,
483 static struct palmas_driver_data tps65917_data = {
484 .features = &tps659038_features,
485 .irq_chip = &tps65917_irq_chip,
488 static const struct of_device_id of_palmas_match_tbl[] = {
490 .compatible = "ti,palmas",
491 .data = &palmas_data,
494 .compatible = "ti,tps659038",
495 .data = &tps659038_data,
498 .compatible = "ti,tps65917",
499 .data = &tps65917_data,
503 MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
505 static int palmas_i2c_probe(struct i2c_client *i2c,
506 const struct i2c_device_id *id)
508 struct palmas *palmas;
509 struct palmas_platform_data *pdata;
510 struct palmas_driver_data *driver_data;
511 struct device_node *node = i2c->dev.of_node;
513 unsigned int reg, addr;
515 const struct of_device_id *match;
517 pdata = dev_get_platdata(&i2c->dev);
519 if (node && !pdata) {
520 pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
525 palmas_dt_to_pdata(i2c, pdata);
531 palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL);
535 i2c_set_clientdata(i2c, palmas);
536 palmas->dev = &i2c->dev;
537 palmas->irq = i2c->irq;
539 match = of_match_device(of_palmas_match_tbl, &i2c->dev);
544 driver_data = (struct palmas_driver_data *)match->data;
545 palmas->features = *driver_data->features;
547 for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
549 palmas->i2c_clients[i] = i2c;
551 palmas->i2c_clients[i] =
552 i2c_new_dummy_device(i2c->adapter,
554 if (IS_ERR(palmas->i2c_clients[i])) {
556 "can't attach client %d\n", i);
557 ret = PTR_ERR(palmas->i2c_clients[i]);
560 palmas->i2c_clients[i]->dev.of_node = of_node_get(node);
562 palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
563 &palmas_regmap_config[i]);
564 if (IS_ERR(palmas->regmap[i])) {
565 ret = PTR_ERR(palmas->regmap[i]);
567 "Failed to allocate regmap %d, err: %d\n",
574 dev_warn(palmas->dev, "IRQ missing: skipping irq request\n");
578 /* Change interrupt line output polarity */
579 if (pdata->irq_flags & IRQ_TYPE_LEVEL_HIGH)
580 reg = PALMAS_POLARITY_CTRL_INT_POLARITY;
583 ret = palmas_update_bits(palmas, PALMAS_PU_PD_OD_BASE,
584 PALMAS_POLARITY_CTRL, PALMAS_POLARITY_CTRL_INT_POLARITY,
587 dev_err(palmas->dev, "POLARITY_CTRL update failed: %d\n", ret);
591 /* Change IRQ into clear on read mode for efficiency */
592 slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
593 addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
594 reg = PALMAS_INT_CTRL_INT_CLEAR;
596 regmap_write(palmas->regmap[slave], addr, reg);
598 ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
599 IRQF_ONESHOT | pdata->irq_flags, 0,
600 driver_data->irq_chip, &palmas->irq_data);
605 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
606 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
607 PALMAS_PRIMARY_SECONDARY_PAD1);
609 if (pdata->mux_from_pdata) {
611 ret = regmap_write(palmas->regmap[slave], addr, reg);
615 ret = regmap_read(palmas->regmap[slave], addr, ®);
620 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0))
621 palmas->gpio_muxed |= PALMAS_GPIO_0_MUXED;
622 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK))
623 palmas->gpio_muxed |= PALMAS_GPIO_1_MUXED;
624 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
625 (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
626 palmas->led_muxed |= PALMAS_LED1_MUXED;
627 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
628 (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
629 palmas->pwm_muxed |= PALMAS_PWM1_MUXED;
630 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK))
631 palmas->gpio_muxed |= PALMAS_GPIO_2_MUXED;
632 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
633 (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
634 palmas->led_muxed |= PALMAS_LED2_MUXED;
635 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
636 (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
637 palmas->pwm_muxed |= PALMAS_PWM2_MUXED;
638 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3))
639 palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED;
641 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
642 PALMAS_PRIMARY_SECONDARY_PAD2);
644 if (pdata->mux_from_pdata) {
646 ret = regmap_write(palmas->regmap[slave], addr, reg);
650 ret = regmap_read(palmas->regmap[slave], addr, ®);
655 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4))
656 palmas->gpio_muxed |= PALMAS_GPIO_4_MUXED;
657 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK))
658 palmas->gpio_muxed |= PALMAS_GPIO_5_MUXED;
659 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6))
660 palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED;
661 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK))
662 palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED;
664 dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
665 palmas->gpio_muxed, palmas->pwm_muxed,
668 reg = pdata->power_ctrl;
670 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
671 addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL);
673 ret = regmap_write(palmas->regmap[slave], addr, reg);
678 * If we are probing with DT do this the DT way and return here
679 * otherwise continue and add devices using mfd helpers.
682 ret = devm_of_platform_populate(&i2c->dev);
685 } else if (pdata->pm_off && !pm_power_off) {
687 pm_power_off = palmas_power_off;
694 regmap_del_irq_chip(palmas->irq, palmas->irq_data);
696 for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
697 if (palmas->i2c_clients[i])
698 i2c_unregister_device(palmas->i2c_clients[i]);
703 static int palmas_i2c_remove(struct i2c_client *i2c)
705 struct palmas *palmas = i2c_get_clientdata(i2c);
708 regmap_del_irq_chip(palmas->irq, palmas->irq_data);
710 for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
711 if (palmas->i2c_clients[i])
712 i2c_unregister_device(palmas->i2c_clients[i]);
715 if (palmas == palmas_dev) {
723 static const struct i2c_device_id palmas_i2c_id[] = {
730 MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
732 static struct i2c_driver palmas_i2c_driver = {
735 .of_match_table = of_palmas_match_tbl,
737 .probe = palmas_i2c_probe,
738 .remove = palmas_i2c_remove,
739 .id_table = palmas_i2c_id,
742 static int __init palmas_i2c_init(void)
744 return i2c_add_driver(&palmas_i2c_driver);
746 /* init early so consumer devices can complete system boot */
747 subsys_initcall(palmas_i2c_init);
749 static void __exit palmas_i2c_exit(void)
751 i2c_del_driver(&palmas_i2c_driver);
753 module_exit(palmas_i2c_exit);
755 MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
756 MODULE_DESCRIPTION("Palmas chip family multi-function driver");
757 MODULE_LICENSE("GPL");