2 * Intel Sunrisepoint LPSS core support.
4 * Copyright (C) 2015, Intel Corporation
6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * Heikki Krogerus <heikki.krogerus@linux.intel.com>
9 * Jarkko Nikula <jarkko.nikula@linux.intel.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/clk.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk-provider.h>
19 #include <linux/debugfs.h>
20 #include <linux/idr.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/mfd/core.h>
26 #include <linux/pm_qos.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/property.h>
29 #include <linux/seq_file.h>
30 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/dma/idma64.h>
34 #include "intel-lpss.h"
36 #define LPSS_DEV_OFFSET 0x000
37 #define LPSS_DEV_SIZE 0x200
38 #define LPSS_PRIV_OFFSET 0x200
39 #define LPSS_PRIV_SIZE 0x100
40 #define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
41 #define LPSS_IDMA64_OFFSET 0x800
42 #define LPSS_IDMA64_SIZE 0x800
44 /* Offsets from lpss->priv */
45 #define LPSS_PRIV_RESETS 0x04
46 #define LPSS_PRIV_RESETS_IDMA BIT(2)
47 #define LPSS_PRIV_RESETS_FUNC 0x3
49 #define LPSS_PRIV_ACTIVELTR 0x10
50 #define LPSS_PRIV_IDLELTR 0x14
52 #define LPSS_PRIV_LTR_REQ BIT(15)
53 #define LPSS_PRIV_LTR_SCALE_MASK 0xc00
54 #define LPSS_PRIV_LTR_SCALE_1US 0x800
55 #define LPSS_PRIV_LTR_SCALE_32US 0xc00
56 #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff
58 #define LPSS_PRIV_SSP_REG 0x20
59 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
61 #define LPSS_PRIV_REMAP_ADDR 0x40
63 #define LPSS_PRIV_CAPS 0xfc
64 #define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
65 #define LPSS_PRIV_CAPS_TYPE_SHIFT 4
66 #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
68 /* This matches the type field in CAPS register */
69 enum intel_lpss_dev_type {
76 const struct intel_lpss_platform_info *info;
77 enum intel_lpss_dev_type type;
79 struct clk_lookup *clock;
80 struct mfd_cell *cell;
83 u32 priv_ctx[LPSS_PRIV_REG_COUNT];
88 struct dentry *debugfs;
91 static const struct resource intel_lpss_dev_resources[] = {
92 DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
93 DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
97 static const struct resource intel_lpss_idma64_resources[] = {
98 DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
103 * Cells needs to be ordered so that the iDMA is created first. This is
104 * because we need to be sure the DMA is available when the host controller
107 static const struct mfd_cell intel_lpss_idma64_cell = {
108 .name = LPSS_IDMA64_DRIVER_NAME,
109 .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
110 .resources = intel_lpss_idma64_resources,
113 static const struct mfd_cell intel_lpss_i2c_cell = {
114 .name = "i2c_designware",
115 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
116 .resources = intel_lpss_dev_resources,
119 static const struct mfd_cell intel_lpss_uart_cell = {
120 .name = "dw-apb-uart",
121 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
122 .resources = intel_lpss_dev_resources,
125 static const struct mfd_cell intel_lpss_spi_cell = {
126 .name = "pxa2xx-spi",
127 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
128 .resources = intel_lpss_dev_resources,
131 static DEFINE_IDA(intel_lpss_devid_ida);
132 static struct dentry *intel_lpss_debugfs;
134 static int intel_lpss_request_dma_module(const char *name)
136 static bool intel_lpss_dma_requested;
138 if (intel_lpss_dma_requested)
141 intel_lpss_dma_requested = true;
142 return request_module("%s", name);
145 static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
147 lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
148 lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
151 static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
155 dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
159 /* Cache the values into lpss structure */
160 intel_lpss_cache_ltr(lpss);
162 debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
163 debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
164 debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
170 static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
172 debugfs_remove_recursive(lpss->debugfs);
175 static void intel_lpss_ltr_set(struct device *dev, s32 val)
177 struct intel_lpss *lpss = dev_get_drvdata(dev);
181 * Program latency tolerance (LTR) accordingly what has been asked
182 * by the PM QoS layer or disable it in case we were passed
183 * negative value or PM_QOS_LATENCY_ANY.
185 ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
187 if (val == PM_QOS_LATENCY_ANY || val < 0) {
188 ltr &= ~LPSS_PRIV_LTR_REQ;
190 ltr |= LPSS_PRIV_LTR_REQ;
191 ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
192 ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
194 if (val > LPSS_PRIV_LTR_VALUE_MASK)
195 ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
197 ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
200 if (ltr == lpss->active_ltr)
203 writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
204 writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
206 /* Cache the values into lpss structure */
207 intel_lpss_cache_ltr(lpss);
210 static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
212 lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
213 dev_pm_qos_expose_latency_tolerance(lpss->dev);
216 static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
218 dev_pm_qos_hide_latency_tolerance(lpss->dev);
219 lpss->dev->power.set_latency_tolerance = NULL;
222 static int intel_lpss_assign_devs(struct intel_lpss *lpss)
224 const struct mfd_cell *cell;
227 type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
228 type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
232 cell = &intel_lpss_i2c_cell;
235 cell = &intel_lpss_uart_cell;
238 cell = &intel_lpss_spi_cell;
244 lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
253 static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
255 return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
258 static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
260 resource_size_t addr = lpss->info->mem->start;
262 lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
265 static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
267 u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
269 /* Bring out the device from reset */
270 writel(value, lpss->priv + LPSS_PRIV_RESETS);
273 static void intel_lpss_init_dev(const struct intel_lpss *lpss)
275 u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
277 /* Set the device in reset state */
278 writel(0, lpss->priv + LPSS_PRIV_RESETS);
280 intel_lpss_deassert_reset(lpss);
282 intel_lpss_set_remap_addr(lpss);
284 if (!intel_lpss_has_idma(lpss))
287 /* Make sure that SPI multiblock DMA transfers are re-enabled */
288 if (lpss->type == LPSS_DEV_SPI)
289 writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
292 static void intel_lpss_unregister_clock_tree(struct clk *clk)
297 parent = clk_get_parent(clk);
303 static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
308 struct clk *tmp = *clk;
310 snprintf(name, sizeof(name), "%s-enable", devname);
311 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
312 lpss->priv, 0, 0, NULL);
316 snprintf(name, sizeof(name), "%s-div", devname);
317 tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
318 0, lpss->priv, 1, 15, 16, 15, 0,
324 snprintf(name, sizeof(name), "%s-update", devname);
325 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
326 CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
334 static int intel_lpss_register_clock(struct intel_lpss *lpss)
336 const struct mfd_cell *cell = lpss->cell;
341 if (!lpss->info->clk_rate)
345 clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
346 lpss->info->clk_rate);
350 snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
353 * Support for clock divider only if it has some preset value.
354 * Otherwise we assume that the divider is not used.
356 if (lpss->type != LPSS_DEV_I2C) {
357 ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
359 goto err_clk_register;
364 /* Clock for the host controller */
365 lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
367 goto err_clk_register;
374 intel_lpss_unregister_clock_tree(clk);
379 static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
381 if (IS_ERR_OR_NULL(lpss->clk))
384 clkdev_drop(lpss->clock);
385 intel_lpss_unregister_clock_tree(lpss->clk);
388 int intel_lpss_probe(struct device *dev,
389 const struct intel_lpss_platform_info *info)
391 struct intel_lpss *lpss;
394 if (!info || !info->mem || info->irq <= 0)
397 lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
401 lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
408 lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
410 dev_set_drvdata(dev, lpss);
412 ret = intel_lpss_assign_devs(lpss);
416 lpss->cell->properties = info->properties;
418 intel_lpss_init_dev(lpss);
420 lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
424 ret = intel_lpss_register_clock(lpss);
426 goto err_clk_register;
428 intel_lpss_ltr_expose(lpss);
430 ret = intel_lpss_debugfs_add(lpss);
432 dev_warn(dev, "Failed to create debugfs entries\n");
434 if (intel_lpss_has_idma(lpss)) {
436 * Ensure the DMA driver is loaded before the host
437 * controller device appears, so that the host controller
438 * driver can request its DMA channels as early as
441 * If the DMA module is not there that's OK as well.
443 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
445 ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
446 1, info->mem, info->irq, NULL);
448 dev_warn(dev, "Failed to add %s, fallback to PIO\n",
449 LPSS_IDMA64_DRIVER_NAME);
452 ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
453 1, info->mem, info->irq, NULL);
457 dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
462 intel_lpss_debugfs_remove(lpss);
463 intel_lpss_ltr_hide(lpss);
464 intel_lpss_unregister_clock(lpss);
467 ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
471 EXPORT_SYMBOL_GPL(intel_lpss_probe);
473 void intel_lpss_remove(struct device *dev)
475 struct intel_lpss *lpss = dev_get_drvdata(dev);
477 mfd_remove_devices(dev);
478 intel_lpss_debugfs_remove(lpss);
479 intel_lpss_ltr_hide(lpss);
480 intel_lpss_unregister_clock(lpss);
481 ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
483 EXPORT_SYMBOL_GPL(intel_lpss_remove);
485 static int resume_lpss_device(struct device *dev, void *data)
487 if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
488 pm_runtime_resume(dev);
493 int intel_lpss_prepare(struct device *dev)
496 * Resume both child devices before entering system sleep. This
497 * ensures that they are in proper state before they get suspended.
499 device_for_each_child_reverse(dev, NULL, resume_lpss_device);
502 EXPORT_SYMBOL_GPL(intel_lpss_prepare);
504 int intel_lpss_suspend(struct device *dev)
506 struct intel_lpss *lpss = dev_get_drvdata(dev);
509 /* Save device context */
510 for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
511 lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
514 * If the device type is not UART, then put the controller into
515 * reset. UART cannot be put into reset since S3/S0ix fail when
516 * no_console_suspend flag is enabled.
518 if (lpss->type != LPSS_DEV_UART)
519 writel(0, lpss->priv + LPSS_PRIV_RESETS);
523 EXPORT_SYMBOL_GPL(intel_lpss_suspend);
525 int intel_lpss_resume(struct device *dev)
527 struct intel_lpss *lpss = dev_get_drvdata(dev);
530 intel_lpss_deassert_reset(lpss);
532 /* Restore device context */
533 for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
534 writel(lpss->priv_ctx[i], lpss->priv + i * 4);
538 EXPORT_SYMBOL_GPL(intel_lpss_resume);
540 static int __init intel_lpss_init(void)
542 intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
545 module_init(intel_lpss_init);
547 static void __exit intel_lpss_exit(void)
549 debugfs_remove(intel_lpss_debugfs);
551 module_exit(intel_lpss_exit);
553 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
554 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
555 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
556 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
557 MODULE_DESCRIPTION("Intel LPSS core driver");
558 MODULE_LICENSE("GPL v2");