drivers/mfd/asic3.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * driver/mfd/asic3.c
   4  *
   5  * Compaq ASIC3 support.
   6  *
   7  * Copyright 2001 Compaq Computer Corporation.
   8  * Copyright 2004-2005 Phil Blundell
   9  * Copyright 2007-2008 OpenedHand Ltd.
  10  *
  11  * Authors: Phil Blundell <pb@handhelds.org>,
  12  *          Samuel Ortiz <sameo@openedhand.com>
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/delay.h>
  17 #include <linux/irq.h>
  18 #include <linux/gpio/driver.h>
  19 #include <linux/export.h>
  20 #include <linux/io.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24
  25 #include <linux/mfd/asic3.h>
  26 #include <linux/mfd/core.h>
  27 #include <linux/mfd/ds1wm.h>
  28 #include <linux/mfd/tmio.h>
  29
  30 #include <linux/mmc/host.h>
  31
  32 enum {
  33         ASIC3_CLOCK_SPI,
  34         ASIC3_CLOCK_OWM,
  35         ASIC3_CLOCK_PWM0,
  36         ASIC3_CLOCK_PWM1,
  37         ASIC3_CLOCK_LED0,
  38         ASIC3_CLOCK_LED1,
  39         ASIC3_CLOCK_LED2,
  40         ASIC3_CLOCK_SD_HOST,
  41         ASIC3_CLOCK_SD_BUS,
  42         ASIC3_CLOCK_SMBUS,
  43         ASIC3_CLOCK_EX0,
  44         ASIC3_CLOCK_EX1,
  45 };
  46
  47 struct asic3_clk {
  48         int enabled;
  49         unsigned int cdex;
  50         unsigned long rate;
  51 };
  52
  53 #define INIT_CDEX(_name, _rate) \
  54         [ASIC3_CLOCK_##_name] = {               \
  55                 .cdex = CLOCK_CDEX_##_name,     \
  56                 .rate = _rate,                  \
  57         }
  58
  59 static struct asic3_clk asic3_clk_init[] __initdata = {
  60         INIT_CDEX(SPI, 0),
  61         INIT_CDEX(OWM, 5000000),
  62         INIT_CDEX(PWM0, 0),
  63         INIT_CDEX(PWM1, 0),
  64         INIT_CDEX(LED0, 0),
  65         INIT_CDEX(LED1, 0),
  66         INIT_CDEX(LED2, 0),
  67         INIT_CDEX(SD_HOST, 24576000),
  68         INIT_CDEX(SD_BUS, 12288000),
  69         INIT_CDEX(SMBUS, 0),
  70         INIT_CDEX(EX0, 32768),
  71         INIT_CDEX(EX1, 24576000),
  72 };
  73
  74 struct asic3 {
  75         void __iomem *mapping;
  76         unsigned int bus_shift;
  77         unsigned int irq_nr;
  78         unsigned int irq_base;
  79         raw_spinlock_t lock;
  80         u16 irq_bothedge[4];
  81         struct gpio_chip gpio;
  82         struct device *dev;
  83         void __iomem *tmio_cnf;
  84
  85         struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
  86 };
  87
  88 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
  89
  90 void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
  91 {
  92         iowrite16(value, asic->mapping +
  93                   (reg >> asic->bus_shift));
  94 }
  95 EXPORT_SYMBOL_GPL(asic3_write_register);
  96
  97 u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
  98 {
  99         return ioread16(asic->mapping +
 100                         (reg >> asic->bus_shift));
 101 }
 102 EXPORT_SYMBOL_GPL(asic3_read_register);
 103
 104 static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
 105 {
 106         unsigned long flags;
 107         u32 val;
 108
 109         raw_spin_lock_irqsave(&asic->lock, flags);
 110         val = asic3_read_register(asic, reg);
 111         if (set)
 112                 val |= bits;
 113         else
 114                 val &= ~bits;
 115         asic3_write_register(asic, reg, val);
 116         raw_spin_unlock_irqrestore(&asic->lock, flags);
 117 }
 118
 119 /* IRQs */
 120 #define MAX_ASIC_ISR_LOOPS    20
 121 #define ASIC3_GPIO_BASE_INCR \
 122         (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
 123
 124 static void asic3_irq_flip_edge(struct asic3 *asic,
 125                                 u32 base, int bit)
 126 {
 127         u16 edge;
 128         unsigned long flags;
 129
 130         raw_spin_lock_irqsave(&asic->lock, flags);
 131         edge = asic3_read_register(asic,
 132                                    base + ASIC3_GPIO_EDGE_TRIGGER);
 133         edge ^= bit;
 134         asic3_write_register(asic,
 135                              base + ASIC3_GPIO_EDGE_TRIGGER, edge);
 136         raw_spin_unlock_irqrestore(&asic->lock, flags);
 137 }
 138
 139 static void asic3_irq_demux(struct irq_desc *desc)
 140 {
 141         struct asic3 *asic = irq_desc_get_handler_data(desc);
 142         struct irq_data *data = irq_desc_get_irq_data(desc);
 143         int iter, i;
 144         unsigned long flags;
 145
 146         data->chip->irq_ack(data);
 147
 148         for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
 149                 u32 status;
 150                 int bank;
 151
 152                 raw_spin_lock_irqsave(&asic->lock, flags);
 153                 status = asic3_read_register(asic,
 154                                              ASIC3_OFFSET(INTR, P_INT_STAT));
 155                 raw_spin_unlock_irqrestore(&asic->lock, flags);
 156
 157                 /* Check all ten register bits */
 158                 if ((status & 0x3ff) == 0)
 159                         break;
 160
 161                 /* Handle GPIO IRQs */
 162                 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
 163                         if (status & (1 << bank)) {
 164                                 unsigned long base, istat;
 165
 166                                 base = ASIC3_GPIO_A_BASE
 167                                        + bank * ASIC3_GPIO_BASE_INCR;
 168                                 raw_spin_lock_irqsave(&asic->lock, flags);
 169                                 istat = asic3_read_register(asic,
 170                                                             base +
 171                                                             ASIC3_GPIO_INT_STATUS);
 172                                 /* Clearing IntStatus */
 173                                 asic3_write_register(asic,
 174                                                      base +
 175                                                      ASIC3_GPIO_INT_STATUS, 0);
 176                                 raw_spin_unlock_irqrestore(&asic->lock, flags);
 177
 178                                 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
 179                                         int bit = (1 << i);
 180                                         unsigned int irqnr;
 181
 182                                         if (!(istat & bit))
 183                                                 continue;
 184
 185                                         irqnr = asic->irq_base +
 186                                                 (ASIC3_GPIOS_PER_BANK * bank)
 187                                                 + i;
 188                                         generic_handle_irq(irqnr);
 189                                         if (asic->irq_bothedge[bank] & bit)
 190                                                 asic3_irq_flip_edge(asic, base,
 191                                                                     bit);
 192                                 }
 193                         }
 194                 }
 195
 196                 /* Handle remaining IRQs in the status register */
 197                 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
 198                         /* They start at bit 4 and go up */
 199                         if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
 200                                 generic_handle_irq(asic->irq_base + i);
 201                 }
 202         }
 203
 204         if (iter >= MAX_ASIC_ISR_LOOPS)
 205                 dev_err(asic->dev, "interrupt processing overrun\n");
 206 }
 207
 208 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
 209 {
 210         int n;
 211
 212         n = (irq - asic->irq_base) >> 4;
 213
 214         return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
 215 }
 216
 217 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
 218 {
 219         return (irq - asic->irq_base) & 0xf;
 220 }
 221
 222 static void asic3_mask_gpio_irq(struct irq_data *data)
 223 {
 224         struct asic3 *asic = irq_data_get_irq_chip_data(data);
 225         u32 val, bank, index;
 226         unsigned long flags;
 227
 228         bank = asic3_irq_to_bank(asic, data->irq);
 229         index = asic3_irq_to_index(asic, data->irq);
 230
 231         raw_spin_lock_irqsave(&asic->lock, flags);
 232         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
 233         val |= 1 << index;
 234         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
 235         raw_spin_unlock_irqrestore(&asic->lock, flags);
 236 }
 237
 238 static void asic3_mask_irq(struct irq_data *data)
 239 {
 240         struct asic3 *asic = irq_data_get_irq_chip_data(data);
 241         int regval;
 242         unsigned long flags;
 243
 244         raw_spin_lock_irqsave(&asic->lock, flags);
 245         regval = asic3_read_register(asic,
 246                                      ASIC3_INTR_BASE +
 247                                      ASIC3_INTR_INT_MASK);
 248
 249         regval &= ~(ASIC3_INTMASK_MASK0 <<
 250                     (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
 251
 252         asic3_write_register(asic,
 253                              ASIC3_INTR_BASE +
 254                              ASIC3_INTR_INT_MASK,
 255                              regval);
 256         raw_spin_unlock_irqrestore(&asic->lock, flags);
 257 }
 258
 259 static void asic3_unmask_gpio_irq(struct irq_data *data)
 260 {
 261         struct asic3 *asic = irq_data_get_irq_chip_data(data);
 262         u32 val, bank, index;
 263         unsigned long flags;
 264
 265         bank = asic3_irq_to_bank(asic, data->irq);
 266         index = asic3_irq_to_index(asic, data->irq);
 267
 268         raw_spin_lock_irqsave(&asic->lock, flags);
 269         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
 270         val &= ~(1 << index);
 271         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
 272         raw_spin_unlock_irqrestore(&asic->lock, flags);
 273 }
 274
 275 static void asic3_unmask_irq(struct irq_data *data)
 276 {
 277         struct asic3 *asic = irq_data_get_irq_chip_data(data);
 278         int regval;
 279         unsigned long flags;
 280
 281         raw_spin_lock_irqsave(&asic->lock, flags);
 282         regval = asic3_read_register(asic,
 283                                      ASIC3_INTR_BASE +
 284                                      ASIC3_INTR_INT_MASK);
 285
 286         regval |= (ASIC3_INTMASK_MASK0 <<
 287                    (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
 288
 289         asic3_write_register(asic,
 290                              ASIC3_INTR_BASE +
 291                              ASIC3_INTR_INT_MASK,
 292                              regval);
 293         raw_spin_unlock_irqrestore(&asic->lock, flags);
 294 }
 295
 296 static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
 297 {
 298         struct asic3 *asic = irq_data_get_irq_chip_data(data);
 299         u32 bank, index;
 300         u16 trigger, level, edge, bit;
 301         unsigned long flags;
 302
 303         bank = asic3_irq_to_bank(asic, data->irq);
 304         index = asic3_irq_to_index(asic, data->irq);
 305         bit = 1<<index;
 306
 307         raw_spin_lock_irqsave(&asic->lock, flags);
 308         level = asic3_read_register(asic,
 309                                     bank + ASIC3_GPIO_LEVEL_TRIGGER);
 310         edge = asic3_read_register(asic,
 311                                    bank + ASIC3_GPIO_EDGE_TRIGGER);
 312         trigger = asic3_read_register(asic,
 313                                       bank + ASIC3_GPIO_TRIGGER_TYPE);
 314         asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
 315
 316         if (type == IRQ_TYPE_EDGE_RISING) {
 317                 trigger |= bit;
 318                 edge |= bit;
 319         } else if (type == IRQ_TYPE_EDGE_FALLING) {
 320                 trigger |= bit;
 321                 edge &= ~bit;
 322         } else if (type == IRQ_TYPE_EDGE_BOTH) {
 323                 trigger |= bit;
 324                 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
 325                         edge &= ~bit;
 326                 else
 327                         edge |= bit;
 328                 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
 329         } else if (type == IRQ_TYPE_LEVEL_LOW) {
 330                 trigger &= ~bit;
 331                 level &= ~bit;
 332         } else if (type == IRQ_TYPE_LEVEL_HIGH) {
 333                 trigger &= ~bit;
 334                 level |= bit;
 335         } else {
 336                 /*
 337                  * if type == IRQ_TYPE_NONE, we should mask interrupts, but
 338                  * be careful to not unmask them if mask was also called.
 339                  * Probably need internal state for mask.
 340                  */
 341                 dev_notice(asic->dev, "irq type not changed\n");
 342         }
 343         asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
 344                              level);
 345         asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
 346                              edge);
 347         asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
 348                              trigger);
 349         raw_spin_unlock_irqrestore(&asic->lock, flags);
 350         return 0;
 351 }
 352
 353 static int asic3_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
 354 {
 355         struct asic3 *asic = irq_data_get_irq_chip_data(data);
 356         u32 bank, index;
 357         u16 bit;
 358
 359         bank = asic3_irq_to_bank(asic, data->irq);
 360         index = asic3_irq_to_index(asic, data->irq);
 361         bit = 1<<index;
 362
 363         asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on);
 364
 365         return 0;
 366 }
 367
 368 static struct irq_chip asic3_gpio_irq_chip = {
 369         .name           = "ASIC3-GPIO",
 370         .irq_ack        = asic3_mask_gpio_irq,
 371         .irq_mask       = asic3_mask_gpio_irq,
 372         .irq_unmask     = asic3_unmask_gpio_irq,
 373         .irq_set_type   = asic3_gpio_irq_type,
 374         .irq_set_wake   = asic3_gpio_irq_set_wake,
 375 };
 376
 377 static struct irq_chip asic3_irq_chip = {
 378         .name           = "ASIC3",
 379         .irq_ack        = asic3_mask_irq,
 380         .irq_mask       = asic3_mask_irq,
 381         .irq_unmask     = asic3_unmask_irq,
 382 };
 383
 384 static int __init asic3_irq_probe(struct platform_device *pdev)
 385 {
 386         struct asic3 *asic = platform_get_drvdata(pdev);
 387         unsigned long clksel = 0;
 388         unsigned int irq, irq_base;
 389         int ret;
 390
 391         ret = platform_get_irq(pdev, 0);
 392         if (ret < 0)
 393                 return ret;
 394         asic->irq_nr = ret;
 395
 396         /* turn on clock to IRQ controller */
 397         clksel |= CLOCK_SEL_CX;
 398         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
 399                              clksel);
 400
 401         irq_base = asic->irq_base;
 402
 403         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
 404                 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
 405                         irq_set_chip(irq, &asic3_gpio_irq_chip);
 406                 else
 407                         irq_set_chip(irq, &asic3_irq_chip);
 408
 409                 irq_set_chip_data(irq, asic);
 410                 irq_set_handler(irq, handle_level_irq);
 411                 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
 412         }
 413
 414         asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
 415                              ASIC3_INTMASK_GINTMASK);
 416
 417         irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic);
 418         irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
 419
 420         return 0;
 421 }
 422
 423 static void asic3_irq_remove(struct platform_device *pdev)
 424 {
 425         struct asic3 *asic = platform_get_drvdata(pdev);
 426         unsigned int irq, irq_base;
 427
 428         irq_base = asic->irq_base;
 429
 430         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
 431                 irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
 432                 irq_set_chip_and_handler(irq, NULL, NULL);
 433                 irq_set_chip_data(irq, NULL);
 434         }
 435         irq_set_chained_handler(asic->irq_nr, NULL);
 436 }
 437
 438 /* GPIOs */
 439 static int asic3_gpio_direction(struct gpio_chip *chip,
 440                                 unsigned offset, int out)
 441 {
 442         u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
 443         unsigned int gpio_base;
 444         unsigned long flags;
 445         struct asic3 *asic;
 446
 447         asic = gpiochip_get_data(chip);
 448         gpio_base = ASIC3_GPIO_TO_BASE(offset);
 449
 450         if (gpio_base > ASIC3_GPIO_D_BASE) {
 451                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 452                         gpio_base, offset);
 453                 return -EINVAL;
 454         }
 455
 456         raw_spin_lock_irqsave(&asic->lock, flags);
 457
 458         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
 459
 460         /* Input is 0, Output is 1 */
 461         if (out)
 462                 out_reg |= mask;
 463         else
 464                 out_reg &= ~mask;
 465
 466         asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
 467
 468         raw_spin_unlock_irqrestore(&asic->lock, flags);
 469
 470         return 0;
 471
 472 }
 473
 474 static int asic3_gpio_direction_input(struct gpio_chip *chip,
 475                                       unsigned offset)
 476 {
 477         return asic3_gpio_direction(chip, offset, 0);
 478 }
 479
 480 static int asic3_gpio_direction_output(struct gpio_chip *chip,
 481                                        unsigned offset, int value)
 482 {
 483         return asic3_gpio_direction(chip, offset, 1);
 484 }
 485
 486 static int asic3_gpio_get(struct gpio_chip *chip,
 487                           unsigned offset)
 488 {
 489         unsigned int gpio_base;
 490         u32 mask = ASIC3_GPIO_TO_MASK(offset);
 491         struct asic3 *asic;
 492
 493         asic = gpiochip_get_data(chip);
 494         gpio_base = ASIC3_GPIO_TO_BASE(offset);
 495
 496         if (gpio_base > ASIC3_GPIO_D_BASE) {
 497                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 498                         gpio_base, offset);
 499                 return -EINVAL;
 500         }
 501
 502         return !!(asic3_read_register(asic,
 503                                       gpio_base + ASIC3_GPIO_STATUS) & mask);
 504 }
 505
 506 static void asic3_gpio_set(struct gpio_chip *chip,
 507                            unsigned offset, int value)
 508 {
 509         u32 mask, out_reg;
 510         unsigned int gpio_base;
 511         unsigned long flags;
 512         struct asic3 *asic;
 513
 514         asic = gpiochip_get_data(chip);
 515         gpio_base = ASIC3_GPIO_TO_BASE(offset);
 516
 517         if (gpio_base > ASIC3_GPIO_D_BASE) {
 518                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 519                         gpio_base, offset);
 520                 return;
 521         }
 522
 523         mask = ASIC3_GPIO_TO_MASK(offset);
 524
 525         raw_spin_lock_irqsave(&asic->lock, flags);
 526
 527         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
 528
 529         if (value)
 530                 out_reg |= mask;
 531         else
 532                 out_reg &= ~mask;
 533
 534         asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
 535
 536         raw_spin_unlock_irqrestore(&asic->lock, flags);
 537 }
 538
 539 static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 540 {
 541         struct asic3 *asic = gpiochip_get_data(chip);
 542
 543         return asic->irq_base + offset;
 544 }
 545
 546 static __init int asic3_gpio_probe(struct platform_device *pdev,
 547                                    u16 *gpio_config, int num)
 548 {
 549         struct asic3 *asic = platform_get_drvdata(pdev);
 550         u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
 551         u16 out_reg[ASIC3_NUM_GPIO_BANKS];
 552         u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
 553         int i;
 554
 555         memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 556         memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 557         memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 558
 559         /* Enable all GPIOs */
 560         asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
 561         asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
 562         asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
 563         asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
 564
 565         for (i = 0; i < num; i++) {
 566                 u8 alt, pin, dir, init, bank_num, bit_num;
 567                 u16 config = gpio_config[i];
 568
 569                 pin = ASIC3_CONFIG_GPIO_PIN(config);
 570                 alt = ASIC3_CONFIG_GPIO_ALT(config);
 571                 dir = ASIC3_CONFIG_GPIO_DIR(config);
 572                 init = ASIC3_CONFIG_GPIO_INIT(config);
 573
 574                 bank_num = ASIC3_GPIO_TO_BANK(pin);
 575                 bit_num = ASIC3_GPIO_TO_BIT(pin);
 576
 577                 alt_reg[bank_num] |= (alt << bit_num);
 578                 out_reg[bank_num] |= (init << bit_num);
 579                 dir_reg[bank_num] |= (dir << bit_num);
 580         }
 581
 582         for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
 583                 asic3_write_register(asic,
 584                                      ASIC3_BANK_TO_BASE(i) +
 585                                      ASIC3_GPIO_DIRECTION,
 586                                      dir_reg[i]);
 587                 asic3_write_register(asic,
 588                                      ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
 589                                      out_reg[i]);
 590                 asic3_write_register(asic,
 591                                      ASIC3_BANK_TO_BASE(i) +
 592                                      ASIC3_GPIO_ALT_FUNCTION,
 593                                      alt_reg[i]);
 594         }
 595
 596         return gpiochip_add_data(&asic->gpio, asic);
 597 }
 598
 599 static int asic3_gpio_remove(struct platform_device *pdev)
 600 {
 601         struct asic3 *asic = platform_get_drvdata(pdev);
 602
 603         gpiochip_remove(&asic->gpio);
 604         return 0;
 605 }
 606
 607 static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
 608 {
 609         unsigned long flags;
 610         u32 cdex;
 611
 612         raw_spin_lock_irqsave(&asic->lock, flags);
 613         if (clk->enabled++ == 0) {
 614                 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
 615                 cdex |= clk->cdex;
 616                 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
 617         }
 618         raw_spin_unlock_irqrestore(&asic->lock, flags);
 619 }
 620
 621 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
 622 {
 623         unsigned long flags;
 624         u32 cdex;
 625
 626         WARN_ON(clk->enabled == 0);
 627
 628         raw_spin_lock_irqsave(&asic->lock, flags);
 629         if (--clk->enabled == 0) {
 630                 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
 631                 cdex &= ~clk->cdex;
 632                 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
 633         }
 634         raw_spin_unlock_irqrestore(&asic->lock, flags);
 635 }
 636
 637 /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
 638 static struct ds1wm_driver_data ds1wm_pdata = {
 639         .active_high = 1,
 640         .reset_recover_delay = 1,
 641 };
 642
 643 static struct resource ds1wm_resources[] = {
 644         {
 645                 .start = ASIC3_OWM_BASE,
 646                 .end   = ASIC3_OWM_BASE + 0x13,
 647                 .flags = IORESOURCE_MEM,
 648         },
 649         {
 650                 .start = ASIC3_IRQ_OWM,
 651                 .end   = ASIC3_IRQ_OWM,
 652                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 653         },
 654 };
 655
 656 static int ds1wm_enable(struct platform_device *pdev)
 657 {
 658         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 659
 660         /* Turn on external clocks and the OWM clock */
 661         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 662         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 663         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
 664         usleep_range(1000, 5000);
 665
 666         /* Reset and enable DS1WM */
 667         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
 668                            ASIC3_EXTCF_OWM_RESET, 1);
 669         usleep_range(1000, 5000);
 670         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
 671                            ASIC3_EXTCF_OWM_RESET, 0);
 672         usleep_range(1000, 5000);
 673         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 674                            ASIC3_EXTCF_OWM_EN, 1);
 675         usleep_range(1000, 5000);
 676
 677         return 0;
 678 }
 679
 680 static int ds1wm_disable(struct platform_device *pdev)
 681 {
 682         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 683
 684         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 685                            ASIC3_EXTCF_OWM_EN, 0);
 686
 687         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
 688         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 689         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 690
 691         return 0;
 692 }
 693
 694 static const struct mfd_cell asic3_cell_ds1wm = {
 695         .name          = "ds1wm",
 696         .enable        = ds1wm_enable,
 697         .disable       = ds1wm_disable,
 698         .platform_data = &ds1wm_pdata,
 699         .pdata_size    = sizeof(ds1wm_pdata),
 700         .num_resources = ARRAY_SIZE(ds1wm_resources),
 701         .resources     = ds1wm_resources,
 702 };
 703
 704 static void asic3_mmc_pwr(struct platform_device *pdev, int state)
 705 {
 706         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 707
 708         tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
 709 }
 710
 711 static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
 712 {
 713         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 714
 715         tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
 716 }
 717
 718 static struct tmio_mmc_data asic3_mmc_data = {
 719         .hclk           = 24576000,
 720         .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
 721         .set_pwr        = asic3_mmc_pwr,
 722         .set_clk_div    = asic3_mmc_clk_div,
 723 };
 724
 725 static struct resource asic3_mmc_resources[] = {
 726         DEFINE_RES_MEM(ASIC3_SD_CTRL_BASE, 0x400),
 727         DEFINE_RES_IRQ(0)
 728 };
 729
 730 static int asic3_mmc_enable(struct platform_device *pdev)
 731 {
 732         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 733
 734         /* Not sure if it must be done bit by bit, but leaving as-is */
 735         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 736                            ASIC3_SDHWCTRL_LEVCD, 1);
 737         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 738                            ASIC3_SDHWCTRL_LEVWP, 1);
 739         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 740                            ASIC3_SDHWCTRL_SUSPEND, 0);
 741         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 742                            ASIC3_SDHWCTRL_PCLR, 0);
 743
 744         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 745         /* CLK32 used for card detection and for interruption detection
 746          * when HCLK is stopped.
 747          */
 748         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 749         usleep_range(1000, 5000);
 750
 751         /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
 752         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
 753                 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
 754
 755         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
 756         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
 757         usleep_range(1000, 5000);
 758
 759         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 760                            ASIC3_EXTCF_SD_MEM_ENABLE, 1);
 761
 762         /* Enable SD card slot 3.3V power supply */
 763         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 764                            ASIC3_SDHWCTRL_SDPWR, 1);
 765
 766         /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
 767         tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
 768                              ASIC3_SD_CTRL_BASE >> 1);
 769
 770         return 0;
 771 }
 772
 773 static int asic3_mmc_disable(struct platform_device *pdev)
 774 {
 775         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 776
 777         /* Put in suspend mode */
 778         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 779                            ASIC3_SDHWCTRL_SUSPEND, 1);
 780
 781         /* Disable clocks */
 782         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
 783         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
 784         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 785         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 786         return 0;
 787 }
 788
 789 static const struct mfd_cell asic3_cell_mmc = {
 790         .name          = "tmio-mmc",
 791         .enable        = asic3_mmc_enable,
 792         .disable       = asic3_mmc_disable,
 793         .suspend       = asic3_mmc_disable,
 794         .resume        = asic3_mmc_enable,
 795         .platform_data = &asic3_mmc_data,
 796         .pdata_size    = sizeof(asic3_mmc_data),
 797         .num_resources = ARRAY_SIZE(asic3_mmc_resources),
 798         .resources     = asic3_mmc_resources,
 799 };
 800
 801 static const int clock_ledn[ASIC3_NUM_LEDS] = {
 802         [0] = ASIC3_CLOCK_LED0,
 803         [1] = ASIC3_CLOCK_LED1,
 804         [2] = ASIC3_CLOCK_LED2,
 805 };
 806
 807 static int asic3_leds_enable(struct platform_device *pdev)
 808 {
 809         const struct mfd_cell *cell = mfd_get_cell(pdev);
 810         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 811
 812         asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
 813
 814         return 0;
 815 }
 816
 817 static int asic3_leds_disable(struct platform_device *pdev)
 818 {
 819         const struct mfd_cell *cell = mfd_get_cell(pdev);
 820         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 821
 822         asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
 823
 824         return 0;
 825 }
 826
 827 static int asic3_leds_suspend(struct platform_device *pdev)
 828 {
 829         const struct mfd_cell *cell = mfd_get_cell(pdev);
 830         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 831
 832         while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
 833                 usleep_range(1000, 5000);
 834
 835         asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
 836
 837         return 0;
 838 }
 839
 840 static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
 841         [0] = {
 842                 .name          = "leds-asic3",
 843                 .id            = 0,
 844                 .enable        = asic3_leds_enable,
 845                 .disable       = asic3_leds_disable,
 846                 .suspend       = asic3_leds_suspend,
 847                 .resume        = asic3_leds_enable,
 848         },
 849         [1] = {
 850                 .name          = "leds-asic3",
 851                 .id            = 1,
 852                 .enable        = asic3_leds_enable,
 853                 .disable       = asic3_leds_disable,
 854                 .suspend       = asic3_leds_suspend,
 855                 .resume        = asic3_leds_enable,
 856         },
 857         [2] = {
 858                 .name          = "leds-asic3",
 859                 .id            = 2,
 860                 .enable        = asic3_leds_enable,
 861                 .disable       = asic3_leds_disable,
 862                 .suspend       = asic3_leds_suspend,
 863                 .resume        = asic3_leds_enable,
 864         },
 865 };
 866
 867 static int __init asic3_mfd_probe(struct platform_device *pdev,
 868                                   struct asic3_platform_data *pdata,
 869                                   struct resource *mem)
 870 {
 871         struct asic3 *asic = platform_get_drvdata(pdev);
 872         struct resource *mem_sdio;
 873         int irq, ret;
 874
 875         mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 876         if (!mem_sdio)
 877                 dev_dbg(asic->dev, "no SDIO MEM resource\n");
 878
 879         irq = platform_get_irq(pdev, 1);
 880         if (irq < 0)
 881                 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
 882
 883         /* DS1WM */
 884         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 885                            ASIC3_EXTCF_OWM_SMB, 0);
 886
 887         ds1wm_resources[0].start >>= asic->bus_shift;
 888         ds1wm_resources[0].end   >>= asic->bus_shift;
 889
 890         /* MMC */
 891         if (mem_sdio) {
 892                 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >>
 893                                           asic->bus_shift) + mem_sdio->start,
 894                                  ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
 895                 if (!asic->tmio_cnf) {
 896                         ret = -ENOMEM;
 897                         dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
 898                         goto out;
 899                 }
 900         }
 901         asic3_mmc_resources[0].start >>= asic->bus_shift;
 902         asic3_mmc_resources[0].end   >>= asic->bus_shift;
 903
 904         if (pdata->clock_rate) {
 905                 ds1wm_pdata.clock_rate = pdata->clock_rate;
 906                 ret = mfd_add_devices(&pdev->dev, pdev->id,
 907                         &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL);
 908                 if (ret < 0)
 909                         goto out;
 910         }
 911
 912         if (mem_sdio && (irq >= 0)) {
 913                 ret = mfd_add_devices(&pdev->dev, pdev->id,
 914                         &asic3_cell_mmc, 1, mem_sdio, irq, NULL);
 915                 if (ret < 0)
 916                         goto out;
 917         }
 918
 919         ret = 0;
 920         if (pdata->leds) {
 921                 int i;
 922
 923                 for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
 924                         asic3_cell_leds[i].platform_data = &pdata->leds[i];
 925                         asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
 926                 }
 927                 ret = mfd_add_devices(&pdev->dev, 0,
 928                         asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0, NULL);
 929         }
 930
 931  out:
 932         return ret;
 933 }
 934
 935 static void asic3_mfd_remove(struct platform_device *pdev)
 936 {
 937         struct asic3 *asic = platform_get_drvdata(pdev);
 938
 939         mfd_remove_devices(&pdev->dev);
 940         iounmap(asic->tmio_cnf);
 941 }
 942
 943 /* Core */
 944 static int __init asic3_probe(struct platform_device *pdev)
 945 {
 946         struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev);
 947         struct asic3 *asic;
 948         struct resource *mem;
 949         unsigned long clksel;
 950         int ret = 0;
 951
 952         asic = devm_kzalloc(&pdev->dev,
 953                             sizeof(struct asic3), GFP_KERNEL);
 954         if (!asic)
 955                 return -ENOMEM;
 956
 957         raw_spin_lock_init(&asic->lock);
 958         platform_set_drvdata(pdev, asic);
 959         asic->dev = &pdev->dev;
 960
 961         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 962         if (!mem) {
 963                 dev_err(asic->dev, "no MEM resource\n");
 964                 return -ENOMEM;
 965         }
 966
 967         asic->mapping = ioremap(mem->start, resource_size(mem));
 968         if (!asic->mapping) {
 969                 dev_err(asic->dev, "Couldn't ioremap\n");
 970                 return -ENOMEM;
 971         }
 972
 973         asic->irq_base = pdata->irq_base;
 974
 975         /* calculate bus shift from mem resource */
 976         asic->bus_shift = 2 - (resource_size(mem) >> 12);
 977
 978         clksel = 0;
 979         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
 980
 981         ret = asic3_irq_probe(pdev);
 982         if (ret < 0) {
 983                 dev_err(asic->dev, "Couldn't probe IRQs\n");
 984                 goto out_unmap;
 985         }
 986
 987         asic->gpio.label = "asic3";
 988         asic->gpio.base = pdata->gpio_base;
 989         asic->gpio.ngpio = ASIC3_NUM_GPIOS;
 990         asic->gpio.get = asic3_gpio_get;
 991         asic->gpio.set = asic3_gpio_set;
 992         asic->gpio.direction_input = asic3_gpio_direction_input;
 993         asic->gpio.direction_output = asic3_gpio_direction_output;
 994         asic->gpio.to_irq = asic3_gpio_to_irq;
 995
 996         ret = asic3_gpio_probe(pdev,
 997                                pdata->gpio_config,
 998                                pdata->gpio_config_num);
 999         if (ret < 0) {
1000                 dev_err(asic->dev, "GPIO probe failed\n");
1001                 goto out_irq;
1002         }
1003
1004         /* Making a per-device copy is only needed for the
1005          * theoretical case of multiple ASIC3s on one board:
1006          */
1007         memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
1008
1009         asic3_mfd_probe(pdev, pdata, mem);
1010
1011         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1012                 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1);
1013
1014         dev_info(asic->dev, "ASIC3 Core driver\n");
1015
1016         return 0;
1017
1018  out_irq:
1019         asic3_irq_remove(pdev);
1020
1021  out_unmap:
1022         iounmap(asic->mapping);
1023
1024         return ret;
1025 }
1026
1027 static int asic3_remove(struct platform_device *pdev)
1028 {
1029         int ret;
1030         struct asic3 *asic = platform_get_drvdata(pdev);
1031
1032         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1033                 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0);
1034
1035         asic3_mfd_remove(pdev);
1036
1037         ret = asic3_gpio_remove(pdev);
1038         if (ret < 0)
1039                 return ret;
1040         asic3_irq_remove(pdev);
1041
1042         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1043
1044         iounmap(asic->mapping);
1045
1046         return 0;
1047 }
1048
1049 static void asic3_shutdown(struct platform_device *pdev)
1050 {
1051 }
1052
1053 static struct platform_driver asic3_device_driver = {
1054         .driver         = {
1055                 .name   = "asic3",
1056         },
1057         .remove         = asic3_remove,
1058         .shutdown       = asic3_shutdown,
1059 };
1060
1061 static int __init asic3_init(void)
1062 {
1063         int retval = 0;
1064
1065         retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
1066
1067         return retval;
1068 }
1069
1070 subsys_initcall(asic3_init);