1 // SPDX-License-Identifier: GPL-2.0-only
5 * Compaq ASIC3 support.
7 * Copyright 2001 Compaq Computer Corporation.
8 * Copyright 2004-2005 Phil Blundell
9 * Copyright 2007-2008 OpenedHand Ltd.
11 * Authors: Phil Blundell <pb@handhelds.org>,
12 * Samuel Ortiz <sameo@openedhand.com>
15 #include <linux/kernel.h>
16 #include <linux/delay.h>
17 #include <linux/irq.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/export.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
25 #include <linux/mfd/asic3.h>
26 #include <linux/mfd/core.h>
27 #include <linux/mfd/ds1wm.h>
28 #include <linux/mfd/tmio.h>
30 #include <linux/mmc/host.h>
53 #define INIT_CDEX(_name, _rate) \
54 [ASIC3_CLOCK_##_name] = { \
55 .cdex = CLOCK_CDEX_##_name, \
59 static struct asic3_clk asic3_clk_init[] __initdata = {
61 INIT_CDEX(OWM, 5000000),
67 INIT_CDEX(SD_HOST, 24576000),
68 INIT_CDEX(SD_BUS, 12288000),
70 INIT_CDEX(EX0, 32768),
71 INIT_CDEX(EX1, 24576000),
75 void __iomem *mapping;
76 unsigned int bus_shift;
78 unsigned int irq_base;
81 struct gpio_chip gpio;
83 void __iomem *tmio_cnf;
85 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
88 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
90 void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
92 iowrite16(value, asic->mapping +
93 (reg >> asic->bus_shift));
95 EXPORT_SYMBOL_GPL(asic3_write_register);
97 u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
99 return ioread16(asic->mapping +
100 (reg >> asic->bus_shift));
102 EXPORT_SYMBOL_GPL(asic3_read_register);
104 static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
109 raw_spin_lock_irqsave(&asic->lock, flags);
110 val = asic3_read_register(asic, reg);
115 asic3_write_register(asic, reg, val);
116 raw_spin_unlock_irqrestore(&asic->lock, flags);
120 #define MAX_ASIC_ISR_LOOPS 20
121 #define ASIC3_GPIO_BASE_INCR \
122 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
124 static void asic3_irq_flip_edge(struct asic3 *asic,
130 raw_spin_lock_irqsave(&asic->lock, flags);
131 edge = asic3_read_register(asic,
132 base + ASIC3_GPIO_EDGE_TRIGGER);
134 asic3_write_register(asic,
135 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
136 raw_spin_unlock_irqrestore(&asic->lock, flags);
139 static void asic3_irq_demux(struct irq_desc *desc)
141 struct asic3 *asic = irq_desc_get_handler_data(desc);
142 struct irq_data *data = irq_desc_get_irq_data(desc);
146 data->chip->irq_ack(data);
148 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
152 raw_spin_lock_irqsave(&asic->lock, flags);
153 status = asic3_read_register(asic,
154 ASIC3_OFFSET(INTR, P_INT_STAT));
155 raw_spin_unlock_irqrestore(&asic->lock, flags);
157 /* Check all ten register bits */
158 if ((status & 0x3ff) == 0)
161 /* Handle GPIO IRQs */
162 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
163 if (status & (1 << bank)) {
164 unsigned long base, istat;
166 base = ASIC3_GPIO_A_BASE
167 + bank * ASIC3_GPIO_BASE_INCR;
168 raw_spin_lock_irqsave(&asic->lock, flags);
169 istat = asic3_read_register(asic,
171 ASIC3_GPIO_INT_STATUS);
172 /* Clearing IntStatus */
173 asic3_write_register(asic,
175 ASIC3_GPIO_INT_STATUS, 0);
176 raw_spin_unlock_irqrestore(&asic->lock, flags);
178 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
185 irqnr = asic->irq_base +
186 (ASIC3_GPIOS_PER_BANK * bank)
188 generic_handle_irq(irqnr);
189 if (asic->irq_bothedge[bank] & bit)
190 asic3_irq_flip_edge(asic, base,
196 /* Handle remaining IRQs in the status register */
197 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
198 /* They start at bit 4 and go up */
199 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
200 generic_handle_irq(asic->irq_base + i);
204 if (iter >= MAX_ASIC_ISR_LOOPS)
205 dev_err(asic->dev, "interrupt processing overrun\n");
208 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
212 n = (irq - asic->irq_base) >> 4;
214 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
217 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
219 return (irq - asic->irq_base) & 0xf;
222 static void asic3_mask_gpio_irq(struct irq_data *data)
224 struct asic3 *asic = irq_data_get_irq_chip_data(data);
225 u32 val, bank, index;
228 bank = asic3_irq_to_bank(asic, data->irq);
229 index = asic3_irq_to_index(asic, data->irq);
231 raw_spin_lock_irqsave(&asic->lock, flags);
232 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
234 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
235 raw_spin_unlock_irqrestore(&asic->lock, flags);
238 static void asic3_mask_irq(struct irq_data *data)
240 struct asic3 *asic = irq_data_get_irq_chip_data(data);
244 raw_spin_lock_irqsave(&asic->lock, flags);
245 regval = asic3_read_register(asic,
247 ASIC3_INTR_INT_MASK);
249 regval &= ~(ASIC3_INTMASK_MASK0 <<
250 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
252 asic3_write_register(asic,
256 raw_spin_unlock_irqrestore(&asic->lock, flags);
259 static void asic3_unmask_gpio_irq(struct irq_data *data)
261 struct asic3 *asic = irq_data_get_irq_chip_data(data);
262 u32 val, bank, index;
265 bank = asic3_irq_to_bank(asic, data->irq);
266 index = asic3_irq_to_index(asic, data->irq);
268 raw_spin_lock_irqsave(&asic->lock, flags);
269 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
270 val &= ~(1 << index);
271 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
272 raw_spin_unlock_irqrestore(&asic->lock, flags);
275 static void asic3_unmask_irq(struct irq_data *data)
277 struct asic3 *asic = irq_data_get_irq_chip_data(data);
281 raw_spin_lock_irqsave(&asic->lock, flags);
282 regval = asic3_read_register(asic,
284 ASIC3_INTR_INT_MASK);
286 regval |= (ASIC3_INTMASK_MASK0 <<
287 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
289 asic3_write_register(asic,
293 raw_spin_unlock_irqrestore(&asic->lock, flags);
296 static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
298 struct asic3 *asic = irq_data_get_irq_chip_data(data);
300 u16 trigger, level, edge, bit;
303 bank = asic3_irq_to_bank(asic, data->irq);
304 index = asic3_irq_to_index(asic, data->irq);
307 raw_spin_lock_irqsave(&asic->lock, flags);
308 level = asic3_read_register(asic,
309 bank + ASIC3_GPIO_LEVEL_TRIGGER);
310 edge = asic3_read_register(asic,
311 bank + ASIC3_GPIO_EDGE_TRIGGER);
312 trigger = asic3_read_register(asic,
313 bank + ASIC3_GPIO_TRIGGER_TYPE);
314 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
316 if (type == IRQ_TYPE_EDGE_RISING) {
319 } else if (type == IRQ_TYPE_EDGE_FALLING) {
322 } else if (type == IRQ_TYPE_EDGE_BOTH) {
324 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
328 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
329 } else if (type == IRQ_TYPE_LEVEL_LOW) {
332 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
337 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
338 * be careful to not unmask them if mask was also called.
339 * Probably need internal state for mask.
341 dev_notice(asic->dev, "irq type not changed\n");
343 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
345 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
347 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
349 raw_spin_unlock_irqrestore(&asic->lock, flags);
353 static int asic3_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
355 struct asic3 *asic = irq_data_get_irq_chip_data(data);
359 bank = asic3_irq_to_bank(asic, data->irq);
360 index = asic3_irq_to_index(asic, data->irq);
363 asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on);
368 static struct irq_chip asic3_gpio_irq_chip = {
369 .name = "ASIC3-GPIO",
370 .irq_ack = asic3_mask_gpio_irq,
371 .irq_mask = asic3_mask_gpio_irq,
372 .irq_unmask = asic3_unmask_gpio_irq,
373 .irq_set_type = asic3_gpio_irq_type,
374 .irq_set_wake = asic3_gpio_irq_set_wake,
377 static struct irq_chip asic3_irq_chip = {
379 .irq_ack = asic3_mask_irq,
380 .irq_mask = asic3_mask_irq,
381 .irq_unmask = asic3_unmask_irq,
384 static int __init asic3_irq_probe(struct platform_device *pdev)
386 struct asic3 *asic = platform_get_drvdata(pdev);
387 unsigned long clksel = 0;
388 unsigned int irq, irq_base;
391 ret = platform_get_irq(pdev, 0);
396 /* turn on clock to IRQ controller */
397 clksel |= CLOCK_SEL_CX;
398 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
401 irq_base = asic->irq_base;
403 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
404 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
405 irq_set_chip(irq, &asic3_gpio_irq_chip);
407 irq_set_chip(irq, &asic3_irq_chip);
409 irq_set_chip_data(irq, asic);
410 irq_set_handler(irq, handle_level_irq);
411 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
414 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
415 ASIC3_INTMASK_GINTMASK);
417 irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic);
418 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
423 static void asic3_irq_remove(struct platform_device *pdev)
425 struct asic3 *asic = platform_get_drvdata(pdev);
426 unsigned int irq, irq_base;
428 irq_base = asic->irq_base;
430 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
431 irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
432 irq_set_chip_and_handler(irq, NULL, NULL);
433 irq_set_chip_data(irq, NULL);
435 irq_set_chained_handler(asic->irq_nr, NULL);
439 static int asic3_gpio_direction(struct gpio_chip *chip,
440 unsigned offset, int out)
442 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
443 unsigned int gpio_base;
447 asic = gpiochip_get_data(chip);
448 gpio_base = ASIC3_GPIO_TO_BASE(offset);
450 if (gpio_base > ASIC3_GPIO_D_BASE) {
451 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
456 raw_spin_lock_irqsave(&asic->lock, flags);
458 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
460 /* Input is 0, Output is 1 */
466 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
468 raw_spin_unlock_irqrestore(&asic->lock, flags);
474 static int asic3_gpio_direction_input(struct gpio_chip *chip,
477 return asic3_gpio_direction(chip, offset, 0);
480 static int asic3_gpio_direction_output(struct gpio_chip *chip,
481 unsigned offset, int value)
483 return asic3_gpio_direction(chip, offset, 1);
486 static int asic3_gpio_get(struct gpio_chip *chip,
489 unsigned int gpio_base;
490 u32 mask = ASIC3_GPIO_TO_MASK(offset);
493 asic = gpiochip_get_data(chip);
494 gpio_base = ASIC3_GPIO_TO_BASE(offset);
496 if (gpio_base > ASIC3_GPIO_D_BASE) {
497 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
502 return !!(asic3_read_register(asic,
503 gpio_base + ASIC3_GPIO_STATUS) & mask);
506 static void asic3_gpio_set(struct gpio_chip *chip,
507 unsigned offset, int value)
510 unsigned int gpio_base;
514 asic = gpiochip_get_data(chip);
515 gpio_base = ASIC3_GPIO_TO_BASE(offset);
517 if (gpio_base > ASIC3_GPIO_D_BASE) {
518 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
523 mask = ASIC3_GPIO_TO_MASK(offset);
525 raw_spin_lock_irqsave(&asic->lock, flags);
527 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
534 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
536 raw_spin_unlock_irqrestore(&asic->lock, flags);
539 static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
541 struct asic3 *asic = gpiochip_get_data(chip);
543 return asic->irq_base + offset;
546 static __init int asic3_gpio_probe(struct platform_device *pdev,
547 u16 *gpio_config, int num)
549 struct asic3 *asic = platform_get_drvdata(pdev);
550 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
551 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
552 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
555 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
556 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
557 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
559 /* Enable all GPIOs */
560 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
561 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
562 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
563 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
565 for (i = 0; i < num; i++) {
566 u8 alt, pin, dir, init, bank_num, bit_num;
567 u16 config = gpio_config[i];
569 pin = ASIC3_CONFIG_GPIO_PIN(config);
570 alt = ASIC3_CONFIG_GPIO_ALT(config);
571 dir = ASIC3_CONFIG_GPIO_DIR(config);
572 init = ASIC3_CONFIG_GPIO_INIT(config);
574 bank_num = ASIC3_GPIO_TO_BANK(pin);
575 bit_num = ASIC3_GPIO_TO_BIT(pin);
577 alt_reg[bank_num] |= (alt << bit_num);
578 out_reg[bank_num] |= (init << bit_num);
579 dir_reg[bank_num] |= (dir << bit_num);
582 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
583 asic3_write_register(asic,
584 ASIC3_BANK_TO_BASE(i) +
585 ASIC3_GPIO_DIRECTION,
587 asic3_write_register(asic,
588 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
590 asic3_write_register(asic,
591 ASIC3_BANK_TO_BASE(i) +
592 ASIC3_GPIO_ALT_FUNCTION,
596 return gpiochip_add_data(&asic->gpio, asic);
599 static int asic3_gpio_remove(struct platform_device *pdev)
601 struct asic3 *asic = platform_get_drvdata(pdev);
603 gpiochip_remove(&asic->gpio);
607 static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
612 raw_spin_lock_irqsave(&asic->lock, flags);
613 if (clk->enabled++ == 0) {
614 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
616 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
618 raw_spin_unlock_irqrestore(&asic->lock, flags);
621 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
626 WARN_ON(clk->enabled == 0);
628 raw_spin_lock_irqsave(&asic->lock, flags);
629 if (--clk->enabled == 0) {
630 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
632 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
634 raw_spin_unlock_irqrestore(&asic->lock, flags);
637 /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
638 static struct ds1wm_driver_data ds1wm_pdata = {
640 .reset_recover_delay = 1,
643 static struct resource ds1wm_resources[] = {
645 .start = ASIC3_OWM_BASE,
646 .end = ASIC3_OWM_BASE + 0x13,
647 .flags = IORESOURCE_MEM,
650 .start = ASIC3_IRQ_OWM,
651 .end = ASIC3_IRQ_OWM,
652 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
656 static int ds1wm_enable(struct platform_device *pdev)
658 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
660 /* Turn on external clocks and the OWM clock */
661 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
662 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
663 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
664 usleep_range(1000, 5000);
666 /* Reset and enable DS1WM */
667 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
668 ASIC3_EXTCF_OWM_RESET, 1);
669 usleep_range(1000, 5000);
670 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
671 ASIC3_EXTCF_OWM_RESET, 0);
672 usleep_range(1000, 5000);
673 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
674 ASIC3_EXTCF_OWM_EN, 1);
675 usleep_range(1000, 5000);
680 static int ds1wm_disable(struct platform_device *pdev)
682 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
684 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
685 ASIC3_EXTCF_OWM_EN, 0);
687 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
688 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
689 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
694 static const struct mfd_cell asic3_cell_ds1wm = {
696 .enable = ds1wm_enable,
697 .disable = ds1wm_disable,
698 .platform_data = &ds1wm_pdata,
699 .pdata_size = sizeof(ds1wm_pdata),
700 .num_resources = ARRAY_SIZE(ds1wm_resources),
701 .resources = ds1wm_resources,
704 static void asic3_mmc_pwr(struct platform_device *pdev, int state)
706 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
708 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
711 static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
713 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
715 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
718 static struct tmio_mmc_data asic3_mmc_data = {
720 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
721 .set_pwr = asic3_mmc_pwr,
722 .set_clk_div = asic3_mmc_clk_div,
725 static struct resource asic3_mmc_resources[] = {
726 DEFINE_RES_MEM(ASIC3_SD_CTRL_BASE, 0x400),
730 static int asic3_mmc_enable(struct platform_device *pdev)
732 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
734 /* Not sure if it must be done bit by bit, but leaving as-is */
735 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
736 ASIC3_SDHWCTRL_LEVCD, 1);
737 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
738 ASIC3_SDHWCTRL_LEVWP, 1);
739 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
740 ASIC3_SDHWCTRL_SUSPEND, 0);
741 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
742 ASIC3_SDHWCTRL_PCLR, 0);
744 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
745 /* CLK32 used for card detection and for interruption detection
746 * when HCLK is stopped.
748 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
749 usleep_range(1000, 5000);
751 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
752 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
753 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
755 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
756 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
757 usleep_range(1000, 5000);
759 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
760 ASIC3_EXTCF_SD_MEM_ENABLE, 1);
762 /* Enable SD card slot 3.3V power supply */
763 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
764 ASIC3_SDHWCTRL_SDPWR, 1);
766 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
767 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
768 ASIC3_SD_CTRL_BASE >> 1);
773 static int asic3_mmc_disable(struct platform_device *pdev)
775 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
777 /* Put in suspend mode */
778 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
779 ASIC3_SDHWCTRL_SUSPEND, 1);
782 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
783 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
784 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
785 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
789 static const struct mfd_cell asic3_cell_mmc = {
791 .enable = asic3_mmc_enable,
792 .disable = asic3_mmc_disable,
793 .suspend = asic3_mmc_disable,
794 .resume = asic3_mmc_enable,
795 .platform_data = &asic3_mmc_data,
796 .pdata_size = sizeof(asic3_mmc_data),
797 .num_resources = ARRAY_SIZE(asic3_mmc_resources),
798 .resources = asic3_mmc_resources,
801 static const int clock_ledn[ASIC3_NUM_LEDS] = {
802 [0] = ASIC3_CLOCK_LED0,
803 [1] = ASIC3_CLOCK_LED1,
804 [2] = ASIC3_CLOCK_LED2,
807 static int asic3_leds_enable(struct platform_device *pdev)
809 const struct mfd_cell *cell = mfd_get_cell(pdev);
810 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
812 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
817 static int asic3_leds_disable(struct platform_device *pdev)
819 const struct mfd_cell *cell = mfd_get_cell(pdev);
820 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
822 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
827 static int asic3_leds_suspend(struct platform_device *pdev)
829 const struct mfd_cell *cell = mfd_get_cell(pdev);
830 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
832 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
833 usleep_range(1000, 5000);
835 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
840 static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
842 .name = "leds-asic3",
844 .enable = asic3_leds_enable,
845 .disable = asic3_leds_disable,
846 .suspend = asic3_leds_suspend,
847 .resume = asic3_leds_enable,
850 .name = "leds-asic3",
852 .enable = asic3_leds_enable,
853 .disable = asic3_leds_disable,
854 .suspend = asic3_leds_suspend,
855 .resume = asic3_leds_enable,
858 .name = "leds-asic3",
860 .enable = asic3_leds_enable,
861 .disable = asic3_leds_disable,
862 .suspend = asic3_leds_suspend,
863 .resume = asic3_leds_enable,
867 static int __init asic3_mfd_probe(struct platform_device *pdev,
868 struct asic3_platform_data *pdata,
869 struct resource *mem)
871 struct asic3 *asic = platform_get_drvdata(pdev);
872 struct resource *mem_sdio;
875 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
877 dev_dbg(asic->dev, "no SDIO MEM resource\n");
879 irq = platform_get_irq(pdev, 1);
881 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
884 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
885 ASIC3_EXTCF_OWM_SMB, 0);
887 ds1wm_resources[0].start >>= asic->bus_shift;
888 ds1wm_resources[0].end >>= asic->bus_shift;
892 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >>
893 asic->bus_shift) + mem_sdio->start,
894 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
895 if (!asic->tmio_cnf) {
897 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
901 asic3_mmc_resources[0].start >>= asic->bus_shift;
902 asic3_mmc_resources[0].end >>= asic->bus_shift;
904 if (pdata->clock_rate) {
905 ds1wm_pdata.clock_rate = pdata->clock_rate;
906 ret = mfd_add_devices(&pdev->dev, pdev->id,
907 &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL);
912 if (mem_sdio && (irq >= 0)) {
913 ret = mfd_add_devices(&pdev->dev, pdev->id,
914 &asic3_cell_mmc, 1, mem_sdio, irq, NULL);
923 for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
924 asic3_cell_leds[i].platform_data = &pdata->leds[i];
925 asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
927 ret = mfd_add_devices(&pdev->dev, 0,
928 asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0, NULL);
935 static void asic3_mfd_remove(struct platform_device *pdev)
937 struct asic3 *asic = platform_get_drvdata(pdev);
939 mfd_remove_devices(&pdev->dev);
940 iounmap(asic->tmio_cnf);
944 static int __init asic3_probe(struct platform_device *pdev)
946 struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev);
948 struct resource *mem;
949 unsigned long clksel;
952 asic = devm_kzalloc(&pdev->dev,
953 sizeof(struct asic3), GFP_KERNEL);
957 raw_spin_lock_init(&asic->lock);
958 platform_set_drvdata(pdev, asic);
959 asic->dev = &pdev->dev;
961 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
963 dev_err(asic->dev, "no MEM resource\n");
967 asic->mapping = ioremap(mem->start, resource_size(mem));
968 if (!asic->mapping) {
969 dev_err(asic->dev, "Couldn't ioremap\n");
973 asic->irq_base = pdata->irq_base;
975 /* calculate bus shift from mem resource */
976 asic->bus_shift = 2 - (resource_size(mem) >> 12);
979 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
981 ret = asic3_irq_probe(pdev);
983 dev_err(asic->dev, "Couldn't probe IRQs\n");
987 asic->gpio.label = "asic3";
988 asic->gpio.base = pdata->gpio_base;
989 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
990 asic->gpio.get = asic3_gpio_get;
991 asic->gpio.set = asic3_gpio_set;
992 asic->gpio.direction_input = asic3_gpio_direction_input;
993 asic->gpio.direction_output = asic3_gpio_direction_output;
994 asic->gpio.to_irq = asic3_gpio_to_irq;
996 ret = asic3_gpio_probe(pdev,
998 pdata->gpio_config_num);
1000 dev_err(asic->dev, "GPIO probe failed\n");
1004 /* Making a per-device copy is only needed for the
1005 * theoretical case of multiple ASIC3s on one board:
1007 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
1009 asic3_mfd_probe(pdev, pdata, mem);
1011 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1012 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1);
1014 dev_info(asic->dev, "ASIC3 Core driver\n");
1019 asic3_irq_remove(pdev);
1022 iounmap(asic->mapping);
1027 static int asic3_remove(struct platform_device *pdev)
1030 struct asic3 *asic = platform_get_drvdata(pdev);
1032 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1033 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0);
1035 asic3_mfd_remove(pdev);
1037 ret = asic3_gpio_remove(pdev);
1040 asic3_irq_remove(pdev);
1042 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1044 iounmap(asic->mapping);
1049 static void asic3_shutdown(struct platform_device *pdev)
1053 static struct platform_driver asic3_device_driver = {
1057 .remove = asic3_remove,
1058 .shutdown = asic3_shutdown,
1061 static int __init asic3_init(void)
1065 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
1070 subsys_initcall(asic3_init);