2 * jmb38x_ms.c - JMicron jmb38x MemoryStick card reader
4 * Copyright (C) 2008 Alex Dubov <oakad@yahoo.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/spinlock.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/memstick.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
22 #define DRIVER_NAME "jmb38x_ms"
25 module_param(no_dma, bool, 0644);
38 INT_STATUS_ENABLE = 0x28,
39 INT_SIGNAL_ENABLE = 0x2c,
42 PAD_OUTPUT_ENABLE = 0x38,
51 struct jmb38x_ms_host {
52 struct jmb38x_ms *chip;
55 struct tasklet_struct notify;
59 unsigned int block_pos;
60 unsigned long timeout_jiffies;
61 struct timer_list timer;
62 struct memstick_host *msh;
63 struct memstick_request *req;
64 unsigned char cmd_flags;
67 unsigned int io_word[2];
73 struct memstick_host *hosts[];
76 #define BLOCK_COUNT_MASK 0xffff0000
77 #define BLOCK_SIZE_MASK 0x00000fff
79 #define DMA_CONTROL_ENABLE 0x00000001
81 #define TPC_DATA_SEL 0x00008000
82 #define TPC_DIR 0x00004000
83 #define TPC_WAIT_INT 0x00002000
84 #define TPC_GET_INT 0x00000800
85 #define TPC_CODE_SZ_MASK 0x00000700
86 #define TPC_DATA_SZ_MASK 0x00000007
88 #define HOST_CONTROL_TDELAY_EN 0x00040000
89 #define HOST_CONTROL_HW_OC_P 0x00010000
90 #define HOST_CONTROL_RESET_REQ 0x00008000
91 #define HOST_CONTROL_REI 0x00004000
92 #define HOST_CONTROL_LED 0x00000400
93 #define HOST_CONTROL_FAST_CLK 0x00000200
94 #define HOST_CONTROL_RESET 0x00000100
95 #define HOST_CONTROL_POWER_EN 0x00000080
96 #define HOST_CONTROL_CLOCK_EN 0x00000040
97 #define HOST_CONTROL_REO 0x00000008
98 #define HOST_CONTROL_IF_SHIFT 4
100 #define HOST_CONTROL_IF_SERIAL 0x0
101 #define HOST_CONTROL_IF_PAR4 0x1
102 #define HOST_CONTROL_IF_PAR8 0x3
104 #define STATUS_BUSY 0x00080000
105 #define STATUS_MS_DAT7 0x00040000
106 #define STATUS_MS_DAT6 0x00020000
107 #define STATUS_MS_DAT5 0x00010000
108 #define STATUS_MS_DAT4 0x00008000
109 #define STATUS_MS_DAT3 0x00004000
110 #define STATUS_MS_DAT2 0x00002000
111 #define STATUS_MS_DAT1 0x00001000
112 #define STATUS_MS_DAT0 0x00000800
113 #define STATUS_HAS_MEDIA 0x00000400
114 #define STATUS_FIFO_EMPTY 0x00000200
115 #define STATUS_FIFO_FULL 0x00000100
116 #define STATUS_MS_CED 0x00000080
117 #define STATUS_MS_ERR 0x00000040
118 #define STATUS_MS_BRQ 0x00000020
119 #define STATUS_MS_CNK 0x00000001
121 #define INT_STATUS_TPC_ERR 0x00080000
122 #define INT_STATUS_CRC_ERR 0x00040000
123 #define INT_STATUS_TIMER_TO 0x00020000
124 #define INT_STATUS_HSK_TO 0x00010000
125 #define INT_STATUS_ANY_ERR 0x00008000
126 #define INT_STATUS_FIFO_WRDY 0x00000080
127 #define INT_STATUS_FIFO_RRDY 0x00000040
128 #define INT_STATUS_MEDIA_OUT 0x00000010
129 #define INT_STATUS_MEDIA_IN 0x00000008
130 #define INT_STATUS_DMA_BOUNDARY 0x00000004
131 #define INT_STATUS_EOTRAN 0x00000002
132 #define INT_STATUS_EOTPC 0x00000001
134 #define INT_STATUS_ALL 0x000f801f
136 #define PAD_OUTPUT_ENABLE_MS 0x0F3F
138 #define PAD_PU_PD_OFF 0x7FFF0000
139 #define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000
140 #define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000
142 #define CLOCK_CONTROL_BY_MMIO 0x00000008
143 #define CLOCK_CONTROL_40MHZ 0x00000001
144 #define CLOCK_CONTROL_50MHZ 0x00000002
145 #define CLOCK_CONTROL_60MHZ 0x00000010
146 #define CLOCK_CONTROL_62_5MHZ 0x00000004
147 #define CLOCK_CONTROL_OFF 0x00000000
149 #define PCI_CTL_CLOCK_DLY_ADDR 0x000000b0
158 static unsigned int jmb38x_ms_read_data(struct jmb38x_ms_host *host,
159 unsigned char *buf, unsigned int length)
161 unsigned int off = 0;
163 while (host->io_pos && length) {
164 buf[off++] = host->io_word[0] & 0xff;
165 host->io_word[0] >>= 8;
173 while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
176 *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA);
182 && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
183 host->io_word[0] = readl(host->addr + DATA);
184 for (host->io_pos = 4; host->io_pos; --host->io_pos) {
185 buf[off++] = host->io_word[0] & 0xff;
186 host->io_word[0] >>= 8;
196 static unsigned int jmb38x_ms_read_reg_data(struct jmb38x_ms_host *host,
200 unsigned int off = 0;
202 while (host->io_pos > 4 && length) {
203 buf[off++] = host->io_word[0] & 0xff;
204 host->io_word[0] >>= 8;
212 while (host->io_pos && length) {
213 buf[off++] = host->io_word[1] & 0xff;
214 host->io_word[1] >>= 8;
222 static unsigned int jmb38x_ms_write_data(struct jmb38x_ms_host *host,
226 unsigned int off = 0;
229 while (host->io_pos < 4 && length) {
230 host->io_word[0] |= buf[off++] << (host->io_pos * 8);
236 if (host->io_pos == 4
237 && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
238 writel(host->io_word[0], host->addr + DATA);
240 host->io_word[0] = 0;
241 } else if (host->io_pos) {
248 while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
252 __raw_writel(*(unsigned int *)(buf + off),
260 host->io_word[0] |= buf[off + 2] << 16;
264 host->io_word[0] |= buf[off + 1] << 8;
268 host->io_word[0] |= buf[off];
277 static unsigned int jmb38x_ms_write_reg_data(struct jmb38x_ms_host *host,
281 unsigned int off = 0;
283 while (host->io_pos < 4 && length) {
284 host->io_word[0] &= ~(0xff << (host->io_pos * 8));
285 host->io_word[0] |= buf[off++] << (host->io_pos * 8);
293 while (host->io_pos < 8 && length) {
294 host->io_word[1] &= ~(0xff << (host->io_pos * 8));
295 host->io_word[1] |= buf[off++] << (host->io_pos * 8);
303 static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host)
307 unsigned int t_size, p_cnt;
310 unsigned long flags = 0;
312 if (host->req->long_data) {
313 length = host->req->sg.length - host->block_pos;
314 off = host->req->sg.offset + host->block_pos;
316 length = host->req->data_len - host->block_pos;
321 unsigned int uninitialized_var(p_off);
323 if (host->req->long_data) {
324 pg = nth_page(sg_page(&host->req->sg),
326 p_off = offset_in_page(off);
327 p_cnt = PAGE_SIZE - p_off;
328 p_cnt = min(p_cnt, length);
330 local_irq_save(flags);
331 buf = kmap_atomic(pg) + p_off;
333 buf = host->req->data + host->block_pos;
334 p_cnt = host->req->data_len - host->block_pos;
337 if (host->req->data_dir == WRITE)
338 t_size = !(host->cmd_flags & REG_DATA)
339 ? jmb38x_ms_write_data(host, buf, p_cnt)
340 : jmb38x_ms_write_reg_data(host, buf, p_cnt);
342 t_size = !(host->cmd_flags & REG_DATA)
343 ? jmb38x_ms_read_data(host, buf, p_cnt)
344 : jmb38x_ms_read_reg_data(host, buf, p_cnt);
346 if (host->req->long_data) {
347 kunmap_atomic(buf - p_off);
348 local_irq_restore(flags);
353 host->block_pos += t_size;
358 if (!length && host->req->data_dir == WRITE) {
359 if (host->cmd_flags & REG_DATA) {
360 writel(host->io_word[0], host->addr + TPC_P0);
361 writel(host->io_word[1], host->addr + TPC_P1);
362 } else if (host->io_pos) {
363 writel(host->io_word[0], host->addr + DATA);
370 static int jmb38x_ms_issue_cmd(struct memstick_host *msh)
372 struct jmb38x_ms_host *host = memstick_priv(msh);
373 unsigned int data_len, cmd, t_val;
375 if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) {
376 dev_dbg(&msh->dev, "no media status\n");
377 host->req->error = -ETIME;
378 return host->req->error;
381 dev_dbg(&msh->dev, "control %08x\n", readl(host->addr + HOST_CONTROL));
382 dev_dbg(&msh->dev, "status %08x\n", readl(host->addr + INT_STATUS));
383 dev_dbg(&msh->dev, "hstatus %08x\n", readl(host->addr + STATUS));
388 host->io_word[0] = 0;
389 host->io_word[1] = 0;
391 cmd = host->req->tpc << 16;
394 if (host->req->data_dir == READ)
397 if (host->req->need_card_int) {
398 if (host->ifmode == MEMSTICK_SERIAL)
405 host->cmd_flags |= DMA_DATA;
407 if (host->req->long_data) {
408 data_len = host->req->sg.length;
410 data_len = host->req->data_len;
411 host->cmd_flags &= ~DMA_DATA;
415 cmd &= ~(TPC_DATA_SEL | 0xf);
416 host->cmd_flags |= REG_DATA;
417 cmd |= data_len & 0xf;
418 host->cmd_flags &= ~DMA_DATA;
421 if (host->cmd_flags & DMA_DATA) {
422 if (1 != dma_map_sg(&host->chip->pdev->dev, &host->req->sg, 1,
423 host->req->data_dir == READ
426 host->req->error = -ENOMEM;
427 return host->req->error;
429 data_len = sg_dma_len(&host->req->sg);
430 writel(sg_dma_address(&host->req->sg),
431 host->addr + DMA_ADDRESS);
432 writel(((1 << 16) & BLOCK_COUNT_MASK)
433 | (data_len & BLOCK_SIZE_MASK),
435 writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL);
436 } else if (!(host->cmd_flags & REG_DATA)) {
437 writel(((1 << 16) & BLOCK_COUNT_MASK)
438 | (data_len & BLOCK_SIZE_MASK),
440 t_val = readl(host->addr + INT_STATUS_ENABLE);
441 t_val |= host->req->data_dir == READ
442 ? INT_STATUS_FIFO_RRDY
443 : INT_STATUS_FIFO_WRDY;
445 writel(t_val, host->addr + INT_STATUS_ENABLE);
446 writel(t_val, host->addr + INT_SIGNAL_ENABLE);
448 cmd &= ~(TPC_DATA_SEL | 0xf);
449 host->cmd_flags |= REG_DATA;
450 cmd |= data_len & 0xf;
452 if (host->req->data_dir == WRITE) {
453 jmb38x_ms_transfer_data(host);
454 writel(host->io_word[0], host->addr + TPC_P0);
455 writel(host->io_word[1], host->addr + TPC_P1);
459 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
460 writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL),
461 host->addr + HOST_CONTROL);
462 host->req->error = 0;
464 writel(cmd, host->addr + TPC);
465 dev_dbg(&msh->dev, "executing TPC %08x, len %x\n", cmd, data_len);
470 static void jmb38x_ms_complete_cmd(struct memstick_host *msh, int last)
472 struct jmb38x_ms_host *host = memstick_priv(msh);
473 unsigned int t_val = 0;
476 del_timer(&host->timer);
478 dev_dbg(&msh->dev, "c control %08x\n",
479 readl(host->addr + HOST_CONTROL));
480 dev_dbg(&msh->dev, "c status %08x\n",
481 readl(host->addr + INT_STATUS));
482 dev_dbg(&msh->dev, "c hstatus %08x\n", readl(host->addr + STATUS));
484 host->req->int_reg = readl(host->addr + STATUS) & 0xff;
486 writel(0, host->addr + BLOCK);
487 writel(0, host->addr + DMA_CONTROL);
489 if (host->cmd_flags & DMA_DATA) {
490 dma_unmap_sg(&host->chip->pdev->dev, &host->req->sg, 1,
491 host->req->data_dir == READ
492 ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
494 t_val = readl(host->addr + INT_STATUS_ENABLE);
495 if (host->req->data_dir == READ)
496 t_val &= ~INT_STATUS_FIFO_RRDY;
498 t_val &= ~INT_STATUS_FIFO_WRDY;
500 writel(t_val, host->addr + INT_STATUS_ENABLE);
501 writel(t_val, host->addr + INT_SIGNAL_ENABLE);
504 writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL),
505 host->addr + HOST_CONTROL);
509 rc = memstick_next_req(msh, &host->req);
510 } while (!rc && jmb38x_ms_issue_cmd(msh));
513 rc = memstick_next_req(msh, &host->req);
515 host->req->error = -ETIME;
520 static irqreturn_t jmb38x_ms_isr(int irq, void *dev_id)
522 struct memstick_host *msh = dev_id;
523 struct jmb38x_ms_host *host = memstick_priv(msh);
524 unsigned int irq_status;
526 spin_lock(&host->lock);
527 irq_status = readl(host->addr + INT_STATUS);
528 dev_dbg(&host->chip->pdev->dev, "irq_status = %08x\n", irq_status);
529 if (irq_status == 0 || irq_status == (~0)) {
530 spin_unlock(&host->lock);
535 if (irq_status & INT_STATUS_ANY_ERR) {
536 if (irq_status & INT_STATUS_CRC_ERR)
537 host->req->error = -EILSEQ;
538 else if (irq_status & INT_STATUS_TPC_ERR) {
539 dev_dbg(&host->chip->pdev->dev, "TPC_ERR\n");
540 jmb38x_ms_complete_cmd(msh, 0);
542 host->req->error = -ETIME;
544 if (host->cmd_flags & DMA_DATA) {
545 if (irq_status & INT_STATUS_EOTRAN)
546 host->cmd_flags |= FIFO_READY;
548 if (irq_status & (INT_STATUS_FIFO_RRDY
549 | INT_STATUS_FIFO_WRDY))
550 jmb38x_ms_transfer_data(host);
552 if (irq_status & INT_STATUS_EOTRAN) {
553 jmb38x_ms_transfer_data(host);
554 host->cmd_flags |= FIFO_READY;
558 if (irq_status & INT_STATUS_EOTPC) {
559 host->cmd_flags |= CMD_READY;
560 if (host->cmd_flags & REG_DATA) {
561 if (host->req->data_dir == READ) {
570 jmb38x_ms_transfer_data(host);
572 host->cmd_flags |= FIFO_READY;
578 if (irq_status & (INT_STATUS_MEDIA_IN | INT_STATUS_MEDIA_OUT)) {
579 dev_dbg(&host->chip->pdev->dev, "media changed\n");
580 memstick_detect_change(msh);
583 writel(irq_status, host->addr + INT_STATUS);
586 && (((host->cmd_flags & CMD_READY)
587 && (host->cmd_flags & FIFO_READY))
588 || host->req->error))
589 jmb38x_ms_complete_cmd(msh, 0);
591 spin_unlock(&host->lock);
595 static void jmb38x_ms_abort(struct timer_list *t)
597 struct jmb38x_ms_host *host = from_timer(host, t, timer);
598 struct memstick_host *msh = host->msh;
601 dev_dbg(&host->chip->pdev->dev, "abort\n");
602 spin_lock_irqsave(&host->lock, flags);
604 host->req->error = -ETIME;
605 jmb38x_ms_complete_cmd(msh, 0);
607 spin_unlock_irqrestore(&host->lock, flags);
610 static void jmb38x_ms_req_tasklet(unsigned long data)
612 struct memstick_host *msh = (struct memstick_host *)data;
613 struct jmb38x_ms_host *host = memstick_priv(msh);
617 spin_lock_irqsave(&host->lock, flags);
620 rc = memstick_next_req(msh, &host->req);
621 dev_dbg(&host->chip->pdev->dev, "tasklet req %d\n", rc);
622 } while (!rc && jmb38x_ms_issue_cmd(msh));
624 spin_unlock_irqrestore(&host->lock, flags);
627 static void jmb38x_ms_dummy_submit(struct memstick_host *msh)
632 static void jmb38x_ms_submit_req(struct memstick_host *msh)
634 struct jmb38x_ms_host *host = memstick_priv(msh);
636 tasklet_schedule(&host->notify);
639 static int jmb38x_ms_reset(struct jmb38x_ms_host *host)
643 writel(HOST_CONTROL_RESET_REQ | HOST_CONTROL_CLOCK_EN
644 | readl(host->addr + HOST_CONTROL),
645 host->addr + HOST_CONTROL);
647 for (cnt = 0; cnt < 20; ++cnt) {
648 if (!(HOST_CONTROL_RESET_REQ
649 & readl(host->addr + HOST_CONTROL)))
654 dev_dbg(&host->chip->pdev->dev, "reset_req timeout\n");
657 writel(HOST_CONTROL_RESET | HOST_CONTROL_CLOCK_EN
658 | readl(host->addr + HOST_CONTROL),
659 host->addr + HOST_CONTROL);
661 for (cnt = 0; cnt < 20; ++cnt) {
662 if (!(HOST_CONTROL_RESET
663 & readl(host->addr + HOST_CONTROL)))
668 dev_dbg(&host->chip->pdev->dev, "reset timeout\n");
672 writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE);
673 writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
677 static int jmb38x_ms_set_param(struct memstick_host *msh,
678 enum memstick_param param,
681 struct jmb38x_ms_host *host = memstick_priv(msh);
682 unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
683 unsigned int clock_ctl = CLOCK_CONTROL_BY_MMIO, clock_delay = 0;
688 if (value == MEMSTICK_POWER_ON) {
689 rc = jmb38x_ms_reset(host);
694 host_ctl |= HOST_CONTROL_POWER_EN
695 | HOST_CONTROL_CLOCK_EN;
696 writel(host_ctl, host->addr + HOST_CONTROL);
698 writel(host->id ? PAD_PU_PD_ON_MS_SOCK1
699 : PAD_PU_PD_ON_MS_SOCK0,
700 host->addr + PAD_PU_PD);
702 writel(PAD_OUTPUT_ENABLE_MS,
703 host->addr + PAD_OUTPUT_ENABLE);
706 dev_dbg(&host->chip->pdev->dev, "power on\n");
707 } else if (value == MEMSTICK_POWER_OFF) {
708 host_ctl &= ~(HOST_CONTROL_POWER_EN
709 | HOST_CONTROL_CLOCK_EN);
710 writel(host_ctl, host->addr + HOST_CONTROL);
711 writel(0, host->addr + PAD_OUTPUT_ENABLE);
712 writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD);
713 dev_dbg(&host->chip->pdev->dev, "power off\n");
717 case MEMSTICK_INTERFACE:
718 dev_dbg(&host->chip->pdev->dev,
719 "Set Host Interface Mode to %d\n", value);
720 host_ctl &= ~(HOST_CONTROL_FAST_CLK | HOST_CONTROL_REI |
722 host_ctl |= HOST_CONTROL_TDELAY_EN | HOST_CONTROL_HW_OC_P;
723 host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT);
725 if (value == MEMSTICK_SERIAL) {
726 host_ctl |= HOST_CONTROL_IF_SERIAL
727 << HOST_CONTROL_IF_SHIFT;
728 host_ctl |= HOST_CONTROL_REI;
729 clock_ctl |= CLOCK_CONTROL_40MHZ;
731 } else if (value == MEMSTICK_PAR4) {
732 host_ctl |= HOST_CONTROL_FAST_CLK;
733 host_ctl |= HOST_CONTROL_IF_PAR4
734 << HOST_CONTROL_IF_SHIFT;
735 host_ctl |= HOST_CONTROL_REO;
736 clock_ctl |= CLOCK_CONTROL_40MHZ;
738 } else if (value == MEMSTICK_PAR8) {
739 host_ctl |= HOST_CONTROL_FAST_CLK;
740 host_ctl |= HOST_CONTROL_IF_PAR8
741 << HOST_CONTROL_IF_SHIFT;
742 clock_ctl |= CLOCK_CONTROL_50MHZ;
747 writel(host_ctl, host->addr + HOST_CONTROL);
748 writel(CLOCK_CONTROL_OFF, host->addr + CLOCK_CONTROL);
749 writel(clock_ctl, host->addr + CLOCK_CONTROL);
750 pci_write_config_byte(host->chip->pdev,
751 PCI_CTL_CLOCK_DLY_ADDR + 1,
753 host->ifmode = value;
759 #define PCI_PMOS0_CONTROL 0xae
760 #define PMOS0_ENABLE 0x01
761 #define PMOS0_OVERCURRENT_LEVEL_2_4V 0x06
762 #define PMOS0_EN_OVERCURRENT_DEBOUNCE 0x40
763 #define PMOS0_SW_LED_POLARITY_ENABLE 0x80
764 #define PMOS0_ACTIVE_BITS (PMOS0_ENABLE | PMOS0_EN_OVERCURRENT_DEBOUNCE | \
765 PMOS0_OVERCURRENT_LEVEL_2_4V)
766 #define PCI_PMOS1_CONTROL 0xbd
767 #define PMOS1_ACTIVE_BITS 0x4a
768 #define PCI_CLOCK_CTL 0xb9
770 static int jmb38x_ms_pmos(struct pci_dev *pdev, int flag)
774 pci_read_config_byte(pdev, PCI_PMOS0_CONTROL, &val);
776 val |= PMOS0_ACTIVE_BITS;
778 val &= ~PMOS0_ACTIVE_BITS;
779 pci_write_config_byte(pdev, PCI_PMOS0_CONTROL, val);
780 dev_dbg(&pdev->dev, "JMB38x: set PMOS0 val 0x%x\n", val);
782 if (pci_resource_flags(pdev, 1)) {
783 pci_read_config_byte(pdev, PCI_PMOS1_CONTROL, &val);
785 val |= PMOS1_ACTIVE_BITS;
787 val &= ~PMOS1_ACTIVE_BITS;
788 pci_write_config_byte(pdev, PCI_PMOS1_CONTROL, val);
789 dev_dbg(&pdev->dev, "JMB38x: set PMOS1 val 0x%x\n", val);
792 pci_read_config_byte(pdev, PCI_CLOCK_CTL, &val);
793 pci_write_config_byte(pdev, PCI_CLOCK_CTL, val & ~0x0f);
794 pci_write_config_byte(pdev, PCI_CLOCK_CTL, val | 0x01);
795 dev_dbg(&pdev->dev, "Clock Control by PCI config is disabled!\n");
802 static int jmb38x_ms_suspend(struct pci_dev *dev, pm_message_t state)
804 struct jmb38x_ms *jm = pci_get_drvdata(dev);
807 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
810 memstick_suspend_host(jm->hosts[cnt]);
814 pci_enable_wake(dev, pci_choose_state(dev, state), 0);
815 pci_disable_device(dev);
816 pci_set_power_state(dev, pci_choose_state(dev, state));
820 static int jmb38x_ms_resume(struct pci_dev *dev)
822 struct jmb38x_ms *jm = pci_get_drvdata(dev);
825 pci_set_power_state(dev, PCI_D0);
826 pci_restore_state(dev);
827 rc = pci_enable_device(dev);
832 jmb38x_ms_pmos(dev, 1);
834 for (rc = 0; rc < jm->host_cnt; ++rc) {
837 memstick_resume_host(jm->hosts[rc]);
838 memstick_detect_change(jm->hosts[rc]);
846 #define jmb38x_ms_suspend NULL
847 #define jmb38x_ms_resume NULL
849 #endif /* CONFIG_PM */
851 static int jmb38x_ms_count_slots(struct pci_dev *pdev)
855 for (cnt = 0; cnt < PCI_ROM_RESOURCE; ++cnt) {
856 if (!(IORESOURCE_MEM & pci_resource_flags(pdev, cnt)))
859 if (256 != pci_resource_len(pdev, cnt))
867 static struct memstick_host *jmb38x_ms_alloc_host(struct jmb38x_ms *jm, int cnt)
869 struct memstick_host *msh;
870 struct jmb38x_ms_host *host;
872 msh = memstick_alloc_host(sizeof(struct jmb38x_ms_host),
877 host = memstick_priv(msh);
880 host->addr = ioremap(pci_resource_start(jm->pdev, cnt),
881 pci_resource_len(jm->pdev, cnt));
885 spin_lock_init(&host->lock);
887 snprintf(host->host_id, sizeof(host->host_id), DRIVER_NAME ":slot%d",
889 host->irq = jm->pdev->irq;
890 host->timeout_jiffies = msecs_to_jiffies(1000);
892 tasklet_init(&host->notify, jmb38x_ms_req_tasklet, (unsigned long)msh);
893 msh->request = jmb38x_ms_submit_req;
894 msh->set_param = jmb38x_ms_set_param;
896 msh->caps = MEMSTICK_CAP_PAR4 | MEMSTICK_CAP_PAR8;
898 timer_setup(&host->timer, jmb38x_ms_abort, 0);
900 if (!request_irq(host->irq, jmb38x_ms_isr, IRQF_SHARED, host->host_id,
910 static void jmb38x_ms_free_host(struct memstick_host *msh)
912 struct jmb38x_ms_host *host = memstick_priv(msh);
914 free_irq(host->irq, msh);
916 memstick_free_host(msh);
919 static int jmb38x_ms_probe(struct pci_dev *pdev,
920 const struct pci_device_id *dev_id)
922 struct jmb38x_ms *jm;
923 int pci_dev_busy = 0;
926 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
930 rc = pci_enable_device(pdev);
934 pci_set_master(pdev);
936 rc = pci_request_regions(pdev, DRIVER_NAME);
942 jmb38x_ms_pmos(pdev, 1);
944 cnt = jmb38x_ms_count_slots(pdev);
951 jm = kzalloc(sizeof(struct jmb38x_ms)
952 + cnt * sizeof(struct memstick_host *), GFP_KERNEL);
960 pci_set_drvdata(pdev, jm);
962 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
963 jm->hosts[cnt] = jmb38x_ms_alloc_host(jm, cnt);
967 rc = memstick_add_host(jm->hosts[cnt]);
970 jmb38x_ms_free_host(jm->hosts[cnt]);
971 jm->hosts[cnt] = NULL;
981 pci_set_drvdata(pdev, NULL);
984 pci_release_regions(pdev);
987 pci_disable_device(pdev);
991 static void jmb38x_ms_remove(struct pci_dev *dev)
993 struct jmb38x_ms *jm = pci_get_drvdata(dev);
994 struct jmb38x_ms_host *host;
998 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
1002 host = memstick_priv(jm->hosts[cnt]);
1004 jm->hosts[cnt]->request = jmb38x_ms_dummy_submit;
1005 tasklet_kill(&host->notify);
1006 writel(0, host->addr + INT_SIGNAL_ENABLE);
1007 writel(0, host->addr + INT_STATUS_ENABLE);
1008 dev_dbg(&jm->pdev->dev, "interrupts off\n");
1009 spin_lock_irqsave(&host->lock, flags);
1011 host->req->error = -ETIME;
1012 jmb38x_ms_complete_cmd(jm->hosts[cnt], 1);
1014 spin_unlock_irqrestore(&host->lock, flags);
1016 memstick_remove_host(jm->hosts[cnt]);
1017 dev_dbg(&jm->pdev->dev, "host removed\n");
1019 jmb38x_ms_free_host(jm->hosts[cnt]);
1022 jmb38x_ms_pmos(dev, 0);
1024 pci_set_drvdata(dev, NULL);
1025 pci_release_regions(dev);
1026 pci_disable_device(dev);
1030 static struct pci_device_id jmb38x_ms_id_tbl [] = {
1031 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_MS) },
1032 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB385_MS) },
1033 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB390_MS) },
1037 static struct pci_driver jmb38x_ms_driver = {
1038 .name = DRIVER_NAME,
1039 .id_table = jmb38x_ms_id_tbl,
1040 .probe = jmb38x_ms_probe,
1041 .remove = jmb38x_ms_remove,
1042 .suspend = jmb38x_ms_suspend,
1043 .resume = jmb38x_ms_resume
1046 module_pci_driver(jmb38x_ms_driver);
1048 MODULE_AUTHOR("Alex Dubov");
1049 MODULE_DESCRIPTION("JMicron jmb38x MemoryStick driver");
1050 MODULE_LICENSE("GPL");
1051 MODULE_DEVICE_TABLE(pci, jmb38x_ms_id_tbl);