1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
9 #include <dt-bindings/memory/tegra30-mc.h>
13 static const unsigned long tegra30_mc_emem_regs[] = {
15 MC_EMEM_ARB_OUTSTANDING_REQ,
16 MC_EMEM_ARB_TIMING_RCD,
17 MC_EMEM_ARB_TIMING_RP,
18 MC_EMEM_ARB_TIMING_RC,
19 MC_EMEM_ARB_TIMING_RAS,
20 MC_EMEM_ARB_TIMING_FAW,
21 MC_EMEM_ARB_TIMING_RRD,
22 MC_EMEM_ARB_TIMING_RAP2PRE,
23 MC_EMEM_ARB_TIMING_WAP2PRE,
24 MC_EMEM_ARB_TIMING_R2R,
25 MC_EMEM_ARB_TIMING_W2W,
26 MC_EMEM_ARB_TIMING_R2W,
27 MC_EMEM_ARB_TIMING_W2R,
29 MC_EMEM_ARB_DA_COVERS,
31 MC_EMEM_ARB_RING1_THROTTLE,
34 static const struct tegra_mc_client tegra30_mc_clients[] = {
38 .swgroup = TEGRA_SWGROUP_PTC,
42 .swgroup = TEGRA_SWGROUP_DC,
56 .swgroup = TEGRA_SWGROUP_DCB,
70 .swgroup = TEGRA_SWGROUP_DC,
84 .swgroup = TEGRA_SWGROUP_DCB,
98 .swgroup = TEGRA_SWGROUP_DC,
111 .name = "display0cb",
112 .swgroup = TEGRA_SWGROUP_DCB,
126 .swgroup = TEGRA_SWGROUP_DC,
139 .name = "display1bb",
140 .swgroup = TEGRA_SWGROUP_DCB,
154 .swgroup = TEGRA_SWGROUP_EPP,
168 .swgroup = TEGRA_SWGROUP_G2,
182 .swgroup = TEGRA_SWGROUP_G2,
196 .swgroup = TEGRA_SWGROUP_MPE,
210 .swgroup = TEGRA_SWGROUP_VI,
224 .swgroup = TEGRA_SWGROUP_AFI,
238 .swgroup = TEGRA_SWGROUP_AVPC,
252 .swgroup = TEGRA_SWGROUP_DC,
265 .name = "displayhcb",
266 .swgroup = TEGRA_SWGROUP_DCB,
280 .swgroup = TEGRA_SWGROUP_NV,
294 .swgroup = TEGRA_SWGROUP_NV2,
308 .swgroup = TEGRA_SWGROUP_G2,
322 .swgroup = TEGRA_SWGROUP_HDA,
335 .name = "host1xdmar",
336 .swgroup = TEGRA_SWGROUP_HC,
350 .swgroup = TEGRA_SWGROUP_HC,
364 .swgroup = TEGRA_SWGROUP_NV,
378 .swgroup = TEGRA_SWGROUP_NV2,
392 .swgroup = TEGRA_SWGROUP_MPE,
406 .swgroup = TEGRA_SWGROUP_MPE,
420 .swgroup = TEGRA_SWGROUP_MPE,
433 .name = "ppcsahbdmar",
434 .swgroup = TEGRA_SWGROUP_PPCS,
447 .name = "ppcsahbslvr",
448 .swgroup = TEGRA_SWGROUP_PPCS,
462 .swgroup = TEGRA_SWGROUP_SATA,
476 .swgroup = TEGRA_SWGROUP_NV,
490 .swgroup = TEGRA_SWGROUP_NV2,
504 .swgroup = TEGRA_SWGROUP_VDE,
518 .swgroup = TEGRA_SWGROUP_VDE,
532 .swgroup = TEGRA_SWGROUP_VDE,
546 .swgroup = TEGRA_SWGROUP_VDE,
560 .swgroup = TEGRA_SWGROUP_MPCORELP,
570 .swgroup = TEGRA_SWGROUP_MPCORE,
580 .swgroup = TEGRA_SWGROUP_EPP,
594 .swgroup = TEGRA_SWGROUP_EPP,
608 .swgroup = TEGRA_SWGROUP_EPP,
622 .swgroup = TEGRA_SWGROUP_MPE,
636 .swgroup = TEGRA_SWGROUP_VI,
650 .swgroup = TEGRA_SWGROUP_VI,
664 .swgroup = TEGRA_SWGROUP_VI,
678 .swgroup = TEGRA_SWGROUP_VI,
692 .swgroup = TEGRA_SWGROUP_G2,
706 .swgroup = TEGRA_SWGROUP_AFI,
720 .swgroup = TEGRA_SWGROUP_AVPC,
734 .swgroup = TEGRA_SWGROUP_NV,
748 .swgroup = TEGRA_SWGROUP_NV2,
762 .swgroup = TEGRA_SWGROUP_HDA,
776 .swgroup = TEGRA_SWGROUP_HC,
790 .swgroup = TEGRA_SWGROUP_ISP,
804 .swgroup = TEGRA_SWGROUP_MPCORELP,
814 .swgroup = TEGRA_SWGROUP_MPCORE,
824 .swgroup = TEGRA_SWGROUP_MPE,
837 .name = "ppcsahbdmaw",
838 .swgroup = TEGRA_SWGROUP_PPCS,
851 .name = "ppcsahbslvw",
852 .swgroup = TEGRA_SWGROUP_PPCS,
866 .swgroup = TEGRA_SWGROUP_SATA,
880 .swgroup = TEGRA_SWGROUP_VDE,
894 .swgroup = TEGRA_SWGROUP_VDE,
908 .swgroup = TEGRA_SWGROUP_VDE,
922 .swgroup = TEGRA_SWGROUP_VDE,
936 static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
937 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
938 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
939 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
940 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
941 { .name = "mpe", .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
942 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
943 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
944 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
945 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
946 { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
947 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
948 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
949 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
950 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
951 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
952 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
955 static const unsigned int tegra30_group_drm[] = {
963 static const struct tegra_smmu_group_soc tegra30_groups[] = {
966 .swgroups = tegra30_group_drm,
967 .num_swgroups = ARRAY_SIZE(tegra30_group_drm),
971 static const struct tegra_smmu_soc tegra30_smmu_soc = {
972 .clients = tegra30_mc_clients,
973 .num_clients = ARRAY_SIZE(tegra30_mc_clients),
974 .swgroups = tegra30_swgroups,
975 .num_swgroups = ARRAY_SIZE(tegra30_swgroups),
976 .groups = tegra30_groups,
977 .num_groups = ARRAY_SIZE(tegra30_groups),
978 .supports_round_robin_arbitration = false,
979 .supports_request_limit = false,
984 #define TEGRA30_MC_RESET(_name, _control, _status, _bit) \
987 .id = TEGRA30_MC_RESET_##_name, \
988 .control = _control, \
993 static const struct tegra_mc_reset tegra30_mc_resets[] = {
994 TEGRA30_MC_RESET(AFI, 0x200, 0x204, 0),
995 TEGRA30_MC_RESET(AVPC, 0x200, 0x204, 1),
996 TEGRA30_MC_RESET(DC, 0x200, 0x204, 2),
997 TEGRA30_MC_RESET(DCB, 0x200, 0x204, 3),
998 TEGRA30_MC_RESET(EPP, 0x200, 0x204, 4),
999 TEGRA30_MC_RESET(2D, 0x200, 0x204, 5),
1000 TEGRA30_MC_RESET(HC, 0x200, 0x204, 6),
1001 TEGRA30_MC_RESET(HDA, 0x200, 0x204, 7),
1002 TEGRA30_MC_RESET(ISP, 0x200, 0x204, 8),
1003 TEGRA30_MC_RESET(MPCORE, 0x200, 0x204, 9),
1004 TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1005 TEGRA30_MC_RESET(MPE, 0x200, 0x204, 11),
1006 TEGRA30_MC_RESET(3D, 0x200, 0x204, 12),
1007 TEGRA30_MC_RESET(3D2, 0x200, 0x204, 13),
1008 TEGRA30_MC_RESET(PPCS, 0x200, 0x204, 14),
1009 TEGRA30_MC_RESET(SATA, 0x200, 0x204, 15),
1010 TEGRA30_MC_RESET(VDE, 0x200, 0x204, 16),
1011 TEGRA30_MC_RESET(VI, 0x200, 0x204, 17),
1014 const struct tegra_mc_soc tegra30_mc_soc = {
1015 .clients = tegra30_mc_clients,
1016 .num_clients = ARRAY_SIZE(tegra30_mc_clients),
1017 .num_address_bits = 32,
1019 .client_id_mask = 0x7f,
1020 .smmu = &tegra30_smmu_soc,
1021 .emem_regs = tegra30_mc_emem_regs,
1022 .num_emem_regs = ARRAY_SIZE(tegra30_mc_emem_regs),
1023 .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1025 .reset_ops = &tegra_mc_reset_ops_common,
1026 .resets = tegra30_mc_resets,
1027 .num_resets = ARRAY_SIZE(tegra30_mc_resets),