drivers/memory/tegra/tegra30.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/of.h>
   7 #include <linux/mm.h>
   8
   9 #include <dt-bindings/memory/tegra30-mc.h>
  10
  11 #include "mc.h"
  12
  13 static const unsigned long tegra30_mc_emem_regs[] = {
  14         MC_EMEM_ARB_CFG,
  15         MC_EMEM_ARB_OUTSTANDING_REQ,
  16         MC_EMEM_ARB_TIMING_RCD,
  17         MC_EMEM_ARB_TIMING_RP,
  18         MC_EMEM_ARB_TIMING_RC,
  19         MC_EMEM_ARB_TIMING_RAS,
  20         MC_EMEM_ARB_TIMING_FAW,
  21         MC_EMEM_ARB_TIMING_RRD,
  22         MC_EMEM_ARB_TIMING_RAP2PRE,
  23         MC_EMEM_ARB_TIMING_WAP2PRE,
  24         MC_EMEM_ARB_TIMING_R2R,
  25         MC_EMEM_ARB_TIMING_W2W,
  26         MC_EMEM_ARB_TIMING_R2W,
  27         MC_EMEM_ARB_TIMING_W2R,
  28         MC_EMEM_ARB_DA_TURNS,
  29         MC_EMEM_ARB_DA_COVERS,
  30         MC_EMEM_ARB_MISC0,
  31         MC_EMEM_ARB_RING1_THROTTLE,
  32 };
  33
  34 static const struct tegra_mc_client tegra30_mc_clients[] = {
  35         {
  36                 .id = 0x00,
  37                 .name = "ptcr",
  38                 .swgroup = TEGRA_SWGROUP_PTC,
  39                 .la = {
  40                         .reg = 0x34c,
  41                         .shift = 0,
  42                         .mask = 0xff,
  43                         .def = 0x0,
  44                 },
  45                 .fifo_size = 16 * 2,
  46         }, {
  47                 .id = 0x01,
  48                 .name = "display0a",
  49                 .swgroup = TEGRA_SWGROUP_DC,
  50                 .smmu = {
  51                         .reg = 0x228,
  52                         .bit = 1,
  53                 },
  54                 .la = {
  55                         .reg = 0x2e8,
  56                         .shift = 0,
  57                         .mask = 0xff,
  58                         .def = 0x4e,
  59                 },
  60                 .fifo_size = 16 * 128,
  61         }, {
  62                 .id = 0x02,
  63                 .name = "display0ab",
  64                 .swgroup = TEGRA_SWGROUP_DCB,
  65                 .smmu = {
  66                         .reg = 0x228,
  67                         .bit = 2,
  68                 },
  69                 .la = {
  70                         .reg = 0x2f4,
  71                         .shift = 0,
  72                         .mask = 0xff,
  73                         .def = 0x4e,
  74                 },
  75                 .fifo_size = 16 * 128,
  76         }, {
  77                 .id = 0x03,
  78                 .name = "display0b",
  79                 .swgroup = TEGRA_SWGROUP_DC,
  80                 .smmu = {
  81                         .reg = 0x228,
  82                         .bit = 3,
  83                 },
  84                 .la = {
  85                         .reg = 0x2e8,
  86                         .shift = 16,
  87                         .mask = 0xff,
  88                         .def = 0x4e,
  89                 },
  90                 .fifo_size = 16 * 64,
  91         }, {
  92                 .id = 0x04,
  93                 .name = "display0bb",
  94                 .swgroup = TEGRA_SWGROUP_DCB,
  95                 .smmu = {
  96                         .reg = 0x228,
  97                         .bit = 4,
  98                 },
  99                 .la = {
 100                         .reg = 0x2f4,
 101                         .shift = 16,
 102                         .mask = 0xff,
 103                         .def = 0x4e,
 104                 },
 105                 .fifo_size = 16 * 64,
 106         }, {
 107                 .id = 0x05,
 108                 .name = "display0c",
 109                 .swgroup = TEGRA_SWGROUP_DC,
 110                 .smmu = {
 111                         .reg = 0x228,
 112                         .bit = 5,
 113                 },
 114                 .la = {
 115                         .reg = 0x2ec,
 116                         .shift = 0,
 117                         .mask = 0xff,
 118                         .def = 0x4e,
 119                 },
 120                 .fifo_size = 16 * 128,
 121         }, {
 122                 .id = 0x06,
 123                 .name = "display0cb",
 124                 .swgroup = TEGRA_SWGROUP_DCB,
 125                 .smmu = {
 126                         .reg = 0x228,
 127                         .bit = 6,
 128                 },
 129                 .la = {
 130                         .reg = 0x2f8,
 131                         .shift = 0,
 132                         .mask = 0xff,
 133                         .def = 0x4e,
 134                 },
 135                 .fifo_size = 16 * 128,
 136         }, {
 137                 .id = 0x07,
 138                 .name = "display1b",
 139                 .swgroup = TEGRA_SWGROUP_DC,
 140                 .smmu = {
 141                         .reg = 0x228,
 142                         .bit = 7,
 143                 },
 144                 .la = {
 145                         .reg = 0x2ec,
 146                         .shift = 16,
 147                         .mask = 0xff,
 148                         .def = 0x4e,
 149                 },
 150                 .fifo_size = 16 * 64,
 151         }, {
 152                 .id = 0x08,
 153                 .name = "display1bb",
 154                 .swgroup = TEGRA_SWGROUP_DCB,
 155                 .smmu = {
 156                         .reg = 0x228,
 157                         .bit = 8,
 158                 },
 159                 .la = {
 160                         .reg = 0x2f8,
 161                         .shift = 16,
 162                         .mask = 0xff,
 163                         .def = 0x4e,
 164                 },
 165                 .fifo_size = 16 * 64,
 166         }, {
 167                 .id = 0x09,
 168                 .name = "eppup",
 169                 .swgroup = TEGRA_SWGROUP_EPP,
 170                 .smmu = {
 171                         .reg = 0x228,
 172                         .bit = 9,
 173                 },
 174                 .la = {
 175                         .reg = 0x300,
 176                         .shift = 0,
 177                         .mask = 0xff,
 178                         .def = 0x17,
 179                 },
 180                 .fifo_size = 16 * 8,
 181         }, {
 182                 .id = 0x0a,
 183                 .name = "g2pr",
 184                 .swgroup = TEGRA_SWGROUP_G2,
 185                 .smmu = {
 186                         .reg = 0x228,
 187                         .bit = 10,
 188                 },
 189                 .la = {
 190                         .reg = 0x308,
 191                         .shift = 0,
 192                         .mask = 0xff,
 193                         .def = 0x09,
 194                 },
 195                 .fifo_size = 16 * 64,
 196         }, {
 197                 .id = 0x0b,
 198                 .name = "g2sr",
 199                 .swgroup = TEGRA_SWGROUP_G2,
 200                 .smmu = {
 201                         .reg = 0x228,
 202                         .bit = 11,
 203                 },
 204                 .la = {
 205                         .reg = 0x308,
 206                         .shift = 16,
 207                         .mask = 0xff,
 208                         .def = 0x09,
 209                 },
 210                 .fifo_size = 16 * 64,
 211         }, {
 212                 .id = 0x0c,
 213                 .name = "mpeunifbr",
 214                 .swgroup = TEGRA_SWGROUP_MPE,
 215                 .smmu = {
 216                         .reg = 0x228,
 217                         .bit = 12,
 218                 },
 219                 .la = {
 220                         .reg = 0x328,
 221                         .shift = 0,
 222                         .mask = 0xff,
 223                         .def = 0x50,
 224                 },
 225                 .fifo_size = 16 * 8,
 226         }, {
 227                 .id = 0x0d,
 228                 .name = "viruv",
 229                 .swgroup = TEGRA_SWGROUP_VI,
 230                 .smmu = {
 231                         .reg = 0x228,
 232                         .bit = 13,
 233                 },
 234                 .la = {
 235                         .reg = 0x364,
 236                         .shift = 0,
 237                         .mask = 0xff,
 238                         .def = 0x2c,
 239                 },
 240                 .fifo_size = 16 * 8,
 241         }, {
 242                 .id = 0x0e,
 243                 .name = "afir",
 244                 .swgroup = TEGRA_SWGROUP_AFI,
 245                 .smmu = {
 246                         .reg = 0x228,
 247                         .bit = 14,
 248                 },
 249                 .la = {
 250                         .reg = 0x2e0,
 251                         .shift = 0,
 252                         .mask = 0xff,
 253                         .def = 0x10,
 254                 },
 255                 .fifo_size = 16 * 32,
 256         }, {
 257                 .id = 0x0f,
 258                 .name = "avpcarm7r",
 259                 .swgroup = TEGRA_SWGROUP_AVPC,
 260                 .smmu = {
 261                         .reg = 0x228,
 262                         .bit = 15,
 263                 },
 264                 .la = {
 265                         .reg = 0x2e4,
 266                         .shift = 0,
 267                         .mask = 0xff,
 268                         .def = 0x04,
 269                 },
 270                 .fifo_size = 16 * 2,
 271         }, {
 272                 .id = 0x10,
 273                 .name = "displayhc",
 274                 .swgroup = TEGRA_SWGROUP_DC,
 275                 .smmu = {
 276                         .reg = 0x228,
 277                         .bit = 16,
 278                 },
 279                 .la = {
 280                         .reg = 0x2f0,
 281                         .shift = 0,
 282                         .mask = 0xff,
 283                         .def = 0xff,
 284                 },
 285                 .fifo_size = 16 * 2,
 286         }, {
 287                 .id = 0x11,
 288                 .name = "displayhcb",
 289                 .swgroup = TEGRA_SWGROUP_DCB,
 290                 .smmu = {
 291                         .reg = 0x228,
 292                         .bit = 17,
 293                 },
 294                 .la = {
 295                         .reg = 0x2fc,
 296                         .shift = 0,
 297                         .mask = 0xff,
 298                         .def = 0xff,
 299                 },
 300                 .fifo_size = 16 * 2,
 301         }, {
 302                 .id = 0x12,
 303                 .name = "fdcdrd",
 304                 .swgroup = TEGRA_SWGROUP_NV,
 305                 .smmu = {
 306                         .reg = 0x228,
 307                         .bit = 18,
 308                 },
 309                 .la = {
 310                         .reg = 0x334,
 311                         .shift = 0,
 312                         .mask = 0xff,
 313                         .def = 0x0a,
 314                 },
 315                 .fifo_size = 16 * 48,
 316         }, {
 317                 .id = 0x13,
 318                 .name = "fdcdrd2",
 319                 .swgroup = TEGRA_SWGROUP_NV2,
 320                 .smmu = {
 321                         .reg = 0x228,
 322                         .bit = 19,
 323                 },
 324                 .la = {
 325                         .reg = 0x33c,
 326                         .shift = 0,
 327                         .mask = 0xff,
 328                         .def = 0x0a,
 329                 },
 330                 .fifo_size = 16 * 48,
 331         }, {
 332                 .id = 0x14,
 333                 .name = "g2dr",
 334                 .swgroup = TEGRA_SWGROUP_G2,
 335                 .smmu = {
 336                         .reg = 0x228,
 337                         .bit = 20,
 338                 },
 339                 .la = {
 340                         .reg = 0x30c,
 341                         .shift = 0,
 342                         .mask = 0xff,
 343                         .def = 0x0a,
 344                 },
 345                 .fifo_size = 16 * 48,
 346         }, {
 347                 .id = 0x15,
 348                 .name = "hdar",
 349                 .swgroup = TEGRA_SWGROUP_HDA,
 350                 .smmu = {
 351                         .reg = 0x228,
 352                         .bit = 21,
 353                 },
 354                 .la = {
 355                         .reg = 0x318,
 356                         .shift = 0,
 357                         .mask = 0xff,
 358                         .def = 0xff,
 359                 },
 360                 .fifo_size = 16 * 16,
 361         }, {
 362                 .id = 0x16,
 363                 .name = "host1xdmar",
 364                 .swgroup = TEGRA_SWGROUP_HC,
 365                 .smmu = {
 366                         .reg = 0x228,
 367                         .bit = 22,
 368                 },
 369                 .la = {
 370                         .reg = 0x310,
 371                         .shift = 0,
 372                         .mask = 0xff,
 373                         .def = 0x05,
 374                 },
 375                 .fifo_size = 16 * 16,
 376         }, {
 377                 .id = 0x17,
 378                 .name = "host1xr",
 379                 .swgroup = TEGRA_SWGROUP_HC,
 380                 .smmu = {
 381                         .reg = 0x228,
 382                         .bit = 23,
 383                 },
 384                 .la = {
 385                         .reg = 0x310,
 386                         .shift = 16,
 387                         .mask = 0xff,
 388                         .def = 0x50,
 389                 },
 390                 .fifo_size = 16 * 8,
 391         }, {
 392                 .id = 0x18,
 393                 .name = "idxsrd",
 394                 .swgroup = TEGRA_SWGROUP_NV,
 395                 .smmu = {
 396                         .reg = 0x228,
 397                         .bit = 24,
 398                 },
 399                 .la = {
 400                         .reg = 0x334,
 401                         .shift = 16,
 402                         .mask = 0xff,
 403                         .def = 0x13,
 404                 },
 405                 .fifo_size = 16 * 64,
 406         }, {
 407                 .id = 0x19,
 408                 .name = "idxsrd2",
 409                 .swgroup = TEGRA_SWGROUP_NV2,
 410                 .smmu = {
 411                         .reg = 0x228,
 412                         .bit = 25,
 413                 },
 414                 .la = {
 415                         .reg = 0x33c,
 416                         .shift = 16,
 417                         .mask = 0xff,
 418                         .def = 0x13,
 419                 },
 420                 .fifo_size = 16 * 64,
 421         }, {
 422                 .id = 0x1a,
 423                 .name = "mpe_ipred",
 424                 .swgroup = TEGRA_SWGROUP_MPE,
 425                 .smmu = {
 426                         .reg = 0x228,
 427                         .bit = 26,
 428                 },
 429                 .la = {
 430                         .reg = 0x328,
 431                         .shift = 16,
 432                         .mask = 0xff,
 433                         .def = 0x80,
 434                 },
 435                 .fifo_size = 16 * 2,
 436         }, {
 437                 .id = 0x1b,
 438                 .name = "mpeamemrd",
 439                 .swgroup = TEGRA_SWGROUP_MPE,
 440                 .smmu = {
 441                         .reg = 0x228,
 442                         .bit = 27,
 443                 },
 444                 .la = {
 445                         .reg = 0x32c,
 446                         .shift = 0,
 447                         .mask = 0xff,
 448                         .def = 0x42,
 449                 },
 450                 .fifo_size = 16 * 64,
 451         }, {
 452                 .id = 0x1c,
 453                 .name = "mpecsrd",
 454                 .swgroup = TEGRA_SWGROUP_MPE,
 455                 .smmu = {
 456                         .reg = 0x228,
 457                         .bit = 28,
 458                 },
 459                 .la = {
 460                         .reg = 0x32c,
 461                         .shift = 16,
 462                         .mask = 0xff,
 463                         .def = 0xff,
 464                 },
 465                 .fifo_size = 16 * 8,
 466         }, {
 467                 .id = 0x1d,
 468                 .name = "ppcsahbdmar",
 469                 .swgroup = TEGRA_SWGROUP_PPCS,
 470                 .smmu = {
 471                         .reg = 0x228,
 472                         .bit = 29,
 473                 },
 474                 .la = {
 475                         .reg = 0x344,
 476                         .shift = 0,
 477                         .mask = 0xff,
 478                         .def = 0x10,
 479                 },
 480                 .fifo_size = 16 * 2,
 481         }, {
 482                 .id = 0x1e,
 483                 .name = "ppcsahbslvr",
 484                 .swgroup = TEGRA_SWGROUP_PPCS,
 485                 .smmu = {
 486                         .reg = 0x228,
 487                         .bit = 30,
 488                 },
 489                 .la = {
 490                         .reg = 0x344,
 491                         .shift = 16,
 492                         .mask = 0xff,
 493                         .def = 0x12,
 494                 },
 495                 .fifo_size = 16 * 8,
 496         }, {
 497                 .id = 0x1f,
 498                 .name = "satar",
 499                 .swgroup = TEGRA_SWGROUP_SATA,
 500                 .smmu = {
 501                         .reg = 0x228,
 502                         .bit = 31,
 503                 },
 504                 .la = {
 505                         .reg = 0x350,
 506                         .shift = 0,
 507                         .mask = 0xff,
 508                         .def = 0x33,
 509                 },
 510                 .fifo_size = 16 * 32,
 511         }, {
 512                 .id = 0x20,
 513                 .name = "texsrd",
 514                 .swgroup = TEGRA_SWGROUP_NV,
 515                 .smmu = {
 516                         .reg = 0x22c,
 517                         .bit = 0,
 518                 },
 519                 .la = {
 520                         .reg = 0x338,
 521                         .shift = 0,
 522                         .mask = 0xff,
 523                         .def = 0x13,
 524                 },
 525                 .fifo_size = 16 * 64,
 526         }, {
 527                 .id = 0x21,
 528                 .name = "texsrd2",
 529                 .swgroup = TEGRA_SWGROUP_NV2,
 530                 .smmu = {
 531                         .reg = 0x22c,
 532                         .bit = 1,
 533                 },
 534                 .la = {
 535                         .reg = 0x340,
 536                         .shift = 0,
 537                         .mask = 0xff,
 538                         .def = 0x13,
 539                 },
 540                 .fifo_size = 16 * 64,
 541         }, {
 542                 .id = 0x22,
 543                 .name = "vdebsevr",
 544                 .swgroup = TEGRA_SWGROUP_VDE,
 545                 .smmu = {
 546                         .reg = 0x22c,
 547                         .bit = 2,
 548                 },
 549                 .la = {
 550                         .reg = 0x354,
 551                         .shift = 0,
 552                         .mask = 0xff,
 553                         .def = 0xff,
 554                 },
 555                 .fifo_size = 16 * 8,
 556         }, {
 557                 .id = 0x23,
 558                 .name = "vdember",
 559                 .swgroup = TEGRA_SWGROUP_VDE,
 560                 .smmu = {
 561                         .reg = 0x22c,
 562                         .bit = 3,
 563                 },
 564                 .la = {
 565                         .reg = 0x354,
 566                         .shift = 16,
 567                         .mask = 0xff,
 568                         .def = 0xd0,
 569                 },
 570                 .fifo_size = 16 * 4,
 571         }, {
 572                 .id = 0x24,
 573                 .name = "vdemcer",
 574                 .swgroup = TEGRA_SWGROUP_VDE,
 575                 .smmu = {
 576                         .reg = 0x22c,
 577                         .bit = 4,
 578                 },
 579                 .la = {
 580                         .reg = 0x358,
 581                         .shift = 0,
 582                         .mask = 0xff,
 583                         .def = 0x2a,
 584                 },
 585                 .fifo_size = 16 * 16,
 586         }, {
 587                 .id = 0x25,
 588                 .name = "vdetper",
 589                 .swgroup = TEGRA_SWGROUP_VDE,
 590                 .smmu = {
 591                         .reg = 0x22c,
 592                         .bit = 5,
 593                 },
 594                 .la = {
 595                         .reg = 0x358,
 596                         .shift = 16,
 597                         .mask = 0xff,
 598                         .def = 0x74,
 599                 },
 600                 .fifo_size = 16 * 16,
 601         }, {
 602                 .id = 0x26,
 603                 .name = "mpcorelpr",
 604                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 605                 .la = {
 606                         .reg = 0x324,
 607                         .shift = 0,
 608                         .mask = 0xff,
 609                         .def = 0x04,
 610                 },
 611                 .fifo_size = 16 * 14,
 612         }, {
 613                 .id = 0x27,
 614                 .name = "mpcorer",
 615                 .swgroup = TEGRA_SWGROUP_MPCORE,
 616                 .la = {
 617                         .reg = 0x320,
 618                         .shift = 0,
 619                         .mask = 0xff,
 620                         .def = 0x04,
 621                 },
 622                 .fifo_size = 16 * 14,
 623         }, {
 624                 .id = 0x28,
 625                 .name = "eppu",
 626                 .swgroup = TEGRA_SWGROUP_EPP,
 627                 .smmu = {
 628                         .reg = 0x22c,
 629                         .bit = 8,
 630                 },
 631                 .la = {
 632                         .reg = 0x300,
 633                         .shift = 16,
 634                         .mask = 0xff,
 635                         .def = 0x6c,
 636                 },
 637                 .fifo_size = 16 * 64,
 638         }, {
 639                 .id = 0x29,
 640                 .name = "eppv",
 641                 .swgroup = TEGRA_SWGROUP_EPP,
 642                 .smmu = {
 643                         .reg = 0x22c,
 644                         .bit = 9,
 645                 },
 646                 .la = {
 647                         .reg = 0x304,
 648                         .shift = 0,
 649                         .mask = 0xff,
 650                         .def = 0x6c,
 651                 },
 652                 .fifo_size = 16 * 64,
 653         }, {
 654                 .id = 0x2a,
 655                 .name = "eppy",
 656                 .swgroup = TEGRA_SWGROUP_EPP,
 657                 .smmu = {
 658                         .reg = 0x22c,
 659                         .bit = 10,
 660                 },
 661                 .la = {
 662                         .reg = 0x304,
 663                         .shift = 16,
 664                         .mask = 0xff,
 665                         .def = 0x6c,
 666                 },
 667                 .fifo_size = 16 * 64,
 668         }, {
 669                 .id = 0x2b,
 670                 .name = "mpeunifbw",
 671                 .swgroup = TEGRA_SWGROUP_MPE,
 672                 .smmu = {
 673                         .reg = 0x22c,
 674                         .bit = 11,
 675                 },
 676                 .la = {
 677                         .reg = 0x330,
 678                         .shift = 0,
 679                         .mask = 0xff,
 680                         .def = 0x13,
 681                 },
 682                 .fifo_size = 16 * 8,
 683         }, {
 684                 .id = 0x2c,
 685                 .name = "viwsb",
 686                 .swgroup = TEGRA_SWGROUP_VI,
 687                 .smmu = {
 688                         .reg = 0x22c,
 689                         .bit = 12,
 690                 },
 691                 .la = {
 692                         .reg = 0x364,
 693                         .shift = 16,
 694                         .mask = 0xff,
 695                         .def = 0x12,
 696                 },
 697                 .fifo_size = 16 * 64,
 698         }, {
 699                 .id = 0x2d,
 700                 .name = "viwu",
 701                 .swgroup = TEGRA_SWGROUP_VI,
 702                 .smmu = {
 703                         .reg = 0x22c,
 704                         .bit = 13,
 705                 },
 706                 .la = {
 707                         .reg = 0x368,
 708                         .shift = 0,
 709                         .mask = 0xff,
 710                         .def = 0xb2,
 711                 },
 712                 .fifo_size = 16 * 64,
 713         }, {
 714                 .id = 0x2e,
 715                 .name = "viwv",
 716                 .swgroup = TEGRA_SWGROUP_VI,
 717                 .smmu = {
 718                         .reg = 0x22c,
 719                         .bit = 14,
 720                 },
 721                 .la = {
 722                         .reg = 0x368,
 723                         .shift = 16,
 724                         .mask = 0xff,
 725                         .def = 0xb2,
 726                 },
 727                 .fifo_size = 16 * 64,
 728         }, {
 729                 .id = 0x2f,
 730                 .name = "viwy",
 731                 .swgroup = TEGRA_SWGROUP_VI,
 732                 .smmu = {
 733                         .reg = 0x22c,
 734                         .bit = 15,
 735                 },
 736                 .la = {
 737                         .reg = 0x36c,
 738                         .shift = 0,
 739                         .mask = 0xff,
 740                         .def = 0x12,
 741                 },
 742                 .fifo_size = 16 * 64,
 743         }, {
 744                 .id = 0x30,
 745                 .name = "g2dw",
 746                 .swgroup = TEGRA_SWGROUP_G2,
 747                 .smmu = {
 748                         .reg = 0x22c,
 749                         .bit = 16,
 750                 },
 751                 .la = {
 752                         .reg = 0x30c,
 753                         .shift = 16,
 754                         .mask = 0xff,
 755                         .def = 0x9,
 756                 },
 757                 .fifo_size = 16 * 128,
 758         }, {
 759                 .id = 0x31,
 760                 .name = "afiw",
 761                 .swgroup = TEGRA_SWGROUP_AFI,
 762                 .smmu = {
 763                         .reg = 0x22c,
 764                         .bit = 17,
 765                 },
 766                 .la = {
 767                         .reg = 0x2e0,
 768                         .shift = 16,
 769                         .mask = 0xff,
 770                         .def = 0x0c,
 771                 },
 772                 .fifo_size = 16 * 32,
 773         }, {
 774                 .id = 0x32,
 775                 .name = "avpcarm7w",
 776                 .swgroup = TEGRA_SWGROUP_AVPC,
 777                 .smmu = {
 778                         .reg = 0x22c,
 779                         .bit = 18,
 780                 },
 781                 .la = {
 782                         .reg = 0x2e4,
 783                         .shift = 16,
 784                         .mask = 0xff,
 785                         .def = 0x0e,
 786                 },
 787                 .fifo_size = 16 * 2,
 788         }, {
 789                 .id = 0x33,
 790                 .name = "fdcdwr",
 791                 .swgroup = TEGRA_SWGROUP_NV,
 792                 .smmu = {
 793                         .reg = 0x22c,
 794                         .bit = 19,
 795                 },
 796                 .la = {
 797                         .reg = 0x338,
 798                         .shift = 16,
 799                         .mask = 0xff,
 800                         .def = 0x0a,
 801                 },
 802                 .fifo_size = 16 * 48,
 803         }, {
 804                 .id = 0x34,
 805                 .name = "fdcdwr2",
 806                 .swgroup = TEGRA_SWGROUP_NV2,
 807                 .smmu = {
 808                         .reg = 0x22c,
 809                         .bit = 20,
 810                 },
 811                 .la = {
 812                         .reg = 0x340,
 813                         .shift = 16,
 814                         .mask = 0xff,
 815                         .def = 0x0a,
 816                 },
 817                 .fifo_size = 16 * 48,
 818         }, {
 819                 .id = 0x35,
 820                 .name = "hdaw",
 821                 .swgroup = TEGRA_SWGROUP_HDA,
 822                 .smmu = {
 823                         .reg = 0x22c,
 824                         .bit = 21,
 825                 },
 826                 .la = {
 827                         .reg = 0x318,
 828                         .shift = 16,
 829                         .mask = 0xff,
 830                         .def = 0xff,
 831                 },
 832                 .fifo_size = 16 * 16,
 833         }, {
 834                 .id = 0x36,
 835                 .name = "host1xw",
 836                 .swgroup = TEGRA_SWGROUP_HC,
 837                 .smmu = {
 838                         .reg = 0x22c,
 839                         .bit = 22,
 840                 },
 841                 .la = {
 842                         .reg = 0x314,
 843                         .shift = 0,
 844                         .mask = 0xff,
 845                         .def = 0x10,
 846                 },
 847                 .fifo_size = 16 * 32,
 848         }, {
 849                 .id = 0x37,
 850                 .name = "ispw",
 851                 .swgroup = TEGRA_SWGROUP_ISP,
 852                 .smmu = {
 853                         .reg = 0x22c,
 854                         .bit = 23,
 855                 },
 856                 .la = {
 857                         .reg = 0x31c,
 858                         .shift = 0,
 859                         .mask = 0xff,
 860                         .def = 0xff,
 861                 },
 862                 .fifo_size = 16 * 64,
 863         }, {
 864                 .id = 0x38,
 865                 .name = "mpcorelpw",
 866                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 867                 .la = {
 868                         .reg = 0x324,
 869                         .shift = 16,
 870                         .mask = 0xff,
 871                         .def = 0x0e,
 872                 },
 873                 .fifo_size = 16 * 24,
 874         }, {
 875                 .id = 0x39,
 876                 .name = "mpcorew",
 877                 .swgroup = TEGRA_SWGROUP_MPCORE,
 878                 .la = {
 879                         .reg = 0x320,
 880                         .shift = 16,
 881                         .mask = 0xff,
 882                         .def = 0x0e,
 883                 },
 884                 .fifo_size = 16 * 24,
 885         }, {
 886                 .id = 0x3a,
 887                 .name = "mpecswr",
 888                 .swgroup = TEGRA_SWGROUP_MPE,
 889                 .smmu = {
 890                         .reg = 0x22c,
 891                         .bit = 26,
 892                 },
 893                 .la = {
 894                         .reg = 0x330,
 895                         .shift = 16,
 896                         .mask = 0xff,
 897                         .def = 0xff,
 898                 },
 899                 .fifo_size = 16 * 8,
 900         }, {
 901                 .id = 0x3b,
 902                 .name = "ppcsahbdmaw",
 903                 .swgroup = TEGRA_SWGROUP_PPCS,
 904                 .smmu = {
 905                         .reg = 0x22c,
 906                         .bit = 27,
 907                 },
 908                 .la = {
 909                         .reg = 0x348,
 910                         .shift = 0,
 911                         .mask = 0xff,
 912                         .def = 0x10,
 913                 },
 914                 .fifo_size = 16 * 2,
 915         }, {
 916                 .id = 0x3c,
 917                 .name = "ppcsahbslvw",
 918                 .swgroup = TEGRA_SWGROUP_PPCS,
 919                 .smmu = {
 920                         .reg = 0x22c,
 921                         .bit = 28,
 922                 },
 923                 .la = {
 924                         .reg = 0x348,
 925                         .shift = 16,
 926                         .mask = 0xff,
 927                         .def = 0x06,
 928                 },
 929                 .fifo_size = 16 * 4,
 930         }, {
 931                 .id = 0x3d,
 932                 .name = "sataw",
 933                 .swgroup = TEGRA_SWGROUP_SATA,
 934                 .smmu = {
 935                         .reg = 0x22c,
 936                         .bit = 29,
 937                 },
 938                 .la = {
 939                         .reg = 0x350,
 940                         .shift = 16,
 941                         .mask = 0xff,
 942                         .def = 0x33,
 943                 },
 944                 .fifo_size = 16 * 32,
 945         }, {
 946                 .id = 0x3e,
 947                 .name = "vdebsevw",
 948                 .swgroup = TEGRA_SWGROUP_VDE,
 949                 .smmu = {
 950                         .reg = 0x22c,
 951                         .bit = 30,
 952                 },
 953                 .la = {
 954                         .reg = 0x35c,
 955                         .shift = 0,
 956                         .mask = 0xff,
 957                         .def = 0xff,
 958                 },
 959                 .fifo_size = 16 * 4,
 960         }, {
 961                 .id = 0x3f,
 962                 .name = "vdedbgw",
 963                 .swgroup = TEGRA_SWGROUP_VDE,
 964                 .smmu = {
 965                         .reg = 0x22c,
 966                         .bit = 31,
 967                 },
 968                 .la = {
 969                         .reg = 0x35c,
 970                         .shift = 16,
 971                         .mask = 0xff,
 972                         .def = 0xff,
 973                 },
 974                 .fifo_size = 16 * 16,
 975         }, {
 976                 .id = 0x40,
 977                 .name = "vdembew",
 978                 .swgroup = TEGRA_SWGROUP_VDE,
 979                 .smmu = {
 980                         .reg = 0x230,
 981                         .bit = 0,
 982                 },
 983                 .la = {
 984                         .reg = 0x360,
 985                         .shift = 0,
 986                         .mask = 0xff,
 987                         .def = 0x42,
 988                 },
 989                 .fifo_size = 16 * 2,
 990         }, {
 991                 .id = 0x41,
 992                 .name = "vdetpmw",
 993                 .swgroup = TEGRA_SWGROUP_VDE,
 994                 .smmu = {
 995                         .reg = 0x230,
 996                         .bit = 1,
 997                 },
 998                 .la = {
 999                         .reg = 0x360,
1000                         .shift = 16,
1001                         .mask = 0xff,
1002                         .def = 0x2a,
1003                 },
1004                 .fifo_size = 16 * 16,
1005         },
1006 };
1007
1008 static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
1009         { .name = "dc",   .swgroup = TEGRA_SWGROUP_DC,   .reg = 0x240 },
1010         { .name = "dcb",  .swgroup = TEGRA_SWGROUP_DCB,  .reg = 0x244 },
1011         { .name = "epp",  .swgroup = TEGRA_SWGROUP_EPP,  .reg = 0x248 },
1012         { .name = "g2",   .swgroup = TEGRA_SWGROUP_G2,   .reg = 0x24c },
1013         { .name = "mpe",  .swgroup = TEGRA_SWGROUP_MPE,  .reg = 0x264 },
1014         { .name = "vi",   .swgroup = TEGRA_SWGROUP_VI,   .reg = 0x280 },
1015         { .name = "afi",  .swgroup = TEGRA_SWGROUP_AFI,  .reg = 0x238 },
1016         { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1017         { .name = "nv",   .swgroup = TEGRA_SWGROUP_NV,   .reg = 0x268 },
1018         { .name = "nv2",  .swgroup = TEGRA_SWGROUP_NV2,  .reg = 0x26c },
1019         { .name = "hda",  .swgroup = TEGRA_SWGROUP_HDA,  .reg = 0x254 },
1020         { .name = "hc",   .swgroup = TEGRA_SWGROUP_HC,   .reg = 0x250 },
1021         { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1022         { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
1023         { .name = "vde",  .swgroup = TEGRA_SWGROUP_VDE,  .reg = 0x27c },
1024         { .name = "isp",  .swgroup = TEGRA_SWGROUP_ISP,  .reg = 0x258 },
1025 };
1026
1027 static const unsigned int tegra30_group_drm[] = {
1028         TEGRA_SWGROUP_DC,
1029         TEGRA_SWGROUP_DCB,
1030         TEGRA_SWGROUP_G2,
1031         TEGRA_SWGROUP_NV,
1032         TEGRA_SWGROUP_NV2,
1033 };
1034
1035 static const struct tegra_smmu_group_soc tegra30_groups[] = {
1036         {
1037                 .name = "drm",
1038                 .swgroups = tegra30_group_drm,
1039                 .num_swgroups = ARRAY_SIZE(tegra30_group_drm),
1040         },
1041 };
1042
1043 static const struct tegra_smmu_soc tegra30_smmu_soc = {
1044         .clients = tegra30_mc_clients,
1045         .num_clients = ARRAY_SIZE(tegra30_mc_clients),
1046         .swgroups = tegra30_swgroups,
1047         .num_swgroups = ARRAY_SIZE(tegra30_swgroups),
1048         .groups = tegra30_groups,
1049         .num_groups = ARRAY_SIZE(tegra30_groups),
1050         .supports_round_robin_arbitration = false,
1051         .supports_request_limit = false,
1052         .num_tlb_lines = 16,
1053         .num_asids = 4,
1054 };
1055
1056 #define TEGRA30_MC_RESET(_name, _control, _status, _bit)        \
1057         {                                                       \
1058                 .name = #_name,                                 \
1059                 .id = TEGRA30_MC_RESET_##_name,                 \
1060                 .control = _control,                            \
1061                 .status = _status,                              \
1062                 .bit = _bit,                                    \
1063         }
1064
1065 static const struct tegra_mc_reset tegra30_mc_resets[] = {
1066         TEGRA30_MC_RESET(AFI,      0x200, 0x204,  0),
1067         TEGRA30_MC_RESET(AVPC,     0x200, 0x204,  1),
1068         TEGRA30_MC_RESET(DC,       0x200, 0x204,  2),
1069         TEGRA30_MC_RESET(DCB,      0x200, 0x204,  3),
1070         TEGRA30_MC_RESET(EPP,      0x200, 0x204,  4),
1071         TEGRA30_MC_RESET(2D,       0x200, 0x204,  5),
1072         TEGRA30_MC_RESET(HC,       0x200, 0x204,  6),
1073         TEGRA30_MC_RESET(HDA,      0x200, 0x204,  7),
1074         TEGRA30_MC_RESET(ISP,      0x200, 0x204,  8),
1075         TEGRA30_MC_RESET(MPCORE,   0x200, 0x204,  9),
1076         TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1077         TEGRA30_MC_RESET(MPE,      0x200, 0x204, 11),
1078         TEGRA30_MC_RESET(3D,       0x200, 0x204, 12),
1079         TEGRA30_MC_RESET(3D2,      0x200, 0x204, 13),
1080         TEGRA30_MC_RESET(PPCS,     0x200, 0x204, 14),
1081         TEGRA30_MC_RESET(SATA,     0x200, 0x204, 15),
1082         TEGRA30_MC_RESET(VDE,      0x200, 0x204, 16),
1083         TEGRA30_MC_RESET(VI,       0x200, 0x204, 17),
1084 };
1085
1086 const struct tegra_mc_soc tegra30_mc_soc = {
1087         .clients = tegra30_mc_clients,
1088         .num_clients = ARRAY_SIZE(tegra30_mc_clients),
1089         .num_address_bits = 32,
1090         .atom_size = 16,
1091         .client_id_mask = 0x7f,
1092         .smmu = &tegra30_smmu_soc,
1093         .emem_regs = tegra30_mc_emem_regs,
1094         .num_emem_regs = ARRAY_SIZE(tegra30_mc_emem_regs),
1095         .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1096                    MC_INT_DECERR_EMEM,
1097         .reset_ops = &tegra_mc_reset_ops_common,
1098         .resets = tegra30_mc_resets,
1099         .num_resets = ARRAY_SIZE(tegra30_mc_resets),
1100 };