drivers/memory/tegra/tegra30.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/of.h>
   7 #include <linux/mm.h>
   8
   9 #include <dt-bindings/memory/tegra30-mc.h>
  10
  11 #include "mc.h"
  12
  13 static const unsigned long tegra30_mc_emem_regs[] = {
  14         MC_EMEM_ARB_CFG,
  15         MC_EMEM_ARB_OUTSTANDING_REQ,
  16         MC_EMEM_ARB_TIMING_RCD,
  17         MC_EMEM_ARB_TIMING_RP,
  18         MC_EMEM_ARB_TIMING_RC,
  19         MC_EMEM_ARB_TIMING_RAS,
  20         MC_EMEM_ARB_TIMING_FAW,
  21         MC_EMEM_ARB_TIMING_RRD,
  22         MC_EMEM_ARB_TIMING_RAP2PRE,
  23         MC_EMEM_ARB_TIMING_WAP2PRE,
  24         MC_EMEM_ARB_TIMING_R2R,
  25         MC_EMEM_ARB_TIMING_W2W,
  26         MC_EMEM_ARB_TIMING_R2W,
  27         MC_EMEM_ARB_TIMING_W2R,
  28         MC_EMEM_ARB_DA_TURNS,
  29         MC_EMEM_ARB_DA_COVERS,
  30         MC_EMEM_ARB_MISC0,
  31         MC_EMEM_ARB_RING1_THROTTLE,
  32 };
  33
  34 static const struct tegra_mc_client tegra30_mc_clients[] = {
  35         {
  36                 .id = 0x00,
  37                 .name = "ptcr",
  38                 .swgroup = TEGRA_SWGROUP_PTC,
  39                 .la = {
  40                         .reg = 0x34c,
  41                         .shift = 0,
  42                         .mask = 0xff,
  43                         .def = 0x0,
  44                 },
  45         }, {
  46                 .id = 0x01,
  47                 .name = "display0a",
  48                 .swgroup = TEGRA_SWGROUP_DC,
  49                 .smmu = {
  50                         .reg = 0x228,
  51                         .bit = 1,
  52                 },
  53                 .la = {
  54                         .reg = 0x2e8,
  55                         .shift = 0,
  56                         .mask = 0xff,
  57                         .def = 0x4e,
  58                 },
  59         }, {
  60                 .id = 0x02,
  61                 .name = "display0ab",
  62                 .swgroup = TEGRA_SWGROUP_DCB,
  63                 .smmu = {
  64                         .reg = 0x228,
  65                         .bit = 2,
  66                 },
  67                 .la = {
  68                         .reg = 0x2f4,
  69                         .shift = 0,
  70                         .mask = 0xff,
  71                         .def = 0x4e,
  72                 },
  73         }, {
  74                 .id = 0x03,
  75                 .name = "display0b",
  76                 .swgroup = TEGRA_SWGROUP_DC,
  77                 .smmu = {
  78                         .reg = 0x228,
  79                         .bit = 3,
  80                 },
  81                 .la = {
  82                         .reg = 0x2e8,
  83                         .shift = 16,
  84                         .mask = 0xff,
  85                         .def = 0x4e,
  86                 },
  87         }, {
  88                 .id = 0x04,
  89                 .name = "display0bb",
  90                 .swgroup = TEGRA_SWGROUP_DCB,
  91                 .smmu = {
  92                         .reg = 0x228,
  93                         .bit = 4,
  94                 },
  95                 .la = {
  96                         .reg = 0x2f4,
  97                         .shift = 16,
  98                         .mask = 0xff,
  99                         .def = 0x4e,
 100                 },
 101         }, {
 102                 .id = 0x05,
 103                 .name = "display0c",
 104                 .swgroup = TEGRA_SWGROUP_DC,
 105                 .smmu = {
 106                         .reg = 0x228,
 107                         .bit = 5,
 108                 },
 109                 .la = {
 110                         .reg = 0x2ec,
 111                         .shift = 0,
 112                         .mask = 0xff,
 113                         .def = 0x4e,
 114                 },
 115         }, {
 116                 .id = 0x06,
 117                 .name = "display0cb",
 118                 .swgroup = TEGRA_SWGROUP_DCB,
 119                 .smmu = {
 120                         .reg = 0x228,
 121                         .bit = 6,
 122                 },
 123                 .la = {
 124                         .reg = 0x2f8,
 125                         .shift = 0,
 126                         .mask = 0xff,
 127                         .def = 0x4e,
 128                 },
 129         }, {
 130                 .id = 0x07,
 131                 .name = "display1b",
 132                 .swgroup = TEGRA_SWGROUP_DC,
 133                 .smmu = {
 134                         .reg = 0x228,
 135                         .bit = 7,
 136                 },
 137                 .la = {
 138                         .reg = 0x2ec,
 139                         .shift = 16,
 140                         .mask = 0xff,
 141                         .def = 0x4e,
 142                 },
 143         }, {
 144                 .id = 0x08,
 145                 .name = "display1bb",
 146                 .swgroup = TEGRA_SWGROUP_DCB,
 147                 .smmu = {
 148                         .reg = 0x228,
 149                         .bit = 8,
 150                 },
 151                 .la = {
 152                         .reg = 0x2f8,
 153                         .shift = 16,
 154                         .mask = 0xff,
 155                         .def = 0x4e,
 156                 },
 157         }, {
 158                 .id = 0x09,
 159                 .name = "eppup",
 160                 .swgroup = TEGRA_SWGROUP_EPP,
 161                 .smmu = {
 162                         .reg = 0x228,
 163                         .bit = 9,
 164                 },
 165                 .la = {
 166                         .reg = 0x300,
 167                         .shift = 0,
 168                         .mask = 0xff,
 169                         .def = 0x17,
 170                 },
 171         }, {
 172                 .id = 0x0a,
 173                 .name = "g2pr",
 174                 .swgroup = TEGRA_SWGROUP_G2,
 175                 .smmu = {
 176                         .reg = 0x228,
 177                         .bit = 10,
 178                 },
 179                 .la = {
 180                         .reg = 0x308,
 181                         .shift = 0,
 182                         .mask = 0xff,
 183                         .def = 0x09,
 184                 },
 185         }, {
 186                 .id = 0x0b,
 187                 .name = "g2sr",
 188                 .swgroup = TEGRA_SWGROUP_G2,
 189                 .smmu = {
 190                         .reg = 0x228,
 191                         .bit = 11,
 192                 },
 193                 .la = {
 194                         .reg = 0x308,
 195                         .shift = 16,
 196                         .mask = 0xff,
 197                         .def = 0x09,
 198                 },
 199         }, {
 200                 .id = 0x0c,
 201                 .name = "mpeunifbr",
 202                 .swgroup = TEGRA_SWGROUP_MPE,
 203                 .smmu = {
 204                         .reg = 0x228,
 205                         .bit = 12,
 206                 },
 207                 .la = {
 208                         .reg = 0x328,
 209                         .shift = 0,
 210                         .mask = 0xff,
 211                         .def = 0x50,
 212                 },
 213         }, {
 214                 .id = 0x0d,
 215                 .name = "viruv",
 216                 .swgroup = TEGRA_SWGROUP_VI,
 217                 .smmu = {
 218                         .reg = 0x228,
 219                         .bit = 13,
 220                 },
 221                 .la = {
 222                         .reg = 0x364,
 223                         .shift = 0,
 224                         .mask = 0xff,
 225                         .def = 0x2c,
 226                 },
 227         }, {
 228                 .id = 0x0e,
 229                 .name = "afir",
 230                 .swgroup = TEGRA_SWGROUP_AFI,
 231                 .smmu = {
 232                         .reg = 0x228,
 233                         .bit = 14,
 234                 },
 235                 .la = {
 236                         .reg = 0x2e0,
 237                         .shift = 0,
 238                         .mask = 0xff,
 239                         .def = 0x10,
 240                 },
 241         }, {
 242                 .id = 0x0f,
 243                 .name = "avpcarm7r",
 244                 .swgroup = TEGRA_SWGROUP_AVPC,
 245                 .smmu = {
 246                         .reg = 0x228,
 247                         .bit = 15,
 248                 },
 249                 .la = {
 250                         .reg = 0x2e4,
 251                         .shift = 0,
 252                         .mask = 0xff,
 253                         .def = 0x04,
 254                 },
 255         }, {
 256                 .id = 0x10,
 257                 .name = "displayhc",
 258                 .swgroup = TEGRA_SWGROUP_DC,
 259                 .smmu = {
 260                         .reg = 0x228,
 261                         .bit = 16,
 262                 },
 263                 .la = {
 264                         .reg = 0x2f0,
 265                         .shift = 0,
 266                         .mask = 0xff,
 267                         .def = 0xff,
 268                 },
 269         }, {
 270                 .id = 0x11,
 271                 .name = "displayhcb",
 272                 .swgroup = TEGRA_SWGROUP_DCB,
 273                 .smmu = {
 274                         .reg = 0x228,
 275                         .bit = 17,
 276                 },
 277                 .la = {
 278                         .reg = 0x2fc,
 279                         .shift = 0,
 280                         .mask = 0xff,
 281                         .def = 0xff,
 282                 },
 283         }, {
 284                 .id = 0x12,
 285                 .name = "fdcdrd",
 286                 .swgroup = TEGRA_SWGROUP_NV,
 287                 .smmu = {
 288                         .reg = 0x228,
 289                         .bit = 18,
 290                 },
 291                 .la = {
 292                         .reg = 0x334,
 293                         .shift = 0,
 294                         .mask = 0xff,
 295                         .def = 0x0a,
 296                 },
 297         }, {
 298                 .id = 0x13,
 299                 .name = "fdcdrd2",
 300                 .swgroup = TEGRA_SWGROUP_NV2,
 301                 .smmu = {
 302                         .reg = 0x228,
 303                         .bit = 19,
 304                 },
 305                 .la = {
 306                         .reg = 0x33c,
 307                         .shift = 0,
 308                         .mask = 0xff,
 309                         .def = 0x0a,
 310                 },
 311         }, {
 312                 .id = 0x14,
 313                 .name = "g2dr",
 314                 .swgroup = TEGRA_SWGROUP_G2,
 315                 .smmu = {
 316                         .reg = 0x228,
 317                         .bit = 20,
 318                 },
 319                 .la = {
 320                         .reg = 0x30c,
 321                         .shift = 0,
 322                         .mask = 0xff,
 323                         .def = 0x0a,
 324                 },
 325         }, {
 326                 .id = 0x15,
 327                 .name = "hdar",
 328                 .swgroup = TEGRA_SWGROUP_HDA,
 329                 .smmu = {
 330                         .reg = 0x228,
 331                         .bit = 21,
 332                 },
 333                 .la = {
 334                         .reg = 0x318,
 335                         .shift = 0,
 336                         .mask = 0xff,
 337                         .def = 0xff,
 338                 },
 339         }, {
 340                 .id = 0x16,
 341                 .name = "host1xdmar",
 342                 .swgroup = TEGRA_SWGROUP_HC,
 343                 .smmu = {
 344                         .reg = 0x228,
 345                         .bit = 22,
 346                 },
 347                 .la = {
 348                         .reg = 0x310,
 349                         .shift = 0,
 350                         .mask = 0xff,
 351                         .def = 0x05,
 352                 },
 353         }, {
 354                 .id = 0x17,
 355                 .name = "host1xr",
 356                 .swgroup = TEGRA_SWGROUP_HC,
 357                 .smmu = {
 358                         .reg = 0x228,
 359                         .bit = 23,
 360                 },
 361                 .la = {
 362                         .reg = 0x310,
 363                         .shift = 16,
 364                         .mask = 0xff,
 365                         .def = 0x50,
 366                 },
 367         }, {
 368                 .id = 0x18,
 369                 .name = "idxsrd",
 370                 .swgroup = TEGRA_SWGROUP_NV,
 371                 .smmu = {
 372                         .reg = 0x228,
 373                         .bit = 24,
 374                 },
 375                 .la = {
 376                         .reg = 0x334,
 377                         .shift = 16,
 378                         .mask = 0xff,
 379                         .def = 0x13,
 380                 },
 381         }, {
 382                 .id = 0x19,
 383                 .name = "idxsrd2",
 384                 .swgroup = TEGRA_SWGROUP_NV2,
 385                 .smmu = {
 386                         .reg = 0x228,
 387                         .bit = 25,
 388                 },
 389                 .la = {
 390                         .reg = 0x33c,
 391                         .shift = 16,
 392                         .mask = 0xff,
 393                         .def = 0x13,
 394                 },
 395         }, {
 396                 .id = 0x1a,
 397                 .name = "mpe_ipred",
 398                 .swgroup = TEGRA_SWGROUP_MPE,
 399                 .smmu = {
 400                         .reg = 0x228,
 401                         .bit = 26,
 402                 },
 403                 .la = {
 404                         .reg = 0x328,
 405                         .shift = 16,
 406                         .mask = 0xff,
 407                         .def = 0x80,
 408                 },
 409         }, {
 410                 .id = 0x1b,
 411                 .name = "mpeamemrd",
 412                 .swgroup = TEGRA_SWGROUP_MPE,
 413                 .smmu = {
 414                         .reg = 0x228,
 415                         .bit = 27,
 416                 },
 417                 .la = {
 418                         .reg = 0x32c,
 419                         .shift = 0,
 420                         .mask = 0xff,
 421                         .def = 0x42,
 422                 },
 423         }, {
 424                 .id = 0x1c,
 425                 .name = "mpecsrd",
 426                 .swgroup = TEGRA_SWGROUP_MPE,
 427                 .smmu = {
 428                         .reg = 0x228,
 429                         .bit = 28,
 430                 },
 431                 .la = {
 432                         .reg = 0x32c,
 433                         .shift = 16,
 434                         .mask = 0xff,
 435                         .def = 0xff,
 436                 },
 437         }, {
 438                 .id = 0x1d,
 439                 .name = "ppcsahbdmar",
 440                 .swgroup = TEGRA_SWGROUP_PPCS,
 441                 .smmu = {
 442                         .reg = 0x228,
 443                         .bit = 29,
 444                 },
 445                 .la = {
 446                         .reg = 0x344,
 447                         .shift = 0,
 448                         .mask = 0xff,
 449                         .def = 0x10,
 450                 },
 451         }, {
 452                 .id = 0x1e,
 453                 .name = "ppcsahbslvr",
 454                 .swgroup = TEGRA_SWGROUP_PPCS,
 455                 .smmu = {
 456                         .reg = 0x228,
 457                         .bit = 30,
 458                 },
 459                 .la = {
 460                         .reg = 0x344,
 461                         .shift = 16,
 462                         .mask = 0xff,
 463                         .def = 0x12,
 464                 },
 465         }, {
 466                 .id = 0x1f,
 467                 .name = "satar",
 468                 .swgroup = TEGRA_SWGROUP_SATA,
 469                 .smmu = {
 470                         .reg = 0x228,
 471                         .bit = 31,
 472                 },
 473                 .la = {
 474                         .reg = 0x350,
 475                         .shift = 0,
 476                         .mask = 0xff,
 477                         .def = 0x33,
 478                 },
 479         }, {
 480                 .id = 0x20,
 481                 .name = "texsrd",
 482                 .swgroup = TEGRA_SWGROUP_NV,
 483                 .smmu = {
 484                         .reg = 0x22c,
 485                         .bit = 0,
 486                 },
 487                 .la = {
 488                         .reg = 0x338,
 489                         .shift = 0,
 490                         .mask = 0xff,
 491                         .def = 0x13,
 492                 },
 493         }, {
 494                 .id = 0x21,
 495                 .name = "texsrd2",
 496                 .swgroup = TEGRA_SWGROUP_NV2,
 497                 .smmu = {
 498                         .reg = 0x22c,
 499                         .bit = 1,
 500                 },
 501                 .la = {
 502                         .reg = 0x340,
 503                         .shift = 0,
 504                         .mask = 0xff,
 505                         .def = 0x13,
 506                 },
 507         }, {
 508                 .id = 0x22,
 509                 .name = "vdebsevr",
 510                 .swgroup = TEGRA_SWGROUP_VDE,
 511                 .smmu = {
 512                         .reg = 0x22c,
 513                         .bit = 2,
 514                 },
 515                 .la = {
 516                         .reg = 0x354,
 517                         .shift = 0,
 518                         .mask = 0xff,
 519                         .def = 0xff,
 520                 },
 521         }, {
 522                 .id = 0x23,
 523                 .name = "vdember",
 524                 .swgroup = TEGRA_SWGROUP_VDE,
 525                 .smmu = {
 526                         .reg = 0x22c,
 527                         .bit = 3,
 528                 },
 529                 .la = {
 530                         .reg = 0x354,
 531                         .shift = 16,
 532                         .mask = 0xff,
 533                         .def = 0xd0,
 534                 },
 535         }, {
 536                 .id = 0x24,
 537                 .name = "vdemcer",
 538                 .swgroup = TEGRA_SWGROUP_VDE,
 539                 .smmu = {
 540                         .reg = 0x22c,
 541                         .bit = 4,
 542                 },
 543                 .la = {
 544                         .reg = 0x358,
 545                         .shift = 0,
 546                         .mask = 0xff,
 547                         .def = 0x2a,
 548                 },
 549         }, {
 550                 .id = 0x25,
 551                 .name = "vdetper",
 552                 .swgroup = TEGRA_SWGROUP_VDE,
 553                 .smmu = {
 554                         .reg = 0x22c,
 555                         .bit = 5,
 556                 },
 557                 .la = {
 558                         .reg = 0x358,
 559                         .shift = 16,
 560                         .mask = 0xff,
 561                         .def = 0x74,
 562                 },
 563         }, {
 564                 .id = 0x26,
 565                 .name = "mpcorelpr",
 566                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 567                 .la = {
 568                         .reg = 0x324,
 569                         .shift = 0,
 570                         .mask = 0xff,
 571                         .def = 0x04,
 572                 },
 573         }, {
 574                 .id = 0x27,
 575                 .name = "mpcorer",
 576                 .swgroup = TEGRA_SWGROUP_MPCORE,
 577                 .la = {
 578                         .reg = 0x320,
 579                         .shift = 0,
 580                         .mask = 0xff,
 581                         .def = 0x04,
 582                 },
 583         }, {
 584                 .id = 0x28,
 585                 .name = "eppu",
 586                 .swgroup = TEGRA_SWGROUP_EPP,
 587                 .smmu = {
 588                         .reg = 0x22c,
 589                         .bit = 8,
 590                 },
 591                 .la = {
 592                         .reg = 0x300,
 593                         .shift = 16,
 594                         .mask = 0xff,
 595                         .def = 0x6c,
 596                 },
 597         }, {
 598                 .id = 0x29,
 599                 .name = "eppv",
 600                 .swgroup = TEGRA_SWGROUP_EPP,
 601                 .smmu = {
 602                         .reg = 0x22c,
 603                         .bit = 9,
 604                 },
 605                 .la = {
 606                         .reg = 0x304,
 607                         .shift = 0,
 608                         .mask = 0xff,
 609                         .def = 0x6c,
 610                 },
 611         }, {
 612                 .id = 0x2a,
 613                 .name = "eppy",
 614                 .swgroup = TEGRA_SWGROUP_EPP,
 615                 .smmu = {
 616                         .reg = 0x22c,
 617                         .bit = 10,
 618                 },
 619                 .la = {
 620                         .reg = 0x304,
 621                         .shift = 16,
 622                         .mask = 0xff,
 623                         .def = 0x6c,
 624                 },
 625         }, {
 626                 .id = 0x2b,
 627                 .name = "mpeunifbw",
 628                 .swgroup = TEGRA_SWGROUP_MPE,
 629                 .smmu = {
 630                         .reg = 0x22c,
 631                         .bit = 11,
 632                 },
 633                 .la = {
 634                         .reg = 0x330,
 635                         .shift = 0,
 636                         .mask = 0xff,
 637                         .def = 0x13,
 638                 },
 639         }, {
 640                 .id = 0x2c,
 641                 .name = "viwsb",
 642                 .swgroup = TEGRA_SWGROUP_VI,
 643                 .smmu = {
 644                         .reg = 0x22c,
 645                         .bit = 12,
 646                 },
 647                 .la = {
 648                         .reg = 0x364,
 649                         .shift = 16,
 650                         .mask = 0xff,
 651                         .def = 0x12,
 652                 },
 653         }, {
 654                 .id = 0x2d,
 655                 .name = "viwu",
 656                 .swgroup = TEGRA_SWGROUP_VI,
 657                 .smmu = {
 658                         .reg = 0x22c,
 659                         .bit = 13,
 660                 },
 661                 .la = {
 662                         .reg = 0x368,
 663                         .shift = 0,
 664                         .mask = 0xff,
 665                         .def = 0xb2,
 666                 },
 667         }, {
 668                 .id = 0x2e,
 669                 .name = "viwv",
 670                 .swgroup = TEGRA_SWGROUP_VI,
 671                 .smmu = {
 672                         .reg = 0x22c,
 673                         .bit = 14,
 674                 },
 675                 .la = {
 676                         .reg = 0x368,
 677                         .shift = 16,
 678                         .mask = 0xff,
 679                         .def = 0xb2,
 680                 },
 681         }, {
 682                 .id = 0x2f,
 683                 .name = "viwy",
 684                 .swgroup = TEGRA_SWGROUP_VI,
 685                 .smmu = {
 686                         .reg = 0x22c,
 687                         .bit = 15,
 688                 },
 689                 .la = {
 690                         .reg = 0x36c,
 691                         .shift = 0,
 692                         .mask = 0xff,
 693                         .def = 0x12,
 694                 },
 695         }, {
 696                 .id = 0x30,
 697                 .name = "g2dw",
 698                 .swgroup = TEGRA_SWGROUP_G2,
 699                 .smmu = {
 700                         .reg = 0x22c,
 701                         .bit = 16,
 702                 },
 703                 .la = {
 704                         .reg = 0x30c,
 705                         .shift = 16,
 706                         .mask = 0xff,
 707                         .def = 0x9,
 708                 },
 709         }, {
 710                 .id = 0x31,
 711                 .name = "afiw",
 712                 .swgroup = TEGRA_SWGROUP_AFI,
 713                 .smmu = {
 714                         .reg = 0x22c,
 715                         .bit = 17,
 716                 },
 717                 .la = {
 718                         .reg = 0x2e0,
 719                         .shift = 16,
 720                         .mask = 0xff,
 721                         .def = 0x0c,
 722                 },
 723         }, {
 724                 .id = 0x32,
 725                 .name = "avpcarm7w",
 726                 .swgroup = TEGRA_SWGROUP_AVPC,
 727                 .smmu = {
 728                         .reg = 0x22c,
 729                         .bit = 18,
 730                 },
 731                 .la = {
 732                         .reg = 0x2e4,
 733                         .shift = 16,
 734                         .mask = 0xff,
 735                         .def = 0x0e,
 736                 },
 737         }, {
 738                 .id = 0x33,
 739                 .name = "fdcdwr",
 740                 .swgroup = TEGRA_SWGROUP_NV,
 741                 .smmu = {
 742                         .reg = 0x22c,
 743                         .bit = 19,
 744                 },
 745                 .la = {
 746                         .reg = 0x338,
 747                         .shift = 16,
 748                         .mask = 0xff,
 749                         .def = 0x0a,
 750                 },
 751         }, {
 752                 .id = 0x34,
 753                 .name = "fdcdwr2",
 754                 .swgroup = TEGRA_SWGROUP_NV2,
 755                 .smmu = {
 756                         .reg = 0x22c,
 757                         .bit = 20,
 758                 },
 759                 .la = {
 760                         .reg = 0x340,
 761                         .shift = 16,
 762                         .mask = 0xff,
 763                         .def = 0x0a,
 764                 },
 765         }, {
 766                 .id = 0x35,
 767                 .name = "hdaw",
 768                 .swgroup = TEGRA_SWGROUP_HDA,
 769                 .smmu = {
 770                         .reg = 0x22c,
 771                         .bit = 21,
 772                 },
 773                 .la = {
 774                         .reg = 0x318,
 775                         .shift = 16,
 776                         .mask = 0xff,
 777                         .def = 0xff,
 778                 },
 779         }, {
 780                 .id = 0x36,
 781                 .name = "host1xw",
 782                 .swgroup = TEGRA_SWGROUP_HC,
 783                 .smmu = {
 784                         .reg = 0x22c,
 785                         .bit = 22,
 786                 },
 787                 .la = {
 788                         .reg = 0x314,
 789                         .shift = 0,
 790                         .mask = 0xff,
 791                         .def = 0x10,
 792                 },
 793         }, {
 794                 .id = 0x37,
 795                 .name = "ispw",
 796                 .swgroup = TEGRA_SWGROUP_ISP,
 797                 .smmu = {
 798                         .reg = 0x22c,
 799                         .bit = 23,
 800                 },
 801                 .la = {
 802                         .reg = 0x31c,
 803                         .shift = 0,
 804                         .mask = 0xff,
 805                         .def = 0xff,
 806                 },
 807         }, {
 808                 .id = 0x38,
 809                 .name = "mpcorelpw",
 810                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 811                 .la = {
 812                         .reg = 0x324,
 813                         .shift = 16,
 814                         .mask = 0xff,
 815                         .def = 0x0e,
 816                 },
 817         }, {
 818                 .id = 0x39,
 819                 .name = "mpcorew",
 820                 .swgroup = TEGRA_SWGROUP_MPCORE,
 821                 .la = {
 822                         .reg = 0x320,
 823                         .shift = 16,
 824                         .mask = 0xff,
 825                         .def = 0x0e,
 826                 },
 827         }, {
 828                 .id = 0x3a,
 829                 .name = "mpecswr",
 830                 .swgroup = TEGRA_SWGROUP_MPE,
 831                 .smmu = {
 832                         .reg = 0x22c,
 833                         .bit = 26,
 834                 },
 835                 .la = {
 836                         .reg = 0x330,
 837                         .shift = 16,
 838                         .mask = 0xff,
 839                         .def = 0xff,
 840                 },
 841         }, {
 842                 .id = 0x3b,
 843                 .name = "ppcsahbdmaw",
 844                 .swgroup = TEGRA_SWGROUP_PPCS,
 845                 .smmu = {
 846                         .reg = 0x22c,
 847                         .bit = 27,
 848                 },
 849                 .la = {
 850                         .reg = 0x348,
 851                         .shift = 0,
 852                         .mask = 0xff,
 853                         .def = 0x10,
 854                 },
 855         }, {
 856                 .id = 0x3c,
 857                 .name = "ppcsahbslvw",
 858                 .swgroup = TEGRA_SWGROUP_PPCS,
 859                 .smmu = {
 860                         .reg = 0x22c,
 861                         .bit = 28,
 862                 },
 863                 .la = {
 864                         .reg = 0x348,
 865                         .shift = 16,
 866                         .mask = 0xff,
 867                         .def = 0x06,
 868                 },
 869         }, {
 870                 .id = 0x3d,
 871                 .name = "sataw",
 872                 .swgroup = TEGRA_SWGROUP_SATA,
 873                 .smmu = {
 874                         .reg = 0x22c,
 875                         .bit = 29,
 876                 },
 877                 .la = {
 878                         .reg = 0x350,
 879                         .shift = 16,
 880                         .mask = 0xff,
 881                         .def = 0x33,
 882                 },
 883         }, {
 884                 .id = 0x3e,
 885                 .name = "vdebsevw",
 886                 .swgroup = TEGRA_SWGROUP_VDE,
 887                 .smmu = {
 888                         .reg = 0x22c,
 889                         .bit = 30,
 890                 },
 891                 .la = {
 892                         .reg = 0x35c,
 893                         .shift = 0,
 894                         .mask = 0xff,
 895                         .def = 0xff,
 896                 },
 897         }, {
 898                 .id = 0x3f,
 899                 .name = "vdedbgw",
 900                 .swgroup = TEGRA_SWGROUP_VDE,
 901                 .smmu = {
 902                         .reg = 0x22c,
 903                         .bit = 31,
 904                 },
 905                 .la = {
 906                         .reg = 0x35c,
 907                         .shift = 16,
 908                         .mask = 0xff,
 909                         .def = 0xff,
 910                 },
 911         }, {
 912                 .id = 0x40,
 913                 .name = "vdembew",
 914                 .swgroup = TEGRA_SWGROUP_VDE,
 915                 .smmu = {
 916                         .reg = 0x230,
 917                         .bit = 0,
 918                 },
 919                 .la = {
 920                         .reg = 0x360,
 921                         .shift = 0,
 922                         .mask = 0xff,
 923                         .def = 0x42,
 924                 },
 925         }, {
 926                 .id = 0x41,
 927                 .name = "vdetpmw",
 928                 .swgroup = TEGRA_SWGROUP_VDE,
 929                 .smmu = {
 930                         .reg = 0x230,
 931                         .bit = 1,
 932                 },
 933                 .la = {
 934                         .reg = 0x360,
 935                         .shift = 16,
 936                         .mask = 0xff,
 937                         .def = 0x2a,
 938                 },
 939         },
 940 };
 941
 942 static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
 943         { .name = "dc",   .swgroup = TEGRA_SWGROUP_DC,   .reg = 0x240 },
 944         { .name = "dcb",  .swgroup = TEGRA_SWGROUP_DCB,  .reg = 0x244 },
 945         { .name = "epp",  .swgroup = TEGRA_SWGROUP_EPP,  .reg = 0x248 },
 946         { .name = "g2",   .swgroup = TEGRA_SWGROUP_G2,   .reg = 0x24c },
 947         { .name = "mpe",  .swgroup = TEGRA_SWGROUP_MPE,  .reg = 0x264 },
 948         { .name = "vi",   .swgroup = TEGRA_SWGROUP_VI,   .reg = 0x280 },
 949         { .name = "afi",  .swgroup = TEGRA_SWGROUP_AFI,  .reg = 0x238 },
 950         { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
 951         { .name = "nv",   .swgroup = TEGRA_SWGROUP_NV,   .reg = 0x268 },
 952         { .name = "nv2",  .swgroup = TEGRA_SWGROUP_NV2,  .reg = 0x26c },
 953         { .name = "hda",  .swgroup = TEGRA_SWGROUP_HDA,  .reg = 0x254 },
 954         { .name = "hc",   .swgroup = TEGRA_SWGROUP_HC,   .reg = 0x250 },
 955         { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
 956         { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
 957         { .name = "vde",  .swgroup = TEGRA_SWGROUP_VDE,  .reg = 0x27c },
 958         { .name = "isp",  .swgroup = TEGRA_SWGROUP_ISP,  .reg = 0x258 },
 959 };
 960
 961 static const unsigned int tegra30_group_drm[] = {
 962         TEGRA_SWGROUP_DC,
 963         TEGRA_SWGROUP_DCB,
 964         TEGRA_SWGROUP_G2,
 965         TEGRA_SWGROUP_NV,
 966         TEGRA_SWGROUP_NV2,
 967 };
 968
 969 static const struct tegra_smmu_group_soc tegra30_groups[] = {
 970         {
 971                 .name = "drm",
 972                 .swgroups = tegra30_group_drm,
 973                 .num_swgroups = ARRAY_SIZE(tegra30_group_drm),
 974         },
 975 };
 976
 977 static const struct tegra_smmu_soc tegra30_smmu_soc = {
 978         .clients = tegra30_mc_clients,
 979         .num_clients = ARRAY_SIZE(tegra30_mc_clients),
 980         .swgroups = tegra30_swgroups,
 981         .num_swgroups = ARRAY_SIZE(tegra30_swgroups),
 982         .groups = tegra30_groups,
 983         .num_groups = ARRAY_SIZE(tegra30_groups),
 984         .supports_round_robin_arbitration = false,
 985         .supports_request_limit = false,
 986         .num_tlb_lines = 16,
 987         .num_asids = 4,
 988 };
 989
 990 #define TEGRA30_MC_RESET(_name, _control, _status, _bit)        \
 991         {                                                       \
 992                 .name = #_name,                                 \
 993                 .id = TEGRA30_MC_RESET_##_name,                 \
 994                 .control = _control,                            \
 995                 .status = _status,                              \
 996                 .bit = _bit,                                    \
 997         }
 998
 999 static const struct tegra_mc_reset tegra30_mc_resets[] = {
1000         TEGRA30_MC_RESET(AFI,      0x200, 0x204,  0),
1001         TEGRA30_MC_RESET(AVPC,     0x200, 0x204,  1),
1002         TEGRA30_MC_RESET(DC,       0x200, 0x204,  2),
1003         TEGRA30_MC_RESET(DCB,      0x200, 0x204,  3),
1004         TEGRA30_MC_RESET(EPP,      0x200, 0x204,  4),
1005         TEGRA30_MC_RESET(2D,       0x200, 0x204,  5),
1006         TEGRA30_MC_RESET(HC,       0x200, 0x204,  6),
1007         TEGRA30_MC_RESET(HDA,      0x200, 0x204,  7),
1008         TEGRA30_MC_RESET(ISP,      0x200, 0x204,  8),
1009         TEGRA30_MC_RESET(MPCORE,   0x200, 0x204,  9),
1010         TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1011         TEGRA30_MC_RESET(MPE,      0x200, 0x204, 11),
1012         TEGRA30_MC_RESET(3D,       0x200, 0x204, 12),
1013         TEGRA30_MC_RESET(3D2,      0x200, 0x204, 13),
1014         TEGRA30_MC_RESET(PPCS,     0x200, 0x204, 14),
1015         TEGRA30_MC_RESET(SATA,     0x200, 0x204, 15),
1016         TEGRA30_MC_RESET(VDE,      0x200, 0x204, 16),
1017         TEGRA30_MC_RESET(VI,       0x200, 0x204, 17),
1018 };
1019
1020 const struct tegra_mc_soc tegra30_mc_soc = {
1021         .clients = tegra30_mc_clients,
1022         .num_clients = ARRAY_SIZE(tegra30_mc_clients),
1023         .num_address_bits = 32,
1024         .atom_size = 16,
1025         .client_id_mask = 0x7f,
1026         .smmu = &tegra30_smmu_soc,
1027         .emem_regs = tegra30_mc_emem_regs,
1028         .num_emem_regs = ARRAY_SIZE(tegra30_mc_emem_regs),
1029         .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1030                    MC_INT_DECERR_EMEM,
1031         .reset_ops = &tegra_mc_reset_ops_common,
1032         .resets = tegra30_mc_resets,
1033         .num_resets = ARRAY_SIZE(tegra30_mc_resets),
1034 };