drivers/memory/tegra/tegra30-emc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Tegra30 External Memory Controller driver
   4  *
   5  * Based on downstream driver from NVIDIA and tegra124-emc.c
   6  * Copyright (C) 2011-2014 NVIDIA Corporation
   7  *
   8  * Author: Dmitry Osipenko <digetx@gmail.com>
   9  * Copyright (C) 2019 GRATE-DRIVER project
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clk/tegra.h>
  14 #include <linux/debugfs.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/sort.h>
  25 #include <linux/types.h>
  26
  27 #include <soc/tegra/fuse.h>
  28
  29 #include "mc.h"
  30
  31 #define EMC_INTSTATUS                           0x000
  32 #define EMC_INTMASK                             0x004
  33 #define EMC_DBG                                 0x008
  34 #define EMC_CFG                                 0x00c
  35 #define EMC_REFCTRL                             0x020
  36 #define EMC_TIMING_CONTROL                      0x028
  37 #define EMC_RC                                  0x02c
  38 #define EMC_RFC                                 0x030
  39 #define EMC_RAS                                 0x034
  40 #define EMC_RP                                  0x038
  41 #define EMC_R2W                                 0x03c
  42 #define EMC_W2R                                 0x040
  43 #define EMC_R2P                                 0x044
  44 #define EMC_W2P                                 0x048
  45 #define EMC_RD_RCD                              0x04c
  46 #define EMC_WR_RCD                              0x050
  47 #define EMC_RRD                                 0x054
  48 #define EMC_REXT                                0x058
  49 #define EMC_WDV                                 0x05c
  50 #define EMC_QUSE                                0x060
  51 #define EMC_QRST                                0x064
  52 #define EMC_QSAFE                               0x068
  53 #define EMC_RDV                                 0x06c
  54 #define EMC_REFRESH                             0x070
  55 #define EMC_BURST_REFRESH_NUM                   0x074
  56 #define EMC_PDEX2WR                             0x078
  57 #define EMC_PDEX2RD                             0x07c
  58 #define EMC_PCHG2PDEN                           0x080
  59 #define EMC_ACT2PDEN                            0x084
  60 #define EMC_AR2PDEN                             0x088
  61 #define EMC_RW2PDEN                             0x08c
  62 #define EMC_TXSR                                0x090
  63 #define EMC_TCKE                                0x094
  64 #define EMC_TFAW                                0x098
  65 #define EMC_TRPAB                               0x09c
  66 #define EMC_TCLKSTABLE                          0x0a0
  67 #define EMC_TCLKSTOP                            0x0a4
  68 #define EMC_TREFBW                              0x0a8
  69 #define EMC_QUSE_EXTRA                          0x0ac
  70 #define EMC_ODT_WRITE                           0x0b0
  71 #define EMC_ODT_READ                            0x0b4
  72 #define EMC_WEXT                                0x0b8
  73 #define EMC_CTT                                 0x0bc
  74 #define EMC_MRS_WAIT_CNT                        0x0c8
  75 #define EMC_MRS                                 0x0cc
  76 #define EMC_EMRS                                0x0d0
  77 #define EMC_SELF_REF                            0x0e0
  78 #define EMC_MRW                                 0x0e8
  79 #define EMC_XM2DQSPADCTRL3                      0x0f8
  80 #define EMC_FBIO_SPARE                          0x100
  81 #define EMC_FBIO_CFG5                           0x104
  82 #define EMC_FBIO_CFG6                           0x114
  83 #define EMC_CFG_RSV                             0x120
  84 #define EMC_AUTO_CAL_CONFIG                     0x2a4
  85 #define EMC_AUTO_CAL_INTERVAL                   0x2a8
  86 #define EMC_AUTO_CAL_STATUS                     0x2ac
  87 #define EMC_STATUS                              0x2b4
  88 #define EMC_CFG_2                               0x2b8
  89 #define EMC_CFG_DIG_DLL                         0x2bc
  90 #define EMC_CFG_DIG_DLL_PERIOD                  0x2c0
  91 #define EMC_CTT_DURATION                        0x2d8
  92 #define EMC_CTT_TERM_CTRL                       0x2dc
  93 #define EMC_ZCAL_INTERVAL                       0x2e0
  94 #define EMC_ZCAL_WAIT_CNT                       0x2e4
  95 #define EMC_ZQ_CAL                              0x2ec
  96 #define EMC_XM2CMDPADCTRL                       0x2f0
  97 #define EMC_XM2DQSPADCTRL2                      0x2fc
  98 #define EMC_XM2DQPADCTRL2                       0x304
  99 #define EMC_XM2CLKPADCTRL                       0x308
 100 #define EMC_XM2COMPPADCTRL                      0x30c
 101 #define EMC_XM2VTTGENPADCTRL                    0x310
 102 #define EMC_XM2VTTGENPADCTRL2                   0x314
 103 #define EMC_XM2QUSEPADCTRL                      0x318
 104 #define EMC_DLL_XFORM_DQS0                      0x328
 105 #define EMC_DLL_XFORM_DQS1                      0x32c
 106 #define EMC_DLL_XFORM_DQS2                      0x330
 107 #define EMC_DLL_XFORM_DQS3                      0x334
 108 #define EMC_DLL_XFORM_DQS4                      0x338
 109 #define EMC_DLL_XFORM_DQS5                      0x33c
 110 #define EMC_DLL_XFORM_DQS6                      0x340
 111 #define EMC_DLL_XFORM_DQS7                      0x344
 112 #define EMC_DLL_XFORM_QUSE0                     0x348
 113 #define EMC_DLL_XFORM_QUSE1                     0x34c
 114 #define EMC_DLL_XFORM_QUSE2                     0x350
 115 #define EMC_DLL_XFORM_QUSE3                     0x354
 116 #define EMC_DLL_XFORM_QUSE4                     0x358
 117 #define EMC_DLL_XFORM_QUSE5                     0x35c
 118 #define EMC_DLL_XFORM_QUSE6                     0x360
 119 #define EMC_DLL_XFORM_QUSE7                     0x364
 120 #define EMC_DLL_XFORM_DQ0                       0x368
 121 #define EMC_DLL_XFORM_DQ1                       0x36c
 122 #define EMC_DLL_XFORM_DQ2                       0x370
 123 #define EMC_DLL_XFORM_DQ3                       0x374
 124 #define EMC_DLI_TRIM_TXDQS0                     0x3a8
 125 #define EMC_DLI_TRIM_TXDQS1                     0x3ac
 126 #define EMC_DLI_TRIM_TXDQS2                     0x3b0
 127 #define EMC_DLI_TRIM_TXDQS3                     0x3b4
 128 #define EMC_DLI_TRIM_TXDQS4                     0x3b8
 129 #define EMC_DLI_TRIM_TXDQS5                     0x3bc
 130 #define EMC_DLI_TRIM_TXDQS6                     0x3c0
 131 #define EMC_DLI_TRIM_TXDQS7                     0x3c4
 132 #define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE     0x3c8
 133 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE      0x3cc
 134 #define EMC_UNSTALL_RW_AFTER_CLKCHANGE          0x3d0
 135 #define EMC_SEL_DPD_CTRL                        0x3d8
 136 #define EMC_PRE_REFRESH_REQ_CNT                 0x3dc
 137 #define EMC_DYN_SELF_REF_CONTROL                0x3e0
 138 #define EMC_TXSRDLL                             0x3e4
 139
 140 #define EMC_STATUS_TIMING_UPDATE_STALLED        BIT(23)
 141
 142 #define EMC_MODE_SET_DLL_RESET                  BIT(8)
 143 #define EMC_MODE_SET_LONG_CNT                   BIT(26)
 144
 145 #define EMC_SELF_REF_CMD_ENABLED                BIT(0)
 146
 147 #define DRAM_DEV_SEL_ALL                        (0 << 30)
 148 #define DRAM_DEV_SEL_0                          (2 << 30)
 149 #define DRAM_DEV_SEL_1                          (1 << 30)
 150 #define DRAM_BROADCAST(num) \
 151         ((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
 152
 153 #define EMC_ZQ_CAL_CMD                          BIT(0)
 154 #define EMC_ZQ_CAL_LONG                         BIT(4)
 155 #define EMC_ZQ_CAL_LONG_CMD_DEV0 \
 156         (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
 157 #define EMC_ZQ_CAL_LONG_CMD_DEV1 \
 158         (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
 159
 160 #define EMC_DBG_READ_MUX_ASSEMBLY               BIT(0)
 161 #define EMC_DBG_WRITE_MUX_ACTIVE                BIT(1)
 162 #define EMC_DBG_FORCE_UPDATE                    BIT(2)
 163 #define EMC_DBG_CFG_PRIORITY                    BIT(24)
 164
 165 #define EMC_CFG5_QUSE_MODE_SHIFT                13
 166 #define EMC_CFG5_QUSE_MODE_MASK                 (7 << EMC_CFG5_QUSE_MODE_SHIFT)
 167
 168 #define EMC_CFG5_QUSE_MODE_INTERNAL_LPBK        2
 169 #define EMC_CFG5_QUSE_MODE_PULSE_INTERN         3
 170
 171 #define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE        BIT(9)
 172
 173 #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE      BIT(10)
 174
 175 #define EMC_XM2QUSEPADCTRL_IVREF_ENABLE         BIT(4)
 176
 177 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE          BIT(5)
 178 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE          BIT(5)
 179
 180 #define EMC_AUTO_CAL_STATUS_ACTIVE              BIT(31)
 181
 182 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK            0x3
 183
 184 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK        0x3ff
 185 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT        16
 186 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
 187         (0x3ff << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
 188
 189 #define EMC_REFCTRL_DEV_SEL_MASK                0x3
 190 #define EMC_REFCTRL_ENABLE                      BIT(31)
 191 #define EMC_REFCTRL_ENABLE_ALL(num) \
 192         (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)
 193 #define EMC_REFCTRL_DISABLE_ALL(num)            ((num) > 1 ? 0 : 2)
 194
 195 #define EMC_CFG_PERIODIC_QRST                   BIT(21)
 196 #define EMC_CFG_DYN_SREF_ENABLE                 BIT(28)
 197
 198 #define EMC_CLKCHANGE_REQ_ENABLE                BIT(0)
 199 #define EMC_CLKCHANGE_PD_ENABLE                 BIT(1)
 200 #define EMC_CLKCHANGE_SR_ENABLE                 BIT(2)
 201
 202 #define EMC_TIMING_UPDATE                       BIT(0)
 203
 204 #define EMC_REFRESH_OVERFLOW_INT                BIT(3)
 205 #define EMC_CLKCHANGE_COMPLETE_INT              BIT(4)
 206
 207 enum emc_dram_type {
 208         DRAM_TYPE_DDR3,
 209         DRAM_TYPE_DDR1,
 210         DRAM_TYPE_LPDDR2,
 211         DRAM_TYPE_DDR2,
 212 };
 213
 214 enum emc_dll_change {
 215         DLL_CHANGE_NONE,
 216         DLL_CHANGE_ON,
 217         DLL_CHANGE_OFF
 218 };
 219
 220 static const u16 emc_timing_registers[] = {
 221         [0] = EMC_RC,
 222         [1] = EMC_RFC,
 223         [2] = EMC_RAS,
 224         [3] = EMC_RP,
 225         [4] = EMC_R2W,
 226         [5] = EMC_W2R,
 227         [6] = EMC_R2P,
 228         [7] = EMC_W2P,
 229         [8] = EMC_RD_RCD,
 230         [9] = EMC_WR_RCD,
 231         [10] = EMC_RRD,
 232         [11] = EMC_REXT,
 233         [12] = EMC_WEXT,
 234         [13] = EMC_WDV,
 235         [14] = EMC_QUSE,
 236         [15] = EMC_QRST,
 237         [16] = EMC_QSAFE,
 238         [17] = EMC_RDV,
 239         [18] = EMC_REFRESH,
 240         [19] = EMC_BURST_REFRESH_NUM,
 241         [20] = EMC_PRE_REFRESH_REQ_CNT,
 242         [21] = EMC_PDEX2WR,
 243         [22] = EMC_PDEX2RD,
 244         [23] = EMC_PCHG2PDEN,
 245         [24] = EMC_ACT2PDEN,
 246         [25] = EMC_AR2PDEN,
 247         [26] = EMC_RW2PDEN,
 248         [27] = EMC_TXSR,
 249         [28] = EMC_TXSRDLL,
 250         [29] = EMC_TCKE,
 251         [30] = EMC_TFAW,
 252         [31] = EMC_TRPAB,
 253         [32] = EMC_TCLKSTABLE,
 254         [33] = EMC_TCLKSTOP,
 255         [34] = EMC_TREFBW,
 256         [35] = EMC_QUSE_EXTRA,
 257         [36] = EMC_FBIO_CFG6,
 258         [37] = EMC_ODT_WRITE,
 259         [38] = EMC_ODT_READ,
 260         [39] = EMC_FBIO_CFG5,
 261         [40] = EMC_CFG_DIG_DLL,
 262         [41] = EMC_CFG_DIG_DLL_PERIOD,
 263         [42] = EMC_DLL_XFORM_DQS0,
 264         [43] = EMC_DLL_XFORM_DQS1,
 265         [44] = EMC_DLL_XFORM_DQS2,
 266         [45] = EMC_DLL_XFORM_DQS3,
 267         [46] = EMC_DLL_XFORM_DQS4,
 268         [47] = EMC_DLL_XFORM_DQS5,
 269         [48] = EMC_DLL_XFORM_DQS6,
 270         [49] = EMC_DLL_XFORM_DQS7,
 271         [50] = EMC_DLL_XFORM_QUSE0,
 272         [51] = EMC_DLL_XFORM_QUSE1,
 273         [52] = EMC_DLL_XFORM_QUSE2,
 274         [53] = EMC_DLL_XFORM_QUSE3,
 275         [54] = EMC_DLL_XFORM_QUSE4,
 276         [55] = EMC_DLL_XFORM_QUSE5,
 277         [56] = EMC_DLL_XFORM_QUSE6,
 278         [57] = EMC_DLL_XFORM_QUSE7,
 279         [58] = EMC_DLI_TRIM_TXDQS0,
 280         [59] = EMC_DLI_TRIM_TXDQS1,
 281         [60] = EMC_DLI_TRIM_TXDQS2,
 282         [61] = EMC_DLI_TRIM_TXDQS3,
 283         [62] = EMC_DLI_TRIM_TXDQS4,
 284         [63] = EMC_DLI_TRIM_TXDQS5,
 285         [64] = EMC_DLI_TRIM_TXDQS6,
 286         [65] = EMC_DLI_TRIM_TXDQS7,
 287         [66] = EMC_DLL_XFORM_DQ0,
 288         [67] = EMC_DLL_XFORM_DQ1,
 289         [68] = EMC_DLL_XFORM_DQ2,
 290         [69] = EMC_DLL_XFORM_DQ3,
 291         [70] = EMC_XM2CMDPADCTRL,
 292         [71] = EMC_XM2DQSPADCTRL2,
 293         [72] = EMC_XM2DQPADCTRL2,
 294         [73] = EMC_XM2CLKPADCTRL,
 295         [74] = EMC_XM2COMPPADCTRL,
 296         [75] = EMC_XM2VTTGENPADCTRL,
 297         [76] = EMC_XM2VTTGENPADCTRL2,
 298         [77] = EMC_XM2QUSEPADCTRL,
 299         [78] = EMC_XM2DQSPADCTRL3,
 300         [79] = EMC_CTT_TERM_CTRL,
 301         [80] = EMC_ZCAL_INTERVAL,
 302         [81] = EMC_ZCAL_WAIT_CNT,
 303         [82] = EMC_MRS_WAIT_CNT,
 304         [83] = EMC_AUTO_CAL_CONFIG,
 305         [84] = EMC_CTT,
 306         [85] = EMC_CTT_DURATION,
 307         [86] = EMC_DYN_SELF_REF_CONTROL,
 308         [87] = EMC_FBIO_SPARE,
 309         [88] = EMC_CFG_RSV,
 310 };
 311
 312 struct emc_timing {
 313         unsigned long rate;
 314
 315         u32 data[ARRAY_SIZE(emc_timing_registers)];
 316
 317         u32 emc_auto_cal_interval;
 318         u32 emc_mode_1;
 319         u32 emc_mode_2;
 320         u32 emc_mode_reset;
 321         u32 emc_zcal_cnt_long;
 322         bool emc_cfg_periodic_qrst;
 323         bool emc_cfg_dyn_self_ref;
 324 };
 325
 326 struct tegra_emc {
 327         struct device *dev;
 328         struct tegra_mc *mc;
 329         struct notifier_block clk_nb;
 330         struct clk *clk;
 331         void __iomem *regs;
 332         unsigned int irq;
 333         bool bad_state;
 334
 335         struct emc_timing *new_timing;
 336         struct emc_timing *timings;
 337         unsigned int num_timings;
 338
 339         u32 mc_override;
 340         u32 emc_cfg;
 341
 342         u32 emc_mode_1;
 343         u32 emc_mode_2;
 344         u32 emc_mode_reset;
 345
 346         bool vref_cal_toggle : 1;
 347         bool zcal_long : 1;
 348         bool dll_on : 1;
 349
 350         struct {
 351                 struct dentry *root;
 352                 unsigned long min_rate;
 353                 unsigned long max_rate;
 354         } debugfs;
 355 };
 356
 357 static int emc_seq_update_timing(struct tegra_emc *emc)
 358 {
 359         u32 val;
 360         int err;
 361
 362         writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL);
 363
 364         err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val,
 365                                 !(val & EMC_STATUS_TIMING_UPDATE_STALLED),
 366                                 1, 200);
 367         if (err) {
 368                 dev_err(emc->dev, "failed to update timing: %d\n", err);
 369                 return err;
 370         }
 371
 372         return 0;
 373 }
 374
 375 static irqreturn_t tegra_emc_isr(int irq, void *data)
 376 {
 377         struct tegra_emc *emc = data;
 378         u32 intmask = EMC_REFRESH_OVERFLOW_INT;
 379         u32 status;
 380
 381         status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
 382         if (!status)
 383                 return IRQ_NONE;
 384
 385         /* notify about HW problem */
 386         if (status & EMC_REFRESH_OVERFLOW_INT)
 387                 dev_err_ratelimited(emc->dev,
 388                                     "refresh request overflow timeout\n");
 389
 390         /* clear interrupts */
 391         writel_relaxed(status, emc->regs + EMC_INTSTATUS);
 392
 393         return IRQ_HANDLED;
 394 }
 395
 396 static struct emc_timing *emc_find_timing(struct tegra_emc *emc,
 397                                           unsigned long rate)
 398 {
 399         struct emc_timing *timing = NULL;
 400         unsigned int i;
 401
 402         for (i = 0; i < emc->num_timings; i++) {
 403                 if (emc->timings[i].rate >= rate) {
 404                         timing = &emc->timings[i];
 405                         break;
 406                 }
 407         }
 408
 409         if (!timing) {
 410                 dev_err(emc->dev, "no timing for rate %lu\n", rate);
 411                 return NULL;
 412         }
 413
 414         return timing;
 415 }
 416
 417 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing,
 418                            bool *schmitt_to_vref)
 419 {
 420         bool preset = false;
 421         u32 val;
 422
 423         if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) {
 424                 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2);
 425
 426                 if (!(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
 427                         val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
 428                         writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2);
 429
 430                         preset = true;
 431                 }
 432         }
 433
 434         if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) {
 435                 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3);
 436
 437                 if (!(val & EMC_XM2DQSPADCTRL3_VREF_ENABLE)) {
 438                         val |= EMC_XM2DQSPADCTRL3_VREF_ENABLE;
 439                         writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3);
 440
 441                         preset = true;
 442                 }
 443         }
 444
 445         if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) {
 446                 val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL);
 447
 448                 if (!(val & EMC_XM2QUSEPADCTRL_IVREF_ENABLE)) {
 449                         val |= EMC_XM2QUSEPADCTRL_IVREF_ENABLE;
 450                         writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL);
 451
 452                         *schmitt_to_vref = true;
 453                         preset = true;
 454                 }
 455         }
 456
 457         return preset;
 458 }
 459
 460 static int emc_prepare_mc_clk_cfg(struct tegra_emc *emc, unsigned long rate)
 461 {
 462         struct tegra_mc *mc = emc->mc;
 463         unsigned int misc0_index = 16;
 464         unsigned int i;
 465         bool same;
 466
 467         for (i = 0; i < mc->num_timings; i++) {
 468                 if (mc->timings[i].rate != rate)
 469                         continue;
 470
 471                 if (mc->timings[i].emem_data[misc0_index] & BIT(27))
 472                         same = true;
 473                 else
 474                         same = false;
 475
 476                 return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same);
 477         }
 478
 479         return -EINVAL;
 480 }
 481
 482 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
 483 {
 484         struct emc_timing *timing = emc_find_timing(emc, rate);
 485         enum emc_dll_change dll_change;
 486         enum emc_dram_type dram_type;
 487         bool schmitt_to_vref = false;
 488         unsigned int pre_wait = 0;
 489         bool qrst_used = false;
 490         unsigned int dram_num;
 491         unsigned int i;
 492         u32 fbio_cfg5;
 493         u32 emc_dbg;
 494         u32 val;
 495         int err;
 496
 497         if (!timing || emc->bad_state)
 498                 return -EINVAL;
 499
 500         dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
 501                 __func__, timing->rate, rate);
 502
 503         emc->bad_state = true;
 504
 505         err = emc_prepare_mc_clk_cfg(emc, rate);
 506         if (err) {
 507                 dev_err(emc->dev, "mc clock preparation failed: %d\n", err);
 508                 return err;
 509         }
 510
 511         emc->vref_cal_toggle = false;
 512         emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
 513         emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG);
 514         emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
 515
 516         if (emc->dll_on == !!(timing->emc_mode_1 & 0x1))
 517                 dll_change = DLL_CHANGE_NONE;
 518         else if (timing->emc_mode_1 & 0x1)
 519                 dll_change = DLL_CHANGE_ON;
 520         else
 521                 dll_change = DLL_CHANGE_OFF;
 522
 523         emc->dll_on = !!(timing->emc_mode_1 & 0x1);
 524
 525         if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL))
 526                 emc->zcal_long = true;
 527         else
 528                 emc->zcal_long = false;
 529
 530         fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
 531         dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK;
 532
 533         dram_num = tegra_mc_get_emem_device_count(emc->mc);
 534
 535         /* disable dynamic self-refresh */
 536         if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) {
 537                 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE;
 538                 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
 539
 540                 pre_wait = 5;
 541         }
 542
 543         /* update MC arbiter settings */
 544         val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ);
 545         if (!(val & MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE) ||
 546             ((val & MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK) > 0x50)) {
 547
 548                 val = MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE |
 549                       MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE | 0x50;
 550                 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ);
 551                 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
 552         }
 553
 554         if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK)
 555                 mc_writel(emc->mc,
 556                           emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK,
 557                           MC_EMEM_ARB_OVERRIDE);
 558
 559         /* check DQ/DQS VREF delay */
 560         if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) {
 561                 if (pre_wait < 3)
 562                         pre_wait = 3;
 563         }
 564
 565         if (pre_wait) {
 566                 err = emc_seq_update_timing(emc);
 567                 if (err)
 568                         return err;
 569
 570                 udelay(pre_wait);
 571         }
 572
 573         /* disable auto-calibration if VREF mode is switching */
 574         if (timing->emc_auto_cal_interval) {
 575                 val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL);
 576                 val ^= timing->data[74];
 577
 578                 if (val & EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE) {
 579                         writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
 580
 581                         err = readl_relaxed_poll_timeout_atomic(
 582                                 emc->regs + EMC_AUTO_CAL_STATUS, val,
 583                                 !(val & EMC_AUTO_CAL_STATUS_ACTIVE), 1, 300);
 584                         if (err) {
 585                                 dev_err(emc->dev,
 586                                         "auto-cal finish timeout: %d\n", err);
 587                                 return err;
 588                         }
 589
 590                         emc->vref_cal_toggle = true;
 591                 }
 592         }
 593
 594         /* program shadow registers */
 595         for (i = 0; i < ARRAY_SIZE(timing->data); i++) {
 596                 /* EMC_XM2CLKPADCTRL should be programmed separately */
 597                 if (i != 73)
 598                         writel_relaxed(timing->data[i],
 599                                        emc->regs + emc_timing_registers[i]);
 600         }
 601
 602         err = tegra_mc_write_emem_configuration(emc->mc, timing->rate);
 603         if (err)
 604                 return err;
 605
 606         /* DDR3: predict MRS long wait count */
 607         if (dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) {
 608                 u32 cnt = 512;
 609
 610                 if (emc->zcal_long)
 611                         cnt -= dram_num * 256;
 612
 613                 val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK;
 614                 if (cnt < val)
 615                         cnt = val;
 616
 617                 val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
 618                 val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) &
 619                         EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
 620
 621                 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT);
 622         }
 623
 624         /* this read also completes the writes */
 625         val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL);
 626
 627         if (!(val & EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE) && schmitt_to_vref) {
 628                 u32 cur_mode, new_mode;
 629
 630                 cur_mode = fbio_cfg5 & EMC_CFG5_QUSE_MODE_MASK;
 631                 cur_mode >>= EMC_CFG5_QUSE_MODE_SHIFT;
 632
 633                 new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK;
 634                 new_mode >>= EMC_CFG5_QUSE_MODE_SHIFT;
 635
 636                 if ((cur_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN &&
 637                      cur_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK) ||
 638                     (new_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN &&
 639                      new_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK))
 640                         qrst_used = true;
 641         }
 642
 643         /* flow control marker 1 */
 644         writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE);
 645
 646         /* enable periodic reset */
 647         if (qrst_used) {
 648                 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,
 649                                emc->regs + EMC_DBG);
 650                 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST,
 651                                emc->regs + EMC_CFG);
 652                 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
 653         }
 654
 655         /* disable auto-refresh to save time after clock change */
 656         writel_relaxed(EMC_REFCTRL_DISABLE_ALL(dram_num),
 657                        emc->regs + EMC_REFCTRL);
 658
 659         /* turn off DLL and enter self-refresh on DDR3 */
 660         if (dram_type == DRAM_TYPE_DDR3) {
 661                 if (dll_change == DLL_CHANGE_OFF)
 662                         writel_relaxed(timing->emc_mode_1,
 663                                        emc->regs + EMC_EMRS);
 664
 665                 writel_relaxed(DRAM_BROADCAST(dram_num) |
 666                                EMC_SELF_REF_CMD_ENABLED,
 667                                emc->regs + EMC_SELF_REF);
 668         }
 669
 670         /* flow control marker 2 */
 671         writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
 672
 673         /* enable write-active MUX, update unshadowed pad control */
 674         writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG);
 675         writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL);
 676
 677         /* restore periodic QRST and disable write-active MUX */
 678         val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST);
 679         if (qrst_used || timing->emc_cfg_periodic_qrst != val) {
 680                 if (timing->emc_cfg_periodic_qrst)
 681                         emc->emc_cfg |= EMC_CFG_PERIODIC_QRST;
 682                 else
 683                         emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST;
 684
 685                 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
 686         }
 687         writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
 688
 689         /* exit self-refresh on DDR3 */
 690         if (dram_type == DRAM_TYPE_DDR3)
 691                 writel_relaxed(DRAM_BROADCAST(dram_num),
 692                                emc->regs + EMC_SELF_REF);
 693
 694         /* set DRAM-mode registers */
 695         if (dram_type == DRAM_TYPE_DDR3) {
 696                 if (timing->emc_mode_1 != emc->emc_mode_1)
 697                         writel_relaxed(timing->emc_mode_1,
 698                                        emc->regs + EMC_EMRS);
 699
 700                 if (timing->emc_mode_2 != emc->emc_mode_2)
 701                         writel_relaxed(timing->emc_mode_2,
 702                                        emc->regs + EMC_EMRS);
 703
 704                 if (timing->emc_mode_reset != emc->emc_mode_reset ||
 705                     dll_change == DLL_CHANGE_ON) {
 706                         val = timing->emc_mode_reset;
 707                         if (dll_change == DLL_CHANGE_ON) {
 708                                 val |= EMC_MODE_SET_DLL_RESET;
 709                                 val |= EMC_MODE_SET_LONG_CNT;
 710                         } else {
 711                                 val &= ~EMC_MODE_SET_DLL_RESET;
 712                         }
 713                         writel_relaxed(val, emc->regs + EMC_MRS);
 714                 }
 715         } else {
 716                 if (timing->emc_mode_2 != emc->emc_mode_2)
 717                         writel_relaxed(timing->emc_mode_2,
 718                                        emc->regs + EMC_MRW);
 719
 720                 if (timing->emc_mode_1 != emc->emc_mode_1)
 721                         writel_relaxed(timing->emc_mode_1,
 722                                        emc->regs + EMC_MRW);
 723         }
 724
 725         emc->emc_mode_1 = timing->emc_mode_1;
 726         emc->emc_mode_2 = timing->emc_mode_2;
 727         emc->emc_mode_reset = timing->emc_mode_reset;
 728
 729         /* issue ZCAL command if turning ZCAL on */
 730         if (emc->zcal_long) {
 731                 writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV0,
 732                                emc->regs + EMC_ZQ_CAL);
 733
 734                 if (dram_num > 1)
 735                         writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV1,
 736                                        emc->regs + EMC_ZQ_CAL);
 737         }
 738
 739         /* flow control marker 3 */
 740         writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE);
 741
 742         /*
 743          * Read and discard an arbitrary MC register (Note: EMC registers
 744          * can't be used) to ensure the register writes are completed.
 745          */
 746         mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
 747
 748         return 0;
 749 }
 750
 751 static int emc_complete_timing_change(struct tegra_emc *emc,
 752                                       unsigned long rate)
 753 {
 754         struct emc_timing *timing = emc_find_timing(emc, rate);
 755         unsigned int dram_num;
 756         int err;
 757         u32 v;
 758
 759         err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
 760                                                 v & EMC_CLKCHANGE_COMPLETE_INT,
 761                                                 1, 100);
 762         if (err) {
 763                 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
 764                 return err;
 765         }
 766
 767         /* re-enable auto-refresh */
 768         dram_num = tegra_mc_get_emem_device_count(emc->mc);
 769         writel_relaxed(EMC_REFCTRL_ENABLE_ALL(dram_num),
 770                        emc->regs + EMC_REFCTRL);
 771
 772         /* restore auto-calibration */
 773         if (emc->vref_cal_toggle)
 774                 writel_relaxed(timing->emc_auto_cal_interval,
 775                                emc->regs + EMC_AUTO_CAL_INTERVAL);
 776
 777         /* restore dynamic self-refresh */
 778         if (timing->emc_cfg_dyn_self_ref) {
 779                 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE;
 780                 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
 781         }
 782
 783         /* set number of clocks to wait after each ZQ command */
 784         if (emc->zcal_long)
 785                 writel_relaxed(timing->emc_zcal_cnt_long,
 786                                emc->regs + EMC_ZCAL_WAIT_CNT);
 787
 788         /* wait for writes to settle */
 789         udelay(2);
 790
 791         /* update restored timing */
 792         err = emc_seq_update_timing(emc);
 793         if (!err)
 794                 emc->bad_state = false;
 795
 796         /* restore early ACK */
 797         mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE);
 798
 799         return err;
 800 }
 801
 802 static int emc_unprepare_timing_change(struct tegra_emc *emc,
 803                                        unsigned long rate)
 804 {
 805         if (!emc->bad_state) {
 806                 /* shouldn't ever happen in practice */
 807                 dev_err(emc->dev, "timing configuration can't be reverted\n");
 808                 emc->bad_state = true;
 809         }
 810
 811         return 0;
 812 }
 813
 814 static int emc_clk_change_notify(struct notifier_block *nb,
 815                                  unsigned long msg, void *data)
 816 {
 817         struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
 818         struct clk_notifier_data *cnd = data;
 819         int err;
 820
 821         switch (msg) {
 822         case PRE_RATE_CHANGE:
 823                 /*
 824                  * Disable interrupt since read accesses are prohibited after
 825                  * stalling.
 826                  */
 827                 disable_irq(emc->irq);
 828                 err = emc_prepare_timing_change(emc, cnd->new_rate);
 829                 enable_irq(emc->irq);
 830                 break;
 831
 832         case ABORT_RATE_CHANGE:
 833                 err = emc_unprepare_timing_change(emc, cnd->old_rate);
 834                 break;
 835
 836         case POST_RATE_CHANGE:
 837                 err = emc_complete_timing_change(emc, cnd->new_rate);
 838                 break;
 839
 840         default:
 841                 return NOTIFY_DONE;
 842         }
 843
 844         return notifier_from_errno(err);
 845 }
 846
 847 static int load_one_timing_from_dt(struct tegra_emc *emc,
 848                                    struct emc_timing *timing,
 849                                    struct device_node *node)
 850 {
 851         u32 value;
 852         int err;
 853
 854         err = of_property_read_u32(node, "clock-frequency", &value);
 855         if (err) {
 856                 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
 857                         node, err);
 858                 return err;
 859         }
 860
 861         timing->rate = value;
 862
 863         err = of_property_read_u32_array(node, "nvidia,emc-configuration",
 864                                          timing->data,
 865                                          ARRAY_SIZE(emc_timing_registers));
 866         if (err) {
 867                 dev_err(emc->dev,
 868                         "timing %pOF: failed to read emc timing data: %d\n",
 869                         node, err);
 870                 return err;
 871         }
 872
 873 #define EMC_READ_BOOL(prop, dtprop) \
 874         timing->prop = of_property_read_bool(node, dtprop);
 875
 876 #define EMC_READ_U32(prop, dtprop) \
 877         err = of_property_read_u32(node, dtprop, &timing->prop); \
 878         if (err) { \
 879                 dev_err(emc->dev, \
 880                         "timing %pOFn: failed to read " #prop ": %d\n", \
 881                         node, err); \
 882                 return err; \
 883         }
 884
 885         EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
 886         EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1")
 887         EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2")
 888         EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset")
 889         EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
 890         EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref")
 891         EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst")
 892
 893 #undef EMC_READ_U32
 894 #undef EMC_READ_BOOL
 895
 896         dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate);
 897
 898         return 0;
 899 }
 900
 901 static int cmp_timings(const void *_a, const void *_b)
 902 {
 903         const struct emc_timing *a = _a;
 904         const struct emc_timing *b = _b;
 905
 906         if (a->rate < b->rate)
 907                 return -1;
 908
 909         if (a->rate > b->rate)
 910                 return 1;
 911
 912         return 0;
 913 }
 914
 915 static int emc_check_mc_timings(struct tegra_emc *emc)
 916 {
 917         struct tegra_mc *mc = emc->mc;
 918         unsigned int i;
 919
 920         if (emc->num_timings != mc->num_timings) {
 921                 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n",
 922                         emc->num_timings, mc->num_timings);
 923                 return -EINVAL;
 924         }
 925
 926         for (i = 0; i < mc->num_timings; i++) {
 927                 if (emc->timings[i].rate != mc->timings[i].rate) {
 928                         dev_err(emc->dev,
 929                                 "emc/mc timing rate mismatch: %lu %lu\n",
 930                                 emc->timings[i].rate, mc->timings[i].rate);
 931                         return -EINVAL;
 932                 }
 933         }
 934
 935         return 0;
 936 }
 937
 938 static int emc_load_timings_from_dt(struct tegra_emc *emc,
 939                                     struct device_node *node)
 940 {
 941         struct device_node *child;
 942         struct emc_timing *timing;
 943         int child_count;
 944         int err;
 945
 946         child_count = of_get_child_count(node);
 947         if (!child_count) {
 948                 dev_err(emc->dev, "no memory timings in: %pOF\n", node);
 949                 return -EINVAL;
 950         }
 951
 952         emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
 953                                     GFP_KERNEL);
 954         if (!emc->timings)
 955                 return -ENOMEM;
 956
 957         emc->num_timings = child_count;
 958         timing = emc->timings;
 959
 960         for_each_child_of_node(node, child) {
 961                 err = load_one_timing_from_dt(emc, timing++, child);
 962                 if (err) {
 963                         of_node_put(child);
 964                         return err;
 965                 }
 966         }
 967
 968         sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
 969              NULL);
 970
 971         err = emc_check_mc_timings(emc);
 972         if (err)
 973                 return err;
 974
 975         dev_info(emc->dev,
 976                  "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
 977                  emc->num_timings,
 978                  tegra_read_ram_code(),
 979                  emc->timings[0].rate / 1000000,
 980                  emc->timings[emc->num_timings - 1].rate / 1000000);
 981
 982         return 0;
 983 }
 984
 985 static struct device_node *emc_find_node_by_ram_code(struct device *dev)
 986 {
 987         struct device_node *np;
 988         u32 value, ram_code;
 989         int err;
 990
 991         ram_code = tegra_read_ram_code();
 992
 993         for_each_child_of_node(dev->of_node, np) {
 994                 err = of_property_read_u32(np, "nvidia,ram-code", &value);
 995                 if (err || value != ram_code)
 996                         continue;
 997
 998                 return np;
 999         }
1000
1001         dev_err(dev, "no memory timings for RAM code %u found in device-tree\n",
1002                 ram_code);
1003
1004         return NULL;
1005 }
1006
1007 static int emc_setup_hw(struct tegra_emc *emc)
1008 {
1009         u32 intmask = EMC_REFRESH_OVERFLOW_INT;
1010         u32 fbio_cfg5, emc_cfg, emc_dbg;
1011         enum emc_dram_type dram_type;
1012
1013         fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
1014         dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK;
1015
1016         emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
1017
1018         /* enable EMC and CAR to handshake on PLL divider/source changes */
1019         emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
1020
1021         /* configure clock change mode accordingly to DRAM type */
1022         switch (dram_type) {
1023         case DRAM_TYPE_LPDDR2:
1024                 emc_cfg |= EMC_CLKCHANGE_PD_ENABLE;
1025                 emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;
1026                 break;
1027
1028         default:
1029                 emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;
1030                 emc_cfg &= ~EMC_CLKCHANGE_PD_ENABLE;
1031                 break;
1032         }
1033
1034         writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
1035
1036         /* initialize interrupt */
1037         writel_relaxed(intmask, emc->regs + EMC_INTMASK);
1038         writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS);
1039
1040         /* ensure that unwanted debug features are disabled */
1041         emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
1042         emc_dbg |= EMC_DBG_CFG_PRIORITY;
1043         emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
1044         emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
1045         emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
1046         writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
1047
1048         return 0;
1049 }
1050
1051 static long emc_round_rate(unsigned long rate,
1052                            unsigned long min_rate,
1053                            unsigned long max_rate,
1054                            void *arg)
1055 {
1056         struct emc_timing *timing = NULL;
1057         struct tegra_emc *emc = arg;
1058         unsigned int i;
1059
1060         min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
1061
1062         for (i = 0; i < emc->num_timings; i++) {
1063                 if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
1064                         continue;
1065
1066                 if (emc->timings[i].rate > max_rate) {
1067                         i = max(i, 1u) - 1;
1068
1069                         if (emc->timings[i].rate < min_rate)
1070                                 break;
1071                 }
1072
1073                 if (emc->timings[i].rate < min_rate)
1074                         continue;
1075
1076                 timing = &emc->timings[i];
1077                 break;
1078         }
1079
1080         if (!timing) {
1081                 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
1082                         rate, min_rate, max_rate);
1083                 return -EINVAL;
1084         }
1085
1086         return timing->rate;
1087 }
1088
1089 /*
1090  * debugfs interface
1091  *
1092  * The memory controller driver exposes some files in debugfs that can be used
1093  * to control the EMC frequency. The top-level directory can be found here:
1094  *
1095  *   /sys/kernel/debug/emc
1096  *
1097  * It contains the following files:
1098  *
1099  *   - available_rates: This file contains a list of valid, space-separated
1100  *     EMC frequencies.
1101  *
1102  *   - min_rate: Writing a value to this file sets the given frequency as the
1103  *       floor of the permitted range. If this is higher than the currently
1104  *       configured EMC frequency, this will cause the frequency to be
1105  *       increased so that it stays within the valid range.
1106  *
1107  *   - max_rate: Similarily to the min_rate file, writing a value to this file
1108  *       sets the given frequency as the ceiling of the permitted range. If
1109  *       the value is lower than the currently configured EMC frequency, this
1110  *       will cause the frequency to be decreased so that it stays within the
1111  *       valid range.
1112  */
1113
1114 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
1115 {
1116         unsigned int i;
1117
1118         for (i = 0; i < emc->num_timings; i++)
1119                 if (rate == emc->timings[i].rate)
1120                         return true;
1121
1122         return false;
1123 }
1124
1125 static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
1126 {
1127         struct tegra_emc *emc = s->private;
1128         const char *prefix = "";
1129         unsigned int i;
1130
1131         for (i = 0; i < emc->num_timings; i++) {
1132                 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
1133                 prefix = " ";
1134         }
1135
1136         seq_puts(s, "\n");
1137
1138         return 0;
1139 }
1140
1141 static int tegra_emc_debug_available_rates_open(struct inode *inode,
1142                                                 struct file *file)
1143 {
1144         return single_open(file, tegra_emc_debug_available_rates_show,
1145                            inode->i_private);
1146 }
1147
1148 static const struct file_operations tegra_emc_debug_available_rates_fops = {
1149         .open = tegra_emc_debug_available_rates_open,
1150         .read = seq_read,
1151         .llseek = seq_lseek,
1152         .release = single_release,
1153 };
1154
1155 static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
1156 {
1157         struct tegra_emc *emc = data;
1158
1159         *rate = emc->debugfs.min_rate;
1160
1161         return 0;
1162 }
1163
1164 static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
1165 {
1166         struct tegra_emc *emc = data;
1167         int err;
1168
1169         if (!tegra_emc_validate_rate(emc, rate))
1170                 return -EINVAL;
1171
1172         err = clk_set_min_rate(emc->clk, rate);
1173         if (err < 0)
1174                 return err;
1175
1176         emc->debugfs.min_rate = rate;
1177
1178         return 0;
1179 }
1180
1181 DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
1182                         tegra_emc_debug_min_rate_get,
1183                         tegra_emc_debug_min_rate_set, "%llu\n");
1184
1185 static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
1186 {
1187         struct tegra_emc *emc = data;
1188
1189         *rate = emc->debugfs.max_rate;
1190
1191         return 0;
1192 }
1193
1194 static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
1195 {
1196         struct tegra_emc *emc = data;
1197         int err;
1198
1199         if (!tegra_emc_validate_rate(emc, rate))
1200                 return -EINVAL;
1201
1202         err = clk_set_max_rate(emc->clk, rate);
1203         if (err < 0)
1204                 return err;
1205
1206         emc->debugfs.max_rate = rate;
1207
1208         return 0;
1209 }
1210
1211 DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
1212                         tegra_emc_debug_max_rate_get,
1213                         tegra_emc_debug_max_rate_set, "%llu\n");
1214
1215 static void tegra_emc_debugfs_init(struct tegra_emc *emc)
1216 {
1217         struct device *dev = emc->dev;
1218         unsigned int i;
1219         int err;
1220
1221         emc->debugfs.min_rate = ULONG_MAX;
1222         emc->debugfs.max_rate = 0;
1223
1224         for (i = 0; i < emc->num_timings; i++) {
1225                 if (emc->timings[i].rate < emc->debugfs.min_rate)
1226                         emc->debugfs.min_rate = emc->timings[i].rate;
1227
1228                 if (emc->timings[i].rate > emc->debugfs.max_rate)
1229                         emc->debugfs.max_rate = emc->timings[i].rate;
1230         }
1231
1232         if (!emc->num_timings) {
1233                 emc->debugfs.min_rate = clk_get_rate(emc->clk);
1234                 emc->debugfs.max_rate = emc->debugfs.min_rate;
1235         }
1236
1237         err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
1238                                  emc->debugfs.max_rate);
1239         if (err < 0) {
1240                 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
1241                         emc->debugfs.min_rate, emc->debugfs.max_rate,
1242                         emc->clk);
1243         }
1244
1245         emc->debugfs.root = debugfs_create_dir("emc", NULL);
1246         if (!emc->debugfs.root) {
1247                 dev_err(emc->dev, "failed to create debugfs directory\n");
1248                 return;
1249         }
1250
1251         debugfs_create_file("available_rates", 0444, emc->debugfs.root,
1252                             emc, &tegra_emc_debug_available_rates_fops);
1253         debugfs_create_file("min_rate", 0644, emc->debugfs.root,
1254                             emc, &tegra_emc_debug_min_rate_fops);
1255         debugfs_create_file("max_rate", 0644, emc->debugfs.root,
1256                             emc, &tegra_emc_debug_max_rate_fops);
1257 }
1258
1259 static int tegra_emc_probe(struct platform_device *pdev)
1260 {
1261         struct platform_device *mc;
1262         struct device_node *np;
1263         struct tegra_emc *emc;
1264         int err;
1265
1266         if (of_get_child_count(pdev->dev.of_node) == 0) {
1267                 dev_info(&pdev->dev,
1268                          "device-tree node doesn't have memory timings\n");
1269                 return -ENODEV;
1270         }
1271
1272         np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0);
1273         if (!np) {
1274                 dev_err(&pdev->dev, "could not get memory controller node\n");
1275                 return -ENOENT;
1276         }
1277
1278         mc = of_find_device_by_node(np);
1279         of_node_put(np);
1280         if (!mc)
1281                 return -ENOENT;
1282
1283         np = emc_find_node_by_ram_code(&pdev->dev);
1284         if (!np)
1285                 return -EINVAL;
1286
1287         emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1288         if (!emc) {
1289                 of_node_put(np);
1290                 return -ENOMEM;
1291         }
1292
1293         emc->mc = platform_get_drvdata(mc);
1294         if (!emc->mc)
1295                 return -EPROBE_DEFER;
1296
1297         emc->clk_nb.notifier_call = emc_clk_change_notify;
1298         emc->dev = &pdev->dev;
1299
1300         err = emc_load_timings_from_dt(emc, np);
1301         of_node_put(np);
1302         if (err)
1303                 return err;
1304
1305         emc->regs = devm_platform_ioremap_resource(pdev, 0);
1306         if (IS_ERR(emc->regs))
1307                 return PTR_ERR(emc->regs);
1308
1309         err = emc_setup_hw(emc);
1310         if (err)
1311                 return err;
1312
1313         err = platform_get_irq(pdev, 0);
1314         if (err < 0) {
1315                 dev_err(&pdev->dev, "interrupt not specified: %d\n", err);
1316                 return err;
1317         }
1318         emc->irq = err;
1319
1320         err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0,
1321                                dev_name(&pdev->dev), emc);
1322         if (err) {
1323                 dev_err(&pdev->dev, "failed to request irq: %d\n", err);
1324                 return err;
1325         }
1326
1327         tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
1328
1329         emc->clk = devm_clk_get(&pdev->dev, "emc");
1330         if (IS_ERR(emc->clk)) {
1331                 err = PTR_ERR(emc->clk);
1332                 dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
1333                 goto unset_cb;
1334         }
1335
1336         err = clk_notifier_register(emc->clk, &emc->clk_nb);
1337         if (err) {
1338                 dev_err(&pdev->dev, "failed to register clk notifier: %d\n",
1339                         err);
1340                 goto unset_cb;
1341         }
1342
1343         platform_set_drvdata(pdev, emc);
1344         tegra_emc_debugfs_init(emc);
1345
1346         return 0;
1347
1348 unset_cb:
1349         tegra20_clk_set_emc_round_callback(NULL, NULL);
1350
1351         return err;
1352 }
1353
1354 static int tegra_emc_suspend(struct device *dev)
1355 {
1356         struct tegra_emc *emc = dev_get_drvdata(dev);
1357         int err;
1358
1359         /* take exclusive control over the clock's rate */
1360         err = clk_rate_exclusive_get(emc->clk);
1361         if (err) {
1362                 dev_err(emc->dev, "failed to acquire clk: %d\n", err);
1363                 return err;
1364         }
1365
1366         /* suspending in a bad state will hang machine */
1367         if (WARN(emc->bad_state, "hardware in a bad state\n"))
1368                 return -EINVAL;
1369
1370         emc->bad_state = true;
1371
1372         return 0;
1373 }
1374
1375 static int tegra_emc_resume(struct device *dev)
1376 {
1377         struct tegra_emc *emc = dev_get_drvdata(dev);
1378
1379         emc_setup_hw(emc);
1380         emc->bad_state = false;
1381
1382         clk_rate_exclusive_put(emc->clk);
1383
1384         return 0;
1385 }
1386
1387 static const struct dev_pm_ops tegra_emc_pm_ops = {
1388         .suspend = tegra_emc_suspend,
1389         .resume = tegra_emc_resume,
1390 };
1391
1392 static const struct of_device_id tegra_emc_of_match[] = {
1393         { .compatible = "nvidia,tegra30-emc", },
1394         {},
1395 };
1396
1397 static struct platform_driver tegra_emc_driver = {
1398         .probe = tegra_emc_probe,
1399         .driver = {
1400                 .name = "tegra30-emc",
1401                 .of_match_table = tegra_emc_of_match,
1402                 .pm = &tegra_emc_pm_ops,
1403                 .suppress_bind_attrs = true,
1404         },
1405 };
1406
1407 static int __init tegra_emc_init(void)
1408 {
1409         return platform_driver_register(&tegra_emc_driver);
1410 }
1411 subsys_initcall(tegra_emc_init);