drivers/memory/tegra/tegra210.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <dt-bindings/memory/tegra210-mc.h>
   7
   8 #include "mc.h"
   9
  10 static const struct tegra_mc_client tegra210_mc_clients[] = {
  11         {
  12                 .id = 0x00,
  13                 .name = "ptcr",
  14                 .swgroup = TEGRA_SWGROUP_PTC,
  15         }, {
  16                 .id = 0x01,
  17                 .name = "display0a",
  18                 .swgroup = TEGRA_SWGROUP_DC,
  19                 .regs = {
  20                         .smmu = {
  21                                 .reg = 0x228,
  22                                 .bit = 1,
  23                         },
  24                         .la = {
  25                                 .reg = 0x2e8,
  26                                 .shift = 0,
  27                                 .mask = 0xff,
  28                                 .def = 0x1e,
  29                         },
  30                 },
  31         }, {
  32                 .id = 0x02,
  33                 .name = "display0ab",
  34                 .swgroup = TEGRA_SWGROUP_DCB,
  35                 .regs = {
  36                         .smmu = {
  37                                 .reg = 0x228,
  38                                 .bit = 2,
  39                         },
  40                         .la = {
  41                                 .reg = 0x2f4,
  42                                 .shift = 0,
  43                                 .mask = 0xff,
  44                                 .def = 0x1e,
  45                         },
  46                 },
  47         }, {
  48                 .id = 0x03,
  49                 .name = "display0b",
  50                 .swgroup = TEGRA_SWGROUP_DC,
  51                 .regs = {
  52                         .smmu = {
  53                                 .reg = 0x228,
  54                                 .bit = 3,
  55                         },
  56                         .la = {
  57                                 .reg = 0x2e8,
  58                                 .shift = 16,
  59                                 .mask = 0xff,
  60                                 .def = 0x1e,
  61                         },
  62                 },
  63         }, {
  64                 .id = 0x04,
  65                 .name = "display0bb",
  66                 .swgroup = TEGRA_SWGROUP_DCB,
  67                 .regs = {
  68                         .smmu = {
  69                                 .reg = 0x228,
  70                                 .bit = 4,
  71                         },
  72                         .la = {
  73                                 .reg = 0x2f4,
  74                                 .shift = 16,
  75                                 .mask = 0xff,
  76                                 .def = 0x1e,
  77                         },
  78                 },
  79         }, {
  80                 .id = 0x05,
  81                 .name = "display0c",
  82                 .swgroup = TEGRA_SWGROUP_DC,
  83                 .regs = {
  84                         .smmu = {
  85                                 .reg = 0x228,
  86                                 .bit = 5,
  87                         },
  88                         .la = {
  89                                 .reg = 0x2ec,
  90                                 .shift = 0,
  91                                 .mask = 0xff,
  92                                 .def = 0x1e,
  93                         },
  94                 },
  95         }, {
  96                 .id = 0x06,
  97                 .name = "display0cb",
  98                 .swgroup = TEGRA_SWGROUP_DCB,
  99                 .regs = {
 100                         .smmu = {
 101                                 .reg = 0x228,
 102                                 .bit = 6,
 103                         },
 104                         .la = {
 105                                 .reg = 0x2f8,
 106                                 .shift = 0,
 107                                 .mask = 0xff,
 108                                 .def = 0x1e,
 109                         },
 110                 },
 111         }, {
 112                 .id = 0x0e,
 113                 .name = "afir",
 114                 .swgroup = TEGRA_SWGROUP_AFI,
 115                 .regs = {
 116                         .smmu = {
 117                                 .reg = 0x228,
 118                                 .bit = 14,
 119                         },
 120                         .la = {
 121                                 .reg = 0x2e0,
 122                                 .shift = 0,
 123                                 .mask = 0xff,
 124                                 .def = 0x2e,
 125                         },
 126                 },
 127         }, {
 128                 .id = 0x0f,
 129                 .name = "avpcarm7r",
 130                 .swgroup = TEGRA_SWGROUP_AVPC,
 131                 .regs = {
 132                         .smmu = {
 133                                 .reg = 0x228,
 134                                 .bit = 15,
 135                         },
 136                         .la = {
 137                                 .reg = 0x2e4,
 138                                 .shift = 0,
 139                                 .mask = 0xff,
 140                                 .def = 0x04,
 141                         },
 142                 },
 143         }, {
 144                 .id = 0x10,
 145                 .name = "displayhc",
 146                 .swgroup = TEGRA_SWGROUP_DC,
 147                 .regs = {
 148                         .smmu = {
 149                                 .reg = 0x228,
 150                                 .bit = 16,
 151                         },
 152                         .la = {
 153                                 .reg = 0x2f0,
 154                                 .shift = 0,
 155                                 .mask = 0xff,
 156                                 .def = 0x1e,
 157                         },
 158                 },
 159         }, {
 160                 .id = 0x11,
 161                 .name = "displayhcb",
 162                 .swgroup = TEGRA_SWGROUP_DCB,
 163                 .regs = {
 164                         .smmu = {
 165                                 .reg = 0x228,
 166                                 .bit = 17,
 167                         },
 168                         .la = {
 169                                 .reg = 0x2fc,
 170                                 .shift = 0,
 171                                 .mask = 0xff,
 172                                 .def = 0x1e,
 173                         },
 174                 },
 175         }, {
 176                 .id = 0x15,
 177                 .name = "hdar",
 178                 .swgroup = TEGRA_SWGROUP_HDA,
 179                 .regs = {
 180                         .smmu = {
 181                                 .reg = 0x228,
 182                                 .bit = 21,
 183                         },
 184                         .la = {
 185                                 .reg = 0x318,
 186                                 .shift = 0,
 187                                 .mask = 0xff,
 188                                 .def = 0x24,
 189                         },
 190                 },
 191         }, {
 192                 .id = 0x16,
 193                 .name = "host1xdmar",
 194                 .swgroup = TEGRA_SWGROUP_HC,
 195                 .regs = {
 196                         .smmu = {
 197                                 .reg = 0x228,
 198                                 .bit = 22,
 199                         },
 200                         .la = {
 201                                 .reg = 0x310,
 202                                 .shift = 0,
 203                                 .mask = 0xff,
 204                                 .def = 0x1e,
 205                         },
 206                 },
 207         }, {
 208                 .id = 0x17,
 209                 .name = "host1xr",
 210                 .swgroup = TEGRA_SWGROUP_HC,
 211                 .regs = {
 212                         .smmu = {
 213                                 .reg = 0x228,
 214                                 .bit = 23,
 215                         },
 216                         .la = {
 217                                 .reg = 0x310,
 218                                 .shift = 16,
 219                                 .mask = 0xff,
 220                                 .def = 0x50,
 221                         },
 222                 },
 223         }, {
 224                 .id = 0x1c,
 225                 .name = "nvencsrd",
 226                 .swgroup = TEGRA_SWGROUP_NVENC,
 227                 .regs = {
 228                         .smmu = {
 229                                 .reg = 0x228,
 230                                 .bit = 28,
 231                         },
 232                         .la = {
 233                                 .reg = 0x328,
 234                                 .shift = 0,
 235                                 .mask = 0xff,
 236                                 .def = 0x23,
 237                         },
 238                 },
 239         }, {
 240                 .id = 0x1d,
 241                 .name = "ppcsahbdmar",
 242                 .swgroup = TEGRA_SWGROUP_PPCS,
 243                 .regs = {
 244                         .smmu = {
 245                                 .reg = 0x228,
 246                                 .bit = 29,
 247                         },
 248                         .la = {
 249                                 .reg = 0x344,
 250                                 .shift = 0,
 251                                 .mask = 0xff,
 252                                 .def = 0x49,
 253                         },
 254                 },
 255         }, {
 256                 .id = 0x1e,
 257                 .name = "ppcsahbslvr",
 258                 .swgroup = TEGRA_SWGROUP_PPCS,
 259                 .regs = {
 260                         .smmu = {
 261                                 .reg = 0x228,
 262                                 .bit = 30,
 263                         },
 264                         .la = {
 265                                 .reg = 0x344,
 266                                 .shift = 16,
 267                                 .mask = 0xff,
 268                                 .def = 0x1a,
 269                         },
 270                 },
 271         }, {
 272                 .id = 0x1f,
 273                 .name = "satar",
 274                 .swgroup = TEGRA_SWGROUP_SATA,
 275                 .regs = {
 276                         .smmu = {
 277                                 .reg = 0x228,
 278                                 .bit = 31,
 279                         },
 280                         .la = {
 281                                 .reg = 0x350,
 282                                 .shift = 0,
 283                                 .mask = 0xff,
 284                                 .def = 0x65,
 285                         },
 286                 },
 287         }, {
 288                 .id = 0x27,
 289                 .name = "mpcorer",
 290                 .swgroup = TEGRA_SWGROUP_MPCORE,
 291                 .regs = {
 292                         .la = {
 293                                 .reg = 0x320,
 294                                 .shift = 0,
 295                                 .mask = 0xff,
 296                                 .def = 0x04,
 297                         },
 298                 },
 299         }, {
 300                 .id = 0x2b,
 301                 .name = "nvencswr",
 302                 .swgroup = TEGRA_SWGROUP_NVENC,
 303                 .regs = {
 304                         .smmu = {
 305                                 .reg = 0x22c,
 306                                 .bit = 11,
 307                         },
 308                         .la = {
 309                                 .reg = 0x328,
 310                                 .shift = 16,
 311                                 .mask = 0xff,
 312                                 .def = 0x80,
 313                         },
 314                 },
 315         }, {
 316                 .id = 0x31,
 317                 .name = "afiw",
 318                 .swgroup = TEGRA_SWGROUP_AFI,
 319                 .regs = {
 320                         .smmu = {
 321                                 .reg = 0x22c,
 322                                 .bit = 17,
 323                         },
 324                         .la = {
 325                                 .reg = 0x2e0,
 326                                 .shift = 16,
 327                                 .mask = 0xff,
 328                                 .def = 0x80,
 329                         },
 330                 },
 331         }, {
 332                 .id = 0x32,
 333                 .name = "avpcarm7w",
 334                 .swgroup = TEGRA_SWGROUP_AVPC,
 335                 .regs = {
 336                         .smmu = {
 337                                 .reg = 0x22c,
 338                                 .bit = 18,
 339                         },
 340                         .la = {
 341                                 .reg = 0x2e4,
 342                                 .shift = 16,
 343                                 .mask = 0xff,
 344                                 .def = 0x80,
 345                         },
 346                 },
 347         }, {
 348                 .id = 0x35,
 349                 .name = "hdaw",
 350                 .swgroup = TEGRA_SWGROUP_HDA,
 351                 .regs = {
 352                         .smmu = {
 353                                 .reg = 0x22c,
 354                                 .bit = 21,
 355                         },
 356                         .la = {
 357                                 .reg = 0x318,
 358                                 .shift = 16,
 359                                 .mask = 0xff,
 360                                 .def = 0x80,
 361                         },
 362                 },
 363         }, {
 364                 .id = 0x36,
 365                 .name = "host1xw",
 366                 .swgroup = TEGRA_SWGROUP_HC,
 367                 .regs = {
 368                         .smmu = {
 369                                 .reg = 0x22c,
 370                                 .bit = 22,
 371                         },
 372                         .la = {
 373                                 .reg = 0x314,
 374                                 .shift = 0,
 375                                 .mask = 0xff,
 376                                 .def = 0x80,
 377                         },
 378                 },
 379         }, {
 380                 .id = 0x39,
 381                 .name = "mpcorew",
 382                 .swgroup = TEGRA_SWGROUP_MPCORE,
 383                 .regs = {
 384                         .la = {
 385                                 .reg = 0x320,
 386                                 .shift = 16,
 387                                 .mask = 0xff,
 388                                 .def = 0x80,
 389                         },
 390                 },
 391         }, {
 392                 .id = 0x3b,
 393                 .name = "ppcsahbdmaw",
 394                 .swgroup = TEGRA_SWGROUP_PPCS,
 395                 .regs = {
 396                         .smmu = {
 397                                 .reg = 0x22c,
 398                                 .bit = 27,
 399                         },
 400                         .la = {
 401                                 .reg = 0x348,
 402                                 .shift = 0,
 403                                 .mask = 0xff,
 404                                 .def = 0x80,
 405                         },
 406                 },
 407         }, {
 408                 .id = 0x3c,
 409                 .name = "ppcsahbslvw",
 410                 .swgroup = TEGRA_SWGROUP_PPCS,
 411                 .regs = {
 412                         .smmu = {
 413                                 .reg = 0x22c,
 414                                 .bit = 28,
 415                         },
 416                         .la = {
 417                                 .reg = 0x348,
 418                                 .shift = 16,
 419                                 .mask = 0xff,
 420                                 .def = 0x80,
 421                         },
 422                 },
 423         }, {
 424                 .id = 0x3d,
 425                 .name = "sataw",
 426                 .swgroup = TEGRA_SWGROUP_SATA,
 427                 .regs = {
 428                         .smmu = {
 429                                 .reg = 0x22c,
 430                                 .bit = 29,
 431                         },
 432                         .la = {
 433                                 .reg = 0x350,
 434                                 .shift = 16,
 435                                 .mask = 0xff,
 436                                 .def = 0x80,
 437                         },
 438                 },
 439         }, {
 440                 .id = 0x44,
 441                 .name = "ispra",
 442                 .swgroup = TEGRA_SWGROUP_ISP2,
 443                 .regs = {
 444                         .smmu = {
 445                                 .reg = 0x230,
 446                                 .bit = 4,
 447                         },
 448                         .la = {
 449                                 .reg = 0x370,
 450                                 .shift = 0,
 451                                 .mask = 0xff,
 452                                 .def = 0x18,
 453                         },
 454                 },
 455         }, {
 456                 .id = 0x46,
 457                 .name = "ispwa",
 458                 .swgroup = TEGRA_SWGROUP_ISP2,
 459                 .regs = {
 460                         .smmu = {
 461                                 .reg = 0x230,
 462                                 .bit = 6,
 463                         },
 464                         .la = {
 465                                 .reg = 0x374,
 466                                 .shift = 0,
 467                                 .mask = 0xff,
 468                                 .def = 0x80,
 469                         },
 470                 },
 471         }, {
 472                 .id = 0x47,
 473                 .name = "ispwb",
 474                 .swgroup = TEGRA_SWGROUP_ISP2,
 475                 .regs = {
 476                         .smmu = {
 477                                 .reg = 0x230,
 478                                 .bit = 7,
 479                         },
 480                         .la = {
 481                                 .reg = 0x374,
 482                                 .shift = 16,
 483                                 .mask = 0xff,
 484                                 .def = 0x80,
 485                         },
 486                 },
 487         }, {
 488                 .id = 0x4a,
 489                 .name = "xusb_hostr",
 490                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 491                 .regs = {
 492                         .smmu = {
 493                                 .reg = 0x230,
 494                                 .bit = 10,
 495                         },
 496                         .la = {
 497                                 .reg = 0x37c,
 498                                 .shift = 0,
 499                                 .mask = 0xff,
 500                                 .def = 0x7a,
 501                         },
 502                 },
 503         }, {
 504                 .id = 0x4b,
 505                 .name = "xusb_hostw",
 506                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 507                 .regs = {
 508                         .smmu = {
 509                                 .reg = 0x230,
 510                                 .bit = 11,
 511                         },
 512                         .la = {
 513                                 .reg = 0x37c,
 514                                 .shift = 16,
 515                                 .mask = 0xff,
 516                                 .def = 0x80,
 517                         },
 518                 },
 519         }, {
 520                 .id = 0x4c,
 521                 .name = "xusb_devr",
 522                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 523                 .regs = {
 524                         .smmu = {
 525                                 .reg = 0x230,
 526                                 .bit = 12,
 527                         },
 528                         .la = {
 529                                 .reg = 0x380,
 530                                 .shift = 0,
 531                                 .mask = 0xff,
 532                                 .def = 0x39,
 533                         },
 534                 },
 535         }, {
 536                 .id = 0x4d,
 537                 .name = "xusb_devw",
 538                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 539                 .regs = {
 540                         .smmu = {
 541                                 .reg = 0x230,
 542                                 .bit = 13,
 543                         },
 544                         .la = {
 545                                 .reg = 0x380,
 546                                 .shift = 16,
 547                                 .mask = 0xff,
 548                                 .def = 0x80,
 549                         },
 550                 },
 551         }, {
 552                 .id = 0x4e,
 553                 .name = "isprab",
 554                 .swgroup = TEGRA_SWGROUP_ISP2B,
 555                 .regs = {
 556                         .smmu = {
 557                                 .reg = 0x230,
 558                                 .bit = 14,
 559                         },
 560                         .la = {
 561                                 .reg = 0x384,
 562                                 .shift = 0,
 563                                 .mask = 0xff,
 564                                 .def = 0x18,
 565                         },
 566                 },
 567         }, {
 568                 .id = 0x50,
 569                 .name = "ispwab",
 570                 .swgroup = TEGRA_SWGROUP_ISP2B,
 571                 .regs = {
 572                         .smmu = {
 573                                 .reg = 0x230,
 574                                 .bit = 16,
 575                         },
 576                         .la = {
 577                                 .reg = 0x388,
 578                                 .shift = 0,
 579                                 .mask = 0xff,
 580                                 .def = 0x80,
 581                         },
 582                 },
 583         }, {
 584                 .id = 0x51,
 585                 .name = "ispwbb",
 586                 .swgroup = TEGRA_SWGROUP_ISP2B,
 587                 .regs = {
 588                         .smmu = {
 589                                 .reg = 0x230,
 590                                 .bit = 17,
 591                         },
 592                         .la = {
 593                                 .reg = 0x388,
 594                                 .shift = 16,
 595                                 .mask = 0xff,
 596                                 .def = 0x80,
 597                         },
 598                 },
 599         }, {
 600                 .id = 0x54,
 601                 .name = "tsecsrd",
 602                 .swgroup = TEGRA_SWGROUP_TSEC,
 603                 .regs = {
 604                         .smmu = {
 605                                 .reg = 0x230,
 606                                 .bit = 20,
 607                         },
 608                         .la = {
 609                                 .reg = 0x390,
 610                                 .shift = 0,
 611                                 .mask = 0xff,
 612                                 .def = 0x9b,
 613                         },
 614                 },
 615         }, {
 616                 .id = 0x55,
 617                 .name = "tsecswr",
 618                 .swgroup = TEGRA_SWGROUP_TSEC,
 619                 .regs = {
 620                         .smmu = {
 621                                 .reg = 0x230,
 622                                 .bit = 21,
 623                         },
 624                         .la = {
 625                                 .reg = 0x390,
 626                                 .shift = 16,
 627                                 .mask = 0xff,
 628                                 .def = 0x80,
 629                         },
 630                 },
 631         }, {
 632                 .id = 0x56,
 633                 .name = "a9avpscr",
 634                 .swgroup = TEGRA_SWGROUP_A9AVP,
 635                 .regs = {
 636                         .smmu = {
 637                                 .reg = 0x230,
 638                                 .bit = 22,
 639                         },
 640                         .la = {
 641                                 .reg = 0x3a4,
 642                                 .shift = 0,
 643                                 .mask = 0xff,
 644                                 .def = 0x04,
 645                         },
 646                 },
 647         }, {
 648                 .id = 0x57,
 649                 .name = "a9avpscw",
 650                 .swgroup = TEGRA_SWGROUP_A9AVP,
 651                 .regs = {
 652                         .smmu = {
 653                                 .reg = 0x230,
 654                                 .bit = 23,
 655                         },
 656                         .la = {
 657                                 .reg = 0x3a4,
 658                                 .shift = 16,
 659                                 .mask = 0xff,
 660                                 .def = 0x80,
 661                         },
 662                 },
 663         }, {
 664                 .id = 0x58,
 665                 .name = "gpusrd",
 666                 .swgroup = TEGRA_SWGROUP_GPU,
 667                 .regs = {
 668                         .smmu = {
 669                                 /* read-only */
 670                                 .reg = 0x230,
 671                                 .bit = 24,
 672                         },
 673                         .la = {
 674                                 .reg = 0x3c8,
 675                                 .shift = 0,
 676                                 .mask = 0xff,
 677                                 .def = 0x1a,
 678                         },
 679                 },
 680         }, {
 681                 .id = 0x59,
 682                 .name = "gpuswr",
 683                 .swgroup = TEGRA_SWGROUP_GPU,
 684                 .regs = {
 685                         .smmu = {
 686                                 /* read-only */
 687                                 .reg = 0x230,
 688                                 .bit = 25,
 689                         },
 690                         .la = {
 691                                 .reg = 0x3c8,
 692                                 .shift = 16,
 693                                 .mask = 0xff,
 694                                 .def = 0x80,
 695                         },
 696                 },
 697         }, {
 698                 .id = 0x5a,
 699                 .name = "displayt",
 700                 .swgroup = TEGRA_SWGROUP_DC,
 701                 .regs = {
 702                         .smmu = {
 703                                 .reg = 0x230,
 704                                 .bit = 26,
 705                         },
 706                         .la = {
 707                                 .reg = 0x2f0,
 708                                 .shift = 16,
 709                                 .mask = 0xff,
 710                                 .def = 0x1e,
 711                         },
 712                 },
 713         }, {
 714                 .id = 0x60,
 715                 .name = "sdmmcra",
 716                 .swgroup = TEGRA_SWGROUP_SDMMC1A,
 717                 .regs = {
 718                         .smmu = {
 719                                 .reg = 0x234,
 720                                 .bit = 0,
 721                         },
 722                         .la = {
 723                                 .reg = 0x3b8,
 724                                 .shift = 0,
 725                                 .mask = 0xff,
 726                                 .def = 0x49,
 727                         },
 728                 },
 729         }, {
 730                 .id = 0x61,
 731                 .name = "sdmmcraa",
 732                 .swgroup = TEGRA_SWGROUP_SDMMC2A,
 733                 .regs = {
 734                         .smmu = {
 735                                 .reg = 0x234,
 736                                 .bit = 1,
 737                         },
 738                         .la = {
 739                                 .reg = 0x3bc,
 740                                 .shift = 0,
 741                                 .mask = 0xff,
 742                                 .def = 0x5a,
 743                         },
 744                 },
 745         }, {
 746                 .id = 0x62,
 747                 .name = "sdmmcr",
 748                 .swgroup = TEGRA_SWGROUP_SDMMC3A,
 749                 .regs = {
 750                         .smmu = {
 751                                 .reg = 0x234,
 752                                 .bit = 2,
 753                         },
 754                         .la = {
 755                                 .reg = 0x3c0,
 756                                 .shift = 0,
 757                                 .mask = 0xff,
 758                                 .def = 0x49,
 759                         },
 760                 },
 761         }, {
 762                 .id = 0x63,
 763                 .swgroup = TEGRA_SWGROUP_SDMMC4A,
 764                 .name = "sdmmcrab",
 765                 .regs = {
 766                         .smmu = {
 767                                 .reg = 0x234,
 768                                 .bit = 3,
 769                         },
 770                         .la = {
 771                                 .reg = 0x3c4,
 772                                 .shift = 0,
 773                                 .mask = 0xff,
 774                                 .def = 0x5a,
 775                         },
 776                 },
 777         }, {
 778                 .id = 0x64,
 779                 .name = "sdmmcwa",
 780                 .swgroup = TEGRA_SWGROUP_SDMMC1A,
 781                 .regs = {
 782                         .smmu = {
 783                                 .reg = 0x234,
 784                                 .bit = 4,
 785                         },
 786                         .la = {
 787                                 .reg = 0x3b8,
 788                                 .shift = 16,
 789                                 .mask = 0xff,
 790                                 .def = 0x80,
 791                         },
 792                 },
 793         }, {
 794                 .id = 0x65,
 795                 .name = "sdmmcwaa",
 796                 .swgroup = TEGRA_SWGROUP_SDMMC2A,
 797                 .regs = {
 798                         .smmu = {
 799                                 .reg = 0x234,
 800                                 .bit = 5,
 801                         },
 802                         .la = {
 803                                 .reg = 0x3bc,
 804                                 .shift = 16,
 805                                 .mask = 0xff,
 806                                 .def = 0x80,
 807                         },
 808                 },
 809         }, {
 810                 .id = 0x66,
 811                 .name = "sdmmcw",
 812                 .swgroup = TEGRA_SWGROUP_SDMMC3A,
 813                 .regs = {
 814                         .smmu = {
 815                                 .reg = 0x234,
 816                                 .bit = 6,
 817                         },
 818                         .la = {
 819                                 .reg = 0x3c0,
 820                                 .shift = 16,
 821                                 .mask = 0xff,
 822                                 .def = 0x80,
 823                         },
 824                 },
 825         }, {
 826                 .id = 0x67,
 827                 .name = "sdmmcwab",
 828                 .swgroup = TEGRA_SWGROUP_SDMMC4A,
 829                 .regs = {
 830                         .smmu = {
 831                                 .reg = 0x234,
 832                                 .bit = 7,
 833                         },
 834                         .la = {
 835                                 .reg = 0x3c4,
 836                                 .shift = 16,
 837                                 .mask = 0xff,
 838                                 .def = 0x80,
 839                         },
 840                 },
 841         }, {
 842                 .id = 0x6c,
 843                 .name = "vicsrd",
 844                 .swgroup = TEGRA_SWGROUP_VIC,
 845                 .regs = {
 846                         .smmu = {
 847                                 .reg = 0x234,
 848                                 .bit = 12,
 849                         },
 850                         .la = {
 851                                 .reg = 0x394,
 852                                 .shift = 0,
 853                                 .mask = 0xff,
 854                                 .def = 0x1a,
 855                         },
 856                 },
 857         }, {
 858                 .id = 0x6d,
 859                 .name = "vicswr",
 860                 .swgroup = TEGRA_SWGROUP_VIC,
 861                 .regs = {
 862                         .smmu = {
 863                                 .reg = 0x234,
 864                                 .bit = 13,
 865                         },
 866                         .la = {
 867                                 .reg = 0x394,
 868                                 .shift = 16,
 869                                 .mask = 0xff,
 870                                 .def = 0x80,
 871                         },
 872                 },
 873         }, {
 874                 .id = 0x72,
 875                 .name = "viw",
 876                 .swgroup = TEGRA_SWGROUP_VI,
 877                 .regs = {
 878                         .smmu = {
 879                                 .reg = 0x234,
 880                                 .bit = 18,
 881                         },
 882                         .la = {
 883                                 .reg = 0x398,
 884                                 .shift = 0,
 885                                 .mask = 0xff,
 886                                 .def = 0x80,
 887                         },
 888                 },
 889         }, {
 890                 .id = 0x73,
 891                 .name = "displayd",
 892                 .swgroup = TEGRA_SWGROUP_DC,
 893                 .regs = {
 894                         .smmu = {
 895                                 .reg = 0x234,
 896                                 .bit = 19,
 897                         },
 898                         .la = {
 899                                 .reg = 0x3c8,
 900                                 .shift = 0,
 901                                 .mask = 0xff,
 902                                 .def = 0x50,
 903                         },
 904                 },
 905         }, {
 906                 .id = 0x78,
 907                 .name = "nvdecsrd",
 908                 .swgroup = TEGRA_SWGROUP_NVDEC,
 909                 .regs = {
 910                         .smmu = {
 911                                 .reg = 0x234,
 912                                 .bit = 24,
 913                         },
 914                         .la = {
 915                                 .reg = 0x3d8,
 916                                 .shift = 0,
 917                                 .mask = 0xff,
 918                                 .def = 0x23,
 919                         },
 920                 },
 921         }, {
 922                 .id = 0x79,
 923                 .name = "nvdecswr",
 924                 .swgroup = TEGRA_SWGROUP_NVDEC,
 925                 .regs = {
 926                         .smmu = {
 927                                 .reg = 0x234,
 928                                 .bit = 25,
 929                         },
 930                         .la = {
 931                                 .reg = 0x3d8,
 932                                 .shift = 16,
 933                                 .mask = 0xff,
 934                                 .def = 0x80,
 935                         },
 936                 },
 937         }, {
 938                 .id = 0x7a,
 939                 .name = "aper",
 940                 .swgroup = TEGRA_SWGROUP_APE,
 941                 .regs = {
 942                         .smmu = {
 943                                 .reg = 0x234,
 944                                 .bit = 26,
 945                         },
 946                         .la = {
 947                                 .reg = 0x3dc,
 948                                 .shift = 0,
 949                                 .mask = 0xff,
 950                                 .def = 0xff,
 951                         },
 952                 },
 953         }, {
 954                 .id = 0x7b,
 955                 .name = "apew",
 956                 .swgroup = TEGRA_SWGROUP_APE,
 957                 .regs = {
 958                         .smmu = {
 959                                 .reg = 0x234,
 960                                 .bit = 27,
 961                         },
 962                         .la = {
 963                                 .reg = 0x3dc,
 964                                 .shift = 16,
 965                                 .mask = 0xff,
 966                                 .def = 0x80,
 967                         },
 968                 },
 969         }, {
 970                 .id = 0x7e,
 971                 .name = "nvjpgsrd",
 972                 .swgroup = TEGRA_SWGROUP_NVJPG,
 973                 .regs = {
 974                         .smmu = {
 975                                 .reg = 0x234,
 976                                 .bit = 30,
 977                         },
 978                         .la = {
 979                                 .reg = 0x3e4,
 980                                 .shift = 0,
 981                                 .mask = 0xff,
 982                                 .def = 0x23,
 983                         },
 984                 },
 985         }, {
 986                 .id = 0x7f,
 987                 .name = "nvjpgswr",
 988                 .swgroup = TEGRA_SWGROUP_NVJPG,
 989                 .regs = {
 990                         .smmu = {
 991                                 .reg = 0x234,
 992                                 .bit = 31,
 993                         },
 994                         .la = {
 995                                 .reg = 0x3e4,
 996                                 .shift = 16,
 997                                 .mask = 0xff,
 998                                 .def = 0x80,
 999                         },
1000                 },
1001         }, {
1002                 .id = 0x80,
1003                 .name = "sesrd",
1004                 .swgroup = TEGRA_SWGROUP_SE,
1005                 .regs = {
1006                         .smmu = {
1007                                 .reg = 0xb98,
1008                                 .bit = 0,
1009                         },
1010                         .la = {
1011                                 .reg = 0x3e0,
1012                                 .shift = 0,
1013                                 .mask = 0xff,
1014                                 .def = 0x2e,
1015                         },
1016                 },
1017         }, {
1018                 .id = 0x81,
1019                 .name = "seswr",
1020                 .swgroup = TEGRA_SWGROUP_SE,
1021                 .regs = {
1022                         .smmu = {
1023                                 .reg = 0xb98,
1024                                 .bit = 1,
1025                         },
1026                         .la = {
1027                                 .reg = 0x3e0,
1028                                 .shift = 16,
1029                                 .mask = 0xff,
1030                                 .def = 0x80,
1031                         },
1032                 },
1033         }, {
1034                 .id = 0x82,
1035                 .name = "axiapr",
1036                 .swgroup = TEGRA_SWGROUP_AXIAP,
1037                 .regs = {
1038                         .smmu = {
1039                                 .reg = 0xb98,
1040                                 .bit = 2,
1041                         },
1042                         .la = {
1043                                 .reg = 0x3a0,
1044                                 .shift = 0,
1045                                 .mask = 0xff,
1046                                 .def = 0xff,
1047                         },
1048                 },
1049         }, {
1050                 .id = 0x83,
1051                 .name = "axiapw",
1052                 .swgroup = TEGRA_SWGROUP_AXIAP,
1053                 .regs = {
1054                         .smmu = {
1055                                 .reg = 0xb98,
1056                                 .bit = 3,
1057                         },
1058                         .la = {
1059                                 .reg = 0x3a0,
1060                                 .shift = 16,
1061                                 .mask = 0xff,
1062                                 .def = 0x80,
1063                         },
1064                 },
1065         }, {
1066                 .id = 0x84,
1067                 .name = "etrr",
1068                 .swgroup = TEGRA_SWGROUP_ETR,
1069                 .regs = {
1070                         .smmu = {
1071                                 .reg = 0xb98,
1072                                 .bit = 4,
1073                         },
1074                         .la = {
1075                                 .reg = 0x3ec,
1076                                 .shift = 0,
1077                                 .mask = 0xff,
1078                                 .def = 0xff,
1079                         },
1080                 },
1081         }, {
1082                 .id = 0x85,
1083                 .name = "etrw",
1084                 .swgroup = TEGRA_SWGROUP_ETR,
1085                 .regs = {
1086                         .smmu = {
1087                                 .reg = 0xb98,
1088                                 .bit = 5,
1089                         },
1090                         .la = {
1091                                 .reg = 0x3ec,
1092                                 .shift = 16,
1093                                 .mask = 0xff,
1094                                 .def = 0x80,
1095                         },
1096                 },
1097         }, {
1098                 .id = 0x86,
1099                 .name = "tsecsrdb",
1100                 .swgroup = TEGRA_SWGROUP_TSECB,
1101                 .regs = {
1102                         .smmu = {
1103                                 .reg = 0xb98,
1104                                 .bit = 6,
1105                         },
1106                         .la = {
1107                                 .reg = 0x3f0,
1108                                 .shift = 0,
1109                                 .mask = 0xff,
1110                                 .def = 0x9b,
1111                         },
1112                 },
1113         }, {
1114                 .id = 0x87,
1115                 .name = "tsecswrb",
1116                 .swgroup = TEGRA_SWGROUP_TSECB,
1117                 .regs = {
1118                         .smmu = {
1119                                 .reg = 0xb98,
1120                                 .bit = 7,
1121                         },
1122                         .la = {
1123                                 .reg = 0x3f0,
1124                                 .shift = 16,
1125                                 .mask = 0xff,
1126                                 .def = 0x80,
1127                         },
1128                 },
1129         }, {
1130                 .id = 0x88,
1131                 .name = "gpusrd2",
1132                 .swgroup = TEGRA_SWGROUP_GPU,
1133                 .regs = {
1134                         .smmu = {
1135                                 /* read-only */
1136                                 .reg = 0xb98,
1137                                 .bit = 8,
1138                         },
1139                         .la = {
1140                                 .reg = 0x3e8,
1141                                 .shift = 0,
1142                                 .mask = 0xff,
1143                                 .def = 0x1a,
1144                         },
1145                 },
1146         }, {
1147                 .id = 0x89,
1148                 .name = "gpuswr2",
1149                 .swgroup = TEGRA_SWGROUP_GPU,
1150                 .regs = {
1151                         .smmu = {
1152                                 /* read-only */
1153                                 .reg = 0xb98,
1154                                 .bit = 9,
1155                         },
1156                         .la = {
1157                                 .reg = 0x3e8,
1158                                 .shift = 16,
1159                                 .mask = 0xff,
1160                                 .def = 0x80,
1161                         },
1162                 },
1163         },
1164 };
1165
1166 static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
1167         { .name = "afi",       .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },
1168         { .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
1169         { .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
1170         { .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
1171         { .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
1172         { .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
1173         { .name = "isp2",      .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },
1174         { .name = "nvenc",     .swgroup = TEGRA_SWGROUP_NVENC,     .reg = 0x264 },
1175         { .name = "nv",        .swgroup = TEGRA_SWGROUP_NV,        .reg = 0x268 },
1176         { .name = "nv2",       .swgroup = TEGRA_SWGROUP_NV2,       .reg = 0x26c },
1177         { .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
1178         { .name = "sata",      .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },
1179         { .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
1180         { .name = "vic",       .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },
1181         { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1182         { .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
1183         { .name = "a9avp",     .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },
1184         { .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
1185         { .name = "ppcs1",     .swgroup = TEGRA_SWGROUP_PPCS1,     .reg = 0x298 },
1186         { .name = "dc1",       .swgroup = TEGRA_SWGROUP_DC1,       .reg = 0xa88 },
1187         { .name = "sdmmc1a",   .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },
1188         { .name = "sdmmc2a",   .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },
1189         { .name = "sdmmc3a",   .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },
1190         { .name = "sdmmc4a",   .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },
1191         { .name = "isp2b",     .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },
1192         { .name = "gpu",       .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },
1193         { .name = "ppcs2",     .swgroup = TEGRA_SWGROUP_PPCS2,     .reg = 0xab0 },
1194         { .name = "nvdec",     .swgroup = TEGRA_SWGROUP_NVDEC,     .reg = 0xab4 },
1195         { .name = "ape",       .swgroup = TEGRA_SWGROUP_APE,       .reg = 0xab8 },
1196         { .name = "se",        .swgroup = TEGRA_SWGROUP_SE,        .reg = 0xabc },
1197         { .name = "nvjpg",     .swgroup = TEGRA_SWGROUP_NVJPG,     .reg = 0xac0 },
1198         { .name = "hc1",       .swgroup = TEGRA_SWGROUP_HC1,       .reg = 0xac4 },
1199         { .name = "se1",       .swgroup = TEGRA_SWGROUP_SE1,       .reg = 0xac8 },
1200         { .name = "axiap",     .swgroup = TEGRA_SWGROUP_AXIAP,     .reg = 0xacc },
1201         { .name = "etr",       .swgroup = TEGRA_SWGROUP_ETR,       .reg = 0xad0 },
1202         { .name = "tsecb",     .swgroup = TEGRA_SWGROUP_TSECB,     .reg = 0xad4 },
1203         { .name = "tsec1",     .swgroup = TEGRA_SWGROUP_TSEC1,     .reg = 0xad8 },
1204         { .name = "tsecb1",    .swgroup = TEGRA_SWGROUP_TSECB1,    .reg = 0xadc },
1205         { .name = "nvdec1",    .swgroup = TEGRA_SWGROUP_NVDEC1,    .reg = 0xae0 },
1206 };
1207
1208 static const unsigned int tegra210_group_display[] = {
1209         TEGRA_SWGROUP_DC,
1210         TEGRA_SWGROUP_DCB,
1211 };
1212
1213 static const struct tegra_smmu_group_soc tegra210_groups[] = {
1214         {
1215                 .name = "display",
1216                 .swgroups = tegra210_group_display,
1217                 .num_swgroups = ARRAY_SIZE(tegra210_group_display),
1218         },
1219 };
1220
1221 static const struct tegra_smmu_soc tegra210_smmu_soc = {
1222         .clients = tegra210_mc_clients,
1223         .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1224         .swgroups = tegra210_swgroups,
1225         .num_swgroups = ARRAY_SIZE(tegra210_swgroups),
1226         .groups = tegra210_groups,
1227         .num_groups = ARRAY_SIZE(tegra210_groups),
1228         .supports_round_robin_arbitration = true,
1229         .supports_request_limit = true,
1230         .num_tlb_lines = 48,
1231         .num_asids = 128,
1232 };
1233
1234 #define TEGRA210_MC_RESET(_name, _control, _status, _bit)       \
1235         {                                                       \
1236                 .name = #_name,                                 \
1237                 .id = TEGRA210_MC_RESET_##_name,                \
1238                 .control = _control,                            \
1239                 .status = _status,                              \
1240                 .bit = _bit,                                    \
1241         }
1242
1243 static const struct tegra_mc_reset tegra210_mc_resets[] = {
1244         TEGRA210_MC_RESET(AFI,       0x200, 0x204,  0),
1245         TEGRA210_MC_RESET(AVPC,      0x200, 0x204,  1),
1246         TEGRA210_MC_RESET(DC,        0x200, 0x204,  2),
1247         TEGRA210_MC_RESET(DCB,       0x200, 0x204,  3),
1248         TEGRA210_MC_RESET(HC,        0x200, 0x204,  6),
1249         TEGRA210_MC_RESET(HDA,       0x200, 0x204,  7),
1250         TEGRA210_MC_RESET(ISP2,      0x200, 0x204,  8),
1251         TEGRA210_MC_RESET(MPCORE,    0x200, 0x204,  9),
1252         TEGRA210_MC_RESET(NVENC,     0x200, 0x204, 11),
1253         TEGRA210_MC_RESET(PPCS,      0x200, 0x204, 14),
1254         TEGRA210_MC_RESET(SATA,      0x200, 0x204, 15),
1255         TEGRA210_MC_RESET(VI,        0x200, 0x204, 17),
1256         TEGRA210_MC_RESET(VIC,       0x200, 0x204, 18),
1257         TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1258         TEGRA210_MC_RESET(XUSB_DEV,  0x200, 0x204, 20),
1259         TEGRA210_MC_RESET(A9AVP,     0x200, 0x204, 21),
1260         TEGRA210_MC_RESET(TSEC,      0x200, 0x204, 22),
1261         TEGRA210_MC_RESET(SDMMC1,    0x200, 0x204, 29),
1262         TEGRA210_MC_RESET(SDMMC2,    0x200, 0x204, 30),
1263         TEGRA210_MC_RESET(SDMMC3,    0x200, 0x204, 31),
1264         TEGRA210_MC_RESET(SDMMC4,    0x970, 0x974,  0),
1265         TEGRA210_MC_RESET(ISP2B,     0x970, 0x974,  1),
1266         TEGRA210_MC_RESET(GPU,       0x970, 0x974,  2),
1267         TEGRA210_MC_RESET(NVDEC,     0x970, 0x974,  5),
1268         TEGRA210_MC_RESET(APE,       0x970, 0x974,  6),
1269         TEGRA210_MC_RESET(SE,        0x970, 0x974,  7),
1270         TEGRA210_MC_RESET(NVJPG,     0x970, 0x974,  8),
1271         TEGRA210_MC_RESET(AXIAP,     0x970, 0x974, 11),
1272         TEGRA210_MC_RESET(ETR,       0x970, 0x974, 12),
1273         TEGRA210_MC_RESET(TSECB,     0x970, 0x974, 13),
1274 };
1275
1276 const struct tegra_mc_soc tegra210_mc_soc = {
1277         .clients = tegra210_mc_clients,
1278         .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1279         .num_address_bits = 34,
1280         .atom_size = 64,
1281         .client_id_mask = 0xff,
1282         .smmu = &tegra210_smmu_soc,
1283         .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1284                    MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1285                    MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1286         .reset_ops = &tegra_mc_reset_ops_common,
1287         .resets = tegra210_mc_resets,
1288         .num_resets = ARRAY_SIZE(tegra210_mc_resets),
1289         .ops = &tegra30_mc_ops,
1290 };