1 // SPDX-License-Identifier: GPL-2.0
3 * Tegra20 External Memory Controller driver
5 * Author: Dmitry Osipenko <digetx@gmail.com>
9 #include <linux/clk/tegra.h>
10 #include <linux/debugfs.h>
11 #include <linux/devfreq.h>
12 #include <linux/err.h>
13 #include <linux/interconnect-provider.h>
14 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_opp.h>
23 #include <linux/slab.h>
24 #include <linux/sort.h>
25 #include <linux/types.h>
27 #include <soc/tegra/common.h>
28 #include <soc/tegra/fuse.h>
32 #define EMC_INTSTATUS 0x000
33 #define EMC_INTMASK 0x004
35 #define EMC_TIMING_CONTROL 0x028
44 #define EMC_RD_RCD 0x04c
45 #define EMC_WR_RCD 0x050
47 #define EMC_REXT 0x058
49 #define EMC_QUSE 0x060
50 #define EMC_QRST 0x064
51 #define EMC_QSAFE 0x068
53 #define EMC_REFRESH 0x070
54 #define EMC_BURST_REFRESH_NUM 0x074
55 #define EMC_PDEX2WR 0x078
56 #define EMC_PDEX2RD 0x07c
57 #define EMC_PCHG2PDEN 0x080
58 #define EMC_ACT2PDEN 0x084
59 #define EMC_AR2PDEN 0x088
60 #define EMC_RW2PDEN 0x08c
61 #define EMC_TXSR 0x090
62 #define EMC_TCKE 0x094
63 #define EMC_TFAW 0x098
64 #define EMC_TRPAB 0x09c
65 #define EMC_TCLKSTABLE 0x0a0
66 #define EMC_TCLKSTOP 0x0a4
67 #define EMC_TREFBW 0x0a8
68 #define EMC_QUSE_EXTRA 0x0ac
69 #define EMC_ODT_WRITE 0x0b0
70 #define EMC_ODT_READ 0x0b4
71 #define EMC_FBIO_CFG5 0x104
72 #define EMC_FBIO_CFG6 0x114
73 #define EMC_STAT_CONTROL 0x160
74 #define EMC_STAT_LLMC_CONTROL 0x178
75 #define EMC_STAT_PWR_CLOCK_LIMIT 0x198
76 #define EMC_STAT_PWR_CLOCKS 0x19c
77 #define EMC_STAT_PWR_COUNT 0x1a0
78 #define EMC_AUTO_CAL_INTERVAL 0x2a8
79 #define EMC_CFG_2 0x2b8
80 #define EMC_CFG_DIG_DLL 0x2bc
81 #define EMC_DLL_XFORM_DQS 0x2c0
82 #define EMC_DLL_XFORM_QUSE 0x2c4
83 #define EMC_ZCAL_REF_CNT 0x2e0
84 #define EMC_ZCAL_WAIT_CNT 0x2e4
85 #define EMC_CFG_CLKTRIM_0 0x2d0
86 #define EMC_CFG_CLKTRIM_1 0x2d4
87 #define EMC_CFG_CLKTRIM_2 0x2d8
89 #define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
90 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
91 #define EMC_CLKCHANGE_SR_ENABLE BIT(2)
93 #define EMC_TIMING_UPDATE BIT(0)
95 #define EMC_REFRESH_OVERFLOW_INT BIT(3)
96 #define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
98 #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
99 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
100 #define EMC_DBG_FORCE_UPDATE BIT(2)
101 #define EMC_DBG_READ_DQM_CTRL BIT(9)
102 #define EMC_DBG_CFG_PRIORITY BIT(24)
104 #define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4)
106 #define EMC_PWR_GATHER_CLEAR (1 << 8)
107 #define EMC_PWR_GATHER_DISABLE (2 << 8)
108 #define EMC_PWR_GATHER_ENABLE (3 << 8)
110 static const u16 emc_timing_registers[] = {
129 EMC_BURST_REFRESH_NUM,
153 EMC_AUTO_CAL_INTERVAL,
161 u32 data[ARRAY_SIZE(emc_timing_registers)];
164 enum emc_rate_request_type {
171 struct emc_rate_request {
172 unsigned long min_rate;
173 unsigned long max_rate;
179 struct icc_provider provider;
180 struct notifier_block clk_nb;
183 unsigned int dram_bus_width;
185 struct emc_timing *timings;
186 unsigned int num_timings;
190 unsigned long min_rate;
191 unsigned long max_rate;
195 * There are multiple sources in the EMC driver which could request
196 * a min/max clock rate, these rates are contained in this array.
198 struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
200 /* protect shared rate-change code path */
201 struct mutex rate_lock;
203 struct devfreq_simple_ondemand_data ondemand_data;
206 static irqreturn_t tegra_emc_isr(int irq, void *data)
208 struct tegra_emc *emc = data;
209 u32 intmask = EMC_REFRESH_OVERFLOW_INT;
212 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
216 /* notify about HW problem */
217 if (status & EMC_REFRESH_OVERFLOW_INT)
218 dev_err_ratelimited(emc->dev,
219 "refresh request overflow timeout\n");
221 /* clear interrupts */
222 writel_relaxed(status, emc->regs + EMC_INTSTATUS);
227 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
230 struct emc_timing *timing = NULL;
233 for (i = 0; i < emc->num_timings; i++) {
234 if (emc->timings[i].rate >= rate) {
235 timing = &emc->timings[i];
241 dev_err(emc->dev, "no timing for rate %lu\n", rate);
248 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
250 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
256 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
257 __func__, timing->rate, rate);
259 /* program shadow registers */
260 for (i = 0; i < ARRAY_SIZE(timing->data); i++)
261 writel_relaxed(timing->data[i],
262 emc->regs + emc_timing_registers[i]);
264 /* wait until programming has settled */
265 readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
270 static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
275 dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
278 /* manually initiate memory timing update */
279 writel_relaxed(EMC_TIMING_UPDATE,
280 emc->regs + EMC_TIMING_CONTROL);
284 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
285 v & EMC_CLKCHANGE_COMPLETE_INT,
288 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
295 static int tegra_emc_clk_change_notify(struct notifier_block *nb,
296 unsigned long msg, void *data)
298 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
299 struct clk_notifier_data *cnd = data;
303 case PRE_RATE_CHANGE:
304 err = emc_prepare_timing_change(emc, cnd->new_rate);
307 case ABORT_RATE_CHANGE:
308 err = emc_prepare_timing_change(emc, cnd->old_rate);
312 err = emc_complete_timing_change(emc, true);
315 case POST_RATE_CHANGE:
316 err = emc_complete_timing_change(emc, false);
323 return notifier_from_errno(err);
326 static int load_one_timing_from_dt(struct tegra_emc *emc,
327 struct emc_timing *timing,
328 struct device_node *node)
333 if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
334 dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
338 err = of_property_read_u32(node, "clock-frequency", &rate);
340 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
345 err = of_property_read_u32_array(node, "nvidia,emc-registers",
347 ARRAY_SIZE(emc_timing_registers));
350 "timing %pOF: failed to read emc timing data: %d\n",
356 * The EMC clock rate is twice the bus rate, and the bus rate is
359 timing->rate = rate * 2 * 1000;
361 dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
362 __func__, node, timing->rate);
367 static int cmp_timings(const void *_a, const void *_b)
369 const struct emc_timing *a = _a;
370 const struct emc_timing *b = _b;
372 if (a->rate < b->rate)
375 if (a->rate > b->rate)
381 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
382 struct device_node *node)
384 struct device_node *child;
385 struct emc_timing *timing;
389 child_count = of_get_child_count(node);
391 dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
395 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
400 emc->num_timings = child_count;
401 timing = emc->timings;
403 for_each_child_of_node(node, child) {
404 err = load_one_timing_from_dt(emc, timing++, child);
411 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
414 dev_info_once(emc->dev,
415 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
417 tegra_read_ram_code(),
418 emc->timings[0].rate / 1000000,
419 emc->timings[emc->num_timings - 1].rate / 1000000);
424 static struct device_node *
425 tegra_emc_find_node_by_ram_code(struct device *dev)
427 struct device_node *np;
431 if (of_get_child_count(dev->of_node) == 0) {
432 dev_info_once(dev, "device-tree doesn't have memory timings\n");
436 if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code"))
437 return of_node_get(dev->of_node);
439 ram_code = tegra_read_ram_code();
441 for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
442 np = of_find_node_by_name(np, "emc-tables")) {
443 err = of_property_read_u32(np, "nvidia,ram-code", &value);
444 if (err || value != ram_code) {
452 dev_err(dev, "no memory timings for RAM code %u found in device tree\n",
458 static int emc_setup_hw(struct tegra_emc *emc)
460 u32 intmask = EMC_REFRESH_OVERFLOW_INT;
461 u32 emc_cfg, emc_dbg, emc_fbio;
463 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
466 * Depending on a memory type, DRAM should enter either self-refresh
467 * or power-down state on EMC clock change.
469 if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) &&
470 !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) {
472 "bootloader didn't specify DRAM auto-suspend mode\n");
476 /* enable EMC and CAR to handshake on PLL divider/source changes */
477 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
478 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
480 /* initialize interrupt */
481 writel_relaxed(intmask, emc->regs + EMC_INTMASK);
482 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
484 /* ensure that unwanted debug features are disabled */
485 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
486 emc_dbg |= EMC_DBG_CFG_PRIORITY;
487 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
488 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
489 emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
490 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
492 emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
494 if (emc_fbio & EMC_FBIO_CFG5_DRAM_WIDTH_X16)
495 emc->dram_bus_width = 16;
497 emc->dram_bus_width = 32;
499 dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
504 static long emc_round_rate(unsigned long rate,
505 unsigned long min_rate,
506 unsigned long max_rate,
509 struct emc_timing *timing = NULL;
510 struct tegra_emc *emc = arg;
513 if (!emc->num_timings)
514 return clk_get_rate(emc->clk);
516 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
518 for (i = 0; i < emc->num_timings; i++) {
519 if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
522 if (emc->timings[i].rate > max_rate) {
525 if (emc->timings[i].rate < min_rate)
529 if (emc->timings[i].rate < min_rate)
532 timing = &emc->timings[i];
537 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
538 rate, min_rate, max_rate);
545 static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
549 for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
550 emc->requested_rate[i].min_rate = 0;
551 emc->requested_rate[i].max_rate = ULONG_MAX;
555 static int emc_request_rate(struct tegra_emc *emc,
556 unsigned long new_min_rate,
557 unsigned long new_max_rate,
558 enum emc_rate_request_type type)
560 struct emc_rate_request *req = emc->requested_rate;
561 unsigned long min_rate = 0, max_rate = ULONG_MAX;
565 /* select minimum and maximum rates among the requested rates */
566 for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
568 min_rate = max(new_min_rate, min_rate);
569 max_rate = min(new_max_rate, max_rate);
571 min_rate = max(req->min_rate, min_rate);
572 max_rate = min(req->max_rate, max_rate);
576 if (min_rate > max_rate) {
577 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
578 __func__, type, min_rate, max_rate);
583 * EMC rate-changes should go via OPP API because it manages voltage
586 err = dev_pm_opp_set_rate(emc->dev, min_rate);
590 emc->requested_rate[type].min_rate = new_min_rate;
591 emc->requested_rate[type].max_rate = new_max_rate;
596 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
597 enum emc_rate_request_type type)
599 struct emc_rate_request *req = &emc->requested_rate[type];
602 mutex_lock(&emc->rate_lock);
603 ret = emc_request_rate(emc, rate, req->max_rate, type);
604 mutex_unlock(&emc->rate_lock);
609 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
610 enum emc_rate_request_type type)
612 struct emc_rate_request *req = &emc->requested_rate[type];
615 mutex_lock(&emc->rate_lock);
616 ret = emc_request_rate(emc, req->min_rate, rate, type);
617 mutex_unlock(&emc->rate_lock);
625 * The memory controller driver exposes some files in debugfs that can be used
626 * to control the EMC frequency. The top-level directory can be found here:
628 * /sys/kernel/debug/emc
630 * It contains the following files:
632 * - available_rates: This file contains a list of valid, space-separated
635 * - min_rate: Writing a value to this file sets the given frequency as the
636 * floor of the permitted range. If this is higher than the currently
637 * configured EMC frequency, this will cause the frequency to be
638 * increased so that it stays within the valid range.
640 * - max_rate: Similarily to the min_rate file, writing a value to this file
641 * sets the given frequency as the ceiling of the permitted range. If
642 * the value is lower than the currently configured EMC frequency, this
643 * will cause the frequency to be decreased so that it stays within the
647 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
651 for (i = 0; i < emc->num_timings; i++)
652 if (rate == emc->timings[i].rate)
658 static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
660 struct tegra_emc *emc = s->private;
661 const char *prefix = "";
664 for (i = 0; i < emc->num_timings; i++) {
665 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
674 static int tegra_emc_debug_available_rates_open(struct inode *inode,
677 return single_open(file, tegra_emc_debug_available_rates_show,
681 static const struct file_operations tegra_emc_debug_available_rates_fops = {
682 .open = tegra_emc_debug_available_rates_open,
685 .release = single_release,
688 static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
690 struct tegra_emc *emc = data;
692 *rate = emc->debugfs.min_rate;
697 static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
699 struct tegra_emc *emc = data;
702 if (!tegra_emc_validate_rate(emc, rate))
705 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
709 emc->debugfs.min_rate = rate;
714 DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
715 tegra_emc_debug_min_rate_get,
716 tegra_emc_debug_min_rate_set, "%llu\n");
718 static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
720 struct tegra_emc *emc = data;
722 *rate = emc->debugfs.max_rate;
727 static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
729 struct tegra_emc *emc = data;
732 if (!tegra_emc_validate_rate(emc, rate))
735 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
739 emc->debugfs.max_rate = rate;
744 DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
745 tegra_emc_debug_max_rate_get,
746 tegra_emc_debug_max_rate_set, "%llu\n");
748 static void tegra_emc_debugfs_init(struct tegra_emc *emc)
750 struct device *dev = emc->dev;
754 emc->debugfs.min_rate = ULONG_MAX;
755 emc->debugfs.max_rate = 0;
757 for (i = 0; i < emc->num_timings; i++) {
758 if (emc->timings[i].rate < emc->debugfs.min_rate)
759 emc->debugfs.min_rate = emc->timings[i].rate;
761 if (emc->timings[i].rate > emc->debugfs.max_rate)
762 emc->debugfs.max_rate = emc->timings[i].rate;
765 if (!emc->num_timings) {
766 emc->debugfs.min_rate = clk_get_rate(emc->clk);
767 emc->debugfs.max_rate = emc->debugfs.min_rate;
770 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
771 emc->debugfs.max_rate);
773 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
774 emc->debugfs.min_rate, emc->debugfs.max_rate,
778 emc->debugfs.root = debugfs_create_dir("emc", NULL);
779 if (!emc->debugfs.root) {
780 dev_err(emc->dev, "failed to create debugfs directory\n");
784 debugfs_create_file("available_rates", 0444, emc->debugfs.root,
785 emc, &tegra_emc_debug_available_rates_fops);
786 debugfs_create_file("min_rate", 0644, emc->debugfs.root,
787 emc, &tegra_emc_debug_min_rate_fops);
788 debugfs_create_file("max_rate", 0644, emc->debugfs.root,
789 emc, &tegra_emc_debug_max_rate_fops);
792 static inline struct tegra_emc *
793 to_tegra_emc_provider(struct icc_provider *provider)
795 return container_of(provider, struct tegra_emc, provider);
798 static struct icc_node_data *
799 emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
801 struct icc_provider *provider = data;
802 struct icc_node_data *ndata;
803 struct icc_node *node;
805 /* External Memory is the only possible ICC route */
806 list_for_each_entry(node, &provider->nodes, node_list) {
807 if (node->id != TEGRA_ICC_EMEM)
810 ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
812 return ERR_PTR(-ENOMEM);
815 * SRC and DST nodes should have matching TAG in order to have
816 * it set by default for a requested path.
818 ndata->tag = TEGRA_MC_ICC_TAG_ISO;
824 return ERR_PTR(-EPROBE_DEFER);
827 static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
829 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
830 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
831 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
832 unsigned long long rate = max(avg_bw, peak_bw);
833 unsigned int dram_data_bus_width_bytes;
837 * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data
838 * is sampled on both clock edges. This means that EMC clock rate
839 * equals to the peak data-rate.
841 dram_data_bus_width_bytes = emc->dram_bus_width / 8;
842 do_div(rate, dram_data_bus_width_bytes);
843 rate = min_t(u64, rate, U32_MAX);
845 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
852 static int tegra_emc_interconnect_init(struct tegra_emc *emc)
854 const struct tegra_mc_soc *soc;
855 struct icc_node *node;
858 emc->mc = devm_tegra_memory_controller_get(emc->dev);
860 return PTR_ERR(emc->mc);
864 emc->provider.dev = emc->dev;
865 emc->provider.set = emc_icc_set;
866 emc->provider.data = &emc->provider;
867 emc->provider.aggregate = soc->icc_ops->aggregate;
868 emc->provider.xlate_extended = emc_of_icc_xlate_extended;
870 err = icc_provider_add(&emc->provider);
874 /* create External Memory Controller node */
875 node = icc_node_create(TEGRA_ICC_EMC);
881 node->name = "External Memory Controller";
882 icc_node_add(node, &emc->provider);
884 /* link External Memory Controller to External Memory (DRAM) */
885 err = icc_link_create(node, TEGRA_ICC_EMEM);
889 /* create External Memory node */
890 node = icc_node_create(TEGRA_ICC_EMEM);
896 node->name = "External Memory (DRAM)";
897 icc_node_add(node, &emc->provider);
902 icc_nodes_remove(&emc->provider);
904 icc_provider_del(&emc->provider);
906 dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
911 static int tegra_emc_opp_table_init(struct tegra_emc *emc)
913 u32 hw_version = BIT(tegra_sku_info.soc_process_id);
914 struct opp_table *hw_opp_table;
917 hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
918 err = PTR_ERR_OR_ZERO(hw_opp_table);
920 dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);
924 err = dev_pm_opp_of_add_table(emc->dev);
927 dev_err(emc->dev, "OPP table not found, please update your device tree\n");
929 dev_err(emc->dev, "failed to add OPP table: %d\n", err);
934 dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
935 hw_version, clk_get_rate(emc->clk) / 1000000);
937 /* first dummy rate-set initializes voltage state */
938 err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
940 dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err);
947 dev_pm_opp_of_remove_table(emc->dev);
949 dev_pm_opp_put_supported_hw(hw_opp_table);
954 static void devm_tegra_emc_unset_callback(void *data)
956 tegra20_clk_set_emc_round_callback(NULL, NULL);
959 static void devm_tegra_emc_unreg_clk_notifier(void *data)
961 struct tegra_emc *emc = data;
963 clk_notifier_unregister(emc->clk, &emc->clk_nb);
966 static int tegra_emc_init_clk(struct tegra_emc *emc)
970 tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
972 err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback,
977 emc->clk = devm_clk_get(emc->dev, NULL);
978 if (IS_ERR(emc->clk)) {
979 dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk);
980 return PTR_ERR(emc->clk);
983 err = clk_notifier_register(emc->clk, &emc->clk_nb);
985 dev_err(emc->dev, "failed to register clk notifier: %d\n", err);
989 err = devm_add_action_or_reset(emc->dev,
990 devm_tegra_emc_unreg_clk_notifier, emc);
997 static int tegra_emc_devfreq_target(struct device *dev, unsigned long *freq,
1000 struct tegra_emc *emc = dev_get_drvdata(dev);
1001 struct dev_pm_opp *opp;
1004 opp = devfreq_recommended_opp(dev, freq, flags);
1006 dev_err(dev, "failed to find opp for %lu Hz\n", *freq);
1007 return PTR_ERR(opp);
1010 rate = dev_pm_opp_get_freq(opp);
1011 dev_pm_opp_put(opp);
1013 return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ);
1016 static int tegra_emc_devfreq_get_dev_status(struct device *dev,
1017 struct devfreq_dev_status *stat)
1019 struct tegra_emc *emc = dev_get_drvdata(dev);
1021 /* freeze counters */
1022 writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL);
1025 * busy_time: number of clocks EMC request was accepted
1026 * total_time: number of clocks PWR_GATHER control was set to ENABLE
1028 stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT);
1029 stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS);
1030 stat->current_frequency = clk_get_rate(emc->clk);
1032 /* clear counters and restart */
1033 writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL);
1034 writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL);
1039 static struct devfreq_dev_profile tegra_emc_devfreq_profile = {
1041 .target = tegra_emc_devfreq_target,
1042 .get_dev_status = tegra_emc_devfreq_get_dev_status,
1045 static int tegra_emc_devfreq_init(struct tegra_emc *emc)
1047 struct devfreq *devfreq;
1050 * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold
1051 * should be less than 50. Secondly, multiple active memory clients
1052 * may cause over 20% of lost clock cycles due to stalls caused by
1053 * competing memory accesses. This means that threshold should be
1054 * set to a less than 30 in order to have a properly working governor.
1056 emc->ondemand_data.upthreshold = 20;
1059 * Reset statistic gathers state, select global bandwidth for the
1060 * statistics collection mode and set clocks counter saturation
1063 writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL);
1064 writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL);
1065 writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT);
1067 devfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile,
1068 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1069 &emc->ondemand_data);
1070 if (IS_ERR(devfreq)) {
1071 dev_err(emc->dev, "failed to initialize devfreq: %pe", devfreq);
1072 return PTR_ERR(devfreq);
1078 static int tegra_emc_probe(struct platform_device *pdev)
1080 struct device_node *np;
1081 struct tegra_emc *emc;
1084 irq = platform_get_irq(pdev, 0);
1086 dev_err(&pdev->dev, "please update your device tree\n");
1090 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1094 mutex_init(&emc->rate_lock);
1095 emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
1096 emc->dev = &pdev->dev;
1098 np = tegra_emc_find_node_by_ram_code(&pdev->dev);
1100 err = tegra_emc_load_timings_from_dt(emc, np);
1106 emc->regs = devm_platform_ioremap_resource(pdev, 0);
1107 if (IS_ERR(emc->regs))
1108 return PTR_ERR(emc->regs);
1110 err = emc_setup_hw(emc);
1114 err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0,
1115 dev_name(&pdev->dev), emc);
1117 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1121 err = tegra_emc_init_clk(emc);
1125 err = tegra_emc_opp_table_init(emc);
1129 platform_set_drvdata(pdev, emc);
1130 tegra_emc_rate_requests_init(emc);
1131 tegra_emc_debugfs_init(emc);
1132 tegra_emc_interconnect_init(emc);
1133 tegra_emc_devfreq_init(emc);
1136 * Don't allow the kernel module to be unloaded. Unloading adds some
1137 * extra complexity which doesn't really worth the effort in a case of
1140 try_module_get(THIS_MODULE);
1145 static const struct of_device_id tegra_emc_of_match[] = {
1146 { .compatible = "nvidia,tegra20-emc", },
1149 MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
1151 static struct platform_driver tegra_emc_driver = {
1152 .probe = tegra_emc_probe,
1154 .name = "tegra20-emc",
1155 .of_match_table = tegra_emc_of_match,
1156 .suppress_bind_attrs = true,
1157 .sync_state = icc_sync_state,
1160 module_platform_driver(tegra_emc_driver);
1162 MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
1163 MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver");
1164 MODULE_LICENSE("GPL v2");