Merge tag 'libata-5.14-2021-07-30' of git://git.kernel.dk/linux-block
[linux-2.6-microblaze.git] / drivers / memory / tegra / tegra186.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2017-2021 NVIDIA CORPORATION.  All rights reserved.
4  */
5
6 #include <linux/io.h>
7 #include <linux/iommu.h>
8 #include <linux/module.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12
13 #include <soc/tegra/mc.h>
14
15 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
16 #include <dt-bindings/memory/tegra186-mc.h>
17 #endif
18
19 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
20 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
21 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
22
23 static void tegra186_mc_program_sid(struct tegra_mc *mc)
24 {
25         unsigned int i;
26
27         for (i = 0; i < mc->soc->num_clients; i++) {
28                 const struct tegra_mc_client *client = &mc->soc->clients[i];
29                 u32 override, security;
30
31                 override = readl(mc->regs + client->regs.sid.override);
32                 security = readl(mc->regs + client->regs.sid.security);
33
34                 dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
35                         client->name, override, security);
36
37                 dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid,
38                         client->name);
39                 writel(client->sid, mc->regs + client->regs.sid.override);
40
41                 override = readl(mc->regs + client->regs.sid.override);
42                 security = readl(mc->regs + client->regs.sid.security);
43
44                 dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
45                         client->name, override, security);
46         }
47 }
48
49 static int tegra186_mc_probe(struct tegra_mc *mc)
50 {
51         int err;
52
53         err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
54         if (err < 0)
55                 return err;
56
57         tegra186_mc_program_sid(mc);
58
59         return 0;
60 }
61
62 static void tegra186_mc_remove(struct tegra_mc *mc)
63 {
64         of_platform_depopulate(mc->dev);
65 }
66
67 static int tegra186_mc_resume(struct tegra_mc *mc)
68 {
69         tegra186_mc_program_sid(mc);
70
71         return 0;
72 }
73
74 static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
75                                             const struct tegra_mc_client *client,
76                                             unsigned int sid)
77 {
78         u32 value, old;
79
80         value = readl(mc->regs + client->regs.sid.security);
81         if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
82                 /*
83                  * If the secure firmware has locked this down the override
84                  * for this memory client, there's nothing we can do here.
85                  */
86                 if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
87                         return;
88
89                 /*
90                  * Otherwise, try to set the override itself. Typically the
91                  * secure firmware will never have set this configuration.
92                  * Instead, it will either have disabled write access to
93                  * this field, or it will already have set an explicit
94                  * override itself.
95                  */
96                 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
97
98                 value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
99                 writel(value, mc->regs + client->regs.sid.security);
100         }
101
102         value = readl(mc->regs + client->regs.sid.override);
103         old = value & MC_SID_STREAMID_OVERRIDE_MASK;
104
105         if (old != sid) {
106                 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
107                         client->name, sid);
108                 writel(sid, mc->regs + client->regs.sid.override);
109         }
110 }
111
112 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
113 {
114 #if IS_ENABLED(CONFIG_IOMMU_API)
115         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
116         struct of_phandle_args args;
117         unsigned int i, index = 0;
118
119         while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
120                                            index, &args)) {
121                 if (args.np == mc->dev->of_node && args.args_count != 0) {
122                         for (i = 0; i < mc->soc->num_clients; i++) {
123                                 const struct tegra_mc_client *client = &mc->soc->clients[i];
124
125                                 if (client->id == args.args[0]) {
126                                         u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK;
127
128                                         tegra186_mc_client_sid_override(mc, client, sid);
129                                 }
130                         }
131                 }
132
133                 index++;
134         }
135 #endif
136
137         return 0;
138 }
139
140 const struct tegra_mc_ops tegra186_mc_ops = {
141         .probe = tegra186_mc_probe,
142         .remove = tegra186_mc_remove,
143         .resume = tegra186_mc_resume,
144         .probe_device = tegra186_mc_probe_device,
145 };
146
147 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
148 static const struct tegra_mc_client tegra186_mc_clients[] = {
149         {
150                 .id = TEGRA186_MEMORY_CLIENT_PTCR,
151                 .name = "ptcr",
152                 .sid = TEGRA186_SID_PASSTHROUGH,
153                 .regs = {
154                         .sid = {
155                                 .override = 0x000,
156                                 .security = 0x004,
157                         },
158                 },
159         }, {
160                 .id = TEGRA186_MEMORY_CLIENT_AFIR,
161                 .name = "afir",
162                 .sid = TEGRA186_SID_AFI,
163                 .regs = {
164                         .sid = {
165                                 .override = 0x070,
166                                 .security = 0x074,
167                         },
168                 },
169         }, {
170                 .id = TEGRA186_MEMORY_CLIENT_HDAR,
171                 .name = "hdar",
172                 .sid = TEGRA186_SID_HDA,
173                 .regs = {
174                         .sid = {
175                                 .override = 0x0a8,
176                                 .security = 0x0ac,
177                         },
178                 },
179         }, {
180                 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
181                 .name = "host1xdmar",
182                 .sid = TEGRA186_SID_HOST1X,
183                 .regs = {
184                         .sid = {
185                                 .override = 0x0b0,
186                                 .security = 0x0b4,
187                         },
188                 },
189         }, {
190                 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
191                 .name = "nvencsrd",
192                 .sid = TEGRA186_SID_NVENC,
193                 .regs = {
194                         .sid = {
195                                 .override = 0x0e0,
196                                 .security = 0x0e4,
197                         },
198                 },
199         }, {
200                 .id = TEGRA186_MEMORY_CLIENT_SATAR,
201                 .name = "satar",
202                 .sid = TEGRA186_SID_SATA,
203                 .regs = {
204                         .sid = {
205                                 .override = 0x0f8,
206                                 .security = 0x0fc,
207                         },
208                 },
209         }, {
210                 .id = TEGRA186_MEMORY_CLIENT_MPCORER,
211                 .name = "mpcorer",
212                 .sid = TEGRA186_SID_PASSTHROUGH,
213                 .regs = {
214                         .sid = {
215                                 .override = 0x138,
216                                 .security = 0x13c,
217                         },
218                 },
219         }, {
220                 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
221                 .name = "nvencswr",
222                 .sid = TEGRA186_SID_NVENC,
223                 .regs = {
224                         .sid = {
225                                 .override = 0x158,
226                                 .security = 0x15c,
227                         },
228                 },
229         }, {
230                 .id = TEGRA186_MEMORY_CLIENT_AFIW,
231                 .name = "afiw",
232                 .sid = TEGRA186_SID_AFI,
233                 .regs = {
234                         .sid = {
235                                 .override = 0x188,
236                                 .security = 0x18c,
237                         },
238                 },
239         }, {
240                 .id = TEGRA186_MEMORY_CLIENT_HDAW,
241                 .name = "hdaw",
242                 .sid = TEGRA186_SID_HDA,
243                 .regs = {
244                         .sid = {
245                                 .override = 0x1a8,
246                                 .security = 0x1ac,
247                         },
248                 },
249         }, {
250                 .id = TEGRA186_MEMORY_CLIENT_MPCOREW,
251                 .name = "mpcorew",
252                 .sid = TEGRA186_SID_PASSTHROUGH,
253                 .regs = {
254                         .sid = {
255                                 .override = 0x1c8,
256                                 .security = 0x1cc,
257                         },
258                 },
259         }, {
260                 .id = TEGRA186_MEMORY_CLIENT_SATAW,
261                 .name = "sataw",
262                 .sid = TEGRA186_SID_SATA,
263                 .regs = {
264                         .sid = {
265                                 .override = 0x1e8,
266                                 .security = 0x1ec,
267                         },
268                 },
269         }, {
270                 .id = TEGRA186_MEMORY_CLIENT_ISPRA,
271                 .name = "ispra",
272                 .sid = TEGRA186_SID_ISP,
273                 .regs = {
274                         .sid = {
275                                 .override = 0x220,
276                                 .security = 0x224,
277                         },
278                 },
279         }, {
280                 .id = TEGRA186_MEMORY_CLIENT_ISPWA,
281                 .name = "ispwa",
282                 .sid = TEGRA186_SID_ISP,
283                 .regs = {
284                         .sid = {
285                                 .override = 0x230,
286                                 .security = 0x234,
287                         },
288                 },
289         }, {
290                 .id = TEGRA186_MEMORY_CLIENT_ISPWB,
291                 .name = "ispwb",
292                 .sid = TEGRA186_SID_ISP,
293                 .regs = {
294                         .sid = {
295                                 .override = 0x238,
296                                 .security = 0x23c,
297                         },
298                 },
299         }, {
300                 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
301                 .name = "xusb_hostr",
302                 .sid = TEGRA186_SID_XUSB_HOST,
303                 .regs = {
304                         .sid = {
305                                 .override = 0x250,
306                                 .security = 0x254,
307                         },
308                 },
309         }, {
310                 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
311                 .name = "xusb_hostw",
312                 .sid = TEGRA186_SID_XUSB_HOST,
313                 .regs = {
314                         .sid = {
315                                 .override = 0x258,
316                                 .security = 0x25c,
317                         },
318                 },
319         }, {
320                 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
321                 .name = "xusb_devr",
322                 .sid = TEGRA186_SID_XUSB_DEV,
323                 .regs = {
324                         .sid = {
325                                 .override = 0x260,
326                                 .security = 0x264,
327                         },
328                 },
329         }, {
330                 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
331                 .name = "xusb_devw",
332                 .sid = TEGRA186_SID_XUSB_DEV,
333                 .regs = {
334                         .sid = {
335                                 .override = 0x268,
336                                 .security = 0x26c,
337                         },
338                 },
339         }, {
340                 .id = TEGRA186_MEMORY_CLIENT_TSECSRD,
341                 .name = "tsecsrd",
342                 .sid = TEGRA186_SID_TSEC,
343                 .regs = {
344                         .sid = {
345                                 .override = 0x2a0,
346                                 .security = 0x2a4,
347                         },
348                 },
349         }, {
350                 .id = TEGRA186_MEMORY_CLIENT_TSECSWR,
351                 .name = "tsecswr",
352                 .sid = TEGRA186_SID_TSEC,
353                 .regs = {
354                         .sid = {
355                                 .override = 0x2a8,
356                                 .security = 0x2ac,
357                         },
358                 },
359         }, {
360                 .id = TEGRA186_MEMORY_CLIENT_GPUSRD,
361                 .name = "gpusrd",
362                 .sid = TEGRA186_SID_GPU,
363                 .regs = {
364                         .sid = {
365                                 .override = 0x2c0,
366                                 .security = 0x2c4,
367                         },
368                 },
369         }, {
370                 .id = TEGRA186_MEMORY_CLIENT_GPUSWR,
371                 .name = "gpuswr",
372                 .sid = TEGRA186_SID_GPU,
373                 .regs = {
374                         .sid = {
375                                 .override = 0x2c8,
376                                 .security = 0x2cc,
377                         },
378                 },
379         }, {
380                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
381                 .name = "sdmmcra",
382                 .sid = TEGRA186_SID_SDMMC1,
383                 .regs = {
384                         .sid = {
385                                 .override = 0x300,
386                                 .security = 0x304,
387                         },
388                 },
389         }, {
390                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
391                 .name = "sdmmcraa",
392                 .sid = TEGRA186_SID_SDMMC2,
393                 .regs = {
394                         .sid = {
395                                 .override = 0x308,
396                                 .security = 0x30c,
397                         },
398                 },
399         }, {
400                 .id = TEGRA186_MEMORY_CLIENT_SDMMCR,
401                 .name = "sdmmcr",
402                 .sid = TEGRA186_SID_SDMMC3,
403                 .regs = {
404                         .sid = {
405                                 .override = 0x310,
406                                 .security = 0x314,
407                         },
408                 },
409         }, {
410                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
411                 .name = "sdmmcrab",
412                 .sid = TEGRA186_SID_SDMMC4,
413                 .regs = {
414                         .sid = {
415                                 .override = 0x318,
416                                 .security = 0x31c,
417                         },
418                 },
419         }, {
420                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
421                 .name = "sdmmcwa",
422                 .sid = TEGRA186_SID_SDMMC1,
423                 .regs = {
424                         .sid = {
425                                 .override = 0x320,
426                                 .security = 0x324,
427                         },
428                 },
429         }, {
430                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
431                 .name = "sdmmcwaa",
432                 .sid = TEGRA186_SID_SDMMC2,
433                 .regs = {
434                         .sid = {
435                                 .override = 0x328,
436                                 .security = 0x32c,
437                         },
438                 },
439         }, {
440                 .id = TEGRA186_MEMORY_CLIENT_SDMMCW,
441                 .name = "sdmmcw",
442                 .sid = TEGRA186_SID_SDMMC3,
443                 .regs = {
444                         .sid = {
445                                 .override = 0x330,
446                                 .security = 0x334,
447                         },
448                 },
449         }, {
450                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
451                 .name = "sdmmcwab",
452                 .sid = TEGRA186_SID_SDMMC4,
453                 .regs = {
454                         .sid = {
455                                 .override = 0x338,
456                                 .security = 0x33c,
457                         },
458                 },
459         }, {
460                 .id = TEGRA186_MEMORY_CLIENT_VICSRD,
461                 .name = "vicsrd",
462                 .sid = TEGRA186_SID_VIC,
463                 .regs = {
464                         .sid = {
465                                 .override = 0x360,
466                                 .security = 0x364,
467                         },
468                 },
469         }, {
470                 .id = TEGRA186_MEMORY_CLIENT_VICSWR,
471                 .name = "vicswr",
472                 .sid = TEGRA186_SID_VIC,
473                 .regs = {
474                         .sid = {
475                                 .override = 0x368,
476                                 .security = 0x36c,
477                         },
478                 },
479         }, {
480                 .id = TEGRA186_MEMORY_CLIENT_VIW,
481                 .name = "viw",
482                 .sid = TEGRA186_SID_VI,
483                 .regs = {
484                         .sid = {
485                                 .override = 0x390,
486                                 .security = 0x394,
487                         },
488                 },
489         }, {
490                 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
491                 .name = "nvdecsrd",
492                 .sid = TEGRA186_SID_NVDEC,
493                 .regs = {
494                         .sid = {
495                                 .override = 0x3c0,
496                                 .security = 0x3c4,
497                         },
498                 },
499         }, {
500                 .id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
501                 .name = "nvdecswr",
502                 .sid = TEGRA186_SID_NVDEC,
503                 .regs = {
504                         .sid = {
505                                 .override = 0x3c8,
506                                 .security = 0x3cc,
507                         },
508                 },
509         }, {
510                 .id = TEGRA186_MEMORY_CLIENT_APER,
511                 .name = "aper",
512                 .sid = TEGRA186_SID_APE,
513                 .regs = {
514                         .sid = {
515                                 .override = 0x3d0,
516                                 .security = 0x3d4,
517                         },
518                 },
519         }, {
520                 .id = TEGRA186_MEMORY_CLIENT_APEW,
521                 .name = "apew",
522                 .sid = TEGRA186_SID_APE,
523                 .regs = {
524                         .sid = {
525                                 .override = 0x3d8,
526                                 .security = 0x3dc,
527                         },
528                 },
529         }, {
530                 .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
531                 .name = "nvjpgsrd",
532                 .sid = TEGRA186_SID_NVJPG,
533                 .regs = {
534                         .sid = {
535                                 .override = 0x3f0,
536                                 .security = 0x3f4,
537                         },
538                 },
539         }, {
540                 .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
541                 .name = "nvjpgswr",
542                 .sid = TEGRA186_SID_NVJPG,
543                 .regs = {
544                         .sid = {
545                                 .override = 0x3f8,
546                                 .security = 0x3fc,
547                         },
548                 },
549         }, {
550                 .id = TEGRA186_MEMORY_CLIENT_SESRD,
551                 .name = "sesrd",
552                 .sid = TEGRA186_SID_SE,
553                 .regs = {
554                         .sid = {
555                                 .override = 0x400,
556                                 .security = 0x404,
557                         },
558                 },
559         }, {
560                 .id = TEGRA186_MEMORY_CLIENT_SESWR,
561                 .name = "seswr",
562                 .sid = TEGRA186_SID_SE,
563                 .regs = {
564                         .sid = {
565                                 .override = 0x408,
566                                 .security = 0x40c,
567                         },
568                 },
569         }, {
570                 .id = TEGRA186_MEMORY_CLIENT_ETRR,
571                 .name = "etrr",
572                 .sid = TEGRA186_SID_ETR,
573                 .regs = {
574                         .sid = {
575                                 .override = 0x420,
576                                 .security = 0x424,
577                         },
578                 },
579         }, {
580                 .id = TEGRA186_MEMORY_CLIENT_ETRW,
581                 .name = "etrw",
582                 .sid = TEGRA186_SID_ETR,
583                 .regs = {
584                         .sid = {
585                                 .override = 0x428,
586                                 .security = 0x42c,
587                         },
588                 },
589         }, {
590                 .id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
591                 .name = "tsecsrdb",
592                 .sid = TEGRA186_SID_TSECB,
593                 .regs = {
594                         .sid = {
595                                 .override = 0x430,
596                                 .security = 0x434,
597                         },
598                 },
599         }, {
600                 .id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
601                 .name = "tsecswrb",
602                 .sid = TEGRA186_SID_TSECB,
603                 .regs = {
604                         .sid = {
605                                 .override = 0x438,
606                                 .security = 0x43c,
607                         },
608                 },
609         }, {
610                 .id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
611                 .name = "gpusrd2",
612                 .sid = TEGRA186_SID_GPU,
613                 .regs = {
614                         .sid = {
615                                 .override = 0x440,
616                                 .security = 0x444,
617                         },
618                 },
619         }, {
620                 .id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
621                 .name = "gpuswr2",
622                 .sid = TEGRA186_SID_GPU,
623                 .regs = {
624                         .sid = {
625                                 .override = 0x448,
626                                 .security = 0x44c,
627                         },
628                 },
629         }, {
630                 .id = TEGRA186_MEMORY_CLIENT_AXISR,
631                 .name = "axisr",
632                 .sid = TEGRA186_SID_GPCDMA_0,
633                 .regs = {
634                         .sid = {
635                                 .override = 0x460,
636                                 .security = 0x464,
637                         },
638                 },
639         }, {
640                 .id = TEGRA186_MEMORY_CLIENT_AXISW,
641                 .name = "axisw",
642                 .sid = TEGRA186_SID_GPCDMA_0,
643                 .regs = {
644                         .sid = {
645                                 .override = 0x468,
646                                 .security = 0x46c,
647                         },
648                 },
649         }, {
650                 .id = TEGRA186_MEMORY_CLIENT_EQOSR,
651                 .name = "eqosr",
652                 .sid = TEGRA186_SID_EQOS,
653                 .regs = {
654                         .sid = {
655                                 .override = 0x470,
656                                 .security = 0x474,
657                         },
658                 },
659         }, {
660                 .id = TEGRA186_MEMORY_CLIENT_EQOSW,
661                 .name = "eqosw",
662                 .sid = TEGRA186_SID_EQOS,
663                 .regs = {
664                         .sid = {
665                                 .override = 0x478,
666                                 .security = 0x47c,
667                         },
668                 },
669         }, {
670                 .id = TEGRA186_MEMORY_CLIENT_UFSHCR,
671                 .name = "ufshcr",
672                 .sid = TEGRA186_SID_UFSHC,
673                 .regs = {
674                         .sid = {
675                                 .override = 0x480,
676                                 .security = 0x484,
677                         },
678                 },
679         }, {
680                 .id = TEGRA186_MEMORY_CLIENT_UFSHCW,
681                 .name = "ufshcw",
682                 .sid = TEGRA186_SID_UFSHC,
683                 .regs = {
684                         .sid = {
685                                 .override = 0x488,
686                                 .security = 0x48c,
687                         },
688                 },
689         }, {
690                 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
691                 .name = "nvdisplayr",
692                 .sid = TEGRA186_SID_NVDISPLAY,
693                 .regs = {
694                         .sid = {
695                                 .override = 0x490,
696                                 .security = 0x494,
697                         },
698                 },
699         }, {
700                 .id = TEGRA186_MEMORY_CLIENT_BPMPR,
701                 .name = "bpmpr",
702                 .sid = TEGRA186_SID_BPMP,
703                 .regs = {
704                         .sid = {
705                                 .override = 0x498,
706                                 .security = 0x49c,
707                         },
708                 },
709         }, {
710                 .id = TEGRA186_MEMORY_CLIENT_BPMPW,
711                 .name = "bpmpw",
712                 .sid = TEGRA186_SID_BPMP,
713                 .regs = {
714                         .sid = {
715                                 .override = 0x4a0,
716                                 .security = 0x4a4,
717                         },
718                 },
719         }, {
720                 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
721                 .name = "bpmpdmar",
722                 .sid = TEGRA186_SID_BPMP,
723                 .regs = {
724                         .sid = {
725                                 .override = 0x4a8,
726                                 .security = 0x4ac,
727                         },
728                 },
729         }, {
730                 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
731                 .name = "bpmpdmaw",
732                 .sid = TEGRA186_SID_BPMP,
733                 .regs = {
734                         .sid = {
735                                 .override = 0x4b0,
736                                 .security = 0x4b4,
737                         },
738                 },
739         }, {
740                 .id = TEGRA186_MEMORY_CLIENT_AONR,
741                 .name = "aonr",
742                 .sid = TEGRA186_SID_AON,
743                 .regs = {
744                         .sid = {
745                                 .override = 0x4b8,
746                                 .security = 0x4bc,
747                         },
748                 },
749         }, {
750                 .id = TEGRA186_MEMORY_CLIENT_AONW,
751                 .name = "aonw",
752                 .sid = TEGRA186_SID_AON,
753                 .regs = {
754                         .sid = {
755                                 .override = 0x4c0,
756                                 .security = 0x4c4,
757                         },
758                 },
759         }, {
760                 .id = TEGRA186_MEMORY_CLIENT_AONDMAR,
761                 .name = "aondmar",
762                 .sid = TEGRA186_SID_AON,
763                 .regs = {
764                         .sid = {
765                                 .override = 0x4c8,
766                                 .security = 0x4cc,
767                         },
768                 },
769         }, {
770                 .id = TEGRA186_MEMORY_CLIENT_AONDMAW,
771                 .name = "aondmaw",
772                 .sid = TEGRA186_SID_AON,
773                 .regs = {
774                         .sid = {
775                                 .override = 0x4d0,
776                                 .security = 0x4d4,
777                         },
778                 },
779         }, {
780                 .id = TEGRA186_MEMORY_CLIENT_SCER,
781                 .name = "scer",
782                 .sid = TEGRA186_SID_SCE,
783                 .regs = {
784                         .sid = {
785                                 .override = 0x4d8,
786                                 .security = 0x4dc,
787                         },
788                 },
789         }, {
790                 .id = TEGRA186_MEMORY_CLIENT_SCEW,
791                 .name = "scew",
792                 .sid = TEGRA186_SID_SCE,
793                 .regs = {
794                         .sid = {
795                                 .override = 0x4e0,
796                                 .security = 0x4e4,
797                         },
798                 },
799         }, {
800                 .id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
801                 .name = "scedmar",
802                 .sid = TEGRA186_SID_SCE,
803                 .regs = {
804                         .sid = {
805                                 .override = 0x4e8,
806                                 .security = 0x4ec,
807                         },
808                 },
809         }, {
810                 .id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
811                 .name = "scedmaw",
812                 .sid = TEGRA186_SID_SCE,
813                 .regs = {
814                         .sid = {
815                                 .override = 0x4f0,
816                                 .security = 0x4f4,
817                         },
818                 },
819         }, {
820                 .id = TEGRA186_MEMORY_CLIENT_APEDMAR,
821                 .name = "apedmar",
822                 .sid = TEGRA186_SID_APE,
823                 .regs = {
824                         .sid = {
825                                 .override = 0x4f8,
826                                 .security = 0x4fc,
827                         },
828                 },
829         }, {
830                 .id = TEGRA186_MEMORY_CLIENT_APEDMAW,
831                 .name = "apedmaw",
832                 .sid = TEGRA186_SID_APE,
833                 .regs = {
834                         .sid = {
835                                 .override = 0x500,
836                                 .security = 0x504,
837                         },
838                 },
839         }, {
840                 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
841                 .name = "nvdisplayr1",
842                 .sid = TEGRA186_SID_NVDISPLAY,
843                 .regs = {
844                         .sid = {
845                                 .override = 0x508,
846                                 .security = 0x50c,
847                         },
848                 },
849         }, {
850                 .id = TEGRA186_MEMORY_CLIENT_VICSRD1,
851                 .name = "vicsrd1",
852                 .sid = TEGRA186_SID_VIC,
853                 .regs = {
854                         .sid = {
855                                 .override = 0x510,
856                                 .security = 0x514,
857                         },
858                 },
859         }, {
860                 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
861                 .name = "nvdecsrd1",
862                 .sid = TEGRA186_SID_NVDEC,
863                 .regs = {
864                         .sid = {
865                                 .override = 0x518,
866                                 .security = 0x51c,
867                         },
868                 },
869         },
870 };
871
872 const struct tegra_mc_soc tegra186_mc_soc = {
873         .num_clients = ARRAY_SIZE(tegra186_mc_clients),
874         .clients = tegra186_mc_clients,
875         .num_address_bits = 40,
876         .ops = &tegra186_mc_ops,
877 };
878 #endif