1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
7 #include <linux/of_device.h>
8 #include <linux/slab.h>
10 #include <dt-bindings/memory/tegra124-mc.h>
14 static const struct tegra_mc_client tegra124_mc_clients[] = {
18 .swgroup = TEGRA_SWGROUP_PTC,
28 .swgroup = TEGRA_SWGROUP_DC,
42 .swgroup = TEGRA_SWGROUP_DCB,
56 .swgroup = TEGRA_SWGROUP_DC,
70 .swgroup = TEGRA_SWGROUP_DCB,
84 .swgroup = TEGRA_SWGROUP_DC,
98 .swgroup = TEGRA_SWGROUP_DCB,
112 .swgroup = TEGRA_SWGROUP_AFI,
126 .swgroup = TEGRA_SWGROUP_AVPC,
140 .swgroup = TEGRA_SWGROUP_DC,
153 .name = "displayhcb",
154 .swgroup = TEGRA_SWGROUP_DCB,
168 .swgroup = TEGRA_SWGROUP_HDA,
181 .name = "host1xdmar",
182 .swgroup = TEGRA_SWGROUP_HC,
196 .swgroup = TEGRA_SWGROUP_HC,
210 .swgroup = TEGRA_SWGROUP_MSENC,
223 .name = "ppcsahbdmar",
224 .swgroup = TEGRA_SWGROUP_PPCS,
237 .name = "ppcsahbslvr",
238 .swgroup = TEGRA_SWGROUP_PPCS,
252 .swgroup = TEGRA_SWGROUP_SATA,
266 .swgroup = TEGRA_SWGROUP_VDE,
280 .swgroup = TEGRA_SWGROUP_VDE,
294 .swgroup = TEGRA_SWGROUP_VDE,
308 .swgroup = TEGRA_SWGROUP_VDE,
322 .swgroup = TEGRA_SWGROUP_MPCORELP,
332 .swgroup = TEGRA_SWGROUP_MPCORE,
342 .swgroup = TEGRA_SWGROUP_MSENC,
356 .swgroup = TEGRA_SWGROUP_AFI,
370 .swgroup = TEGRA_SWGROUP_AVPC,
384 .swgroup = TEGRA_SWGROUP_HDA,
398 .swgroup = TEGRA_SWGROUP_HC,
412 .swgroup = TEGRA_SWGROUP_MPCORELP,
422 .swgroup = TEGRA_SWGROUP_MPCORE,
431 .name = "ppcsahbdmaw",
432 .swgroup = TEGRA_SWGROUP_PPCS,
445 .name = "ppcsahbslvw",
446 .swgroup = TEGRA_SWGROUP_PPCS,
460 .swgroup = TEGRA_SWGROUP_SATA,
474 .swgroup = TEGRA_SWGROUP_VDE,
488 .swgroup = TEGRA_SWGROUP_VDE,
502 .swgroup = TEGRA_SWGROUP_VDE,
516 .swgroup = TEGRA_SWGROUP_VDE,
530 .swgroup = TEGRA_SWGROUP_ISP2,
544 .swgroup = TEGRA_SWGROUP_ISP2,
558 .swgroup = TEGRA_SWGROUP_ISP2,
571 .name = "xusb_hostr",
572 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
585 .name = "xusb_hostw",
586 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
600 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
614 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
628 .swgroup = TEGRA_SWGROUP_ISP2B,
642 .swgroup = TEGRA_SWGROUP_ISP2B,
656 .swgroup = TEGRA_SWGROUP_ISP2B,
670 .swgroup = TEGRA_SWGROUP_TSEC,
684 .swgroup = TEGRA_SWGROUP_TSEC,
698 .swgroup = TEGRA_SWGROUP_A9AVP,
712 .swgroup = TEGRA_SWGROUP_A9AVP,
726 .swgroup = TEGRA_SWGROUP_GPU,
741 .swgroup = TEGRA_SWGROUP_GPU,
756 .swgroup = TEGRA_SWGROUP_DC,
770 .swgroup = TEGRA_SWGROUP_SDMMC1A,
784 .swgroup = TEGRA_SWGROUP_SDMMC2A,
798 .swgroup = TEGRA_SWGROUP_SDMMC3A,
811 .swgroup = TEGRA_SWGROUP_SDMMC4A,
826 .swgroup = TEGRA_SWGROUP_SDMMC1A,
840 .swgroup = TEGRA_SWGROUP_SDMMC2A,
854 .swgroup = TEGRA_SWGROUP_SDMMC3A,
868 .swgroup = TEGRA_SWGROUP_SDMMC4A,
882 .swgroup = TEGRA_SWGROUP_VIC,
896 .swgroup = TEGRA_SWGROUP_VIC,
910 .swgroup = TEGRA_SWGROUP_VI,
924 .swgroup = TEGRA_SWGROUP_DC,
938 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
939 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
940 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
941 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
942 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
943 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
944 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
945 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
946 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
947 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
948 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
949 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
950 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
951 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
952 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
953 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
954 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
955 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
956 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
957 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
958 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
959 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
960 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
961 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
964 static const unsigned int tegra124_group_drm[] = {
970 static const struct tegra_smmu_group_soc tegra124_groups[] = {
973 .swgroups = tegra124_group_drm,
974 .num_swgroups = ARRAY_SIZE(tegra124_group_drm),
978 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
981 .id = TEGRA124_MC_RESET_##_name, \
982 .control = _control, \
987 static const struct tegra_mc_reset tegra124_mc_resets[] = {
988 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
989 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
990 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
991 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
992 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
993 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
994 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
995 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
996 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
997 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
998 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
999 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
1000 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
1001 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
1002 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
1003 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1004 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1005 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1006 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1007 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1008 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1009 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1010 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1011 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1014 static int tegra124_mc_icc_set(struct icc_node *src, struct icc_node *dst)
1016 /* TODO: program PTSA */
1020 static int tegra124_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
1021 u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
1024 * ISO clients need to reserve extra bandwidth up-front because
1025 * there could be high bandwidth pressure during initial filling
1026 * of the client's FIFO buffers. Secondly, we need to take into
1027 * account impurities of the memory subsystem.
1029 if (tag & TEGRA_MC_ICC_TAG_ISO)
1030 peak_bw = tegra_mc_scale_percents(peak_bw, 400);
1033 *agg_peak = max(*agg_peak, peak_bw);
1038 static struct icc_node_data *
1039 tegra124_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1041 struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
1042 const struct tegra_mc_client *client;
1043 unsigned int i, idx = spec->args[0];
1044 struct icc_node_data *ndata;
1045 struct icc_node *node;
1047 list_for_each_entry(node, &mc->provider.nodes, node_list) {
1048 if (node->id != idx)
1051 ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
1053 return ERR_PTR(-ENOMEM);
1055 client = &mc->soc->clients[idx];
1058 switch (client->swgroup) {
1059 case TEGRA_SWGROUP_DC:
1060 case TEGRA_SWGROUP_DCB:
1061 case TEGRA_SWGROUP_PTC:
1062 case TEGRA_SWGROUP_VI:
1063 /* these clients are isochronous by default */
1064 ndata->tag = TEGRA_MC_ICC_TAG_ISO;
1068 ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;
1075 for (i = 0; i < mc->soc->num_clients; i++) {
1076 if (mc->soc->clients[i].id == idx)
1077 return ERR_PTR(-EPROBE_DEFER);
1080 dev_err(mc->dev, "invalid ICC client ID %u\n", idx);
1082 return ERR_PTR(-EINVAL);
1085 static const struct tegra_mc_icc_ops tegra124_mc_icc_ops = {
1086 .xlate_extended = tegra124_mc_of_icc_xlate_extended,
1087 .aggregate = tegra124_mc_icc_aggreate,
1088 .set = tegra124_mc_icc_set,
1091 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1092 static const unsigned long tegra124_mc_emem_regs[] = {
1094 MC_EMEM_ARB_OUTSTANDING_REQ,
1095 MC_EMEM_ARB_TIMING_RCD,
1096 MC_EMEM_ARB_TIMING_RP,
1097 MC_EMEM_ARB_TIMING_RC,
1098 MC_EMEM_ARB_TIMING_RAS,
1099 MC_EMEM_ARB_TIMING_FAW,
1100 MC_EMEM_ARB_TIMING_RRD,
1101 MC_EMEM_ARB_TIMING_RAP2PRE,
1102 MC_EMEM_ARB_TIMING_WAP2PRE,
1103 MC_EMEM_ARB_TIMING_R2R,
1104 MC_EMEM_ARB_TIMING_W2W,
1105 MC_EMEM_ARB_TIMING_R2W,
1106 MC_EMEM_ARB_TIMING_W2R,
1107 MC_EMEM_ARB_DA_TURNS,
1108 MC_EMEM_ARB_DA_COVERS,
1111 MC_EMEM_ARB_RING1_THROTTLE
1114 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1115 .clients = tegra124_mc_clients,
1116 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1117 .swgroups = tegra124_swgroups,
1118 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1119 .groups = tegra124_groups,
1120 .num_groups = ARRAY_SIZE(tegra124_groups),
1121 .supports_round_robin_arbitration = true,
1122 .supports_request_limit = true,
1123 .num_tlb_lines = 32,
1127 const struct tegra_mc_soc tegra124_mc_soc = {
1128 .clients = tegra124_mc_clients,
1129 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1130 .num_address_bits = 34,
1132 .client_id_mask = 0x7f,
1133 .smmu = &tegra124_smmu_soc,
1134 .emem_regs = tegra124_mc_emem_regs,
1135 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1136 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1137 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1138 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1139 .reset_ops = &tegra_mc_reset_ops_common,
1140 .resets = tegra124_mc_resets,
1141 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1142 .icc_ops = &tegra124_mc_icc_ops,
1144 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1146 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1147 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1148 .clients = tegra124_mc_clients,
1149 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1150 .swgroups = tegra124_swgroups,
1151 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1152 .groups = tegra124_groups,
1153 .num_groups = ARRAY_SIZE(tegra124_groups),
1154 .supports_round_robin_arbitration = true,
1155 .supports_request_limit = true,
1156 .num_tlb_lines = 32,
1160 const struct tegra_mc_soc tegra132_mc_soc = {
1161 .clients = tegra124_mc_clients,
1162 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1163 .num_address_bits = 34,
1165 .client_id_mask = 0x7f,
1166 .smmu = &tegra132_smmu_soc,
1167 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1168 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1169 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1170 .reset_ops = &tegra_mc_reset_ops_common,
1171 .resets = tegra124_mc_resets,
1172 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1173 .icc_ops = &tegra124_mc_icc_ops,
1175 #endif /* CONFIG_ARCH_TEGRA_132_SOC */