1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
9 #include <dt-bindings/memory/tegra124-mc.h>
13 static const struct tegra_mc_client tegra124_mc_clients[] = {
17 .swgroup = TEGRA_SWGROUP_PTC,
27 .swgroup = TEGRA_SWGROUP_DC,
41 .swgroup = TEGRA_SWGROUP_DCB,
55 .swgroup = TEGRA_SWGROUP_DC,
69 .swgroup = TEGRA_SWGROUP_DCB,
83 .swgroup = TEGRA_SWGROUP_DC,
97 .swgroup = TEGRA_SWGROUP_DCB,
111 .swgroup = TEGRA_SWGROUP_AFI,
125 .swgroup = TEGRA_SWGROUP_AVPC,
139 .swgroup = TEGRA_SWGROUP_DC,
152 .name = "displayhcb",
153 .swgroup = TEGRA_SWGROUP_DCB,
167 .swgroup = TEGRA_SWGROUP_HDA,
180 .name = "host1xdmar",
181 .swgroup = TEGRA_SWGROUP_HC,
195 .swgroup = TEGRA_SWGROUP_HC,
209 .swgroup = TEGRA_SWGROUP_MSENC,
222 .name = "ppcsahbdmar",
223 .swgroup = TEGRA_SWGROUP_PPCS,
236 .name = "ppcsahbslvr",
237 .swgroup = TEGRA_SWGROUP_PPCS,
251 .swgroup = TEGRA_SWGROUP_SATA,
265 .swgroup = TEGRA_SWGROUP_VDE,
279 .swgroup = TEGRA_SWGROUP_VDE,
293 .swgroup = TEGRA_SWGROUP_VDE,
307 .swgroup = TEGRA_SWGROUP_VDE,
321 .swgroup = TEGRA_SWGROUP_MPCORELP,
331 .swgroup = TEGRA_SWGROUP_MPCORE,
341 .swgroup = TEGRA_SWGROUP_MSENC,
355 .swgroup = TEGRA_SWGROUP_AFI,
369 .swgroup = TEGRA_SWGROUP_AVPC,
383 .swgroup = TEGRA_SWGROUP_HDA,
397 .swgroup = TEGRA_SWGROUP_HC,
411 .swgroup = TEGRA_SWGROUP_MPCORELP,
421 .swgroup = TEGRA_SWGROUP_MPCORE,
430 .name = "ppcsahbdmaw",
431 .swgroup = TEGRA_SWGROUP_PPCS,
444 .name = "ppcsahbslvw",
445 .swgroup = TEGRA_SWGROUP_PPCS,
459 .swgroup = TEGRA_SWGROUP_SATA,
473 .swgroup = TEGRA_SWGROUP_VDE,
487 .swgroup = TEGRA_SWGROUP_VDE,
501 .swgroup = TEGRA_SWGROUP_VDE,
515 .swgroup = TEGRA_SWGROUP_VDE,
529 .swgroup = TEGRA_SWGROUP_ISP2,
543 .swgroup = TEGRA_SWGROUP_ISP2,
557 .swgroup = TEGRA_SWGROUP_ISP2,
570 .name = "xusb_hostr",
571 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
584 .name = "xusb_hostw",
585 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
599 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
613 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
627 .swgroup = TEGRA_SWGROUP_ISP2B,
641 .swgroup = TEGRA_SWGROUP_ISP2B,
655 .swgroup = TEGRA_SWGROUP_ISP2B,
669 .swgroup = TEGRA_SWGROUP_TSEC,
683 .swgroup = TEGRA_SWGROUP_TSEC,
697 .swgroup = TEGRA_SWGROUP_A9AVP,
711 .swgroup = TEGRA_SWGROUP_A9AVP,
725 .swgroup = TEGRA_SWGROUP_GPU,
740 .swgroup = TEGRA_SWGROUP_GPU,
755 .swgroup = TEGRA_SWGROUP_DC,
769 .swgroup = TEGRA_SWGROUP_SDMMC1A,
783 .swgroup = TEGRA_SWGROUP_SDMMC2A,
797 .swgroup = TEGRA_SWGROUP_SDMMC3A,
810 .swgroup = TEGRA_SWGROUP_SDMMC4A,
825 .swgroup = TEGRA_SWGROUP_SDMMC1A,
839 .swgroup = TEGRA_SWGROUP_SDMMC2A,
853 .swgroup = TEGRA_SWGROUP_SDMMC3A,
867 .swgroup = TEGRA_SWGROUP_SDMMC4A,
881 .swgroup = TEGRA_SWGROUP_VIC,
895 .swgroup = TEGRA_SWGROUP_VIC,
909 .swgroup = TEGRA_SWGROUP_VI,
923 .swgroup = TEGRA_SWGROUP_DC,
937 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
938 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
939 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
940 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
941 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
942 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
943 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
944 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
945 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
946 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
947 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
948 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
949 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
950 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
951 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
952 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
953 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
954 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
955 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
956 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
957 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
958 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
959 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
960 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
963 static const unsigned int tegra124_group_drm[] = {
969 static const struct tegra_smmu_group_soc tegra124_groups[] = {
972 .swgroups = tegra124_group_drm,
973 .num_swgroups = ARRAY_SIZE(tegra124_group_drm),
977 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
980 .id = TEGRA124_MC_RESET_##_name, \
981 .control = _control, \
986 static const struct tegra_mc_reset tegra124_mc_resets[] = {
987 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
988 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
989 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
990 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
991 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
992 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
993 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
994 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
995 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
996 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
997 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
998 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
999 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
1000 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
1001 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
1002 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1003 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1004 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1005 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1006 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1007 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1008 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1009 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1010 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1013 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1014 static const unsigned long tegra124_mc_emem_regs[] = {
1016 MC_EMEM_ARB_OUTSTANDING_REQ,
1017 MC_EMEM_ARB_TIMING_RCD,
1018 MC_EMEM_ARB_TIMING_RP,
1019 MC_EMEM_ARB_TIMING_RC,
1020 MC_EMEM_ARB_TIMING_RAS,
1021 MC_EMEM_ARB_TIMING_FAW,
1022 MC_EMEM_ARB_TIMING_RRD,
1023 MC_EMEM_ARB_TIMING_RAP2PRE,
1024 MC_EMEM_ARB_TIMING_WAP2PRE,
1025 MC_EMEM_ARB_TIMING_R2R,
1026 MC_EMEM_ARB_TIMING_W2W,
1027 MC_EMEM_ARB_TIMING_R2W,
1028 MC_EMEM_ARB_TIMING_W2R,
1029 MC_EMEM_ARB_DA_TURNS,
1030 MC_EMEM_ARB_DA_COVERS,
1033 MC_EMEM_ARB_RING1_THROTTLE
1036 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1037 .clients = tegra124_mc_clients,
1038 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1039 .swgroups = tegra124_swgroups,
1040 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1041 .groups = tegra124_groups,
1042 .num_groups = ARRAY_SIZE(tegra124_groups),
1043 .supports_round_robin_arbitration = true,
1044 .supports_request_limit = true,
1045 .num_tlb_lines = 32,
1049 const struct tegra_mc_soc tegra124_mc_soc = {
1050 .clients = tegra124_mc_clients,
1051 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1052 .num_address_bits = 34,
1054 .client_id_mask = 0x7f,
1055 .smmu = &tegra124_smmu_soc,
1056 .emem_regs = tegra124_mc_emem_regs,
1057 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1058 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1059 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1060 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1061 .reset_ops = &tegra_mc_reset_ops_common,
1062 .resets = tegra124_mc_resets,
1063 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1065 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1067 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1068 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1069 .clients = tegra124_mc_clients,
1070 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1071 .swgroups = tegra124_swgroups,
1072 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1073 .groups = tegra124_groups,
1074 .num_groups = ARRAY_SIZE(tegra124_groups),
1075 .supports_round_robin_arbitration = true,
1076 .supports_request_limit = true,
1077 .num_tlb_lines = 32,
1081 const struct tegra_mc_soc tegra132_mc_soc = {
1082 .clients = tegra124_mc_clients,
1083 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1084 .num_address_bits = 34,
1086 .client_id_mask = 0x7f,
1087 .smmu = &tegra132_smmu_soc,
1088 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1089 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1090 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1091 .reset_ops = &tegra_mc_reset_ops_common,
1092 .resets = tegra124_mc_resets,
1093 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1095 #endif /* CONFIG_ARCH_TEGRA_132_SOC */