drivers/memory/tegra/tegra124.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/of.h>
   7 #include <linux/mm.h>
   8
   9 #include <dt-bindings/memory/tegra124-mc.h>
  10
  11 #include "mc.h"
  12
  13 static const struct tegra_mc_client tegra124_mc_clients[] = {
  14         {
  15                 .id = 0x00,
  16                 .name = "ptcr",
  17                 .swgroup = TEGRA_SWGROUP_PTC,
  18                 .la = {
  19                         .reg = 0x34c,
  20                         .shift = 0,
  21                         .mask = 0xff,
  22                         .def = 0x0,
  23                 },
  24         }, {
  25                 .id = 0x01,
  26                 .name = "display0a",
  27                 .swgroup = TEGRA_SWGROUP_DC,
  28                 .smmu = {
  29                         .reg = 0x228,
  30                         .bit = 1,
  31                 },
  32                 .la = {
  33                         .reg = 0x2e8,
  34                         .shift = 0,
  35                         .mask = 0xff,
  36                         .def = 0xc2,
  37                 },
  38         }, {
  39                 .id = 0x02,
  40                 .name = "display0ab",
  41                 .swgroup = TEGRA_SWGROUP_DCB,
  42                 .smmu = {
  43                         .reg = 0x228,
  44                         .bit = 2,
  45                 },
  46                 .la = {
  47                         .reg = 0x2f4,
  48                         .shift = 0,
  49                         .mask = 0xff,
  50                         .def = 0xc6,
  51                 },
  52         }, {
  53                 .id = 0x03,
  54                 .name = "display0b",
  55                 .swgroup = TEGRA_SWGROUP_DC,
  56                 .smmu = {
  57                         .reg = 0x228,
  58                         .bit = 3,
  59                 },
  60                 .la = {
  61                         .reg = 0x2e8,
  62                         .shift = 16,
  63                         .mask = 0xff,
  64                         .def = 0x50,
  65                 },
  66         }, {
  67                 .id = 0x04,
  68                 .name = "display0bb",
  69                 .swgroup = TEGRA_SWGROUP_DCB,
  70                 .smmu = {
  71                         .reg = 0x228,
  72                         .bit = 4,
  73                 },
  74                 .la = {
  75                         .reg = 0x2f4,
  76                         .shift = 16,
  77                         .mask = 0xff,
  78                         .def = 0x50,
  79                 },
  80         }, {
  81                 .id = 0x05,
  82                 .name = "display0c",
  83                 .swgroup = TEGRA_SWGROUP_DC,
  84                 .smmu = {
  85                         .reg = 0x228,
  86                         .bit = 5,
  87                 },
  88                 .la = {
  89                         .reg = 0x2ec,
  90                         .shift = 0,
  91                         .mask = 0xff,
  92                         .def = 0x50,
  93                 },
  94         }, {
  95                 .id = 0x06,
  96                 .name = "display0cb",
  97                 .swgroup = TEGRA_SWGROUP_DCB,
  98                 .smmu = {
  99                         .reg = 0x228,
 100                         .bit = 6,
 101                 },
 102                 .la = {
 103                         .reg = 0x2f8,
 104                         .shift = 0,
 105                         .mask = 0xff,
 106                         .def = 0x50,
 107                 },
 108         }, {
 109                 .id = 0x0e,
 110                 .name = "afir",
 111                 .swgroup = TEGRA_SWGROUP_AFI,
 112                 .smmu = {
 113                         .reg = 0x228,
 114                         .bit = 14,
 115                 },
 116                 .la = {
 117                         .reg = 0x2e0,
 118                         .shift = 0,
 119                         .mask = 0xff,
 120                         .def = 0x13,
 121                 },
 122         }, {
 123                 .id = 0x0f,
 124                 .name = "avpcarm7r",
 125                 .swgroup = TEGRA_SWGROUP_AVPC,
 126                 .smmu = {
 127                         .reg = 0x228,
 128                         .bit = 15,
 129                 },
 130                 .la = {
 131                         .reg = 0x2e4,
 132                         .shift = 0,
 133                         .mask = 0xff,
 134                         .def = 0x04,
 135                 },
 136         }, {
 137                 .id = 0x10,
 138                 .name = "displayhc",
 139                 .swgroup = TEGRA_SWGROUP_DC,
 140                 .smmu = {
 141                         .reg = 0x228,
 142                         .bit = 16,
 143                 },
 144                 .la = {
 145                         .reg = 0x2f0,
 146                         .shift = 0,
 147                         .mask = 0xff,
 148                         .def = 0x50,
 149                 },
 150         }, {
 151                 .id = 0x11,
 152                 .name = "displayhcb",
 153                 .swgroup = TEGRA_SWGROUP_DCB,
 154                 .smmu = {
 155                         .reg = 0x228,
 156                         .bit = 17,
 157                 },
 158                 .la = {
 159                         .reg = 0x2fc,
 160                         .shift = 0,
 161                         .mask = 0xff,
 162                         .def = 0x50,
 163                 },
 164         }, {
 165                 .id = 0x15,
 166                 .name = "hdar",
 167                 .swgroup = TEGRA_SWGROUP_HDA,
 168                 .smmu = {
 169                         .reg = 0x228,
 170                         .bit = 21,
 171                 },
 172                 .la = {
 173                         .reg = 0x318,
 174                         .shift = 0,
 175                         .mask = 0xff,
 176                         .def = 0x24,
 177                 },
 178         }, {
 179                 .id = 0x16,
 180                 .name = "host1xdmar",
 181                 .swgroup = TEGRA_SWGROUP_HC,
 182                 .smmu = {
 183                         .reg = 0x228,
 184                         .bit = 22,
 185                 },
 186                 .la = {
 187                         .reg = 0x310,
 188                         .shift = 0,
 189                         .mask = 0xff,
 190                         .def = 0x1e,
 191                 },
 192         }, {
 193                 .id = 0x17,
 194                 .name = "host1xr",
 195                 .swgroup = TEGRA_SWGROUP_HC,
 196                 .smmu = {
 197                         .reg = 0x228,
 198                         .bit = 23,
 199                 },
 200                 .la = {
 201                         .reg = 0x310,
 202                         .shift = 16,
 203                         .mask = 0xff,
 204                         .def = 0x50,
 205                 },
 206         }, {
 207                 .id = 0x1c,
 208                 .name = "msencsrd",
 209                 .swgroup = TEGRA_SWGROUP_MSENC,
 210                 .smmu = {
 211                         .reg = 0x228,
 212                         .bit = 28,
 213                 },
 214                 .la = {
 215                         .reg = 0x328,
 216                         .shift = 0,
 217                         .mask = 0xff,
 218                         .def = 0x23,
 219                 },
 220         }, {
 221                 .id = 0x1d,
 222                 .name = "ppcsahbdmar",
 223                 .swgroup = TEGRA_SWGROUP_PPCS,
 224                 .smmu = {
 225                         .reg = 0x228,
 226                         .bit = 29,
 227                 },
 228                 .la = {
 229                         .reg = 0x344,
 230                         .shift = 0,
 231                         .mask = 0xff,
 232                         .def = 0x49,
 233                 },
 234         }, {
 235                 .id = 0x1e,
 236                 .name = "ppcsahbslvr",
 237                 .swgroup = TEGRA_SWGROUP_PPCS,
 238                 .smmu = {
 239                         .reg = 0x228,
 240                         .bit = 30,
 241                 },
 242                 .la = {
 243                         .reg = 0x344,
 244                         .shift = 16,
 245                         .mask = 0xff,
 246                         .def = 0x1a,
 247                 },
 248         }, {
 249                 .id = 0x1f,
 250                 .name = "satar",
 251                 .swgroup = TEGRA_SWGROUP_SATA,
 252                 .smmu = {
 253                         .reg = 0x228,
 254                         .bit = 31,
 255                 },
 256                 .la = {
 257                         .reg = 0x350,
 258                         .shift = 0,
 259                         .mask = 0xff,
 260                         .def = 0x65,
 261                 },
 262         }, {
 263                 .id = 0x22,
 264                 .name = "vdebsevr",
 265                 .swgroup = TEGRA_SWGROUP_VDE,
 266                 .smmu = {
 267                         .reg = 0x22c,
 268                         .bit = 2,
 269                 },
 270                 .la = {
 271                         .reg = 0x354,
 272                         .shift = 0,
 273                         .mask = 0xff,
 274                         .def = 0x4f,
 275                 },
 276         }, {
 277                 .id = 0x23,
 278                 .name = "vdember",
 279                 .swgroup = TEGRA_SWGROUP_VDE,
 280                 .smmu = {
 281                         .reg = 0x22c,
 282                         .bit = 3,
 283                 },
 284                 .la = {
 285                         .reg = 0x354,
 286                         .shift = 16,
 287                         .mask = 0xff,
 288                         .def = 0x3d,
 289                 },
 290         }, {
 291                 .id = 0x24,
 292                 .name = "vdemcer",
 293                 .swgroup = TEGRA_SWGROUP_VDE,
 294                 .smmu = {
 295                         .reg = 0x22c,
 296                         .bit = 4,
 297                 },
 298                 .la = {
 299                         .reg = 0x358,
 300                         .shift = 0,
 301                         .mask = 0xff,
 302                         .def = 0x66,
 303                 },
 304         }, {
 305                 .id = 0x25,
 306                 .name = "vdetper",
 307                 .swgroup = TEGRA_SWGROUP_VDE,
 308                 .smmu = {
 309                         .reg = 0x22c,
 310                         .bit = 5,
 311                 },
 312                 .la = {
 313                         .reg = 0x358,
 314                         .shift = 16,
 315                         .mask = 0xff,
 316                         .def = 0xa5,
 317                 },
 318         }, {
 319                 .id = 0x26,
 320                 .name = "mpcorelpr",
 321                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 322                 .la = {
 323                         .reg = 0x324,
 324                         .shift = 0,
 325                         .mask = 0xff,
 326                         .def = 0x04,
 327                 },
 328         }, {
 329                 .id = 0x27,
 330                 .name = "mpcorer",
 331                 .swgroup = TEGRA_SWGROUP_MPCORE,
 332                 .la = {
 333                         .reg = 0x320,
 334                         .shift = 0,
 335                         .mask = 0xff,
 336                         .def = 0x04,
 337                 },
 338         }, {
 339                 .id = 0x2b,
 340                 .name = "msencswr",
 341                 .swgroup = TEGRA_SWGROUP_MSENC,
 342                 .smmu = {
 343                         .reg = 0x22c,
 344                         .bit = 11,
 345                 },
 346                 .la = {
 347                         .reg = 0x328,
 348                         .shift = 16,
 349                         .mask = 0xff,
 350                         .def = 0x80,
 351                 },
 352         }, {
 353                 .id = 0x31,
 354                 .name = "afiw",
 355                 .swgroup = TEGRA_SWGROUP_AFI,
 356                 .smmu = {
 357                         .reg = 0x22c,
 358                         .bit = 17,
 359                 },
 360                 .la = {
 361                         .reg = 0x2e0,
 362                         .shift = 16,
 363                         .mask = 0xff,
 364                         .def = 0x80,
 365                 },
 366         }, {
 367                 .id = 0x32,
 368                 .name = "avpcarm7w",
 369                 .swgroup = TEGRA_SWGROUP_AVPC,
 370                 .smmu = {
 371                         .reg = 0x22c,
 372                         .bit = 18,
 373                 },
 374                 .la = {
 375                         .reg = 0x2e4,
 376                         .shift = 16,
 377                         .mask = 0xff,
 378                         .def = 0x80,
 379                 },
 380         }, {
 381                 .id = 0x35,
 382                 .name = "hdaw",
 383                 .swgroup = TEGRA_SWGROUP_HDA,
 384                 .smmu = {
 385                         .reg = 0x22c,
 386                         .bit = 21,
 387                 },
 388                 .la = {
 389                         .reg = 0x318,
 390                         .shift = 16,
 391                         .mask = 0xff,
 392                         .def = 0x80,
 393                 },
 394         }, {
 395                 .id = 0x36,
 396                 .name = "host1xw",
 397                 .swgroup = TEGRA_SWGROUP_HC,
 398                 .smmu = {
 399                         .reg = 0x22c,
 400                         .bit = 22,
 401                 },
 402                 .la = {
 403                         .reg = 0x314,
 404                         .shift = 0,
 405                         .mask = 0xff,
 406                         .def = 0x80,
 407                 },
 408         }, {
 409                 .id = 0x38,
 410                 .name = "mpcorelpw",
 411                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 412                 .la = {
 413                         .reg = 0x324,
 414                         .shift = 16,
 415                         .mask = 0xff,
 416                         .def = 0x80,
 417                 },
 418         }, {
 419                 .id = 0x39,
 420                 .name = "mpcorew",
 421                 .swgroup = TEGRA_SWGROUP_MPCORE,
 422                 .la = {
 423                         .reg = 0x320,
 424                         .shift = 16,
 425                         .mask = 0xff,
 426                         .def = 0x80,
 427                 },
 428         }, {
 429                 .id = 0x3b,
 430                 .name = "ppcsahbdmaw",
 431                 .swgroup = TEGRA_SWGROUP_PPCS,
 432                 .smmu = {
 433                         .reg = 0x22c,
 434                         .bit = 27,
 435                 },
 436                 .la = {
 437                         .reg = 0x348,
 438                         .shift = 0,
 439                         .mask = 0xff,
 440                         .def = 0x80,
 441                 },
 442         }, {
 443                 .id = 0x3c,
 444                 .name = "ppcsahbslvw",
 445                 .swgroup = TEGRA_SWGROUP_PPCS,
 446                 .smmu = {
 447                         .reg = 0x22c,
 448                         .bit = 28,
 449                 },
 450                 .la = {
 451                         .reg = 0x348,
 452                         .shift = 16,
 453                         .mask = 0xff,
 454                         .def = 0x80,
 455                 },
 456         }, {
 457                 .id = 0x3d,
 458                 .name = "sataw",
 459                 .swgroup = TEGRA_SWGROUP_SATA,
 460                 .smmu = {
 461                         .reg = 0x22c,
 462                         .bit = 29,
 463                 },
 464                 .la = {
 465                         .reg = 0x350,
 466                         .shift = 16,
 467                         .mask = 0xff,
 468                         .def = 0x65,
 469                 },
 470         }, {
 471                 .id = 0x3e,
 472                 .name = "vdebsevw",
 473                 .swgroup = TEGRA_SWGROUP_VDE,
 474                 .smmu = {
 475                         .reg = 0x22c,
 476                         .bit = 30,
 477                 },
 478                 .la = {
 479                         .reg = 0x35c,
 480                         .shift = 0,
 481                         .mask = 0xff,
 482                         .def = 0x80,
 483                 },
 484         }, {
 485                 .id = 0x3f,
 486                 .name = "vdedbgw",
 487                 .swgroup = TEGRA_SWGROUP_VDE,
 488                 .smmu = {
 489                         .reg = 0x22c,
 490                         .bit = 31,
 491                 },
 492                 .la = {
 493                         .reg = 0x35c,
 494                         .shift = 16,
 495                         .mask = 0xff,
 496                         .def = 0x80,
 497                 },
 498         }, {
 499                 .id = 0x40,
 500                 .name = "vdembew",
 501                 .swgroup = TEGRA_SWGROUP_VDE,
 502                 .smmu = {
 503                         .reg = 0x230,
 504                         .bit = 0,
 505                 },
 506                 .la = {
 507                         .reg = 0x360,
 508                         .shift = 0,
 509                         .mask = 0xff,
 510                         .def = 0x80,
 511                 },
 512         }, {
 513                 .id = 0x41,
 514                 .name = "vdetpmw",
 515                 .swgroup = TEGRA_SWGROUP_VDE,
 516                 .smmu = {
 517                         .reg = 0x230,
 518                         .bit = 1,
 519                 },
 520                 .la = {
 521                         .reg = 0x360,
 522                         .shift = 16,
 523                         .mask = 0xff,
 524                         .def = 0x80,
 525                 },
 526         }, {
 527                 .id = 0x44,
 528                 .name = "ispra",
 529                 .swgroup = TEGRA_SWGROUP_ISP2,
 530                 .smmu = {
 531                         .reg = 0x230,
 532                         .bit = 4,
 533                 },
 534                 .la = {
 535                         .reg = 0x370,
 536                         .shift = 0,
 537                         .mask = 0xff,
 538                         .def = 0x18,
 539                 },
 540         }, {
 541                 .id = 0x46,
 542                 .name = "ispwa",
 543                 .swgroup = TEGRA_SWGROUP_ISP2,
 544                 .smmu = {
 545                         .reg = 0x230,
 546                         .bit = 6,
 547                 },
 548                 .la = {
 549                         .reg = 0x374,
 550                         .shift = 0,
 551                         .mask = 0xff,
 552                         .def = 0x80,
 553                 },
 554         }, {
 555                 .id = 0x47,
 556                 .name = "ispwb",
 557                 .swgroup = TEGRA_SWGROUP_ISP2,
 558                 .smmu = {
 559                         .reg = 0x230,
 560                         .bit = 7,
 561                 },
 562                 .la = {
 563                         .reg = 0x374,
 564                         .shift = 16,
 565                         .mask = 0xff,
 566                         .def = 0x80,
 567                 },
 568         }, {
 569                 .id = 0x4a,
 570                 .name = "xusb_hostr",
 571                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 572                 .smmu = {
 573                         .reg = 0x230,
 574                         .bit = 10,
 575                 },
 576                 .la = {
 577                         .reg = 0x37c,
 578                         .shift = 0,
 579                         .mask = 0xff,
 580                         .def = 0x39,
 581                 },
 582         }, {
 583                 .id = 0x4b,
 584                 .name = "xusb_hostw",
 585                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 586                 .smmu = {
 587                         .reg = 0x230,
 588                         .bit = 11,
 589                 },
 590                 .la = {
 591                         .reg = 0x37c,
 592                         .shift = 16,
 593                         .mask = 0xff,
 594                         .def = 0x80,
 595                 },
 596         }, {
 597                 .id = 0x4c,
 598                 .name = "xusb_devr",
 599                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 600                 .smmu = {
 601                         .reg = 0x230,
 602                         .bit = 12,
 603                 },
 604                 .la = {
 605                         .reg = 0x380,
 606                         .shift = 0,
 607                         .mask = 0xff,
 608                         .def = 0x39,
 609                 },
 610         }, {
 611                 .id = 0x4d,
 612                 .name = "xusb_devw",
 613                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 614                 .smmu = {
 615                         .reg = 0x230,
 616                         .bit = 13,
 617                 },
 618                 .la = {
 619                         .reg = 0x380,
 620                         .shift = 16,
 621                         .mask = 0xff,
 622                         .def = 0x80,
 623                 },
 624         }, {
 625                 .id = 0x4e,
 626                 .name = "isprab",
 627                 .swgroup = TEGRA_SWGROUP_ISP2B,
 628                 .smmu = {
 629                         .reg = 0x230,
 630                         .bit = 14,
 631                 },
 632                 .la = {
 633                         .reg = 0x384,
 634                         .shift = 0,
 635                         .mask = 0xff,
 636                         .def = 0x18,
 637                 },
 638         }, {
 639                 .id = 0x50,
 640                 .name = "ispwab",
 641                 .swgroup = TEGRA_SWGROUP_ISP2B,
 642                 .smmu = {
 643                         .reg = 0x230,
 644                         .bit = 16,
 645                 },
 646                 .la = {
 647                         .reg = 0x388,
 648                         .shift = 0,
 649                         .mask = 0xff,
 650                         .def = 0x80,
 651                 },
 652         }, {
 653                 .id = 0x51,
 654                 .name = "ispwbb",
 655                 .swgroup = TEGRA_SWGROUP_ISP2B,
 656                 .smmu = {
 657                         .reg = 0x230,
 658                         .bit = 17,
 659                 },
 660                 .la = {
 661                         .reg = 0x388,
 662                         .shift = 16,
 663                         .mask = 0xff,
 664                         .def = 0x80,
 665                 },
 666         }, {
 667                 .id = 0x54,
 668                 .name = "tsecsrd",
 669                 .swgroup = TEGRA_SWGROUP_TSEC,
 670                 .smmu = {
 671                         .reg = 0x230,
 672                         .bit = 20,
 673                 },
 674                 .la = {
 675                         .reg = 0x390,
 676                         .shift = 0,
 677                         .mask = 0xff,
 678                         .def = 0x9b,
 679                 },
 680         }, {
 681                 .id = 0x55,
 682                 .name = "tsecswr",
 683                 .swgroup = TEGRA_SWGROUP_TSEC,
 684                 .smmu = {
 685                         .reg = 0x230,
 686                         .bit = 21,
 687                 },
 688                 .la = {
 689                         .reg = 0x390,
 690                         .shift = 16,
 691                         .mask = 0xff,
 692                         .def = 0x80,
 693                 },
 694         }, {
 695                 .id = 0x56,
 696                 .name = "a9avpscr",
 697                 .swgroup = TEGRA_SWGROUP_A9AVP,
 698                 .smmu = {
 699                         .reg = 0x230,
 700                         .bit = 22,
 701                 },
 702                 .la = {
 703                         .reg = 0x3a4,
 704                         .shift = 0,
 705                         .mask = 0xff,
 706                         .def = 0x04,
 707                 },
 708         }, {
 709                 .id = 0x57,
 710                 .name = "a9avpscw",
 711                 .swgroup = TEGRA_SWGROUP_A9AVP,
 712                 .smmu = {
 713                         .reg = 0x230,
 714                         .bit = 23,
 715                 },
 716                 .la = {
 717                         .reg = 0x3a4,
 718                         .shift = 16,
 719                         .mask = 0xff,
 720                         .def = 0x80,
 721                 },
 722         }, {
 723                 .id = 0x58,
 724                 .name = "gpusrd",
 725                 .swgroup = TEGRA_SWGROUP_GPU,
 726                 .smmu = {
 727                         /* read-only */
 728                         .reg = 0x230,
 729                         .bit = 24,
 730                 },
 731                 .la = {
 732                         .reg = 0x3c8,
 733                         .shift = 0,
 734                         .mask = 0xff,
 735                         .def = 0x1a,
 736                 },
 737         }, {
 738                 .id = 0x59,
 739                 .name = "gpuswr",
 740                 .swgroup = TEGRA_SWGROUP_GPU,
 741                 .smmu = {
 742                         /* read-only */
 743                         .reg = 0x230,
 744                         .bit = 25,
 745                 },
 746                 .la = {
 747                         .reg = 0x3c8,
 748                         .shift = 16,
 749                         .mask = 0xff,
 750                         .def = 0x80,
 751                 },
 752         }, {
 753                 .id = 0x5a,
 754                 .name = "displayt",
 755                 .swgroup = TEGRA_SWGROUP_DC,
 756                 .smmu = {
 757                         .reg = 0x230,
 758                         .bit = 26,
 759                 },
 760                 .la = {
 761                         .reg = 0x2f0,
 762                         .shift = 16,
 763                         .mask = 0xff,
 764                         .def = 0x50,
 765                 },
 766         }, {
 767                 .id = 0x60,
 768                 .name = "sdmmcra",
 769                 .swgroup = TEGRA_SWGROUP_SDMMC1A,
 770                 .smmu = {
 771                         .reg = 0x234,
 772                         .bit = 0,
 773                 },
 774                 .la = {
 775                         .reg = 0x3b8,
 776                         .shift = 0,
 777                         .mask = 0xff,
 778                         .def = 0x49,
 779                 },
 780         }, {
 781                 .id = 0x61,
 782                 .name = "sdmmcraa",
 783                 .swgroup = TEGRA_SWGROUP_SDMMC2A,
 784                 .smmu = {
 785                         .reg = 0x234,
 786                         .bit = 1,
 787                 },
 788                 .la = {
 789                         .reg = 0x3bc,
 790                         .shift = 0,
 791                         .mask = 0xff,
 792                         .def = 0x49,
 793                 },
 794         }, {
 795                 .id = 0x62,
 796                 .name = "sdmmcr",
 797                 .swgroup = TEGRA_SWGROUP_SDMMC3A,
 798                 .smmu = {
 799                         .reg = 0x234,
 800                         .bit = 2,
 801                 },
 802                 .la = {
 803                         .reg = 0x3c0,
 804                         .shift = 0,
 805                         .mask = 0xff,
 806                         .def = 0x49,
 807                 },
 808         }, {
 809                 .id = 0x63,
 810                 .swgroup = TEGRA_SWGROUP_SDMMC4A,
 811                 .name = "sdmmcrab",
 812                 .smmu = {
 813                         .reg = 0x234,
 814                         .bit = 3,
 815                 },
 816                 .la = {
 817                         .reg = 0x3c4,
 818                         .shift = 0,
 819                         .mask = 0xff,
 820                         .def = 0x49,
 821                 },
 822         }, {
 823                 .id = 0x64,
 824                 .name = "sdmmcwa",
 825                 .swgroup = TEGRA_SWGROUP_SDMMC1A,
 826                 .smmu = {
 827                         .reg = 0x234,
 828                         .bit = 4,
 829                 },
 830                 .la = {
 831                         .reg = 0x3b8,
 832                         .shift = 16,
 833                         .mask = 0xff,
 834                         .def = 0x80,
 835                 },
 836         }, {
 837                 .id = 0x65,
 838                 .name = "sdmmcwaa",
 839                 .swgroup = TEGRA_SWGROUP_SDMMC2A,
 840                 .smmu = {
 841                         .reg = 0x234,
 842                         .bit = 5,
 843                 },
 844                 .la = {
 845                         .reg = 0x3bc,
 846                         .shift = 16,
 847                         .mask = 0xff,
 848                         .def = 0x80,
 849                 },
 850         }, {
 851                 .id = 0x66,
 852                 .name = "sdmmcw",
 853                 .swgroup = TEGRA_SWGROUP_SDMMC3A,
 854                 .smmu = {
 855                         .reg = 0x234,
 856                         .bit = 6,
 857                 },
 858                 .la = {
 859                         .reg = 0x3c0,
 860                         .shift = 16,
 861                         .mask = 0xff,
 862                         .def = 0x80,
 863                 },
 864         }, {
 865                 .id = 0x67,
 866                 .name = "sdmmcwab",
 867                 .swgroup = TEGRA_SWGROUP_SDMMC4A,
 868                 .smmu = {
 869                         .reg = 0x234,
 870                         .bit = 7,
 871                 },
 872                 .la = {
 873                         .reg = 0x3c4,
 874                         .shift = 16,
 875                         .mask = 0xff,
 876                         .def = 0x80,
 877                 },
 878         }, {
 879                 .id = 0x6c,
 880                 .name = "vicsrd",
 881                 .swgroup = TEGRA_SWGROUP_VIC,
 882                 .smmu = {
 883                         .reg = 0x234,
 884                         .bit = 12,
 885                 },
 886                 .la = {
 887                         .reg = 0x394,
 888                         .shift = 0,
 889                         .mask = 0xff,
 890                         .def = 0x1a,
 891                 },
 892         }, {
 893                 .id = 0x6d,
 894                 .name = "vicswr",
 895                 .swgroup = TEGRA_SWGROUP_VIC,
 896                 .smmu = {
 897                         .reg = 0x234,
 898                         .bit = 13,
 899                 },
 900                 .la = {
 901                         .reg = 0x394,
 902                         .shift = 16,
 903                         .mask = 0xff,
 904                         .def = 0x80,
 905                 },
 906         }, {
 907                 .id = 0x72,
 908                 .name = "viw",
 909                 .swgroup = TEGRA_SWGROUP_VI,
 910                 .smmu = {
 911                         .reg = 0x234,
 912                         .bit = 18,
 913                 },
 914                 .la = {
 915                         .reg = 0x398,
 916                         .shift = 0,
 917                         .mask = 0xff,
 918                         .def = 0x80,
 919                 },
 920         }, {
 921                 .id = 0x73,
 922                 .name = "displayd",
 923                 .swgroup = TEGRA_SWGROUP_DC,
 924                 .smmu = {
 925                         .reg = 0x234,
 926                         .bit = 19,
 927                 },
 928                 .la = {
 929                         .reg = 0x3c8,
 930                         .shift = 0,
 931                         .mask = 0xff,
 932                         .def = 0x50,
 933                 },
 934         },
 935 };
 936
 937 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
 938         { .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
 939         { .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
 940         { .name = "afi",       .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },
 941         { .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
 942         { .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
 943         { .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
 944         { .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
 945         { .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
 946         { .name = "sata",      .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },
 947         { .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
 948         { .name = "isp2",      .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },
 949         { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
 950         { .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
 951         { .name = "isp2b",     .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },
 952         { .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
 953         { .name = "a9avp",     .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },
 954         { .name = "gpu",       .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },
 955         { .name = "sdmmc1a",   .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },
 956         { .name = "sdmmc2a",   .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },
 957         { .name = "sdmmc3a",   .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },
 958         { .name = "sdmmc4a",   .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },
 959         { .name = "vic",       .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },
 960         { .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
 961 };
 962
 963 static const unsigned int tegra124_group_drm[] = {
 964         TEGRA_SWGROUP_DC,
 965         TEGRA_SWGROUP_DCB,
 966         TEGRA_SWGROUP_VIC,
 967 };
 968
 969 static const struct tegra_smmu_group_soc tegra124_groups[] = {
 970         {
 971                 .name = "drm",
 972                 .swgroups = tegra124_group_drm,
 973                 .num_swgroups = ARRAY_SIZE(tegra124_group_drm),
 974         },
 975 };
 976
 977 #define TEGRA124_MC_RESET(_name, _control, _status, _bit)       \
 978         {                                                       \
 979                 .name = #_name,                                 \
 980                 .id = TEGRA124_MC_RESET_##_name,                \
 981                 .control = _control,                            \
 982                 .status = _status,                              \
 983                 .bit = _bit,                                    \
 984         }
 985
 986 static const struct tegra_mc_reset tegra124_mc_resets[] = {
 987         TEGRA124_MC_RESET(AFI,       0x200, 0x204,  0),
 988         TEGRA124_MC_RESET(AVPC,      0x200, 0x204,  1),
 989         TEGRA124_MC_RESET(DC,        0x200, 0x204,  2),
 990         TEGRA124_MC_RESET(DCB,       0x200, 0x204,  3),
 991         TEGRA124_MC_RESET(HC,        0x200, 0x204,  6),
 992         TEGRA124_MC_RESET(HDA,       0x200, 0x204,  7),
 993         TEGRA124_MC_RESET(ISP2,      0x200, 0x204,  8),
 994         TEGRA124_MC_RESET(MPCORE,    0x200, 0x204,  9),
 995         TEGRA124_MC_RESET(MPCORELP,  0x200, 0x204, 10),
 996         TEGRA124_MC_RESET(MSENC,     0x200, 0x204, 11),
 997         TEGRA124_MC_RESET(PPCS,      0x200, 0x204, 14),
 998         TEGRA124_MC_RESET(SATA,      0x200, 0x204, 15),
 999         TEGRA124_MC_RESET(VDE,       0x200, 0x204, 16),
1000         TEGRA124_MC_RESET(VI,        0x200, 0x204, 17),
1001         TEGRA124_MC_RESET(VIC,       0x200, 0x204, 18),
1002         TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1003         TEGRA124_MC_RESET(XUSB_DEV,  0x200, 0x204, 20),
1004         TEGRA124_MC_RESET(TSEC,      0x200, 0x204, 21),
1005         TEGRA124_MC_RESET(SDMMC1,    0x200, 0x204, 22),
1006         TEGRA124_MC_RESET(SDMMC2,    0x200, 0x204, 23),
1007         TEGRA124_MC_RESET(SDMMC3,    0x200, 0x204, 25),
1008         TEGRA124_MC_RESET(SDMMC4,    0x970, 0x974,  0),
1009         TEGRA124_MC_RESET(ISP2B,     0x970, 0x974,  1),
1010         TEGRA124_MC_RESET(GPU,       0x970, 0x974,  2),
1011 };
1012
1013 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1014 static const unsigned long tegra124_mc_emem_regs[] = {
1015         MC_EMEM_ARB_CFG,
1016         MC_EMEM_ARB_OUTSTANDING_REQ,
1017         MC_EMEM_ARB_TIMING_RCD,
1018         MC_EMEM_ARB_TIMING_RP,
1019         MC_EMEM_ARB_TIMING_RC,
1020         MC_EMEM_ARB_TIMING_RAS,
1021         MC_EMEM_ARB_TIMING_FAW,
1022         MC_EMEM_ARB_TIMING_RRD,
1023         MC_EMEM_ARB_TIMING_RAP2PRE,
1024         MC_EMEM_ARB_TIMING_WAP2PRE,
1025         MC_EMEM_ARB_TIMING_R2R,
1026         MC_EMEM_ARB_TIMING_W2W,
1027         MC_EMEM_ARB_TIMING_R2W,
1028         MC_EMEM_ARB_TIMING_W2R,
1029         MC_EMEM_ARB_DA_TURNS,
1030         MC_EMEM_ARB_DA_COVERS,
1031         MC_EMEM_ARB_MISC0,
1032         MC_EMEM_ARB_MISC1,
1033         MC_EMEM_ARB_RING1_THROTTLE
1034 };
1035
1036 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1037         .clients = tegra124_mc_clients,
1038         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1039         .swgroups = tegra124_swgroups,
1040         .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1041         .groups = tegra124_groups,
1042         .num_groups = ARRAY_SIZE(tegra124_groups),
1043         .supports_round_robin_arbitration = true,
1044         .supports_request_limit = true,
1045         .num_tlb_lines = 32,
1046         .num_asids = 128,
1047 };
1048
1049 const struct tegra_mc_soc tegra124_mc_soc = {
1050         .clients = tegra124_mc_clients,
1051         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1052         .num_address_bits = 34,
1053         .atom_size = 32,
1054         .client_id_mask = 0x7f,
1055         .smmu = &tegra124_smmu_soc,
1056         .emem_regs = tegra124_mc_emem_regs,
1057         .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1058         .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1059                    MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1060                    MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1061         .reset_ops = &tegra_mc_reset_ops_common,
1062         .resets = tegra124_mc_resets,
1063         .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1064 };
1065 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1066
1067 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1068 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1069         .clients = tegra124_mc_clients,
1070         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1071         .swgroups = tegra124_swgroups,
1072         .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1073         .groups = tegra124_groups,
1074         .num_groups = ARRAY_SIZE(tegra124_groups),
1075         .supports_round_robin_arbitration = true,
1076         .supports_request_limit = true,
1077         .num_tlb_lines = 32,
1078         .num_asids = 128,
1079 };
1080
1081 const struct tegra_mc_soc tegra132_mc_soc = {
1082         .clients = tegra124_mc_clients,
1083         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1084         .num_address_bits = 34,
1085         .atom_size = 32,
1086         .client_id_mask = 0x7f,
1087         .smmu = &tegra132_smmu_soc,
1088         .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1089                    MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1090                    MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1091         .reset_ops = &tegra_mc_reset_ops_common,
1092         .resets = tegra124_mc_resets,
1093         .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1094 };
1095 #endif /* CONFIG_ARCH_TEGRA_132_SOC */