1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
9 #include <dt-bindings/memory/tegra124-mc.h>
13 static const struct tegra_mc_client tegra124_mc_clients[] = {
17 .swgroup = TEGRA_SWGROUP_PTC,
21 .swgroup = TEGRA_SWGROUP_DC,
35 .swgroup = TEGRA_SWGROUP_DCB,
49 .swgroup = TEGRA_SWGROUP_DC,
63 .swgroup = TEGRA_SWGROUP_DCB,
77 .swgroup = TEGRA_SWGROUP_DC,
91 .swgroup = TEGRA_SWGROUP_DCB,
105 .swgroup = TEGRA_SWGROUP_AFI,
119 .swgroup = TEGRA_SWGROUP_AVPC,
133 .swgroup = TEGRA_SWGROUP_DC,
146 .name = "displayhcb",
147 .swgroup = TEGRA_SWGROUP_DCB,
161 .swgroup = TEGRA_SWGROUP_HDA,
174 .name = "host1xdmar",
175 .swgroup = TEGRA_SWGROUP_HC,
189 .swgroup = TEGRA_SWGROUP_HC,
203 .swgroup = TEGRA_SWGROUP_MSENC,
216 .name = "ppcsahbdmar",
217 .swgroup = TEGRA_SWGROUP_PPCS,
230 .name = "ppcsahbslvr",
231 .swgroup = TEGRA_SWGROUP_PPCS,
245 .swgroup = TEGRA_SWGROUP_SATA,
259 .swgroup = TEGRA_SWGROUP_VDE,
273 .swgroup = TEGRA_SWGROUP_VDE,
287 .swgroup = TEGRA_SWGROUP_VDE,
301 .swgroup = TEGRA_SWGROUP_VDE,
315 .swgroup = TEGRA_SWGROUP_MPCORELP,
325 .swgroup = TEGRA_SWGROUP_MPCORE,
335 .swgroup = TEGRA_SWGROUP_MSENC,
349 .swgroup = TEGRA_SWGROUP_AFI,
363 .swgroup = TEGRA_SWGROUP_AVPC,
377 .swgroup = TEGRA_SWGROUP_HDA,
391 .swgroup = TEGRA_SWGROUP_HC,
405 .swgroup = TEGRA_SWGROUP_MPCORELP,
415 .swgroup = TEGRA_SWGROUP_MPCORE,
424 .name = "ppcsahbdmaw",
425 .swgroup = TEGRA_SWGROUP_PPCS,
438 .name = "ppcsahbslvw",
439 .swgroup = TEGRA_SWGROUP_PPCS,
453 .swgroup = TEGRA_SWGROUP_SATA,
467 .swgroup = TEGRA_SWGROUP_VDE,
481 .swgroup = TEGRA_SWGROUP_VDE,
495 .swgroup = TEGRA_SWGROUP_VDE,
509 .swgroup = TEGRA_SWGROUP_VDE,
523 .swgroup = TEGRA_SWGROUP_ISP2,
537 .swgroup = TEGRA_SWGROUP_ISP2,
551 .swgroup = TEGRA_SWGROUP_ISP2,
564 .name = "xusb_hostr",
565 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
578 .name = "xusb_hostw",
579 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
593 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
607 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
621 .swgroup = TEGRA_SWGROUP_ISP2B,
635 .swgroup = TEGRA_SWGROUP_ISP2B,
649 .swgroup = TEGRA_SWGROUP_ISP2B,
663 .swgroup = TEGRA_SWGROUP_TSEC,
677 .swgroup = TEGRA_SWGROUP_TSEC,
691 .swgroup = TEGRA_SWGROUP_A9AVP,
705 .swgroup = TEGRA_SWGROUP_A9AVP,
719 .swgroup = TEGRA_SWGROUP_GPU,
734 .swgroup = TEGRA_SWGROUP_GPU,
749 .swgroup = TEGRA_SWGROUP_DC,
763 .swgroup = TEGRA_SWGROUP_SDMMC1A,
777 .swgroup = TEGRA_SWGROUP_SDMMC2A,
791 .swgroup = TEGRA_SWGROUP_SDMMC3A,
804 .swgroup = TEGRA_SWGROUP_SDMMC4A,
819 .swgroup = TEGRA_SWGROUP_SDMMC1A,
833 .swgroup = TEGRA_SWGROUP_SDMMC2A,
847 .swgroup = TEGRA_SWGROUP_SDMMC3A,
861 .swgroup = TEGRA_SWGROUP_SDMMC4A,
875 .swgroup = TEGRA_SWGROUP_VIC,
889 .swgroup = TEGRA_SWGROUP_VIC,
903 .swgroup = TEGRA_SWGROUP_VI,
917 .swgroup = TEGRA_SWGROUP_DC,
931 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
932 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
933 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
934 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
935 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
936 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
937 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
938 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
939 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
940 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
941 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
942 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
943 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
944 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
945 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
946 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
947 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
948 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
949 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
950 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
951 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
952 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
953 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
954 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
957 static const unsigned int tegra124_group_drm[] = {
964 static const struct tegra_smmu_group_soc tegra124_groups[] = {
967 .swgroups = tegra124_group_drm,
968 .num_swgroups = ARRAY_SIZE(tegra124_group_drm),
972 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
975 .id = TEGRA124_MC_RESET_##_name, \
976 .control = _control, \
981 static const struct tegra_mc_reset tegra124_mc_resets[] = {
982 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
983 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
984 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
985 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
986 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
987 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
988 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
989 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
990 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
991 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
992 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
993 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
994 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
995 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
996 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
997 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
998 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
999 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1000 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1001 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1002 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1003 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1004 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1005 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1008 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1009 static const unsigned long tegra124_mc_emem_regs[] = {
1011 MC_EMEM_ARB_OUTSTANDING_REQ,
1012 MC_EMEM_ARB_TIMING_RCD,
1013 MC_EMEM_ARB_TIMING_RP,
1014 MC_EMEM_ARB_TIMING_RC,
1015 MC_EMEM_ARB_TIMING_RAS,
1016 MC_EMEM_ARB_TIMING_FAW,
1017 MC_EMEM_ARB_TIMING_RRD,
1018 MC_EMEM_ARB_TIMING_RAP2PRE,
1019 MC_EMEM_ARB_TIMING_WAP2PRE,
1020 MC_EMEM_ARB_TIMING_R2R,
1021 MC_EMEM_ARB_TIMING_W2W,
1022 MC_EMEM_ARB_TIMING_R2W,
1023 MC_EMEM_ARB_TIMING_W2R,
1024 MC_EMEM_ARB_DA_TURNS,
1025 MC_EMEM_ARB_DA_COVERS,
1028 MC_EMEM_ARB_RING1_THROTTLE
1031 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1032 .clients = tegra124_mc_clients,
1033 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1034 .swgroups = tegra124_swgroups,
1035 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1036 .groups = tegra124_groups,
1037 .num_groups = ARRAY_SIZE(tegra124_groups),
1038 .supports_round_robin_arbitration = true,
1039 .supports_request_limit = true,
1040 .num_tlb_lines = 32,
1044 const struct tegra_mc_soc tegra124_mc_soc = {
1045 .clients = tegra124_mc_clients,
1046 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1047 .num_address_bits = 34,
1049 .client_id_mask = 0x7f,
1050 .smmu = &tegra124_smmu_soc,
1051 .emem_regs = tegra124_mc_emem_regs,
1052 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1053 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1054 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1055 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1056 .reset_ops = &tegra_mc_reset_ops_common,
1057 .resets = tegra124_mc_resets,
1058 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1060 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1062 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1063 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1064 .clients = tegra124_mc_clients,
1065 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1066 .swgroups = tegra124_swgroups,
1067 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1068 .groups = tegra124_groups,
1069 .num_groups = ARRAY_SIZE(tegra124_groups),
1070 .supports_round_robin_arbitration = true,
1071 .supports_request_limit = true,
1072 .num_tlb_lines = 32,
1076 const struct tegra_mc_soc tegra132_mc_soc = {
1077 .clients = tegra124_mc_clients,
1078 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1079 .num_address_bits = 34,
1081 .client_id_mask = 0x7f,
1082 .smmu = &tegra132_smmu_soc,
1083 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1084 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1085 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1086 .reset_ops = &tegra_mc_reset_ops_common,
1087 .resets = tegra124_mc_resets,
1088 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1090 #endif /* CONFIG_ARCH_TEGRA_132_SOC */