drivers/memory/tegra/mc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/dma-mapping.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/sort.h>
  17
  18 #include <soc/tegra/fuse.h>
  19
  20 #include "mc.h"
  21
  22 static const struct of_device_id tegra_mc_of_match[] = {
  23 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  24         { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
  25 #endif
  26 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  27         { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
  28 #endif
  29 #ifdef CONFIG_ARCH_TEGRA_114_SOC
  30         { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
  31 #endif
  32 #ifdef CONFIG_ARCH_TEGRA_124_SOC
  33         { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
  34 #endif
  35 #ifdef CONFIG_ARCH_TEGRA_132_SOC
  36         { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
  37 #endif
  38 #ifdef CONFIG_ARCH_TEGRA_210_SOC
  39         { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
  40 #endif
  41         { }
  42 };
  43 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
  44
  45 static void tegra_mc_devm_action_put_device(void *data)
  46 {
  47         struct tegra_mc *mc = data;
  48
  49         put_device(mc->dev);
  50 }
  51
  52 /**
  53  * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle
  54  * @dev: device pointer for the consumer device
  55  *
  56  * This function will search for the Memory Controller node in a device-tree
  57  * and retrieve the Memory Controller handle.
  58  *
  59  * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc.
  60  */
  61 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev)
  62 {
  63         struct platform_device *pdev;
  64         struct device_node *np;
  65         struct tegra_mc *mc;
  66         int err;
  67
  68         np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0);
  69         if (!np)
  70                 return ERR_PTR(-ENOENT);
  71
  72         pdev = of_find_device_by_node(np);
  73         of_node_put(np);
  74         if (!pdev)
  75                 return ERR_PTR(-ENODEV);
  76
  77         mc = platform_get_drvdata(pdev);
  78         if (!mc) {
  79                 put_device(&pdev->dev);
  80                 return ERR_PTR(-EPROBE_DEFER);
  81         }
  82
  83         err = devm_add_action(dev, tegra_mc_devm_action_put_device, mc);
  84         if (err) {
  85                 put_device(mc->dev);
  86                 return ERR_PTR(err);
  87         }
  88
  89         return mc;
  90 }
  91 EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get);
  92
  93 static int tegra_mc_block_dma_common(struct tegra_mc *mc,
  94                                      const struct tegra_mc_reset *rst)
  95 {
  96         unsigned long flags;
  97         u32 value;
  98
  99         spin_lock_irqsave(&mc->lock, flags);
 100
 101         value = mc_readl(mc, rst->control) | BIT(rst->bit);
 102         mc_writel(mc, value, rst->control);
 103
 104         spin_unlock_irqrestore(&mc->lock, flags);
 105
 106         return 0;
 107 }
 108
 109 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc,
 110                                        const struct tegra_mc_reset *rst)
 111 {
 112         return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;
 113 }
 114
 115 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc,
 116                                        const struct tegra_mc_reset *rst)
 117 {
 118         unsigned long flags;
 119         u32 value;
 120
 121         spin_lock_irqsave(&mc->lock, flags);
 122
 123         value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
 124         mc_writel(mc, value, rst->control);
 125
 126         spin_unlock_irqrestore(&mc->lock, flags);
 127
 128         return 0;
 129 }
 130
 131 static int tegra_mc_reset_status_common(struct tegra_mc *mc,
 132                                         const struct tegra_mc_reset *rst)
 133 {
 134         return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;
 135 }
 136
 137 const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = {
 138         .block_dma = tegra_mc_block_dma_common,
 139         .dma_idling = tegra_mc_dma_idling_common,
 140         .unblock_dma = tegra_mc_unblock_dma_common,
 141         .reset_status = tegra_mc_reset_status_common,
 142 };
 143
 144 static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev)
 145 {
 146         return container_of(rcdev, struct tegra_mc, reset);
 147 }
 148
 149 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc,
 150                                                         unsigned long id)
 151 {
 152         unsigned int i;
 153
 154         for (i = 0; i < mc->soc->num_resets; i++)
 155                 if (mc->soc->resets[i].id == id)
 156                         return &mc->soc->resets[i];
 157
 158         return NULL;
 159 }
 160
 161 static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev,
 162                                     unsigned long id)
 163 {
 164         struct tegra_mc *mc = reset_to_mc(rcdev);
 165         const struct tegra_mc_reset_ops *rst_ops;
 166         const struct tegra_mc_reset *rst;
 167         int retries = 500;
 168         int err;
 169
 170         rst = tegra_mc_reset_find(mc, id);
 171         if (!rst)
 172                 return -ENODEV;
 173
 174         rst_ops = mc->soc->reset_ops;
 175         if (!rst_ops)
 176                 return -ENODEV;
 177
 178         if (rst_ops->block_dma) {
 179                 /* block clients DMA requests */
 180                 err = rst_ops->block_dma(mc, rst);
 181                 if (err) {
 182                         dev_err(mc->dev, "failed to block %s DMA: %d\n",
 183                                 rst->name, err);
 184                         return err;
 185                 }
 186         }
 187
 188         if (rst_ops->dma_idling) {
 189                 /* wait for completion of the outstanding DMA requests */
 190                 while (!rst_ops->dma_idling(mc, rst)) {
 191                         if (!retries--) {
 192                                 dev_err(mc->dev, "failed to flush %s DMA\n",
 193                                         rst->name);
 194                                 return -EBUSY;
 195                         }
 196
 197                         usleep_range(10, 100);
 198                 }
 199         }
 200
 201         if (rst_ops->hotreset_assert) {
 202                 /* clear clients DMA requests sitting before arbitration */
 203                 err = rst_ops->hotreset_assert(mc, rst);
 204                 if (err) {
 205                         dev_err(mc->dev, "failed to hot reset %s: %d\n",
 206                                 rst->name, err);
 207                         return err;
 208                 }
 209         }
 210
 211         return 0;
 212 }
 213
 214 static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev,
 215                                       unsigned long id)
 216 {
 217         struct tegra_mc *mc = reset_to_mc(rcdev);
 218         const struct tegra_mc_reset_ops *rst_ops;
 219         const struct tegra_mc_reset *rst;
 220         int err;
 221
 222         rst = tegra_mc_reset_find(mc, id);
 223         if (!rst)
 224                 return -ENODEV;
 225
 226         rst_ops = mc->soc->reset_ops;
 227         if (!rst_ops)
 228                 return -ENODEV;
 229
 230         if (rst_ops->hotreset_deassert) {
 231                 /* take out client from hot reset */
 232                 err = rst_ops->hotreset_deassert(mc, rst);
 233                 if (err) {
 234                         dev_err(mc->dev, "failed to deassert hot reset %s: %d\n",
 235                                 rst->name, err);
 236                         return err;
 237                 }
 238         }
 239
 240         if (rst_ops->unblock_dma) {
 241                 /* allow new DMA requests to proceed to arbitration */
 242                 err = rst_ops->unblock_dma(mc, rst);
 243                 if (err) {
 244                         dev_err(mc->dev, "failed to unblock %s DMA : %d\n",
 245                                 rst->name, err);
 246                         return err;
 247                 }
 248         }
 249
 250         return 0;
 251 }
 252
 253 static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev,
 254                                     unsigned long id)
 255 {
 256         struct tegra_mc *mc = reset_to_mc(rcdev);
 257         const struct tegra_mc_reset_ops *rst_ops;
 258         const struct tegra_mc_reset *rst;
 259
 260         rst = tegra_mc_reset_find(mc, id);
 261         if (!rst)
 262                 return -ENODEV;
 263
 264         rst_ops = mc->soc->reset_ops;
 265         if (!rst_ops)
 266                 return -ENODEV;
 267
 268         return rst_ops->reset_status(mc, rst);
 269 }
 270
 271 static const struct reset_control_ops tegra_mc_reset_ops = {
 272         .assert = tegra_mc_hotreset_assert,
 273         .deassert = tegra_mc_hotreset_deassert,
 274         .status = tegra_mc_hotreset_status,
 275 };
 276
 277 static int tegra_mc_reset_setup(struct tegra_mc *mc)
 278 {
 279         int err;
 280
 281         mc->reset.ops = &tegra_mc_reset_ops;
 282         mc->reset.owner = THIS_MODULE;
 283         mc->reset.of_node = mc->dev->of_node;
 284         mc->reset.of_reset_n_cells = 1;
 285         mc->reset.nr_resets = mc->soc->num_resets;
 286
 287         err = reset_controller_register(&mc->reset);
 288         if (err < 0)
 289                 return err;
 290
 291         return 0;
 292 }
 293
 294 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
 295 {
 296         unsigned long long tick;
 297         unsigned int i;
 298         u32 value;
 299
 300         /* compute the number of MC clock cycles per tick */
 301         tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
 302         do_div(tick, NSEC_PER_SEC);
 303
 304         value = mc_readl(mc, MC_EMEM_ARB_CFG);
 305         value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
 306         value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
 307         mc_writel(mc, value, MC_EMEM_ARB_CFG);
 308
 309         /* write latency allowance defaults */
 310         for (i = 0; i < mc->soc->num_clients; i++) {
 311                 const struct tegra_mc_la *la = &mc->soc->clients[i].la;
 312                 u32 value;
 313
 314                 value = mc_readl(mc, la->reg);
 315                 value &= ~(la->mask << la->shift);
 316                 value |= (la->def & la->mask) << la->shift;
 317                 mc_writel(mc, value, la->reg);
 318         }
 319
 320         /* latch new values */
 321         mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
 322
 323         return 0;
 324 }
 325
 326 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
 327 {
 328         unsigned int i;
 329         struct tegra_mc_timing *timing = NULL;
 330
 331         for (i = 0; i < mc->num_timings; i++) {
 332                 if (mc->timings[i].rate == rate) {
 333                         timing = &mc->timings[i];
 334                         break;
 335                 }
 336         }
 337
 338         if (!timing) {
 339                 dev_err(mc->dev, "no memory timing registered for rate %lu\n",
 340                         rate);
 341                 return -EINVAL;
 342         }
 343
 344         for (i = 0; i < mc->soc->num_emem_regs; ++i)
 345                 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
 346
 347         return 0;
 348 }
 349
 350 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
 351 {
 352         u8 dram_count;
 353
 354         dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
 355         dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
 356         dram_count++;
 357
 358         return dram_count;
 359 }
 360
 361 static int load_one_timing(struct tegra_mc *mc,
 362                            struct tegra_mc_timing *timing,
 363                            struct device_node *node)
 364 {
 365         int err;
 366         u32 tmp;
 367
 368         err = of_property_read_u32(node, "clock-frequency", &tmp);
 369         if (err) {
 370                 dev_err(mc->dev,
 371                         "timing %pOFn: failed to read rate\n", node);
 372                 return err;
 373         }
 374
 375         timing->rate = tmp;
 376         timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
 377                                          sizeof(u32), GFP_KERNEL);
 378         if (!timing->emem_data)
 379                 return -ENOMEM;
 380
 381         err = of_property_read_u32_array(node, "nvidia,emem-configuration",
 382                                          timing->emem_data,
 383                                          mc->soc->num_emem_regs);
 384         if (err) {
 385                 dev_err(mc->dev,
 386                         "timing %pOFn: failed to read EMEM configuration\n",
 387                         node);
 388                 return err;
 389         }
 390
 391         return 0;
 392 }
 393
 394 static int load_timings(struct tegra_mc *mc, struct device_node *node)
 395 {
 396         struct device_node *child;
 397         struct tegra_mc_timing *timing;
 398         int child_count = of_get_child_count(node);
 399         int i = 0, err;
 400
 401         mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
 402                                    GFP_KERNEL);
 403         if (!mc->timings)
 404                 return -ENOMEM;
 405
 406         mc->num_timings = child_count;
 407
 408         for_each_child_of_node(node, child) {
 409                 timing = &mc->timings[i++];
 410
 411                 err = load_one_timing(mc, timing, child);
 412                 if (err) {
 413                         of_node_put(child);
 414                         return err;
 415                 }
 416         }
 417
 418         return 0;
 419 }
 420
 421 static int tegra_mc_setup_timings(struct tegra_mc *mc)
 422 {
 423         struct device_node *node;
 424         u32 ram_code, node_ram_code;
 425         int err;
 426
 427         ram_code = tegra_read_ram_code();
 428
 429         mc->num_timings = 0;
 430
 431         for_each_child_of_node(mc->dev->of_node, node) {
 432                 err = of_property_read_u32(node, "nvidia,ram-code",
 433                                            &node_ram_code);
 434                 if (err || (node_ram_code != ram_code))
 435                         continue;
 436
 437                 err = load_timings(mc, node);
 438                 of_node_put(node);
 439                 if (err)
 440                         return err;
 441                 break;
 442         }
 443
 444         if (mc->num_timings == 0)
 445                 dev_warn(mc->dev,
 446                          "no memory timings for RAM code %u registered\n",
 447                          ram_code);
 448
 449         return 0;
 450 }
 451
 452 static const char *const status_names[32] = {
 453         [ 1] = "External interrupt",
 454         [ 6] = "EMEM address decode error",
 455         [ 7] = "GART page fault",
 456         [ 8] = "Security violation",
 457         [ 9] = "EMEM arbitration error",
 458         [10] = "Page fault",
 459         [11] = "Invalid APB ASID update",
 460         [12] = "VPR violation",
 461         [13] = "Secure carveout violation",
 462         [16] = "MTS carveout violation",
 463 };
 464
 465 static const char *const error_names[8] = {
 466         [2] = "EMEM decode error",
 467         [3] = "TrustZone violation",
 468         [4] = "Carveout violation",
 469         [6] = "SMMU translation error",
 470 };
 471
 472 static irqreturn_t tegra_mc_irq(int irq, void *data)
 473 {
 474         struct tegra_mc *mc = data;
 475         unsigned long status;
 476         unsigned int bit;
 477
 478         /* mask all interrupts to avoid flooding */
 479         status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
 480         if (!status)
 481                 return IRQ_NONE;
 482
 483         for_each_set_bit(bit, &status, 32) {
 484                 const char *error = status_names[bit] ?: "unknown";
 485                 const char *client = "unknown", *desc;
 486                 const char *direction, *secure;
 487                 phys_addr_t addr = 0;
 488                 unsigned int i;
 489                 char perm[7];
 490                 u8 id, type;
 491                 u32 value;
 492
 493                 value = mc_readl(mc, MC_ERR_STATUS);
 494
 495 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 496                 if (mc->soc->num_address_bits > 32) {
 497                         addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
 498                                 MC_ERR_STATUS_ADR_HI_MASK);
 499                         addr <<= 32;
 500                 }
 501 #endif
 502
 503                 if (value & MC_ERR_STATUS_RW)
 504                         direction = "write";
 505                 else
 506                         direction = "read";
 507
 508                 if (value & MC_ERR_STATUS_SECURITY)
 509                         secure = "secure ";
 510                 else
 511                         secure = "";
 512
 513                 id = value & mc->soc->client_id_mask;
 514
 515                 for (i = 0; i < mc->soc->num_clients; i++) {
 516                         if (mc->soc->clients[i].id == id) {
 517                                 client = mc->soc->clients[i].name;
 518                                 break;
 519                         }
 520                 }
 521
 522                 type = (value & MC_ERR_STATUS_TYPE_MASK) >>
 523                        MC_ERR_STATUS_TYPE_SHIFT;
 524                 desc = error_names[type];
 525
 526                 switch (value & MC_ERR_STATUS_TYPE_MASK) {
 527                 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
 528                         perm[0] = ' ';
 529                         perm[1] = '[';
 530
 531                         if (value & MC_ERR_STATUS_READABLE)
 532                                 perm[2] = 'R';
 533                         else
 534                                 perm[2] = '-';
 535
 536                         if (value & MC_ERR_STATUS_WRITABLE)
 537                                 perm[3] = 'W';
 538                         else
 539                                 perm[3] = '-';
 540
 541                         if (value & MC_ERR_STATUS_NONSECURE)
 542                                 perm[4] = '-';
 543                         else
 544                                 perm[4] = 'S';
 545
 546                         perm[5] = ']';
 547                         perm[6] = '\0';
 548                         break;
 549
 550                 default:
 551                         perm[0] = '\0';
 552                         break;
 553                 }
 554
 555                 value = mc_readl(mc, MC_ERR_ADR);
 556                 addr |= value;
 557
 558                 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
 559                                     client, secure, direction, &addr, error,
 560                                     desc, perm);
 561         }
 562
 563         /* clear interrupts */
 564         mc_writel(mc, status, MC_INTSTATUS);
 565
 566         return IRQ_HANDLED;
 567 }
 568
 569 static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
 570 {
 571         struct tegra_mc *mc = data;
 572         unsigned long status;
 573         unsigned int bit;
 574
 575         /* mask all interrupts to avoid flooding */
 576         status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
 577         if (!status)
 578                 return IRQ_NONE;
 579
 580         for_each_set_bit(bit, &status, 32) {
 581                 const char *direction = "read", *secure = "";
 582                 const char *error = status_names[bit];
 583                 const char *client, *desc;
 584                 phys_addr_t addr;
 585                 u32 value, reg;
 586                 u8 id, type;
 587
 588                 switch (BIT(bit)) {
 589                 case MC_INT_DECERR_EMEM:
 590                         reg = MC_DECERR_EMEM_OTHERS_STATUS;
 591                         value = mc_readl(mc, reg);
 592
 593                         id = value & mc->soc->client_id_mask;
 594                         desc = error_names[2];
 595
 596                         if (value & BIT(31))
 597                                 direction = "write";
 598                         break;
 599
 600                 case MC_INT_INVALID_GART_PAGE:
 601                         reg = MC_GART_ERROR_REQ;
 602                         value = mc_readl(mc, reg);
 603
 604                         id = (value >> 1) & mc->soc->client_id_mask;
 605                         desc = error_names[2];
 606
 607                         if (value & BIT(0))
 608                                 direction = "write";
 609                         break;
 610
 611                 case MC_INT_SECURITY_VIOLATION:
 612                         reg = MC_SECURITY_VIOLATION_STATUS;
 613                         value = mc_readl(mc, reg);
 614
 615                         id = value & mc->soc->client_id_mask;
 616                         type = (value & BIT(30)) ? 4 : 3;
 617                         desc = error_names[type];
 618                         secure = "secure ";
 619
 620                         if (value & BIT(31))
 621                                 direction = "write";
 622                         break;
 623
 624                 default:
 625                         continue;
 626                 }
 627
 628                 client = mc->soc->clients[id].name;
 629                 addr = mc_readl(mc, reg + sizeof(u32));
 630
 631                 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
 632                                     client, secure, direction, &addr, error,
 633                                     desc);
 634         }
 635
 636         /* clear interrupts */
 637         mc_writel(mc, status, MC_INTSTATUS);
 638
 639         return IRQ_HANDLED;
 640 }
 641
 642 static int tegra_mc_probe(struct platform_device *pdev)
 643 {
 644         struct resource *res;
 645         struct tegra_mc *mc;
 646         void *isr;
 647         u64 mask;
 648         int err;
 649
 650         mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
 651         if (!mc)
 652                 return -ENOMEM;
 653
 654         platform_set_drvdata(pdev, mc);
 655         spin_lock_init(&mc->lock);
 656         mc->soc = of_device_get_match_data(&pdev->dev);
 657         mc->dev = &pdev->dev;
 658
 659         mask = DMA_BIT_MASK(mc->soc->num_address_bits);
 660
 661         err = dma_coerce_mask_and_coherent(&pdev->dev, mask);
 662         if (err < 0) {
 663                 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
 664                 return err;
 665         }
 666
 667         /* length of MC tick in nanoseconds */
 668         mc->tick = 30;
 669
 670         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 671         mc->regs = devm_ioremap_resource(&pdev->dev, res);
 672         if (IS_ERR(mc->regs))
 673                 return PTR_ERR(mc->regs);
 674
 675         mc->clk = devm_clk_get(&pdev->dev, "mc");
 676         if (IS_ERR(mc->clk)) {
 677                 dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
 678                         PTR_ERR(mc->clk));
 679                 return PTR_ERR(mc->clk);
 680         }
 681
 682 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 683         if (mc->soc == &tegra20_mc_soc) {
 684                 isr = tegra20_mc_irq;
 685         } else
 686 #endif
 687         {
 688                 /* ensure that debug features are disabled */
 689                 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG);
 690
 691                 err = tegra_mc_setup_latency_allowance(mc);
 692                 if (err < 0) {
 693                         dev_err(&pdev->dev,
 694                                 "failed to setup latency allowance: %d\n",
 695                                 err);
 696                         return err;
 697                 }
 698
 699                 isr = tegra_mc_irq;
 700
 701                 err = tegra_mc_setup_timings(mc);
 702                 if (err < 0) {
 703                         dev_err(&pdev->dev, "failed to setup timings: %d\n",
 704                                 err);
 705                         return err;
 706                 }
 707         }
 708
 709         mc->irq = platform_get_irq(pdev, 0);
 710         if (mc->irq < 0)
 711                 return mc->irq;
 712
 713         WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n");
 714
 715         mc_writel(mc, mc->soc->intmask, MC_INTMASK);
 716
 717         err = devm_request_irq(&pdev->dev, mc->irq, isr, 0,
 718                                dev_name(&pdev->dev), mc);
 719         if (err < 0) {
 720                 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
 721                         err);
 722                 return err;
 723         }
 724
 725         err = tegra_mc_reset_setup(mc);
 726         if (err < 0)
 727                 dev_err(&pdev->dev, "failed to register reset controller: %d\n",
 728                         err);
 729
 730         if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) {
 731                 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
 732                 if (IS_ERR(mc->smmu)) {
 733                         dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
 734                                 PTR_ERR(mc->smmu));
 735                         mc->smmu = NULL;
 736                 }
 737         }
 738
 739         if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) {
 740                 mc->gart = tegra_gart_probe(&pdev->dev, mc);
 741                 if (IS_ERR(mc->gart)) {
 742                         dev_err(&pdev->dev, "failed to probe GART: %ld\n",
 743                                 PTR_ERR(mc->gart));
 744                         mc->gart = NULL;
 745                 }
 746         }
 747
 748         return 0;
 749 }
 750
 751 static int tegra_mc_suspend(struct device *dev)
 752 {
 753         struct tegra_mc *mc = dev_get_drvdata(dev);
 754         int err;
 755
 756         if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
 757                 err = tegra_gart_suspend(mc->gart);
 758                 if (err)
 759                         return err;
 760         }
 761
 762         return 0;
 763 }
 764
 765 static int tegra_mc_resume(struct device *dev)
 766 {
 767         struct tegra_mc *mc = dev_get_drvdata(dev);
 768         int err;
 769
 770         if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
 771                 err = tegra_gart_resume(mc->gart);
 772                 if (err)
 773                         return err;
 774         }
 775
 776         return 0;
 777 }
 778
 779 static const struct dev_pm_ops tegra_mc_pm_ops = {
 780         .suspend = tegra_mc_suspend,
 781         .resume = tegra_mc_resume,
 782 };
 783
 784 static struct platform_driver tegra_mc_driver = {
 785         .driver = {
 786                 .name = "tegra-mc",
 787                 .of_match_table = tegra_mc_of_match,
 788                 .pm = &tegra_mc_pm_ops,
 789                 .suppress_bind_attrs = true,
 790         },
 791         .prevent_deferred_probe = true,
 792         .probe = tegra_mc_probe,
 793 };
 794
 795 static int tegra_mc_init(void)
 796 {
 797         return platform_driver_register(&tegra_mc_driver);
 798 }
 799 arch_initcall(tegra_mc_init);
 800
 801 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
 802 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
 803 MODULE_LICENSE("GPL v2");