1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/export.h>
10 #include <linux/interrupt.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/sort.h>
19 #include <soc/tegra/fuse.h>
23 static const struct of_device_id tegra_mc_of_match[] = {
24 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
25 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
27 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
28 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
30 #ifdef CONFIG_ARCH_TEGRA_114_SOC
31 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
33 #ifdef CONFIG_ARCH_TEGRA_124_SOC
34 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
36 #ifdef CONFIG_ARCH_TEGRA_132_SOC
37 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
39 #ifdef CONFIG_ARCH_TEGRA_210_SOC
40 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
44 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
46 static void tegra_mc_devm_action_put_device(void *data)
48 struct tegra_mc *mc = data;
54 * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle
55 * @dev: device pointer for the consumer device
57 * This function will search for the Memory Controller node in a device-tree
58 * and retrieve the Memory Controller handle.
60 * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc.
62 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev)
64 struct platform_device *pdev;
65 struct device_node *np;
69 np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0);
71 return ERR_PTR(-ENOENT);
73 pdev = of_find_device_by_node(np);
76 return ERR_PTR(-ENODEV);
78 mc = platform_get_drvdata(pdev);
80 put_device(&pdev->dev);
81 return ERR_PTR(-EPROBE_DEFER);
84 err = devm_add_action(dev, tegra_mc_devm_action_put_device, mc);
92 EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get);
94 static int tegra_mc_block_dma_common(struct tegra_mc *mc,
95 const struct tegra_mc_reset *rst)
100 spin_lock_irqsave(&mc->lock, flags);
102 value = mc_readl(mc, rst->control) | BIT(rst->bit);
103 mc_writel(mc, value, rst->control);
105 spin_unlock_irqrestore(&mc->lock, flags);
110 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc,
111 const struct tegra_mc_reset *rst)
113 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;
116 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc,
117 const struct tegra_mc_reset *rst)
122 spin_lock_irqsave(&mc->lock, flags);
124 value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
125 mc_writel(mc, value, rst->control);
127 spin_unlock_irqrestore(&mc->lock, flags);
132 static int tegra_mc_reset_status_common(struct tegra_mc *mc,
133 const struct tegra_mc_reset *rst)
135 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;
138 const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = {
139 .block_dma = tegra_mc_block_dma_common,
140 .dma_idling = tegra_mc_dma_idling_common,
141 .unblock_dma = tegra_mc_unblock_dma_common,
142 .reset_status = tegra_mc_reset_status_common,
145 static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev)
147 return container_of(rcdev, struct tegra_mc, reset);
150 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc,
155 for (i = 0; i < mc->soc->num_resets; i++)
156 if (mc->soc->resets[i].id == id)
157 return &mc->soc->resets[i];
162 static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev,
165 struct tegra_mc *mc = reset_to_mc(rcdev);
166 const struct tegra_mc_reset_ops *rst_ops;
167 const struct tegra_mc_reset *rst;
171 rst = tegra_mc_reset_find(mc, id);
175 rst_ops = mc->soc->reset_ops;
179 if (rst_ops->block_dma) {
180 /* block clients DMA requests */
181 err = rst_ops->block_dma(mc, rst);
183 dev_err(mc->dev, "failed to block %s DMA: %d\n",
189 if (rst_ops->dma_idling) {
190 /* wait for completion of the outstanding DMA requests */
191 while (!rst_ops->dma_idling(mc, rst)) {
193 dev_err(mc->dev, "failed to flush %s DMA\n",
198 usleep_range(10, 100);
202 if (rst_ops->hotreset_assert) {
203 /* clear clients DMA requests sitting before arbitration */
204 err = rst_ops->hotreset_assert(mc, rst);
206 dev_err(mc->dev, "failed to hot reset %s: %d\n",
215 static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev,
218 struct tegra_mc *mc = reset_to_mc(rcdev);
219 const struct tegra_mc_reset_ops *rst_ops;
220 const struct tegra_mc_reset *rst;
223 rst = tegra_mc_reset_find(mc, id);
227 rst_ops = mc->soc->reset_ops;
231 if (rst_ops->hotreset_deassert) {
232 /* take out client from hot reset */
233 err = rst_ops->hotreset_deassert(mc, rst);
235 dev_err(mc->dev, "failed to deassert hot reset %s: %d\n",
241 if (rst_ops->unblock_dma) {
242 /* allow new DMA requests to proceed to arbitration */
243 err = rst_ops->unblock_dma(mc, rst);
245 dev_err(mc->dev, "failed to unblock %s DMA : %d\n",
254 static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev,
257 struct tegra_mc *mc = reset_to_mc(rcdev);
258 const struct tegra_mc_reset_ops *rst_ops;
259 const struct tegra_mc_reset *rst;
261 rst = tegra_mc_reset_find(mc, id);
265 rst_ops = mc->soc->reset_ops;
269 return rst_ops->reset_status(mc, rst);
272 static const struct reset_control_ops tegra_mc_reset_ops = {
273 .assert = tegra_mc_hotreset_assert,
274 .deassert = tegra_mc_hotreset_deassert,
275 .status = tegra_mc_hotreset_status,
278 static int tegra_mc_reset_setup(struct tegra_mc *mc)
282 mc->reset.ops = &tegra_mc_reset_ops;
283 mc->reset.owner = THIS_MODULE;
284 mc->reset.of_node = mc->dev->of_node;
285 mc->reset.of_reset_n_cells = 1;
286 mc->reset.nr_resets = mc->soc->num_resets;
288 err = reset_controller_register(&mc->reset);
295 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
297 unsigned long long tick;
301 /* compute the number of MC clock cycles per tick */
302 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
303 do_div(tick, NSEC_PER_SEC);
305 value = mc_readl(mc, MC_EMEM_ARB_CFG);
306 value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
307 value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
308 mc_writel(mc, value, MC_EMEM_ARB_CFG);
310 /* write latency allowance defaults */
311 for (i = 0; i < mc->soc->num_clients; i++) {
312 const struct tegra_mc_la *la = &mc->soc->clients[i].la;
315 value = mc_readl(mc, la->reg);
316 value &= ~(la->mask << la->shift);
317 value |= (la->def & la->mask) << la->shift;
318 mc_writel(mc, value, la->reg);
321 /* latch new values */
322 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
327 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
330 struct tegra_mc_timing *timing = NULL;
332 for (i = 0; i < mc->num_timings; i++) {
333 if (mc->timings[i].rate == rate) {
334 timing = &mc->timings[i];
340 dev_err(mc->dev, "no memory timing registered for rate %lu\n",
345 for (i = 0; i < mc->soc->num_emem_regs; ++i)
346 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
350 EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration);
352 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
356 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
357 dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
362 EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count);
364 static int load_one_timing(struct tegra_mc *mc,
365 struct tegra_mc_timing *timing,
366 struct device_node *node)
371 err = of_property_read_u32(node, "clock-frequency", &tmp);
374 "timing %pOFn: failed to read rate\n", node);
379 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
380 sizeof(u32), GFP_KERNEL);
381 if (!timing->emem_data)
384 err = of_property_read_u32_array(node, "nvidia,emem-configuration",
386 mc->soc->num_emem_regs);
389 "timing %pOFn: failed to read EMEM configuration\n",
397 static int load_timings(struct tegra_mc *mc, struct device_node *node)
399 struct device_node *child;
400 struct tegra_mc_timing *timing;
401 int child_count = of_get_child_count(node);
404 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
409 mc->num_timings = child_count;
411 for_each_child_of_node(node, child) {
412 timing = &mc->timings[i++];
414 err = load_one_timing(mc, timing, child);
424 static int tegra_mc_setup_timings(struct tegra_mc *mc)
426 struct device_node *node;
427 u32 ram_code, node_ram_code;
430 ram_code = tegra_read_ram_code();
434 for_each_child_of_node(mc->dev->of_node, node) {
435 err = of_property_read_u32(node, "nvidia,ram-code",
437 if (err || (node_ram_code != ram_code))
440 err = load_timings(mc, node);
447 if (mc->num_timings == 0)
449 "no memory timings for RAM code %u registered\n",
455 static const char *const status_names[32] = {
456 [ 1] = "External interrupt",
457 [ 6] = "EMEM address decode error",
458 [ 7] = "GART page fault",
459 [ 8] = "Security violation",
460 [ 9] = "EMEM arbitration error",
462 [11] = "Invalid APB ASID update",
463 [12] = "VPR violation",
464 [13] = "Secure carveout violation",
465 [16] = "MTS carveout violation",
468 static const char *const error_names[8] = {
469 [2] = "EMEM decode error",
470 [3] = "TrustZone violation",
471 [4] = "Carveout violation",
472 [6] = "SMMU translation error",
475 static irqreturn_t tegra_mc_irq(int irq, void *data)
477 struct tegra_mc *mc = data;
478 unsigned long status;
481 /* mask all interrupts to avoid flooding */
482 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
486 for_each_set_bit(bit, &status, 32) {
487 const char *error = status_names[bit] ?: "unknown";
488 const char *client = "unknown", *desc;
489 const char *direction, *secure;
490 phys_addr_t addr = 0;
496 value = mc_readl(mc, MC_ERR_STATUS);
498 #ifdef CONFIG_PHYS_ADDR_T_64BIT
499 if (mc->soc->num_address_bits > 32) {
500 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
501 MC_ERR_STATUS_ADR_HI_MASK);
506 if (value & MC_ERR_STATUS_RW)
511 if (value & MC_ERR_STATUS_SECURITY)
516 id = value & mc->soc->client_id_mask;
518 for (i = 0; i < mc->soc->num_clients; i++) {
519 if (mc->soc->clients[i].id == id) {
520 client = mc->soc->clients[i].name;
525 type = (value & MC_ERR_STATUS_TYPE_MASK) >>
526 MC_ERR_STATUS_TYPE_SHIFT;
527 desc = error_names[type];
529 switch (value & MC_ERR_STATUS_TYPE_MASK) {
530 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
534 if (value & MC_ERR_STATUS_READABLE)
539 if (value & MC_ERR_STATUS_WRITABLE)
544 if (value & MC_ERR_STATUS_NONSECURE)
558 value = mc_readl(mc, MC_ERR_ADR);
561 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
562 client, secure, direction, &addr, error,
566 /* clear interrupts */
567 mc_writel(mc, status, MC_INTSTATUS);
572 static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
574 struct tegra_mc *mc = data;
575 unsigned long status;
578 /* mask all interrupts to avoid flooding */
579 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
583 for_each_set_bit(bit, &status, 32) {
584 const char *direction = "read", *secure = "";
585 const char *error = status_names[bit];
586 const char *client, *desc;
592 case MC_INT_DECERR_EMEM:
593 reg = MC_DECERR_EMEM_OTHERS_STATUS;
594 value = mc_readl(mc, reg);
596 id = value & mc->soc->client_id_mask;
597 desc = error_names[2];
603 case MC_INT_INVALID_GART_PAGE:
604 reg = MC_GART_ERROR_REQ;
605 value = mc_readl(mc, reg);
607 id = (value >> 1) & mc->soc->client_id_mask;
608 desc = error_names[2];
614 case MC_INT_SECURITY_VIOLATION:
615 reg = MC_SECURITY_VIOLATION_STATUS;
616 value = mc_readl(mc, reg);
618 id = value & mc->soc->client_id_mask;
619 type = (value & BIT(30)) ? 4 : 3;
620 desc = error_names[type];
631 client = mc->soc->clients[id].name;
632 addr = mc_readl(mc, reg + sizeof(u32));
634 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
635 client, secure, direction, &addr, error,
639 /* clear interrupts */
640 mc_writel(mc, status, MC_INTSTATUS);
646 * Memory Controller (MC) has few Memory Clients that are issuing memory
647 * bandwidth allocation requests to the MC interconnect provider. The MC
648 * provider aggregates the requests and then sends the aggregated request
649 * up to the External Memory Controller (EMC) interconnect provider which
650 * re-configures hardware interface to External Memory (EMEM) in accordance
651 * to the required bandwidth. Each MC interconnect node represents an
652 * individual Memory Client.
654 * Memory interconnect topology:
660 * | | +-----+ +------+
661 * ... | MC +--->+ EMC +--->+ EMEM |
662 * | | +-----+ +------+
668 static int tegra_mc_interconnect_setup(struct tegra_mc *mc)
670 struct icc_node *node;
674 /* older device-trees don't have interconnect properties */
675 if (!device_property_present(mc->dev, "#interconnect-cells") ||
679 mc->provider.dev = mc->dev;
680 mc->provider.data = &mc->provider;
681 mc->provider.set = mc->soc->icc_ops->set;
682 mc->provider.aggregate = mc->soc->icc_ops->aggregate;
683 mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended;
685 err = icc_provider_add(&mc->provider);
689 /* create Memory Controller node */
690 node = icc_node_create(TEGRA_ICC_MC);
696 node->name = "Memory Controller";
697 icc_node_add(node, &mc->provider);
699 /* link Memory Controller to External Memory Controller */
700 err = icc_link_create(node, TEGRA_ICC_EMC);
704 for (i = 0; i < mc->soc->num_clients; i++) {
705 /* create MC client node */
706 node = icc_node_create(mc->soc->clients[i].id);
712 node->name = mc->soc->clients[i].name;
713 icc_node_add(node, &mc->provider);
715 /* link Memory Client to Memory Controller */
716 err = icc_link_create(node, TEGRA_ICC_MC);
722 * MC driver is registered too early, so early that generic driver
723 * syncing doesn't work for the MC. But it doesn't really matter
724 * since syncing works for the EMC drivers, hence we can sync the
725 * MC driver by ourselves and then EMC will complete syncing of
726 * the whole ICC state.
728 icc_sync_state(mc->dev);
733 icc_nodes_remove(&mc->provider);
735 icc_provider_del(&mc->provider);
740 static int tegra_mc_probe(struct platform_device *pdev)
742 struct resource *res;
748 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
752 platform_set_drvdata(pdev, mc);
753 spin_lock_init(&mc->lock);
754 mc->soc = of_device_get_match_data(&pdev->dev);
755 mc->dev = &pdev->dev;
757 mask = DMA_BIT_MASK(mc->soc->num_address_bits);
759 err = dma_coerce_mask_and_coherent(&pdev->dev, mask);
761 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
765 /* length of MC tick in nanoseconds */
768 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
769 mc->regs = devm_ioremap_resource(&pdev->dev, res);
770 if (IS_ERR(mc->regs))
771 return PTR_ERR(mc->regs);
773 mc->clk = devm_clk_get(&pdev->dev, "mc");
774 if (IS_ERR(mc->clk)) {
775 dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
777 return PTR_ERR(mc->clk);
780 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
781 if (mc->soc == &tegra20_mc_soc) {
782 isr = tegra20_mc_irq;
786 /* ensure that debug features are disabled */
787 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG);
789 err = tegra_mc_setup_latency_allowance(mc);
792 "failed to setup latency allowance: %d\n",
799 err = tegra_mc_setup_timings(mc);
801 dev_err(&pdev->dev, "failed to setup timings: %d\n",
807 mc->irq = platform_get_irq(pdev, 0);
811 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n");
813 mc_writel(mc, mc->soc->intmask, MC_INTMASK);
815 err = devm_request_irq(&pdev->dev, mc->irq, isr, 0,
816 dev_name(&pdev->dev), mc);
818 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
823 err = tegra_mc_reset_setup(mc);
825 dev_err(&pdev->dev, "failed to register reset controller: %d\n",
828 err = tegra_mc_interconnect_setup(mc);
830 dev_err(&pdev->dev, "failed to initialize interconnect: %d\n",
833 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) {
834 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
835 if (IS_ERR(mc->smmu)) {
836 dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
842 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) {
843 mc->gart = tegra_gart_probe(&pdev->dev, mc);
844 if (IS_ERR(mc->gart)) {
845 dev_err(&pdev->dev, "failed to probe GART: %ld\n",
854 static int tegra_mc_suspend(struct device *dev)
856 struct tegra_mc *mc = dev_get_drvdata(dev);
859 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
860 err = tegra_gart_suspend(mc->gart);
868 static int tegra_mc_resume(struct device *dev)
870 struct tegra_mc *mc = dev_get_drvdata(dev);
873 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
874 err = tegra_gart_resume(mc->gart);
882 static const struct dev_pm_ops tegra_mc_pm_ops = {
883 .suspend = tegra_mc_suspend,
884 .resume = tegra_mc_resume,
887 static struct platform_driver tegra_mc_driver = {
890 .of_match_table = tegra_mc_of_match,
891 .pm = &tegra_mc_pm_ops,
892 .suppress_bind_attrs = true,
894 .prevent_deferred_probe = true,
895 .probe = tegra_mc_probe,
898 static int tegra_mc_init(void)
900 return platform_driver_register(&tegra_mc_driver);
902 arch_initcall(tegra_mc_init);
904 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
905 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
906 MODULE_LICENSE("GPL v2");