1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019 Samsung Electronics Co., Ltd.
4 * Author: Lukasz Luba <l.luba@partner.samsung.com>
8 #include <linux/devfreq.h>
9 #include <linux/devfreq-event.h>
10 #include <linux/device.h>
11 #include <linux/interrupt.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/of_device.h>
17 #include <linux/pm_opp.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include "../jedec_ddr.h"
23 #include "../of_memory.h"
26 module_param(irqmode, int, 0644);
27 MODULE_PARM_DESC(irqmode, "Enable IRQ mode (0=off [default], 1=on)");
29 #define EXYNOS5_DREXI_TIMINGAREF (0x0030)
30 #define EXYNOS5_DREXI_TIMINGROW0 (0x0034)
31 #define EXYNOS5_DREXI_TIMINGDATA0 (0x0038)
32 #define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C)
33 #define EXYNOS5_DREXI_TIMINGROW1 (0x00E4)
34 #define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8)
35 #define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC)
36 #define CDREX_PAUSE (0x2091c)
37 #define CDREX_LPDDR3PHY_CON3 (0x20a20)
38 #define CDREX_LPDDR3PHY_CLKM_SRC (0x20700)
39 #define EXYNOS5_TIMING_SET_SWI BIT(28)
40 #define USE_MX_MSPLL_TIMINGS (1)
41 #define USE_BPLL_TIMINGS (0)
42 #define EXYNOS5_AREF_NORMAL (0x2e)
44 #define DREX_PPCCLKCON (0x0130)
45 #define DREX_PEREV2CONFIG (0x013c)
46 #define DREX_PMNC_PPC (0xE000)
47 #define DREX_CNTENS_PPC (0xE010)
48 #define DREX_CNTENC_PPC (0xE020)
49 #define DREX_INTENS_PPC (0xE030)
50 #define DREX_INTENC_PPC (0xE040)
51 #define DREX_FLAG_PPC (0xE050)
52 #define DREX_PMCNT2_PPC (0xE130)
55 * A value for register DREX_PMNC_PPC which should be written to reset
56 * the cycle counter CCNT (a reference wall clock). It sets zero to the
59 #define CC_RESET BIT(2)
62 * A value for register DREX_PMNC_PPC which does the reset of all performance
65 #define PPC_COUNTER_RESET BIT(1)
68 * Enables all configured counters (including cycle counter). The value should
69 * be written to the register DREX_PMNC_PPC.
71 #define PPC_ENABLE BIT(0)
73 /* A value for register DREX_PPCCLKCON which enables performance events clock.
74 * Must be written before first access to the performance counters register
75 * set, otherwise it could crash.
77 #define PEREV_CLK_EN BIT(0)
80 * Values which are used to enable counters, interrupts or configure flags of
81 * the performance counters. They configure counter 2 and cycle counter.
83 #define PERF_CNT2 BIT(2)
84 #define PERF_CCNT BIT(31)
87 * Performance event types which are used for setting the preferred event
88 * to track in the counters.
89 * There is a set of different types, the values are from range 0 to 0x6f.
90 * These settings should be written to the configuration register which manages
91 * the type of the event (register DREX_PEREV2CONFIG).
93 #define READ_TRANSFER_CH0 (0x6d)
94 #define READ_TRANSFER_CH1 (0x6f)
96 #define PERF_COUNTER_START_VALUE 0xff000000
97 #define PERF_EVENT_UP_DOWN_THRESHOLD 900000000ULL
100 * struct dmc_opp_table - Operating level desciption
101 * @freq_hz: target frequency in Hz
102 * @volt_uv: target voltage in uV
104 * Covers frequency and voltage settings of the DMC operating mode.
106 struct dmc_opp_table {
112 * struct exynos5_dmc - main structure describing DMC device
114 * @df: devfreq device structure returned by devfreq framework
115 * @gov_data: configuration of devfreq governor
116 * @base_drexi0: DREX0 registers mapping
117 * @base_drexi1: DREX1 registers mapping
118 * @clk_regmap: regmap for clock controller registers
119 * @lock: protects curr_rate and frequency/voltage setting section
120 * @curr_rate: current frequency
121 * @curr_volt: current voltage
123 * @opp_count: number of 'opp' elements
124 * @timings_arr_size: number of 'timings' elements
125 * @timing_row: values for timing row register, for each OPP
126 * @timing_data: values for timing data register, for each OPP
127 * @timing_power: balues for timing power register, for each OPP
128 * @timings: DDR memory timings, from device tree
129 * @min_tck: DDR memory minimum timing values, from device tree
130 * @bypass_timing_row: value for timing row register for bypass timings
131 * @bypass_timing_data: value for timing data register for bypass timings
132 * @bypass_timing_power: value for timing power register for bypass
134 * @vdd_mif: Memory interface regulator
135 * @fout_spll: clock: SPLL
136 * @fout_bpll: clock: BPLL
137 * @mout_spll: clock: mux SPLL
138 * @mout_bpll: clock: mux BPLL
139 * @mout_mclk_cdrex: clock: mux mclk_cdrex
140 * @mout_mx_mspll_ccore: clock: mux mx_mspll_ccore
141 * @counter: devfreq events
142 * @num_counters: number of 'counter' elements
143 * @last_overflow_ts: time (in ns) of last overflow of each DREX
144 * @load: utilization in percents
145 * @total: total time between devfreq events
146 * @in_irq_mode: whether running in interrupt mode (true)
149 * The main structure for the Dynamic Memory Controller which covers clocks,
150 * memory regions, HW information, parameters and current operating mode.
155 struct devfreq_simple_ondemand_data gov_data;
156 void __iomem *base_drexi0;
157 void __iomem *base_drexi1;
158 struct regmap *clk_regmap;
159 /* Protects curr_rate and frequency/voltage setting section */
161 unsigned long curr_rate;
162 unsigned long curr_volt;
163 struct dmc_opp_table *opp;
165 u32 timings_arr_size;
169 const struct lpddr3_timings *timings;
170 const struct lpddr3_min_tck *min_tck;
171 u32 bypass_timing_row;
172 u32 bypass_timing_data;
173 u32 bypass_timing_power;
174 struct regulator *vdd_mif;
175 struct clk *fout_spll;
176 struct clk *fout_bpll;
177 struct clk *mout_spll;
178 struct clk *mout_bpll;
179 struct clk *mout_mclk_cdrex;
180 struct clk *mout_mx_mspll_ccore;
181 struct devfreq_event_dev **counter;
183 u64 last_overflow_ts[2];
189 #define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \
190 { .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end }
192 #define TIMING_VAL2REG(timing, t_val) \
195 __val = (t_val) << (timing)->bit_beg; \
206 static const struct timing_reg timing_row_reg_fields[] = {
207 TIMING_FIELD("tRFC", 24, 31),
208 TIMING_FIELD("tRRD", 20, 23),
209 TIMING_FIELD("tRP", 16, 19),
210 TIMING_FIELD("tRCD", 12, 15),
211 TIMING_FIELD("tRC", 6, 11),
212 TIMING_FIELD("tRAS", 0, 5),
215 static const struct timing_reg timing_data_reg_fields[] = {
216 TIMING_FIELD("tWTR", 28, 31),
217 TIMING_FIELD("tWR", 24, 27),
218 TIMING_FIELD("tRTP", 20, 23),
219 TIMING_FIELD("tW2W-C2C", 14, 14),
220 TIMING_FIELD("tR2R-C2C", 12, 12),
221 TIMING_FIELD("WL", 8, 11),
222 TIMING_FIELD("tDQSCK", 4, 7),
223 TIMING_FIELD("RL", 0, 3),
226 static const struct timing_reg timing_power_reg_fields[] = {
227 TIMING_FIELD("tFAW", 26, 31),
228 TIMING_FIELD("tXSR", 16, 25),
229 TIMING_FIELD("tXP", 8, 15),
230 TIMING_FIELD("tCKE", 4, 7),
231 TIMING_FIELD("tMRD", 0, 3),
234 #define TIMING_COUNT (ARRAY_SIZE(timing_row_reg_fields) + \
235 ARRAY_SIZE(timing_data_reg_fields) + \
236 ARRAY_SIZE(timing_power_reg_fields))
238 static int exynos5_counters_set_event(struct exynos5_dmc *dmc)
242 for (i = 0; i < dmc->num_counters; i++) {
243 if (!dmc->counter[i])
245 ret = devfreq_event_set_event(dmc->counter[i]);
252 static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc)
256 for (i = 0; i < dmc->num_counters; i++) {
257 if (!dmc->counter[i])
259 ret = devfreq_event_enable_edev(dmc->counter[i]);
266 static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc)
270 for (i = 0; i < dmc->num_counters; i++) {
271 if (!dmc->counter[i])
273 ret = devfreq_event_disable_edev(dmc->counter[i]);
281 * find_target_freq_idx() - Finds requested frequency in local DMC configuration
282 * @dmc: device for which the information is checked
283 * @target_rate: requested frequency in KHz
285 * Seeks in the local DMC driver structure for the requested frequency value
286 * and returns index or error value.
288 static int find_target_freq_idx(struct exynos5_dmc *dmc,
289 unsigned long target_rate)
293 for (i = dmc->opp_count - 1; i >= 0; i--)
294 if (dmc->opp[i].freq_hz <= target_rate)
301 * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
302 * @dmc: device for which the new settings is going to be applied
303 * @set: boolean variable passing set value
305 * Changes the register set, which holds timing parameters.
306 * There is two register sets: 0 and 1. The register set 0
307 * is used in normal operation when the clock is provided from main PLL.
308 * The bank register set 1 is used when the main PLL frequency is going to be
309 * changed and the clock is taken from alternative, stable source.
310 * This function switches between these banks according to the
311 * currently used clock source.
313 static int exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
318 ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®);
323 reg |= EXYNOS5_TIMING_SET_SWI;
325 reg &= ~EXYNOS5_TIMING_SET_SWI;
327 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);
333 * exynos5_init_freq_table() - Initialized PM OPP framework
334 * @dmc: DMC device for which the frequencies are used for OPP init
335 * @profile: devfreq device's profile
337 * Populate the devfreq device's OPP table based on current frequency, voltage.
339 static int exynos5_init_freq_table(struct exynos5_dmc *dmc,
340 struct devfreq_dev_profile *profile)
346 ret = devm_pm_opp_of_add_table(dmc->dev);
348 dev_err(dmc->dev, "Failed to get OPP table\n");
352 dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev);
354 dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count,
355 sizeof(struct dmc_opp_table), GFP_KERNEL);
359 idx = dmc->opp_count - 1;
360 for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) {
361 struct dev_pm_opp *opp;
363 opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq);
367 dmc->opp[idx - i].freq_hz = freq;
368 dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp);
377 * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
378 * @dmc: device for which the new settings is going to be applied
380 * Low-level function for changing timings for DRAM memory clocking from
381 * 'bypass' clock source (fixed frequency @400MHz).
382 * It uses timing bank registers set 1.
384 static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc)
386 writel(EXYNOS5_AREF_NORMAL,
387 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
389 writel(dmc->bypass_timing_row,
390 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
391 writel(dmc->bypass_timing_row,
392 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
393 writel(dmc->bypass_timing_data,
394 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
395 writel(dmc->bypass_timing_data,
396 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
397 writel(dmc->bypass_timing_power,
398 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
399 writel(dmc->bypass_timing_power,
400 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
404 * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
405 * @dmc: device for which the new settings is going to be applied
406 * @target_rate: target frequency of the DMC
408 * Low-level function for changing timings for DRAM memory operating from main
409 * clock source (BPLL), which can have different frequencies. Thus, each
410 * frequency must have corresponding timings register values in order to keep
412 * It uses timing bank registers set 0.
414 static int exynos5_dram_change_timings(struct exynos5_dmc *dmc,
415 unsigned long target_rate)
419 for (idx = dmc->opp_count - 1; idx >= 0; idx--)
420 if (dmc->opp[idx].freq_hz <= target_rate)
426 writel(EXYNOS5_AREF_NORMAL,
427 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
429 writel(dmc->timing_row[idx],
430 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
431 writel(dmc->timing_row[idx],
432 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
433 writel(dmc->timing_data[idx],
434 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
435 writel(dmc->timing_data[idx],
436 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
437 writel(dmc->timing_power[idx],
438 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
439 writel(dmc->timing_power[idx],
440 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
446 * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC
447 * @dmc: device for which it is going to be set
448 * @target_volt: new voltage which is chosen to be final
450 * Function tries to align voltage to the safe level for 'normal' mode.
451 * It checks the need of higher voltage and changes the value. The target
452 * voltage might be lower that currently set and still the system will be
455 static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc,
456 unsigned long target_volt)
460 if (dmc->curr_volt <= target_volt)
463 ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
466 dmc->curr_volt = target_volt;
472 * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC
473 * @dmc: device for which it is going to be set
474 * @target_volt: new voltage which is chosen to be final
476 * Function tries to align voltage to the safe level for the 'bypass' mode.
477 * It checks the need of higher voltage and changes the value.
478 * The target voltage must not be less than currently needed, because
479 * for current frequency the device might become unstable.
481 static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
482 unsigned long target_volt)
486 if (dmc->curr_volt >= target_volt)
489 ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
492 dmc->curr_volt = target_volt;
498 * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
499 * @dmc: device for which it is going to be set
500 * @target_rate: new frequency which is chosen to be final
502 * Function changes the DRAM timings for the temporary 'bypass' mode.
504 static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc,
505 unsigned long target_rate)
507 int idx = find_target_freq_idx(dmc, target_rate);
512 exynos5_set_bypass_dram_timings(dmc);
518 * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock
519 * @dmc: DMC device for which the switching is going to happen
520 * @target_rate: new frequency which is going to be set as a final
521 * @target_volt: new voltage which is going to be set as a final
523 * Function configures DMC and clocks for operating in temporary 'bypass' mode.
524 * This mode is used only temporary but if required, changes voltage and timings
525 * for DRAM chips. It switches the main clock to stable clock source for the
526 * period of the main PLL reconfiguration.
529 exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc,
530 unsigned long target_rate,
531 unsigned long target_volt)
536 * Having higher voltage for a particular frequency does not harm
537 * the chip. Use it for the temporary frequency change when one
538 * voltage manipulation might be avoided.
540 ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt);
545 * Longer delays for DRAM does not cause crash, the opposite does.
547 ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate);
552 * Delays are long enough, so use them for the new coming clock.
554 ret = exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);
560 * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC
561 * using safe procedure
562 * @dmc: device for which the frequency is going to be changed
563 * @target_rate: requested new frequency
564 * @target_volt: requested voltage which corresponds to the new frequency
566 * The DMC frequency change procedure requires a few steps.
567 * The main requirement is to change the clock source in the clk mux
568 * for the time of main clock PLL locking. The assumption is that the
569 * alternative clock source set as parent is stable.
570 * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass'
571 * clock. This requires alignment in DRAM timing parameters for the new
572 * T-period. There is two bank sets for keeping DRAM
573 * timings: set 0 and set 1. The set 0 is used when main clock source is
574 * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between
575 * the two bank sets is part of the process.
576 * The voltage must also be aligned to the minimum required level. There is
577 * this intermediate step with switching to 'bypass' parent clock source.
578 * if the old voltage is lower, it requires an increase of the voltage level.
579 * The complexity of the voltage manipulation is hidden in low level function.
580 * In this function there is last alignment of the voltage level at the end.
583 exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
584 unsigned long target_rate,
585 unsigned long target_volt)
589 ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate,
595 * Voltage is set at least to a level needed for this frequency,
596 * so switching clock source is safe now.
598 clk_prepare_enable(dmc->fout_spll);
599 clk_prepare_enable(dmc->mout_spll);
600 clk_prepare_enable(dmc->mout_mx_mspll_ccore);
602 ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore);
607 * We are safe to increase the timings for current bypass frequency.
608 * Thanks to this the settings will be ready for the upcoming clock
611 exynos5_dram_change_timings(dmc, target_rate);
613 clk_set_rate(dmc->fout_bpll, target_rate);
615 ret = exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);
619 ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
624 * Make sure if the voltage is not from 'bypass' settings and align to
625 * the right level for power efficiency.
627 ret = exynos5_dmc_align_target_voltage(dmc, target_volt);
630 clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
631 clk_disable_unprepare(dmc->mout_spll);
632 clk_disable_unprepare(dmc->fout_spll);
638 * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP
640 * @dmc: device for which the frequency is going to be changed
641 * @freq: requested frequency in KHz
642 * @target_rate: returned frequency which is the same or lower than
644 * @target_volt: returned voltage which corresponds to the returned
646 * @flags: devfreq flags provided for this frequency change request
648 * Function gets requested frequency and checks OPP framework for needed
649 * frequency and voltage. It populates the values 'target_rate' and
650 * 'target_volt' or returns error value when OPP framework fails.
652 static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc,
654 unsigned long *target_rate,
655 unsigned long *target_volt, u32 flags)
657 struct dev_pm_opp *opp;
659 opp = devfreq_recommended_opp(dmc->dev, freq, flags);
663 *target_rate = dev_pm_opp_get_freq(opp);
664 *target_volt = dev_pm_opp_get_voltage(opp);
671 * exynos5_dmc_target() - Function responsible for changing frequency of DMC
672 * @dev: device for which the frequency is going to be changed
673 * @freq: requested frequency in KHz
674 * @flags: flags provided for this frequency change request
676 * An entry function provided to the devfreq framework which provides frequency
677 * change of the DMC. The function gets the possible rate from OPP table based
678 * on requested frequency. It calls the next function responsible for the
679 * frequency and voltage change. In case of failure, does not set 'curr_rate'
680 * and returns error value to the framework.
682 static int exynos5_dmc_target(struct device *dev, unsigned long *freq,
685 struct exynos5_dmc *dmc = dev_get_drvdata(dev);
686 unsigned long target_rate = 0;
687 unsigned long target_volt = 0;
690 ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt,
696 if (target_rate == dmc->curr_rate)
699 mutex_lock(&dmc->lock);
701 ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);
704 mutex_unlock(&dmc->lock);
708 dmc->curr_rate = target_rate;
710 mutex_unlock(&dmc->lock);
715 * exynos5_counters_get() - Gets the performance counters values.
716 * @dmc: device for which the counters are going to be checked
717 * @load_count: variable which is populated with counter value
718 * @total_count: variable which is used as 'wall clock' reference
720 * Function which provides performance counters values. It sums up counters for
721 * two DMC channels. The 'total_count' is used as a reference and max value.
722 * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%].
724 static int exynos5_counters_get(struct exynos5_dmc *dmc,
725 unsigned long *load_count,
726 unsigned long *total_count)
728 unsigned long total = 0;
729 struct devfreq_event_data event;
734 /* Take into account only read+write counters, but stop all */
735 for (i = 0; i < dmc->num_counters; i++) {
736 if (!dmc->counter[i])
739 ret = devfreq_event_get_event(dmc->counter[i], &event);
743 *load_count += event.load_count;
745 if (total < event.total_count)
746 total = event.total_count;
749 *total_count = total;
755 * exynos5_dmc_start_perf_events() - Setup and start performance event counters
756 * @dmc: device for which the counters are going to be checked
757 * @beg_value: initial value for the counter
759 * Function which enables needed counters, interrupts and sets initial values
760 * then starts the counters.
762 static void exynos5_dmc_start_perf_events(struct exynos5_dmc *dmc,
765 /* Enable interrupts for counter 2 */
766 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC);
767 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC);
769 /* Enable counter 2 and CCNT */
770 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC);
771 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC);
773 /* Clear overflow flag for all counters */
774 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
775 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
777 /* Reset all counters */
778 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC);
779 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC);
782 * Set start value for the counters, the number of samples that
783 * will be gathered is calculated as: 0xffffffff - beg_value
785 writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC);
786 writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC);
788 /* Start all counters */
789 writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC);
790 writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC);
794 * exynos5_dmc_perf_events_calc() - Calculate utilization
795 * @dmc: device for which the counters are going to be checked
796 * @diff_ts: time between last interrupt and current one
798 * Function which calculates needed utilization for the devfreq governor.
799 * It prepares values for 'busy_time' and 'total_time' based on elapsed time
800 * between interrupts, which approximates utilization.
802 static void exynos5_dmc_perf_events_calc(struct exynos5_dmc *dmc, u64 diff_ts)
805 * This is a simple algorithm for managing traffic on DMC.
806 * When there is almost no load the counters overflow every 4s,
807 * no mater the DMC frequency.
808 * The high load might be approximated using linear function.
809 * Knowing that, simple calculation can provide 'busy_time' and
810 * 'total_time' to the devfreq governor which picks up target
812 * We want a fast ramp up and slow decay in frequency change function.
814 if (diff_ts < PERF_EVENT_UP_DOWN_THRESHOLD) {
816 * Set higher utilization for the simple_ondemand governor.
817 * The governor should increase the frequency of the DMC.
823 * Set low utilization for the simple_ondemand governor.
824 * The governor should decrease the frequency of the DMC.
830 dev_dbg(dmc->dev, "diff_ts=%llu\n", diff_ts);
834 * exynos5_dmc_perf_events_check() - Checks the status of the counters
835 * @dmc: device for which the counters are going to be checked
837 * Function which is called from threaded IRQ to check the counters state
838 * and to call approximation for the needed utilization.
840 static void exynos5_dmc_perf_events_check(struct exynos5_dmc *dmc)
847 /* Stop all counters */
848 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
849 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
851 /* Check the source in interrupt flag registers (which channel) */
852 val = readl(dmc->base_drexi0 + DREX_FLAG_PPC);
854 diff_ts = ts - dmc->last_overflow_ts[0];
855 dmc->last_overflow_ts[0] = ts;
856 dev_dbg(dmc->dev, "drex0 0xE050 val= 0x%08x\n", val);
858 val = readl(dmc->base_drexi1 + DREX_FLAG_PPC);
859 diff_ts = ts - dmc->last_overflow_ts[1];
860 dmc->last_overflow_ts[1] = ts;
861 dev_dbg(dmc->dev, "drex1 0xE050 val= 0x%08x\n", val);
864 exynos5_dmc_perf_events_calc(dmc, diff_ts);
866 exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE);
870 * exynos5_dmc_enable_perf_events() - Enable performance events
871 * @dmc: device for which the counters are going to be checked
873 * Function which is setup needed environment and enables counters.
875 static void exynos5_dmc_enable_perf_events(struct exynos5_dmc *dmc)
879 /* Enable Performance Event Clock */
880 writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON);
881 writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON);
883 /* Select read transfers as performance event2 */
884 writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG);
885 writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG);
888 dmc->last_overflow_ts[0] = ts;
889 dmc->last_overflow_ts[1] = ts;
891 /* Devfreq shouldn't be faster than initialization, play safe though. */
897 * exynos5_dmc_disable_perf_events() - Disable performance events
898 * @dmc: device for which the counters are going to be checked
900 * Function which stops, disables performance event counters and interrupts.
902 static void exynos5_dmc_disable_perf_events(struct exynos5_dmc *dmc)
904 /* Stop all counters */
905 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
906 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
908 /* Disable interrupts for counter 2 */
909 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC);
910 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC);
912 /* Disable counter 2 and CCNT */
913 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC);
914 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC);
916 /* Clear overflow flag for all counters */
917 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
918 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
922 * exynos5_dmc_get_status() - Read current DMC performance statistics.
923 * @dev: device for which the statistics are requested
924 * @stat: structure which has statistic fields
926 * Function reads the DMC performance counters and calculates 'busy_time'
927 * and 'total_time'. To protect from overflow, the values are shifted right
928 * by 10. After read out the counters are setup to count again.
930 static int exynos5_dmc_get_status(struct device *dev,
931 struct devfreq_dev_status *stat)
933 struct exynos5_dmc *dmc = dev_get_drvdata(dev);
934 unsigned long load, total;
937 if (dmc->in_irq_mode) {
938 mutex_lock(&dmc->lock);
939 stat->current_frequency = dmc->curr_rate;
940 mutex_unlock(&dmc->lock);
942 stat->busy_time = dmc->load;
943 stat->total_time = dmc->total;
945 ret = exynos5_counters_get(dmc, &load, &total);
949 /* To protect from overflow, divide by 1024 */
950 stat->busy_time = load >> 10;
951 stat->total_time = total >> 10;
953 ret = exynos5_counters_set_event(dmc);
955 dev_err(dev, "could not set event counter\n");
964 * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency
965 * @dev: device for which the framework checks operating frequency
966 * @freq: returned frequency value
968 * It returns the currently used frequency of the DMC. The real operating
969 * frequency might be lower when the clock source value could not be divided
970 * to the requested value.
972 static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq)
974 struct exynos5_dmc *dmc = dev_get_drvdata(dev);
976 mutex_lock(&dmc->lock);
977 *freq = dmc->curr_rate;
978 mutex_unlock(&dmc->lock);
984 * exynos5_dmc_df_profile - Devfreq governor's profile structure
986 * It provides to the devfreq framework needed functions and polling period.
988 static struct devfreq_dev_profile exynos5_dmc_df_profile = {
989 .timer = DEVFREQ_TIMER_DELAYED,
990 .target = exynos5_dmc_target,
991 .get_dev_status = exynos5_dmc_get_status,
992 .get_cur_freq = exynos5_dmc_get_cur_freq,
996 * exynos5_dmc_align_init_freq() - Align initial frequency value
997 * @dmc: device for which the frequency is going to be set
998 * @bootloader_init_freq: initial frequency set by the bootloader in KHz
1000 * The initial bootloader frequency, which is present during boot, might be
1001 * different that supported frequency values in the driver. It is possible
1002 * due to different PLL settings or used PLL as a source.
1003 * This function provides the 'initial_freq' for the devfreq framework
1004 * statistics engine which supports only registered values. Thus, some alignment
1007 static unsigned long
1008 exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
1009 unsigned long bootloader_init_freq)
1011 unsigned long aligned_freq;
1014 idx = find_target_freq_idx(dmc, bootloader_init_freq);
1016 aligned_freq = dmc->opp[idx].freq_hz;
1018 aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz;
1020 return aligned_freq;
1024 * create_timings_aligned() - Create register values and align with standard
1025 * @dmc: device for which the frequency is going to be set
1026 * @reg_timing_row: array to fill with values for timing row register
1027 * @reg_timing_data: array to fill with values for timing data register
1028 * @reg_timing_power: array to fill with values for timing power register
1029 * @clk_period_ps: the period of the clock, known as tCK
1031 * The function calculates timings and creates a register value ready for
1032 * a frequency transition. The register contains a few timings. They are
1033 * shifted by a known offset. The timing value is calculated based on memory
1034 * specyfication: minimal time required and minimal cycles required.
1036 static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
1037 u32 *reg_timing_data, u32 *reg_timing_power,
1041 const struct timing_reg *reg;
1043 if (clk_period_ps == 0)
1046 *reg_timing_row = 0;
1047 *reg_timing_data = 0;
1048 *reg_timing_power = 0;
1050 val = dmc->timings->tRFC / clk_period_ps;
1051 val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
1052 val = max(val, dmc->min_tck->tRFC);
1053 reg = &timing_row_reg_fields[0];
1054 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1056 val = dmc->timings->tRRD / clk_period_ps;
1057 val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
1058 val = max(val, dmc->min_tck->tRRD);
1059 reg = &timing_row_reg_fields[1];
1060 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1062 val = dmc->timings->tRPab / clk_period_ps;
1063 val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
1064 val = max(val, dmc->min_tck->tRPab);
1065 reg = &timing_row_reg_fields[2];
1066 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1068 val = dmc->timings->tRCD / clk_period_ps;
1069 val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
1070 val = max(val, dmc->min_tck->tRCD);
1071 reg = &timing_row_reg_fields[3];
1072 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1074 val = dmc->timings->tRC / clk_period_ps;
1075 val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
1076 val = max(val, dmc->min_tck->tRC);
1077 reg = &timing_row_reg_fields[4];
1078 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1080 val = dmc->timings->tRAS / clk_period_ps;
1081 val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
1082 val = max(val, dmc->min_tck->tRAS);
1083 reg = &timing_row_reg_fields[5];
1084 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1086 /* data related timings */
1087 val = dmc->timings->tWTR / clk_period_ps;
1088 val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
1089 val = max(val, dmc->min_tck->tWTR);
1090 reg = &timing_data_reg_fields[0];
1091 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1093 val = dmc->timings->tWR / clk_period_ps;
1094 val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
1095 val = max(val, dmc->min_tck->tWR);
1096 reg = &timing_data_reg_fields[1];
1097 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1099 val = dmc->timings->tRTP / clk_period_ps;
1100 val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
1101 val = max(val, dmc->min_tck->tRTP);
1102 reg = &timing_data_reg_fields[2];
1103 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1105 val = dmc->timings->tW2W_C2C / clk_period_ps;
1106 val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
1107 val = max(val, dmc->min_tck->tW2W_C2C);
1108 reg = &timing_data_reg_fields[3];
1109 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1111 val = dmc->timings->tR2R_C2C / clk_period_ps;
1112 val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
1113 val = max(val, dmc->min_tck->tR2R_C2C);
1114 reg = &timing_data_reg_fields[4];
1115 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1117 val = dmc->timings->tWL / clk_period_ps;
1118 val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
1119 val = max(val, dmc->min_tck->tWL);
1120 reg = &timing_data_reg_fields[5];
1121 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1123 val = dmc->timings->tDQSCK / clk_period_ps;
1124 val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
1125 val = max(val, dmc->min_tck->tDQSCK);
1126 reg = &timing_data_reg_fields[6];
1127 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1129 val = dmc->timings->tRL / clk_period_ps;
1130 val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
1131 val = max(val, dmc->min_tck->tRL);
1132 reg = &timing_data_reg_fields[7];
1133 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1135 /* power related timings */
1136 val = dmc->timings->tFAW / clk_period_ps;
1137 val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
1138 val = max(val, dmc->min_tck->tFAW);
1139 reg = &timing_power_reg_fields[0];
1140 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1142 val = dmc->timings->tXSR / clk_period_ps;
1143 val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
1144 val = max(val, dmc->min_tck->tXSR);
1145 reg = &timing_power_reg_fields[1];
1146 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1148 val = dmc->timings->tXP / clk_period_ps;
1149 val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
1150 val = max(val, dmc->min_tck->tXP);
1151 reg = &timing_power_reg_fields[2];
1152 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1154 val = dmc->timings->tCKE / clk_period_ps;
1155 val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
1156 val = max(val, dmc->min_tck->tCKE);
1157 reg = &timing_power_reg_fields[3];
1158 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1160 val = dmc->timings->tMRD / clk_period_ps;
1161 val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
1162 val = max(val, dmc->min_tck->tMRD);
1163 reg = &timing_power_reg_fields[4];
1164 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1170 * of_get_dram_timings() - helper function for parsing DT settings for DRAM
1171 * @dmc: device for which the frequency is going to be set
1173 * The function parses DT entries with DRAM information.
1175 static int of_get_dram_timings(struct exynos5_dmc *dmc)
1179 struct device_node *np_ddr;
1180 u32 freq_mhz, clk_period_ps;
1182 np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0);
1184 dev_warn(dmc->dev, "could not find 'device-handle' in DT\n");
1188 dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
1189 sizeof(u32), GFP_KERNEL);
1190 if (!dmc->timing_row)
1193 dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
1194 sizeof(u32), GFP_KERNEL);
1195 if (!dmc->timing_data)
1198 dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
1199 sizeof(u32), GFP_KERNEL);
1200 if (!dmc->timing_power)
1203 dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev,
1205 &dmc->timings_arr_size);
1206 if (!dmc->timings) {
1207 of_node_put(np_ddr);
1208 dev_warn(dmc->dev, "could not get timings from DT\n");
1212 dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev);
1213 if (!dmc->min_tck) {
1214 of_node_put(np_ddr);
1215 dev_warn(dmc->dev, "could not get tck from DT\n");
1219 /* Sorted array of OPPs with frequency ascending */
1220 for (idx = 0; idx < dmc->opp_count; idx++) {
1221 freq_mhz = dmc->opp[idx].freq_hz / 1000000;
1222 clk_period_ps = 1000000 / freq_mhz;
1224 ret = create_timings_aligned(dmc, &dmc->timing_row[idx],
1225 &dmc->timing_data[idx],
1226 &dmc->timing_power[idx],
1230 of_node_put(np_ddr);
1232 /* Take the highest frequency's timings as 'bypass' */
1233 dmc->bypass_timing_row = dmc->timing_row[idx - 1];
1234 dmc->bypass_timing_data = dmc->timing_data[idx - 1];
1235 dmc->bypass_timing_power = dmc->timing_power[idx - 1];
1241 * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
1242 * @dmc: DMC structure containing needed fields
1244 * Get the needed clocks defined in DT device, enable and set the right parents.
1245 * Read current frequency and initialize the initial rate for governor.
1247 static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
1250 unsigned long target_volt = 0;
1251 unsigned long target_rate = 0;
1254 dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll");
1255 if (IS_ERR(dmc->fout_spll))
1256 return PTR_ERR(dmc->fout_spll);
1258 dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll");
1259 if (IS_ERR(dmc->fout_bpll))
1260 return PTR_ERR(dmc->fout_bpll);
1262 dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex");
1263 if (IS_ERR(dmc->mout_mclk_cdrex))
1264 return PTR_ERR(dmc->mout_mclk_cdrex);
1266 dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll");
1267 if (IS_ERR(dmc->mout_bpll))
1268 return PTR_ERR(dmc->mout_bpll);
1270 dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev,
1271 "mout_mx_mspll_ccore");
1272 if (IS_ERR(dmc->mout_mx_mspll_ccore))
1273 return PTR_ERR(dmc->mout_mx_mspll_ccore);
1275 dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2");
1276 if (IS_ERR(dmc->mout_spll)) {
1277 dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll");
1278 if (IS_ERR(dmc->mout_spll))
1279 return PTR_ERR(dmc->mout_spll);
1283 * Convert frequency to KHz values and set it for the governor.
1285 dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex);
1286 dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate);
1287 exynos5_dmc_df_profile.initial_freq = dmc->curr_rate;
1289 ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate,
1294 dmc->curr_volt = target_volt;
1296 ret = clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
1300 clk_prepare_enable(dmc->fout_bpll);
1301 clk_prepare_enable(dmc->mout_bpll);
1304 * Some bootloaders do not set clock routes correctly.
1305 * Stop one path in clocks to PHY.
1307 regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, &tmp);
1308 tmp &= ~(BIT(1) | BIT(0));
1309 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, tmp);
1315 * exynos5_performance_counters_init() - Initializes performance DMC's counters
1316 * @dmc: DMC for which it does the setup
1318 * Initialization of performance counters in DMC for estimating usage.
1319 * The counter's values are used for calculation of a memory bandwidth and based
1320 * on that the governor changes the frequency.
1321 * The counters are not used when the governor is GOVERNOR_USERSPACE.
1323 static int exynos5_performance_counters_init(struct exynos5_dmc *dmc)
1328 dmc->num_counters = devfreq_event_get_edev_count(dmc->dev,
1330 if (dmc->num_counters < 0) {
1331 dev_err(dmc->dev, "could not get devfreq-event counters\n");
1332 return dmc->num_counters;
1335 counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters;
1336 dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL);
1340 for (i = 0; i < dmc->num_counters; i++) {
1342 devfreq_event_get_edev_by_phandle(dmc->dev,
1343 "devfreq-events", i);
1344 if (IS_ERR_OR_NULL(dmc->counter[i]))
1345 return -EPROBE_DEFER;
1348 ret = exynos5_counters_enable_edev(dmc);
1350 dev_err(dmc->dev, "could not enable event counter\n");
1354 ret = exynos5_counters_set_event(dmc);
1356 exynos5_counters_disable_edev(dmc);
1357 dev_err(dmc->dev, "could not set event counter\n");
1365 * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC
1366 * @dmc: device which is used for changing this feature
1368 * There is a need of pausing DREX DMC when divider or MUX in clock tree
1369 * changes its configuration. In such situation access to the memory is blocked
1370 * in DMC automatically. This feature is used when clock frequency change
1371 * request appears and touches clock tree.
1373 static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc)
1378 ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val);
1383 regmap_write(dmc->clk_regmap, CDREX_PAUSE, val);
1388 static irqreturn_t dmc_irq_thread(int irq, void *priv)
1391 struct exynos5_dmc *dmc = priv;
1393 mutex_lock(&dmc->df->lock);
1394 exynos5_dmc_perf_events_check(dmc);
1395 res = update_devfreq(dmc->df);
1396 mutex_unlock(&dmc->df->lock);
1399 dev_warn(dmc->dev, "devfreq failed with %d\n", res);
1405 * exynos5_dmc_probe() - Probe function for the DMC driver
1406 * @pdev: platform device for which the driver is going to be initialized
1408 * Initialize basic components: clocks, regulators, performance counters, etc.
1409 * Read out product version and based on the information setup
1410 * internal structures for the controller (frequency and voltage) and for DRAM
1411 * memory parameters: timings for each operating frequency.
1412 * Register new devfreq device for controlling DVFS of the DMC.
1414 static int exynos5_dmc_probe(struct platform_device *pdev)
1417 struct device *dev = &pdev->dev;
1418 struct device_node *np = dev->of_node;
1419 struct exynos5_dmc *dmc;
1422 dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL);
1426 mutex_init(&dmc->lock);
1429 platform_set_drvdata(pdev, dmc);
1431 dmc->base_drexi0 = devm_platform_ioremap_resource(pdev, 0);
1432 if (IS_ERR(dmc->base_drexi0))
1433 return PTR_ERR(dmc->base_drexi0);
1435 dmc->base_drexi1 = devm_platform_ioremap_resource(pdev, 1);
1436 if (IS_ERR(dmc->base_drexi1))
1437 return PTR_ERR(dmc->base_drexi1);
1439 dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np,
1440 "samsung,syscon-clk");
1441 if (IS_ERR(dmc->clk_regmap))
1442 return PTR_ERR(dmc->clk_regmap);
1444 ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile);
1446 dev_warn(dev, "couldn't initialize frequency settings\n");
1450 dmc->vdd_mif = devm_regulator_get(dev, "vdd");
1451 if (IS_ERR(dmc->vdd_mif)) {
1452 ret = PTR_ERR(dmc->vdd_mif);
1456 ret = exynos5_dmc_init_clks(dmc);
1460 ret = of_get_dram_timings(dmc);
1462 dev_warn(dev, "couldn't initialize timings settings\n");
1466 ret = exynos5_dmc_set_pause_on_switching(dmc);
1468 dev_warn(dev, "couldn't get access to PAUSE register\n");
1472 /* There is two modes in which the driver works: polling or IRQ */
1473 irq[0] = platform_get_irq_byname(pdev, "drex_0");
1474 irq[1] = platform_get_irq_byname(pdev, "drex_1");
1475 if (irq[0] > 0 && irq[1] > 0 && irqmode) {
1476 ret = devm_request_threaded_irq(dev, irq[0], NULL,
1477 dmc_irq_thread, IRQF_ONESHOT,
1478 dev_name(dev), dmc);
1480 dev_err(dev, "couldn't grab IRQ\n");
1484 ret = devm_request_threaded_irq(dev, irq[1], NULL,
1485 dmc_irq_thread, IRQF_ONESHOT,
1486 dev_name(dev), dmc);
1488 dev_err(dev, "couldn't grab IRQ\n");
1493 * Setup default thresholds for the devfreq governor.
1494 * The values are chosen based on experiments.
1496 dmc->gov_data.upthreshold = 55;
1497 dmc->gov_data.downdifferential = 5;
1499 exynos5_dmc_enable_perf_events(dmc);
1501 dmc->in_irq_mode = 1;
1503 ret = exynos5_performance_counters_init(dmc);
1505 dev_warn(dev, "couldn't probe performance counters\n");
1510 * Setup default thresholds for the devfreq governor.
1511 * The values are chosen based on experiments.
1513 dmc->gov_data.upthreshold = 10;
1514 dmc->gov_data.downdifferential = 5;
1516 exynos5_dmc_df_profile.polling_ms = 100;
1519 dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
1520 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1523 if (IS_ERR(dmc->df)) {
1524 ret = PTR_ERR(dmc->df);
1525 goto err_devfreq_add;
1528 if (dmc->in_irq_mode)
1529 exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE);
1531 dev_info(dev, "DMC initialized, in irq mode: %d\n", dmc->in_irq_mode);
1536 if (dmc->in_irq_mode)
1537 exynos5_dmc_disable_perf_events(dmc);
1539 exynos5_counters_disable_edev(dmc);
1541 clk_disable_unprepare(dmc->mout_bpll);
1542 clk_disable_unprepare(dmc->fout_bpll);
1548 * exynos5_dmc_remove() - Remove function for the platform device
1549 * @pdev: platform device which is going to be removed
1551 * The function relies on 'devm' framework function which automatically
1552 * clean the device's resources. It just calls explicitly disable function for
1553 * the performance counters.
1555 static int exynos5_dmc_remove(struct platform_device *pdev)
1557 struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev);
1559 if (dmc->in_irq_mode)
1560 exynos5_dmc_disable_perf_events(dmc);
1562 exynos5_counters_disable_edev(dmc);
1564 clk_disable_unprepare(dmc->mout_bpll);
1565 clk_disable_unprepare(dmc->fout_bpll);
1570 static const struct of_device_id exynos5_dmc_of_match[] = {
1571 { .compatible = "samsung,exynos5422-dmc", },
1574 MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match);
1576 static struct platform_driver exynos5_dmc_platdrv = {
1577 .probe = exynos5_dmc_probe,
1578 .remove = exynos5_dmc_remove,
1580 .name = "exynos5-dmc",
1581 .of_match_table = exynos5_dmc_of_match,
1584 module_platform_driver(exynos5_dmc_platdrv);
1585 MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change");
1586 MODULE_LICENSE("GPL v2");
1587 MODULE_AUTHOR("Lukasz Luba");