drivers/memory/samsung/exynos5422-dmc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 Samsung Electronics Co., Ltd.
   4  * Author: Lukasz Luba <l.luba@partner.samsung.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/devfreq.h>
   9 #include <linux/devfreq-event.h>
  10 #include <linux/device.h>
  11 #include <linux/io.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_opp.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/regmap.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/slab.h>
  20 #include "../jedec_ddr.h"
  21 #include "../of_memory.h"
  22
  23 #define EXYNOS5_DREXI_TIMINGAREF                (0x0030)
  24 #define EXYNOS5_DREXI_TIMINGROW0                (0x0034)
  25 #define EXYNOS5_DREXI_TIMINGDATA0               (0x0038)
  26 #define EXYNOS5_DREXI_TIMINGPOWER0              (0x003C)
  27 #define EXYNOS5_DREXI_TIMINGROW1                (0x00E4)
  28 #define EXYNOS5_DREXI_TIMINGDATA1               (0x00E8)
  29 #define EXYNOS5_DREXI_TIMINGPOWER1              (0x00EC)
  30 #define CDREX_PAUSE                             (0x2091c)
  31 #define CDREX_LPDDR3PHY_CON3                    (0x20a20)
  32 #define CDREX_LPDDR3PHY_CLKM_SRC                (0x20700)
  33 #define EXYNOS5_TIMING_SET_SWI                  BIT(28)
  34 #define USE_MX_MSPLL_TIMINGS                    (1)
  35 #define USE_BPLL_TIMINGS                        (0)
  36 #define EXYNOS5_AREF_NORMAL                     (0x2e)
  37
  38 /**
  39  * struct dmc_opp_table - Operating level desciption
  40  *
  41  * Covers frequency and voltage settings of the DMC operating mode.
  42  */
  43 struct dmc_opp_table {
  44         u32 freq_hz;
  45         u32 volt_uv;
  46 };
  47
  48 /**
  49  * struct exynos5_dmc - main structure describing DMC device
  50  *
  51  * The main structure for the Dynamic Memory Controller which covers clocks,
  52  * memory regions, HW information, parameters and current operating mode.
  53  */
  54 struct exynos5_dmc {
  55         struct device *dev;
  56         struct devfreq *df;
  57         struct devfreq_simple_ondemand_data gov_data;
  58         void __iomem *base_drexi0;
  59         void __iomem *base_drexi1;
  60         struct regmap *clk_regmap;
  61         struct mutex lock;
  62         unsigned long curr_rate;
  63         unsigned long curr_volt;
  64         unsigned long bypass_rate;
  65         struct dmc_opp_table *opp;
  66         struct dmc_opp_table opp_bypass;
  67         int opp_count;
  68         u32 timings_arr_size;
  69         u32 *timing_row;
  70         u32 *timing_data;
  71         u32 *timing_power;
  72         const struct lpddr3_timings *timings;
  73         const struct lpddr3_min_tck *min_tck;
  74         u32 bypass_timing_row;
  75         u32 bypass_timing_data;
  76         u32 bypass_timing_power;
  77         struct regulator *vdd_mif;
  78         struct clk *fout_spll;
  79         struct clk *fout_bpll;
  80         struct clk *mout_spll;
  81         struct clk *mout_bpll;
  82         struct clk *mout_mclk_cdrex;
  83         struct clk *mout_mx_mspll_ccore;
  84         struct clk *mx_mspll_ccore_phy;
  85         struct clk *mout_mx_mspll_ccore_phy;
  86         struct devfreq_event_dev **counter;
  87         int num_counters;
  88 };
  89
  90 #define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \
  91         { .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end }
  92
  93 #define TIMING_VAL2REG(timing, t_val)                   \
  94 ({                                                      \
  95                 u32 __val;                              \
  96                 __val = (t_val) << (timing)->bit_beg;   \
  97                 __val;                                  \
  98 })
  99
 100 struct timing_reg {
 101         char *name;
 102         int bit_beg;
 103         int bit_end;
 104         unsigned int val;
 105 };
 106
 107 static const struct timing_reg timing_row[] = {
 108         TIMING_FIELD("tRFC", 24, 31),
 109         TIMING_FIELD("tRRD", 20, 23),
 110         TIMING_FIELD("tRP", 16, 19),
 111         TIMING_FIELD("tRCD", 12, 15),
 112         TIMING_FIELD("tRC", 6, 11),
 113         TIMING_FIELD("tRAS", 0, 5),
 114 };
 115
 116 static const struct timing_reg timing_data[] = {
 117         TIMING_FIELD("tWTR", 28, 31),
 118         TIMING_FIELD("tWR", 24, 27),
 119         TIMING_FIELD("tRTP", 20, 23),
 120         TIMING_FIELD("tW2W-C2C", 14, 14),
 121         TIMING_FIELD("tR2R-C2C", 12, 12),
 122         TIMING_FIELD("WL", 8, 11),
 123         TIMING_FIELD("tDQSCK", 4, 7),
 124         TIMING_FIELD("RL", 0, 3),
 125 };
 126
 127 static const struct timing_reg timing_power[] = {
 128         TIMING_FIELD("tFAW", 26, 31),
 129         TIMING_FIELD("tXSR", 16, 25),
 130         TIMING_FIELD("tXP", 8, 15),
 131         TIMING_FIELD("tCKE", 4, 7),
 132         TIMING_FIELD("tMRD", 0, 3),
 133 };
 134
 135 #define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \
 136                       ARRAY_SIZE(timing_power))
 137
 138 static int exynos5_counters_set_event(struct exynos5_dmc *dmc)
 139 {
 140         int i, ret;
 141
 142         for (i = 0; i < dmc->num_counters; i++) {
 143                 if (!dmc->counter[i])
 144                         continue;
 145                 ret = devfreq_event_set_event(dmc->counter[i]);
 146                 if (ret < 0)
 147                         return ret;
 148         }
 149         return 0;
 150 }
 151
 152 static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc)
 153 {
 154         int i, ret;
 155
 156         for (i = 0; i < dmc->num_counters; i++) {
 157                 if (!dmc->counter[i])
 158                         continue;
 159                 ret = devfreq_event_enable_edev(dmc->counter[i]);
 160                 if (ret < 0)
 161                         return ret;
 162         }
 163         return 0;
 164 }
 165
 166 static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc)
 167 {
 168         int i, ret;
 169
 170         for (i = 0; i < dmc->num_counters; i++) {
 171                 if (!dmc->counter[i])
 172                         continue;
 173                 ret = devfreq_event_disable_edev(dmc->counter[i]);
 174                 if (ret < 0)
 175                         return ret;
 176         }
 177         return 0;
 178 }
 179
 180 /**
 181  * find_target_freq_id() - Finds requested frequency in local DMC configuration
 182  * @dmc:        device for which the information is checked
 183  * @target_rate:        requested frequency in KHz
 184  *
 185  * Seeks in the local DMC driver structure for the requested frequency value
 186  * and returns index or error value.
 187  */
 188 static int find_target_freq_idx(struct exynos5_dmc *dmc,
 189                                 unsigned long target_rate)
 190 {
 191         int i;
 192
 193         for (i = dmc->opp_count - 1; i >= 0; i--)
 194                 if (dmc->opp[i].freq_hz <= target_rate)
 195                         return i;
 196
 197         return -EINVAL;
 198 }
 199
 200 /**
 201  * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
 202  * @dmc:        device for which the new settings is going to be applied
 203  * @set:        boolean variable passing set value
 204  *
 205  * Changes the register set, which holds timing parameters.
 206  * There is two register sets: 0 and 1. The register set 0
 207  * is used in normal operation when the clock is provided from main PLL.
 208  * The bank register set 1 is used when the main PLL frequency is going to be
 209  * changed and the clock is taken from alternative, stable source.
 210  * This function switches between these banks according to the
 211  * currently used clock source.
 212  */
 213 static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
 214 {
 215         unsigned int reg;
 216         int ret;
 217
 218         ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, &reg);
 219
 220         if (set)
 221                 reg |= EXYNOS5_TIMING_SET_SWI;
 222         else
 223                 reg &= ~EXYNOS5_TIMING_SET_SWI;
 224
 225         regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);
 226 }
 227
 228 /**
 229  * exynos5_init_freq_table() - Initialized PM OPP framework
 230  * @dmc:        DMC device for which the frequencies are used for OPP init
 231  * @profile:    devfreq device's profile
 232  *
 233  * Populate the devfreq device's OPP table based on current frequency, voltage.
 234  */
 235 static int exynos5_init_freq_table(struct exynos5_dmc *dmc,
 236                                    struct devfreq_dev_profile *profile)
 237 {
 238         int i, ret;
 239         int idx;
 240         unsigned long freq;
 241
 242         ret = dev_pm_opp_of_add_table(dmc->dev);
 243         if (ret < 0) {
 244                 dev_err(dmc->dev, "Failed to get OPP table\n");
 245                 return ret;
 246         }
 247
 248         dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev);
 249
 250         dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count,
 251                                       sizeof(struct dmc_opp_table), GFP_KERNEL);
 252         if (!dmc->opp)
 253                 goto err_opp;
 254
 255         idx = dmc->opp_count - 1;
 256         for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) {
 257                 struct dev_pm_opp *opp;
 258
 259                 opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq);
 260                 if (IS_ERR(opp))
 261                         goto err_free_tables;
 262
 263                 dmc->opp[idx - i].freq_hz = freq;
 264                 dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp);
 265
 266                 dev_pm_opp_put(opp);
 267         }
 268
 269         return 0;
 270
 271 err_free_tables:
 272         kfree(dmc->opp);
 273 err_opp:
 274         dev_pm_opp_of_remove_table(dmc->dev);
 275
 276         return -EINVAL;
 277 }
 278
 279 /**
 280  * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
 281  * @dmc:        device for which the new settings is going to be applied
 282  * @param:      DRAM parameters which passes timing data
 283  *
 284  * Low-level function for changing timings for DRAM memory clocking from
 285  * 'bypass' clock source (fixed frequency @400MHz).
 286  * It uses timing bank registers set 1.
 287  */
 288 static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc)
 289 {
 290         writel(EXYNOS5_AREF_NORMAL,
 291                dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
 292
 293         writel(dmc->bypass_timing_row,
 294                dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
 295         writel(dmc->bypass_timing_row,
 296                dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
 297         writel(dmc->bypass_timing_data,
 298                dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
 299         writel(dmc->bypass_timing_data,
 300                dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
 301         writel(dmc->bypass_timing_power,
 302                dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
 303         writel(dmc->bypass_timing_power,
 304                dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
 305 }
 306
 307 /**
 308  * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
 309  * @dmc:        device for which the new settings is going to be applied
 310  * @target_rate:        target frequency of the DMC
 311  *
 312  * Low-level function for changing timings for DRAM memory operating from main
 313  * clock source (BPLL), which can have different frequencies. Thus, each
 314  * frequency must have corresponding timings register values in order to keep
 315  * the needed delays.
 316  * It uses timing bank registers set 0.
 317  */
 318 static int exynos5_dram_change_timings(struct exynos5_dmc *dmc,
 319                                        unsigned long target_rate)
 320 {
 321         int idx;
 322
 323         for (idx = dmc->opp_count - 1; idx >= 0; idx--)
 324                 if (dmc->opp[idx].freq_hz <= target_rate)
 325                         break;
 326
 327         if (idx < 0)
 328                 return -EINVAL;
 329
 330         writel(EXYNOS5_AREF_NORMAL,
 331                dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
 332
 333         writel(dmc->timing_row[idx],
 334                dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
 335         writel(dmc->timing_row[idx],
 336                dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
 337         writel(dmc->timing_data[idx],
 338                dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
 339         writel(dmc->timing_data[idx],
 340                dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
 341         writel(dmc->timing_power[idx],
 342                dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
 343         writel(dmc->timing_power[idx],
 344                dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
 345
 346         return 0;
 347 }
 348
 349 /**
 350  * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC
 351  * @dmc:        device for which it is going to be set
 352  * @target_volt:        new voltage which is chosen to be final
 353  *
 354  * Function tries to align voltage to the safe level for 'normal' mode.
 355  * It checks the need of higher voltage and changes the value. The target
 356  * voltage might be lower that currently set and still the system will be
 357  * stable.
 358  */
 359 static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc,
 360                                             unsigned long target_volt)
 361 {
 362         int ret = 0;
 363
 364         if (dmc->curr_volt <= target_volt)
 365                 return 0;
 366
 367         ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
 368                                     target_volt);
 369         if (!ret)
 370                 dmc->curr_volt = target_volt;
 371
 372         return ret;
 373 }
 374
 375 /**
 376  * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC
 377  * @dmc:        device for which it is going to be set
 378  * @target_volt:        new voltage which is chosen to be final
 379  *
 380  * Function tries to align voltage to the safe level for the 'bypass' mode.
 381  * It checks the need of higher voltage and changes the value.
 382  * The target voltage must not be less than currently needed, because
 383  * for current frequency the device might become unstable.
 384  */
 385 static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
 386                                             unsigned long target_volt)
 387 {
 388         int ret = 0;
 389         unsigned long bypass_volt = dmc->opp_bypass.volt_uv;
 390
 391         target_volt = max(bypass_volt, target_volt);
 392
 393         if (dmc->curr_volt >= target_volt)
 394                 return 0;
 395
 396         ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
 397                                     target_volt);
 398         if (!ret)
 399                 dmc->curr_volt = target_volt;
 400
 401         return ret;
 402 }
 403
 404 /**
 405  * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
 406  * @dmc:        device for which it is going to be set
 407  * @target_rate:        new frequency which is chosen to be final
 408  *
 409  * Function changes the DRAM timings for the temporary 'bypass' mode.
 410  */
 411 static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc,
 412                                                  unsigned long target_rate)
 413 {
 414         int idx = find_target_freq_idx(dmc, target_rate);
 415
 416         if (idx < 0)
 417                 return -EINVAL;
 418
 419         exynos5_set_bypass_dram_timings(dmc);
 420
 421         return 0;
 422 }
 423
 424 /**
 425  * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock
 426  * @dmc:        DMC device for which the switching is going to happen
 427  * @target_rate:        new frequency which is going to be set as a final
 428  * @target_volt:        new voltage which is going to be set as a final
 429  *
 430  * Function configures DMC and clocks for operating in temporary 'bypass' mode.
 431  * This mode is used only temporary but if required, changes voltage and timings
 432  * for DRAM chips. It switches the main clock to stable clock source for the
 433  * period of the main PLL reconfiguration.
 434  */
 435 static int
 436 exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc,
 437                                            unsigned long target_rate,
 438                                            unsigned long target_volt)
 439 {
 440         int ret;
 441
 442         /*
 443          * Having higher voltage for a particular frequency does not harm
 444          * the chip. Use it for the temporary frequency change when one
 445          * voltage manipulation might be avoided.
 446          */
 447         ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt);
 448         if (ret)
 449                 return ret;
 450
 451         /*
 452          * Longer delays for DRAM does not cause crash, the opposite does.
 453          */
 454         ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate);
 455         if (ret)
 456                 return ret;
 457
 458         /*
 459          * Delays are long enough, so use them for the new coming clock.
 460          */
 461         exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);
 462
 463         return ret;
 464 }
 465
 466 /**
 467  * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC
 468  * using safe procedure
 469  * @dmc:        device for which the frequency is going to be changed
 470  * @target_rate:        requested new frequency
 471  * @target_volt:        requested voltage which corresponds to the new frequency
 472  *
 473  * The DMC frequency change procedure requires a few steps.
 474  * The main requirement is to change the clock source in the clk mux
 475  * for the time of main clock PLL locking. The assumption is that the
 476  * alternative clock source set as parent is stable.
 477  * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass'
 478  * clock. This requires alignment in DRAM timing parameters for the new
 479  * T-period. There is two bank sets for keeping DRAM
 480  * timings: set 0 and set 1. The set 0 is used when main clock source is
 481  * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between
 482  * the two bank sets is part of the process.
 483  * The voltage must also be aligned to the minimum required level. There is
 484  * this intermediate step with switching to 'bypass' parent clock source.
 485  * if the old voltage is lower, it requires an increase of the voltage level.
 486  * The complexity of the voltage manipulation is hidden in low level function.
 487  * In this function there is last alignment of the voltage level at the end.
 488  */
 489 static int
 490 exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
 491                                  unsigned long target_rate,
 492                                  unsigned long target_volt)
 493 {
 494         int ret;
 495
 496         ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate,
 497                                                          target_volt);
 498         if (ret)
 499                 return ret;
 500
 501         /*
 502          * Voltage is set at least to a level needed for this frequency,
 503          * so switching clock source is safe now.
 504          */
 505         clk_prepare_enable(dmc->fout_spll);
 506         clk_prepare_enable(dmc->mout_spll);
 507         clk_prepare_enable(dmc->mout_mx_mspll_ccore);
 508
 509         ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore);
 510         if (ret)
 511                 goto disable_clocks;
 512
 513         /*
 514          * We are safe to increase the timings for current bypass frequency.
 515          * Thanks to this the settings will be ready for the upcoming clock
 516          * source change.
 517          */
 518         exynos5_dram_change_timings(dmc, target_rate);
 519
 520         clk_set_rate(dmc->fout_bpll, target_rate);
 521
 522         exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);
 523
 524         ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
 525         if (ret)
 526                 goto disable_clocks;
 527
 528         /*
 529          * Make sure if the voltage is not from 'bypass' settings and align to
 530          * the right level for power efficiency.
 531          */
 532         ret = exynos5_dmc_align_target_voltage(dmc, target_volt);
 533
 534 disable_clocks:
 535         clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
 536         clk_disable_unprepare(dmc->mout_spll);
 537         clk_disable_unprepare(dmc->fout_spll);
 538
 539         return ret;
 540 }
 541
 542 /**
 543  * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP
 544  * table.
 545  * @dmc:        device for which the frequency is going to be changed
 546  * @freq:       requested frequency in KHz
 547  * @target_rate:        returned frequency which is the same or lower than
 548  *                      requested
 549  * @target_volt:        returned voltage which corresponds to the returned
 550  *                      frequency
 551  *
 552  * Function gets requested frequency and checks OPP framework for needed
 553  * frequency and voltage. It populates the values 'target_rate' and
 554  * 'target_volt' or returns error value when OPP framework fails.
 555  */
 556 static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc,
 557                                      unsigned long *freq,
 558                                      unsigned long *target_rate,
 559                                      unsigned long *target_volt, u32 flags)
 560 {
 561         struct dev_pm_opp *opp;
 562
 563         opp = devfreq_recommended_opp(dmc->dev, freq, flags);
 564         if (IS_ERR(opp))
 565                 return PTR_ERR(opp);
 566
 567         *target_rate = dev_pm_opp_get_freq(opp);
 568         *target_volt = dev_pm_opp_get_voltage(opp);
 569         dev_pm_opp_put(opp);
 570
 571         return 0;
 572 }
 573
 574 /**
 575  * exynos5_dmc_target() - Function responsible for changing frequency of DMC
 576  * @dev:        device for which the frequency is going to be changed
 577  * @freq:       requested frequency in KHz
 578  * @flags:      flags provided for this frequency change request
 579  *
 580  * An entry function provided to the devfreq framework which provides frequency
 581  * change of the DMC. The function gets the possible rate from OPP table based
 582  * on requested frequency. It calls the next function responsible for the
 583  * frequency and voltage change. In case of failure, does not set 'curr_rate'
 584  * and returns error value to the framework.
 585  */
 586 static int exynos5_dmc_target(struct device *dev, unsigned long *freq,
 587                               u32 flags)
 588 {
 589         struct exynos5_dmc *dmc = dev_get_drvdata(dev);
 590         unsigned long target_rate = 0;
 591         unsigned long target_volt = 0;
 592         int ret;
 593
 594         ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt,
 595                                         flags);
 596
 597         if (ret)
 598                 return ret;
 599
 600         if (target_rate == dmc->curr_rate)
 601                 return 0;
 602
 603         mutex_lock(&dmc->lock);
 604
 605         ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);
 606
 607         if (ret) {
 608                 mutex_unlock(&dmc->lock);
 609                 return ret;
 610         }
 611
 612         dmc->curr_rate = target_rate;
 613
 614         mutex_unlock(&dmc->lock);
 615         return 0;
 616 }
 617
 618 /**
 619  * exynos5_counters_get() - Gets the performance counters values.
 620  * @dmc:        device for which the counters are going to be checked
 621  * @load_count: variable which is populated with counter value
 622  * @total_count:        variable which is used as 'wall clock' reference
 623  *
 624  * Function which provides performance counters values. It sums up counters for
 625  * two DMC channels. The 'total_count' is used as a reference and max value.
 626  * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%].
 627  */
 628 static int exynos5_counters_get(struct exynos5_dmc *dmc,
 629                                 unsigned long *load_count,
 630                                 unsigned long *total_count)
 631 {
 632         unsigned long total = 0;
 633         struct devfreq_event_data event;
 634         int ret, i;
 635
 636         *load_count = 0;
 637
 638         /* Take into account only read+write counters, but stop all */
 639         for (i = 0; i < dmc->num_counters; i++) {
 640                 if (!dmc->counter[i])
 641                         continue;
 642
 643                 ret = devfreq_event_get_event(dmc->counter[i], &event);
 644                 if (ret < 0)
 645                         return ret;
 646
 647                 *load_count += event.load_count;
 648
 649                 if (total < event.total_count)
 650                         total = event.total_count;
 651         }
 652
 653         *total_count = total;
 654
 655         return 0;
 656 }
 657
 658 /**
 659  * exynos5_dmc_get_status() - Read current DMC performance statistics.
 660  * @dev:        device for which the statistics are requested
 661  * @stat:       structure which has statistic fields
 662  *
 663  * Function reads the DMC performance counters and calculates 'busy_time'
 664  * and 'total_time'. To protect from overflow, the values are shifted right
 665  * by 10. After read out the counters are setup to count again.
 666  */
 667 static int exynos5_dmc_get_status(struct device *dev,
 668                                   struct devfreq_dev_status *stat)
 669 {
 670         struct exynos5_dmc *dmc = dev_get_drvdata(dev);
 671         unsigned long load, total;
 672         int ret;
 673
 674         ret = exynos5_counters_get(dmc, &load, &total);
 675         if (ret < 0)
 676                 return -EINVAL;
 677
 678         /* To protect from overflow in calculation ratios, divide by 1024 */
 679         stat->busy_time = load >> 10;
 680         stat->total_time = total >> 10;
 681
 682         ret = exynos5_counters_set_event(dmc);
 683         if (ret < 0) {
 684                 dev_err(dev, "could not set event counter\n");
 685                 return ret;
 686         }
 687
 688         return 0;
 689 }
 690
 691 /**
 692  * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency
 693  * @dev:        device for which the framework checks operating frequency
 694  * @freq:       returned frequency value
 695  *
 696  * It returns the currently used frequency of the DMC. The real operating
 697  * frequency might be lower when the clock source value could not be divided
 698  * to the requested value.
 699  */
 700 static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq)
 701 {
 702         struct exynos5_dmc *dmc = dev_get_drvdata(dev);
 703
 704         mutex_lock(&dmc->lock);
 705         *freq = dmc->curr_rate;
 706         mutex_unlock(&dmc->lock);
 707
 708         return 0;
 709 }
 710
 711 /**
 712  * exynos5_dmc_df_profile - Devfreq governor's profile structure
 713  *
 714  * It provides to the devfreq framework needed functions and polling period.
 715  */
 716 static struct devfreq_dev_profile exynos5_dmc_df_profile = {
 717         .polling_ms = 500,
 718         .target = exynos5_dmc_target,
 719         .get_dev_status = exynos5_dmc_get_status,
 720         .get_cur_freq = exynos5_dmc_get_cur_freq,
 721 };
 722
 723 /**
 724  * exynos5_dmc_align_initial_frequency() - Align initial frequency value
 725  * @dmc:        device for which the frequency is going to be set
 726  * @bootloader_init_freq:       initial frequency set by the bootloader in KHz
 727  *
 728  * The initial bootloader frequency, which is present during boot, might be
 729  * different that supported frequency values in the driver. It is possible
 730  * due to different PLL settings or used PLL as a source.
 731  * This function provides the 'initial_freq' for the devfreq framework
 732  * statistics engine which supports only registered values. Thus, some alignment
 733  * must be made.
 734  */
 735 unsigned long
 736 exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
 737                             unsigned long bootloader_init_freq)
 738 {
 739         unsigned long aligned_freq;
 740         int idx;
 741
 742         idx = find_target_freq_idx(dmc, bootloader_init_freq);
 743         if (idx >= 0)
 744                 aligned_freq = dmc->opp[idx].freq_hz;
 745         else
 746                 aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz;
 747
 748         return aligned_freq;
 749 }
 750
 751 /**
 752  * create_timings_aligned() - Create register values and align with standard
 753  * @dmc:        device for which the frequency is going to be set
 754  * @idx:        speed bin in the OPP table
 755  * @clk_period_ps:      the period of the clock, known as tCK
 756  *
 757  * The function calculates timings and creates a register value ready for
 758  * a frequency transition. The register contains a few timings. They are
 759  * shifted by a known offset. The timing value is calculated based on memory
 760  * specyfication: minimal time required and minimal cycles required.
 761  */
 762 static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
 763                                   u32 *reg_timing_data, u32 *reg_timing_power,
 764                                   u32 clk_period_ps)
 765 {
 766         u32 val;
 767         const struct timing_reg *reg;
 768
 769         if (clk_period_ps == 0)
 770                 return -EINVAL;
 771
 772         *reg_timing_row = 0;
 773         *reg_timing_data = 0;
 774         *reg_timing_power = 0;
 775
 776         val = dmc->timings->tRFC / clk_period_ps;
 777         val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
 778         val = max(val, dmc->min_tck->tRFC);
 779         reg = &timing_row[0];
 780         *reg_timing_row |= TIMING_VAL2REG(reg, val);
 781
 782         val = dmc->timings->tRRD / clk_period_ps;
 783         val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
 784         val = max(val, dmc->min_tck->tRRD);
 785         reg = &timing_row[1];
 786         *reg_timing_row |= TIMING_VAL2REG(reg, val);
 787
 788         val = dmc->timings->tRPab / clk_period_ps;
 789         val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
 790         val = max(val, dmc->min_tck->tRPab);
 791         reg = &timing_row[2];
 792         *reg_timing_row |= TIMING_VAL2REG(reg, val);
 793
 794         val = dmc->timings->tRCD / clk_period_ps;
 795         val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
 796         val = max(val, dmc->min_tck->tRCD);
 797         reg = &timing_row[3];
 798         *reg_timing_row |= TIMING_VAL2REG(reg, val);
 799
 800         val = dmc->timings->tRC / clk_period_ps;
 801         val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
 802         val = max(val, dmc->min_tck->tRC);
 803         reg = &timing_row[4];
 804         *reg_timing_row |= TIMING_VAL2REG(reg, val);
 805
 806         val = dmc->timings->tRAS / clk_period_ps;
 807         val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
 808         val = max(val, dmc->min_tck->tRAS);
 809         reg = &timing_row[5];
 810         *reg_timing_row |= TIMING_VAL2REG(reg, val);
 811
 812         /* data related timings */
 813         val = dmc->timings->tWTR / clk_period_ps;
 814         val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
 815         val = max(val, dmc->min_tck->tWTR);
 816         reg = &timing_data[0];
 817         *reg_timing_data |= TIMING_VAL2REG(reg, val);
 818
 819         val = dmc->timings->tWR / clk_period_ps;
 820         val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
 821         val = max(val, dmc->min_tck->tWR);
 822         reg = &timing_data[1];
 823         *reg_timing_data |= TIMING_VAL2REG(reg, val);
 824
 825         val = dmc->timings->tRTP / clk_period_ps;
 826         val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
 827         val = max(val, dmc->min_tck->tRTP);
 828         reg = &timing_data[2];
 829         *reg_timing_data |= TIMING_VAL2REG(reg, val);
 830
 831         val = dmc->timings->tW2W_C2C / clk_period_ps;
 832         val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
 833         val = max(val, dmc->min_tck->tW2W_C2C);
 834         reg = &timing_data[3];
 835         *reg_timing_data |= TIMING_VAL2REG(reg, val);
 836
 837         val = dmc->timings->tR2R_C2C / clk_period_ps;
 838         val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
 839         val = max(val, dmc->min_tck->tR2R_C2C);
 840         reg = &timing_data[4];
 841         *reg_timing_data |= TIMING_VAL2REG(reg, val);
 842
 843         val = dmc->timings->tWL / clk_period_ps;
 844         val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
 845         val = max(val, dmc->min_tck->tWL);
 846         reg = &timing_data[5];
 847         *reg_timing_data |= TIMING_VAL2REG(reg, val);
 848
 849         val = dmc->timings->tDQSCK / clk_period_ps;
 850         val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
 851         val = max(val, dmc->min_tck->tDQSCK);
 852         reg = &timing_data[6];
 853         *reg_timing_data |= TIMING_VAL2REG(reg, val);
 854
 855         val = dmc->timings->tRL / clk_period_ps;
 856         val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
 857         val = max(val, dmc->min_tck->tRL);
 858         reg = &timing_data[7];
 859         *reg_timing_data |= TIMING_VAL2REG(reg, val);
 860
 861         /* power related timings */
 862         val = dmc->timings->tFAW / clk_period_ps;
 863         val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
 864         val = max(val, dmc->min_tck->tXP);
 865         reg = &timing_power[0];
 866         *reg_timing_power |= TIMING_VAL2REG(reg, val);
 867
 868         val = dmc->timings->tXSR / clk_period_ps;
 869         val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
 870         val = max(val, dmc->min_tck->tXSR);
 871         reg = &timing_power[1];
 872         *reg_timing_power |= TIMING_VAL2REG(reg, val);
 873
 874         val = dmc->timings->tXP / clk_period_ps;
 875         val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
 876         val = max(val, dmc->min_tck->tXP);
 877         reg = &timing_power[2];
 878         *reg_timing_power |= TIMING_VAL2REG(reg, val);
 879
 880         val = dmc->timings->tCKE / clk_period_ps;
 881         val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
 882         val = max(val, dmc->min_tck->tCKE);
 883         reg = &timing_power[3];
 884         *reg_timing_power |= TIMING_VAL2REG(reg, val);
 885
 886         val = dmc->timings->tMRD / clk_period_ps;
 887         val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
 888         val = max(val, dmc->min_tck->tMRD);
 889         reg = &timing_power[4];
 890         *reg_timing_power |= TIMING_VAL2REG(reg, val);
 891
 892         return 0;
 893 }
 894
 895 /**
 896  * of_get_dram_timings() - helper function for parsing DT settings for DRAM
 897  * @dmc:        device for which the frequency is going to be set
 898  *
 899  * The function parses DT entries with DRAM information.
 900  */
 901 static int of_get_dram_timings(struct exynos5_dmc *dmc)
 902 {
 903         int ret = 0;
 904         int idx;
 905         struct device_node *np_ddr;
 906         u32 freq_mhz, clk_period_ps;
 907
 908         np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0);
 909         if (!np_ddr) {
 910                 dev_warn(dmc->dev, "could not find 'device-handle' in DT\n");
 911                 return -EINVAL;
 912         }
 913
 914         dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
 915                                              sizeof(u32), GFP_KERNEL);
 916         if (!dmc->timing_row)
 917                 return -ENOMEM;
 918
 919         dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
 920                                               sizeof(u32), GFP_KERNEL);
 921         if (!dmc->timing_data)
 922                 return -ENOMEM;
 923
 924         dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
 925                                                sizeof(u32), GFP_KERNEL);
 926         if (!dmc->timing_power)
 927                 return -ENOMEM;
 928
 929         dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev,
 930                                                  DDR_TYPE_LPDDR3,
 931                                                  &dmc->timings_arr_size);
 932         if (!dmc->timings) {
 933                 of_node_put(np_ddr);
 934                 dev_warn(dmc->dev, "could not get timings from DT\n");
 935                 return -EINVAL;
 936         }
 937
 938         dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev);
 939         if (!dmc->min_tck) {
 940                 of_node_put(np_ddr);
 941                 dev_warn(dmc->dev, "could not get tck from DT\n");
 942                 return -EINVAL;
 943         }
 944
 945         /* Sorted array of OPPs with frequency ascending */
 946         for (idx = 0; idx < dmc->opp_count; idx++) {
 947                 freq_mhz = dmc->opp[idx].freq_hz / 1000000;
 948                 clk_period_ps = 1000000 / freq_mhz;
 949
 950                 ret = create_timings_aligned(dmc, &dmc->timing_row[idx],
 951                                              &dmc->timing_data[idx],
 952                                              &dmc->timing_power[idx],
 953                                              clk_period_ps);
 954         }
 955
 956         of_node_put(np_ddr);
 957
 958         /* Take the highest frequency's timings as 'bypass' */
 959         dmc->bypass_timing_row = dmc->timing_row[idx - 1];
 960         dmc->bypass_timing_data = dmc->timing_data[idx - 1];
 961         dmc->bypass_timing_power = dmc->timing_power[idx - 1];
 962
 963         return ret;
 964 }
 965
 966 /**
 967  * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
 968  * @dmc:        DMC structure containing needed fields
 969  *
 970  * Get the needed clocks defined in DT device, enable and set the right parents.
 971  * Read current frequency and initialize the initial rate for governor.
 972  */
 973 static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
 974 {
 975         int ret;
 976         unsigned long target_volt = 0;
 977         unsigned long target_rate = 0;
 978         unsigned int tmp;
 979
 980         dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll");
 981         if (IS_ERR(dmc->fout_spll))
 982                 return PTR_ERR(dmc->fout_spll);
 983
 984         dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll");
 985         if (IS_ERR(dmc->fout_bpll))
 986                 return PTR_ERR(dmc->fout_bpll);
 987
 988         dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex");
 989         if (IS_ERR(dmc->mout_mclk_cdrex))
 990                 return PTR_ERR(dmc->mout_mclk_cdrex);
 991
 992         dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll");
 993         if (IS_ERR(dmc->mout_bpll))
 994                 return PTR_ERR(dmc->mout_bpll);
 995
 996         dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev,
 997                                                 "mout_mx_mspll_ccore");
 998         if (IS_ERR(dmc->mout_mx_mspll_ccore))
 999                 return PTR_ERR(dmc->mout_mx_mspll_ccore);
1000
1001         dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2");
1002         if (IS_ERR(dmc->mout_spll)) {
1003                 dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll");
1004                 if (IS_ERR(dmc->mout_spll))
1005                         return PTR_ERR(dmc->mout_spll);
1006         }
1007
1008         /*
1009          * Convert frequency to KHz values and set it for the governor.
1010          */
1011         dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex);
1012         dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate);
1013         exynos5_dmc_df_profile.initial_freq = dmc->curr_rate;
1014
1015         ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate,
1016                                         &target_volt, 0);
1017         if (ret)
1018                 return ret;
1019
1020         dmc->curr_volt = target_volt;
1021
1022         clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
1023
1024         dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore);
1025
1026         clk_prepare_enable(dmc->fout_bpll);
1027         clk_prepare_enable(dmc->mout_bpll);
1028
1029         /*
1030          * Some bootloaders do not set clock routes correctly.
1031          * Stop one path in clocks to PHY.
1032          */
1033         regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, &tmp);
1034         tmp &= ~(BIT(1) | BIT(0));
1035         regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, tmp);
1036
1037         return 0;
1038 }
1039
1040 /**
1041  * exynos5_performance_counters_init() - Initializes performance DMC's counters
1042  * @dmc:        DMC for which it does the setup
1043  *
1044  * Initialization of performance counters in DMC for estimating usage.
1045  * The counter's values are used for calculation of a memory bandwidth and based
1046  * on that the governor changes the frequency.
1047  * The counters are not used when the governor is GOVERNOR_USERSPACE.
1048  */
1049 static int exynos5_performance_counters_init(struct exynos5_dmc *dmc)
1050 {
1051         int counters_size;
1052         int ret, i;
1053
1054         dmc->num_counters = devfreq_event_get_edev_count(dmc->dev);
1055         if (dmc->num_counters < 0) {
1056                 dev_err(dmc->dev, "could not get devfreq-event counters\n");
1057                 return dmc->num_counters;
1058         }
1059
1060         counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters;
1061         dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL);
1062         if (!dmc->counter)
1063                 return -ENOMEM;
1064
1065         for (i = 0; i < dmc->num_counters; i++) {
1066                 dmc->counter[i] =
1067                         devfreq_event_get_edev_by_phandle(dmc->dev, i);
1068                 if (IS_ERR_OR_NULL(dmc->counter[i]))
1069                         return -EPROBE_DEFER;
1070         }
1071
1072         ret = exynos5_counters_enable_edev(dmc);
1073         if (ret < 0) {
1074                 dev_err(dmc->dev, "could not enable event counter\n");
1075                 return ret;
1076         }
1077
1078         ret = exynos5_counters_set_event(dmc);
1079         if (ret < 0) {
1080                 exynos5_counters_disable_edev(dmc);
1081                 dev_err(dmc->dev, "counld not set event counter\n");
1082                 return ret;
1083         }
1084
1085         return 0;
1086 }
1087
1088 /**
1089  * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC
1090  * @dmc:        device which is used for changing this feature
1091  * @set:        a boolean state passing enable/disable request
1092  *
1093  * There is a need of pausing DREX DMC when divider or MUX in clock tree
1094  * changes its configuration. In such situation access to the memory is blocked
1095  * in DMC automatically. This feature is used when clock frequency change
1096  * request appears and touches clock tree.
1097  */
1098 static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc)
1099 {
1100         unsigned int val;
1101         int ret;
1102
1103         ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val);
1104         if (ret)
1105                 return ret;
1106
1107         val |= 1UL;
1108         regmap_write(dmc->clk_regmap, CDREX_PAUSE, val);
1109
1110         return 0;
1111 }
1112
1113 /**
1114  * exynos5_dmc_probe() - Probe function for the DMC driver
1115  * @pdev:       platform device for which the driver is going to be initialized
1116  *
1117  * Initialize basic components: clocks, regulators, performance counters, etc.
1118  * Read out product version and based on the information setup
1119  * internal structures for the controller (frequency and voltage) and for DRAM
1120  * memory parameters: timings for each operating frequency.
1121  * Register new devfreq device for controlling DVFS of the DMC.
1122  */
1123 static int exynos5_dmc_probe(struct platform_device *pdev)
1124 {
1125         int ret = 0;
1126         struct device *dev = &pdev->dev;
1127         struct device_node *np = dev->of_node;
1128         struct exynos5_dmc *dmc;
1129         struct resource *res;
1130
1131         dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL);
1132         if (!dmc)
1133                 return -ENOMEM;
1134
1135         mutex_init(&dmc->lock);
1136
1137         dmc->dev = dev;
1138         platform_set_drvdata(pdev, dmc);
1139
1140         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1141         dmc->base_drexi0 = devm_ioremap_resource(dev, res);
1142         if (IS_ERR(dmc->base_drexi0))
1143                 return PTR_ERR(dmc->base_drexi0);
1144
1145         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1146         dmc->base_drexi1 = devm_ioremap_resource(dev, res);
1147         if (IS_ERR(dmc->base_drexi1))
1148                 return PTR_ERR(dmc->base_drexi1);
1149
1150         dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np,
1151                                 "samsung,syscon-clk");
1152         if (IS_ERR(dmc->clk_regmap))
1153                 return PTR_ERR(dmc->clk_regmap);
1154
1155         ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile);
1156         if (ret) {
1157                 dev_warn(dev, "couldn't initialize frequency settings\n");
1158                 return ret;
1159         }
1160
1161         dmc->vdd_mif = devm_regulator_get(dev, "vdd");
1162         if (IS_ERR(dmc->vdd_mif)) {
1163                 ret = PTR_ERR(dmc->vdd_mif);
1164                 return ret;
1165         }
1166
1167         ret = exynos5_dmc_init_clks(dmc);
1168         if (ret)
1169                 return ret;
1170
1171         ret = of_get_dram_timings(dmc);
1172         if (ret) {
1173                 dev_warn(dev, "couldn't initialize timings settings\n");
1174                 goto remove_clocks;
1175         }
1176
1177         ret = exynos5_performance_counters_init(dmc);
1178         if (ret) {
1179                 dev_warn(dev, "couldn't probe performance counters\n");
1180                 goto remove_clocks;
1181         }
1182
1183         ret = exynos5_dmc_set_pause_on_switching(dmc);
1184         if (ret) {
1185                 dev_warn(dev, "couldn't get access to PAUSE register\n");
1186                 goto err_devfreq_add;
1187         }
1188
1189         /*
1190          * Setup default thresholds for the devfreq governor.
1191          * The values are chosen based on experiments.
1192          */
1193         dmc->gov_data.upthreshold = 30;
1194         dmc->gov_data.downdifferential = 5;
1195
1196         dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
1197                                           DEVFREQ_GOV_SIMPLE_ONDEMAND,
1198                                           &dmc->gov_data);
1199
1200         if (IS_ERR(dmc->df)) {
1201                 ret = PTR_ERR(dmc->df);
1202                 goto err_devfreq_add;
1203         }
1204
1205         dev_info(dev, "DMC initialized\n");
1206
1207         return 0;
1208
1209 err_devfreq_add:
1210         exynos5_counters_disable_edev(dmc);
1211 remove_clocks:
1212         clk_disable_unprepare(dmc->mout_bpll);
1213         clk_disable_unprepare(dmc->fout_bpll);
1214
1215         return ret;
1216 }
1217
1218 /**
1219  * exynos5_dmc_remove() - Remove function for the platform device
1220  * @pdev:       platform device which is going to be removed
1221  *
1222  * The function relies on 'devm' framework function which automatically
1223  * clean the device's resources. It just calls explicitly disable function for
1224  * the performance counters.
1225  */
1226 static int exynos5_dmc_remove(struct platform_device *pdev)
1227 {
1228         struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev);
1229
1230         exynos5_counters_disable_edev(dmc);
1231
1232         clk_disable_unprepare(dmc->mout_bpll);
1233         clk_disable_unprepare(dmc->fout_bpll);
1234
1235         dev_pm_opp_remove_table(dmc->dev);
1236
1237         return 0;
1238 }
1239
1240 static const struct of_device_id exynos5_dmc_of_match[] = {
1241         { .compatible = "samsung,exynos5422-dmc", },
1242         { },
1243 };
1244 MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match);
1245
1246 static struct platform_driver exynos5_dmc_platdrv = {
1247         .probe  = exynos5_dmc_probe,
1248         .remove = exynos5_dmc_remove,
1249         .driver = {
1250                 .name   = "exynos5-dmc",
1251                 .of_match_table = exynos5_dmc_of_match,
1252         },
1253 };
1254 module_platform_driver(exynos5_dmc_platdrv);
1255 MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change");
1256 MODULE_LICENSE("GPL v2");
1257 MODULE_AUTHOR("Lukasz Luba");