1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RPC-IF core driver
5 * Copyright (C) 2018-2019 Renesas Solutions Corp.
6 * Copyright (C) 2019 Macronix International Co., Ltd.
7 * Copyright (C) 2019-2020 Cogent Embedded, Inc.
10 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
15 #include <linux/of_device.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
19 #include <memory/renesas-rpc-if.h>
21 #define RPCIF_CMNCR 0x0000 /* R/W */
22 #define RPCIF_CMNCR_MD BIT(31)
23 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
24 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
25 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
26 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
27 #define RPCIF_CMNCR_MOIIO(val) (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \
28 RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val))
29 #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* documented for RZ/G2L */
30 #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* documented for RZ/G2L */
31 #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
32 #define RPCIF_CMNCR_IOFV(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
33 RPCIF_CMNCR_IO3FV(val))
34 #define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
36 #define RPCIF_SSLDR 0x0004 /* R/W */
37 #define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
38 #define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
39 #define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
41 #define RPCIF_DRCR 0x000C /* R/W */
42 #define RPCIF_DRCR_SSLN BIT(24)
43 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
44 #define RPCIF_DRCR_RCF BIT(9)
45 #define RPCIF_DRCR_RBE BIT(8)
46 #define RPCIF_DRCR_SSLE BIT(0)
48 #define RPCIF_DRCMR 0x0010 /* R/W */
49 #define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
50 #define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
52 #define RPCIF_DREAR 0x0014 /* R/W */
53 #define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
54 #define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
56 #define RPCIF_DROPR 0x0018 /* R/W */
58 #define RPCIF_DRENR 0x001C /* R/W */
59 #define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
60 #define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
61 #define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
62 #define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
63 #define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
64 #define RPCIF_DRENR_DME BIT(15)
65 #define RPCIF_DRENR_CDE BIT(14)
66 #define RPCIF_DRENR_OCDE BIT(12)
67 #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
68 #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
70 #define RPCIF_SMCR 0x0020 /* R/W */
71 #define RPCIF_SMCR_SSLKP BIT(8)
72 #define RPCIF_SMCR_SPIRE BIT(2)
73 #define RPCIF_SMCR_SPIWE BIT(1)
74 #define RPCIF_SMCR_SPIE BIT(0)
76 #define RPCIF_SMCMR 0x0024 /* R/W */
77 #define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
78 #define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
80 #define RPCIF_SMADR 0x0028 /* R/W */
82 #define RPCIF_SMOPR 0x002C /* R/W */
83 #define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
84 #define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
85 #define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
86 #define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
88 #define RPCIF_SMENR 0x0030 /* R/W */
89 #define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
90 #define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
91 #define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
92 #define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
93 #define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
94 #define RPCIF_SMENR_DME BIT(15)
95 #define RPCIF_SMENR_CDE BIT(14)
96 #define RPCIF_SMENR_OCDE BIT(12)
97 #define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
98 #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
99 #define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
101 #define RPCIF_SMRDR0 0x0038 /* R */
102 #define RPCIF_SMRDR1 0x003C /* R */
103 #define RPCIF_SMWDR0 0x0040 /* W */
104 #define RPCIF_SMWDR1 0x0044 /* W */
106 #define RPCIF_CMNSR 0x0048 /* R */
107 #define RPCIF_CMNSR_SSLF BIT(1)
108 #define RPCIF_CMNSR_TEND BIT(0)
110 #define RPCIF_DRDMCR 0x0058 /* R/W */
111 #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
113 #define RPCIF_DRDRENR 0x005C /* R/W */
114 #define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
115 #define RPCIF_DRDRENR_ADDRE BIT(8)
116 #define RPCIF_DRDRENR_OPDRE BIT(4)
117 #define RPCIF_DRDRENR_DRDRE BIT(0)
119 #define RPCIF_SMDMCR 0x0060 /* R/W */
120 #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
122 #define RPCIF_SMDRENR 0x0064 /* R/W */
123 #define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
124 #define RPCIF_SMDRENR_ADDRE BIT(8)
125 #define RPCIF_SMDRENR_OPDRE BIT(4)
126 #define RPCIF_SMDRENR_SPIDRE BIT(0)
128 #define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
129 #define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
131 #define RPCIF_PHYCNT 0x007C /* R/W */
132 #define RPCIF_PHYCNT_CAL BIT(31)
133 #define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
134 #define RPCIF_PHYCNT_EXDS BIT(21)
135 #define RPCIF_PHYCNT_OCT BIT(20)
136 #define RPCIF_PHYCNT_DDRCAL BIT(19)
137 #define RPCIF_PHYCNT_HS BIT(18)
138 #define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */
139 #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) /* valid for R-Car and RZ/G2{E,H,M,N} */
140 #define RPCIF_PHYCNT_WBUF2 BIT(4)
141 #define RPCIF_PHYCNT_WBUF BIT(2)
142 #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
143 #define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)
145 #define RPCIF_PHYOFFSET1 0x0080 /* R/W */
146 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
148 #define RPCIF_PHYOFFSET2 0x0084 /* R/W */
149 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
151 #define RPCIF_PHYINT 0x0088 /* R/W */
152 #define RPCIF_PHYINT_WPVAL BIT(1)
154 static const struct regmap_range rpcif_volatile_ranges[] = {
155 regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
156 regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
157 regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
160 static const struct regmap_access_table rpcif_volatile_table = {
161 .yes_ranges = rpcif_volatile_ranges,
162 .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges),
167 * Custom accessor functions to ensure SMRDR0 and SMWDR0 are always accessed
168 * with proper width. Requires SMENR_SPIDE to be correctly set before!
170 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
172 struct rpcif *rpc = context;
174 if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
175 u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
178 *val = readb(rpc->base + reg);
180 } else if (spide == 0xC) {
181 *val = readw(rpc->base + reg);
183 } else if (spide != 0xF) {
188 *val = readl(rpc->base + reg);
192 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
194 struct rpcif *rpc = context;
196 if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
197 u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
200 writeb(val, rpc->base + reg);
202 } else if (spide == 0xC) {
203 writew(val, rpc->base + reg);
205 } else if (spide != 0xF) {
210 writel(val, rpc->base + reg);
214 static const struct regmap_config rpcif_regmap_config = {
218 .reg_read = rpcif_reg_read,
219 .reg_write = rpcif_reg_write,
221 .max_register = RPCIF_PHYINT,
222 .volatile_table = &rpcif_volatile_table,
225 int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
227 struct platform_device *pdev = to_platform_device(dev);
228 struct resource *res;
232 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
233 rpc->base = devm_ioremap_resource(&pdev->dev, res);
234 if (IS_ERR(rpc->base))
235 return PTR_ERR(rpc->base);
237 rpc->regmap = devm_regmap_init(&pdev->dev, NULL, rpc, &rpcif_regmap_config);
238 if (IS_ERR(rpc->regmap)) {
240 "failed to init regmap for rpcif, error %ld\n",
241 PTR_ERR(rpc->regmap));
242 return PTR_ERR(rpc->regmap);
245 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
246 rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
247 if (IS_ERR(rpc->dirmap))
248 return PTR_ERR(rpc->dirmap);
249 rpc->size = resource_size(res);
251 rpc->type = (uintptr_t)of_device_get_match_data(dev);
252 rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
254 return PTR_ERR_OR_ZERO(rpc->rstc);
256 EXPORT_SYMBOL(rpcif_sw_init);
258 static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif *rpc)
260 regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000);
261 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000);
262 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
263 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022);
264 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
265 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024);
266 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_CKSEL(3),
267 RPCIF_PHYCNT_CKSEL(3));
268 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
269 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
272 int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
276 pm_runtime_get_sync(rpc->dev);
278 if (rpc->type == RPCIF_RZ_G2L) {
281 ret = reset_control_reset(rpc->rstc);
284 usleep_range(200, 300);
285 rpcif_rzg2l_timing_adjust_sdr(rpc);
288 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK,
289 RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0));
291 if (rpc->type == RPCIF_RCAR_GEN3)
292 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
293 RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7));
295 regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3),
296 RPCIF_PHYOFFSET1_DDRTMG(3));
297 regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET2, RPCIF_PHYOFFSET2_OCTTMG(7),
298 RPCIF_PHYOFFSET2_OCTTMG(4));
301 regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
302 RPCIF_PHYINT_WPVAL, 0);
304 if (rpc->type == RPCIF_RCAR_GEN3)
305 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
306 RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3),
307 RPCIF_CMNCR_MOIIO(3) |
308 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
310 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
311 RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
313 RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
314 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
316 /* Set RCF after BSZ update */
317 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
318 /* Dummy read according to spec */
319 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
320 regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
321 RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
323 pm_runtime_put(rpc->dev);
325 rpc->bus_size = hyperflash ? 2 : 1;
329 EXPORT_SYMBOL(rpcif_hw_init);
331 static int wait_msg_xfer_end(struct rpcif *rpc)
335 return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
336 sts & RPCIF_CMNSR_TEND, 0,
340 static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes)
342 if (rpc->bus_size == 2)
344 nbytes = clamp(nbytes, 1U, 4U);
345 return GENMASK(3, 4 - nbytes);
348 static u8 rpcif_bit_size(u8 buswidth)
350 return buswidth > 4 ? 2 : ilog2(buswidth);
353 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
365 if (op->cmd.buswidth) {
366 rpc->enable = RPCIF_SMENR_CDE |
367 RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
368 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
370 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
372 if (op->ocmd.buswidth) {
373 rpc->enable |= RPCIF_SMENR_OCDE |
374 RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
375 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
378 if (op->addr.buswidth) {
380 RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
381 if (op->addr.nbytes == 4)
382 rpc->enable |= RPCIF_SMENR_ADE(0xF);
384 rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
385 2, 3 - op->addr.nbytes));
387 rpc->ddr |= RPCIF_SMDRENR_ADDRE;
392 rpc->smadr = op->addr.val;
395 if (op->dummy.buswidth) {
396 rpc->enable |= RPCIF_SMENR_DME;
397 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
401 if (op->option.buswidth) {
402 rpc->enable |= RPCIF_SMENR_OPDE(
403 rpcif_bits_set(rpc, op->option.nbytes)) |
404 RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
406 rpc->ddr |= RPCIF_SMDRENR_OPDRE;
407 rpc->option = op->option.val;
410 rpc->dir = op->data.dir;
411 if (op->data.buswidth) {
414 rpc->buffer = op->data.buf.in;
415 switch (op->data.dir) {
417 rpc->smcr = RPCIF_SMCR_SPIRE;
420 rpc->smcr = RPCIF_SMCR_SPIWE;
426 rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
431 nbytes = op->data.nbytes;
432 rpc->xferlen = nbytes;
434 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
437 EXPORT_SYMBOL(rpcif_prepare);
439 int rpcif_manual_xfer(struct rpcif *rpc)
441 u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
444 pm_runtime_get_sync(rpc->dev);
446 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
447 RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
448 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
449 RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
450 regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
451 regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
452 regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
453 regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
454 regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
459 while (pos < rpc->xferlen) {
460 u32 bytes_left = rpc->xferlen - pos;
463 smcr = rpc->smcr | RPCIF_SMCR_SPIE;
465 /* nbytes may only be 1, 2, 4, or 8 */
466 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
467 if (bytes_left > nbytes)
468 smcr |= RPCIF_SMCR_SSLKP;
470 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
471 regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
473 memcpy(data, rpc->buffer + pos, nbytes);
475 regmap_write(rpc->regmap, RPCIF_SMWDR1,
477 regmap_write(rpc->regmap, RPCIF_SMWDR0,
480 regmap_write(rpc->regmap, RPCIF_SMWDR0,
484 regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
485 ret = wait_msg_xfer_end(rpc);
490 smenr = rpc->enable &
491 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
496 * RPC-IF spoils the data for the commands without an address
497 * phase (like RDID) in the manual mode, so we'll have to work
498 * around this issue by using the external address space read
501 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
504 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
506 regmap_write(rpc->regmap, RPCIF_DRCR,
507 RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
508 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
509 regmap_write(rpc->regmap, RPCIF_DREAR,
511 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
512 regmap_write(rpc->regmap, RPCIF_DRENR,
513 smenr & ~RPCIF_SMENR_SPIDE(0xF));
514 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
515 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
516 memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
517 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
518 /* Dummy read according to spec */
519 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
522 while (pos < rpc->xferlen) {
523 u32 bytes_left = rpc->xferlen - pos;
526 /* nbytes may only be 1, 2, 4, or 8 */
527 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
529 regmap_write(rpc->regmap, RPCIF_SMADR,
531 smenr &= ~RPCIF_SMENR_SPIDE(0xF);
532 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
533 regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
534 regmap_write(rpc->regmap, RPCIF_SMCR,
535 rpc->smcr | RPCIF_SMCR_SPIE);
536 ret = wait_msg_xfer_end(rpc);
541 regmap_read(rpc->regmap, RPCIF_SMRDR1,
543 regmap_read(rpc->regmap, RPCIF_SMRDR0,
546 regmap_read(rpc->regmap, RPCIF_SMRDR0,
549 memcpy(rpc->buffer + pos, data, nbytes);
555 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
556 regmap_write(rpc->regmap, RPCIF_SMCR,
557 rpc->smcr | RPCIF_SMCR_SPIE);
558 ret = wait_msg_xfer_end(rpc);
564 pm_runtime_put(rpc->dev);
568 if (reset_control_reset(rpc->rstc))
569 dev_err(rpc->dev, "Failed to reset HW\n");
570 rpcif_hw_init(rpc, rpc->bus_size == 2);
573 EXPORT_SYMBOL(rpcif_manual_xfer);
575 static void memcpy_fromio_readw(void *to,
576 const void __iomem *from,
579 const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4;
582 if (count && ((unsigned long)from & 1)) {
583 *(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1));
589 while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) {
590 *(u16 *)to = __raw_readw(from);
595 while (count >= maxw) {
597 *(u64 *)to = __raw_readq(from);
599 *(u32 *)to = __raw_readl(from);
606 *(u16 *)to = __raw_readw(from);
612 *(u16 *)buf = __raw_readw(from);
617 ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
619 loff_t from = offs & (rpc->size - 1);
620 size_t size = rpc->size - from;
625 pm_runtime_get_sync(rpc->dev);
627 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
628 regmap_write(rpc->regmap, RPCIF_DRCR, 0);
629 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
630 regmap_write(rpc->regmap, RPCIF_DREAR,
631 RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
632 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
633 regmap_write(rpc->regmap, RPCIF_DRENR,
634 rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
635 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
636 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
638 if (rpc->bus_size == 2)
639 memcpy_fromio_readw(buf, rpc->dirmap + from, len);
641 memcpy_fromio(buf, rpc->dirmap + from, len);
643 pm_runtime_put(rpc->dev);
647 EXPORT_SYMBOL(rpcif_dirmap_read);
649 static int rpcif_probe(struct platform_device *pdev)
651 struct platform_device *vdev;
652 struct device_node *flash;
656 flash = of_get_next_child(pdev->dev.of_node, NULL);
658 dev_warn(&pdev->dev, "no flash node found\n");
662 if (of_device_is_compatible(flash, "jedec,spi-nor")) {
664 } else if (of_device_is_compatible(flash, "cfi-flash")) {
665 name = "rpc-if-hyperflash";
668 dev_warn(&pdev->dev, "unknown flash type\n");
673 vdev = platform_device_alloc(name, pdev->id);
676 vdev->dev.parent = &pdev->dev;
677 platform_set_drvdata(pdev, vdev);
679 ret = platform_device_add(vdev);
681 platform_device_put(vdev);
688 static int rpcif_remove(struct platform_device *pdev)
690 struct platform_device *vdev = platform_get_drvdata(pdev);
692 platform_device_unregister(vdev);
697 static const struct of_device_id rpcif_of_match[] = {
698 { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 },
699 { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L },
702 MODULE_DEVICE_TABLE(of, rpcif_of_match);
704 static struct platform_driver rpcif_driver = {
705 .probe = rpcif_probe,
706 .remove = rpcif_remove,
709 .of_match_table = rpcif_of_match,
712 module_platform_driver(rpcif_driver);
714 MODULE_DESCRIPTION("Renesas RPC-IF core driver");
715 MODULE_LICENSE("GPL v2");