drivers/memory/renesas-rpc-if.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas RPC-IF core driver
   4  *
   5  * Copyright (C) 2018-2019 Renesas Solutions Corp.
   6  * Copyright (C) 2019 Macronix International Co., Ltd.
   7  * Copyright (C) 2019-2020 Cogent Embedded, Inc.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/of.h>
  15 #include <linux/regmap.h>
  16 #include <linux/reset.h>
  17
  18 #include <memory/renesas-rpc-if.h>
  19
  20 #define RPCIF_CMNCR             0x0000  /* R/W */
  21 #define RPCIF_CMNCR_MD          BIT(31)
  22 #define RPCIF_CMNCR_SFDE        BIT(24) /* undocumented but must be set */
  23 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
  24 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
  25 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
  26 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
  27 #define RPCIF_CMNCR_MOIIO_HIZ   (RPCIF_CMNCR_MOIIO0(3) | \
  28                                  RPCIF_CMNCR_MOIIO1(3) | \
  29                                  RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3))
  30 #define RPCIF_CMNCR_IO3FV(val)  (((val) & 0x3) << 14) /* undocumented */
  31 #define RPCIF_CMNCR_IO2FV(val)  (((val) & 0x3) << 12) /* undocumented */
  32 #define RPCIF_CMNCR_IO0FV(val)  (((val) & 0x3) << 8)
  33 #define RPCIF_CMNCR_IOFV_HIZ    (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
  34                                  RPCIF_CMNCR_IO3FV(3))
  35 #define RPCIF_CMNCR_BSZ(val)    (((val) & 0x3) << 0)
  36
  37 #define RPCIF_SSLDR             0x0004  /* R/W */
  38 #define RPCIF_SSLDR_SPNDL(d)    (((d) & 0x7) << 16)
  39 #define RPCIF_SSLDR_SLNDL(d)    (((d) & 0x7) << 8)
  40 #define RPCIF_SSLDR_SCKDL(d)    (((d) & 0x7) << 0)
  41
  42 #define RPCIF_DRCR              0x000C  /* R/W */
  43 #define RPCIF_DRCR_SSLN         BIT(24)
  44 #define RPCIF_DRCR_RBURST(v)    ((((v) - 1) & 0x1F) << 16)
  45 #define RPCIF_DRCR_RCF          BIT(9)
  46 #define RPCIF_DRCR_RBE          BIT(8)
  47 #define RPCIF_DRCR_SSLE         BIT(0)
  48
  49 #define RPCIF_DRCMR             0x0010  /* R/W */
  50 #define RPCIF_DRCMR_CMD(c)      (((c) & 0xFF) << 16)
  51 #define RPCIF_DRCMR_OCMD(c)     (((c) & 0xFF) << 0)
  52
  53 #define RPCIF_DREAR             0x0014  /* R/W */
  54 #define RPCIF_DREAR_EAV(c)      (((c) & 0xF) << 16)
  55 #define RPCIF_DREAR_EAC(c)      (((c) & 0x7) << 0)
  56
  57 #define RPCIF_DROPR             0x0018  /* R/W */
  58
  59 #define RPCIF_DRENR             0x001C  /* R/W */
  60 #define RPCIF_DRENR_CDB(o)      (u32)((((o) & 0x3) << 30))
  61 #define RPCIF_DRENR_OCDB(o)     (((o) & 0x3) << 28)
  62 #define RPCIF_DRENR_ADB(o)      (((o) & 0x3) << 24)
  63 #define RPCIF_DRENR_OPDB(o)     (((o) & 0x3) << 20)
  64 #define RPCIF_DRENR_DRDB(o)     (((o) & 0x3) << 16)
  65 #define RPCIF_DRENR_DME         BIT(15)
  66 #define RPCIF_DRENR_CDE         BIT(14)
  67 #define RPCIF_DRENR_OCDE        BIT(12)
  68 #define RPCIF_DRENR_ADE(v)      (((v) & 0xF) << 8)
  69 #define RPCIF_DRENR_OPDE(v)     (((v) & 0xF) << 4)
  70
  71 #define RPCIF_SMCR              0x0020  /* R/W */
  72 #define RPCIF_SMCR_SSLKP        BIT(8)
  73 #define RPCIF_SMCR_SPIRE        BIT(2)
  74 #define RPCIF_SMCR_SPIWE        BIT(1)
  75 #define RPCIF_SMCR_SPIE         BIT(0)
  76
  77 #define RPCIF_SMCMR             0x0024  /* R/W */
  78 #define RPCIF_SMCMR_CMD(c)      (((c) & 0xFF) << 16)
  79 #define RPCIF_SMCMR_OCMD(c)     (((c) & 0xFF) << 0)
  80
  81 #define RPCIF_SMADR             0x0028  /* R/W */
  82
  83 #define RPCIF_SMOPR             0x002C  /* R/W */
  84 #define RPCIF_SMOPR_OPD3(o)     (((o) & 0xFF) << 24)
  85 #define RPCIF_SMOPR_OPD2(o)     (((o) & 0xFF) << 16)
  86 #define RPCIF_SMOPR_OPD1(o)     (((o) & 0xFF) << 8)
  87 #define RPCIF_SMOPR_OPD0(o)     (((o) & 0xFF) << 0)
  88
  89 #define RPCIF_SMENR             0x0030  /* R/W */
  90 #define RPCIF_SMENR_CDB(o)      (((o) & 0x3) << 30)
  91 #define RPCIF_SMENR_OCDB(o)     (((o) & 0x3) << 28)
  92 #define RPCIF_SMENR_ADB(o)      (((o) & 0x3) << 24)
  93 #define RPCIF_SMENR_OPDB(o)     (((o) & 0x3) << 20)
  94 #define RPCIF_SMENR_SPIDB(o)    (((o) & 0x3) << 16)
  95 #define RPCIF_SMENR_DME         BIT(15)
  96 #define RPCIF_SMENR_CDE         BIT(14)
  97 #define RPCIF_SMENR_OCDE        BIT(12)
  98 #define RPCIF_SMENR_ADE(v)      (((v) & 0xF) << 8)
  99 #define RPCIF_SMENR_OPDE(v)     (((v) & 0xF) << 4)
 100 #define RPCIF_SMENR_SPIDE(v)    (((v) & 0xF) << 0)
 101
 102 #define RPCIF_SMRDR0            0x0038  /* R */
 103 #define RPCIF_SMRDR1            0x003C  /* R */
 104 #define RPCIF_SMWDR0            0x0040  /* W */
 105 #define RPCIF_SMWDR1            0x0044  /* W */
 106
 107 #define RPCIF_CMNSR             0x0048  /* R */
 108 #define RPCIF_CMNSR_SSLF        BIT(1)
 109 #define RPCIF_CMNSR_TEND        BIT(0)
 110
 111 #define RPCIF_DRDMCR            0x0058  /* R/W */
 112 #define RPCIF_DMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
 113
 114 #define RPCIF_DRDRENR           0x005C  /* R/W */
 115 #define RPCIF_DRDRENR_HYPE(v)   (((v) & 0x7) << 12)
 116 #define RPCIF_DRDRENR_ADDRE     BIT(8)
 117 #define RPCIF_DRDRENR_OPDRE     BIT(4)
 118 #define RPCIF_DRDRENR_DRDRE     BIT(0)
 119
 120 #define RPCIF_SMDMCR            0x0060  /* R/W */
 121 #define RPCIF_SMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
 122
 123 #define RPCIF_SMDRENR           0x0064  /* R/W */
 124 #define RPCIF_SMDRENR_HYPE(v)   (((v) & 0x7) << 12)
 125 #define RPCIF_SMDRENR_ADDRE     BIT(8)
 126 #define RPCIF_SMDRENR_OPDRE     BIT(4)
 127 #define RPCIF_SMDRENR_SPIDRE    BIT(0)
 128
 129 #define RPCIF_PHYCNT            0x007C  /* R/W */
 130 #define RPCIF_PHYCNT_CAL        BIT(31)
 131 #define RPCIF_PHYCNT_OCTA(v)    (((v) & 0x3) << 22)
 132 #define RPCIF_PHYCNT_EXDS       BIT(21)
 133 #define RPCIF_PHYCNT_OCT        BIT(20)
 134 #define RPCIF_PHYCNT_DDRCAL     BIT(19)
 135 #define RPCIF_PHYCNT_HS         BIT(18)
 136 #define RPCIF_PHYCNT_STRTIM(v)  (((v) & 0x7) << 15)
 137 #define RPCIF_PHYCNT_WBUF2      BIT(4)
 138 #define RPCIF_PHYCNT_WBUF       BIT(2)
 139 #define RPCIF_PHYCNT_PHYMEM(v)  (((v) & 0x3) << 0)
 140
 141 #define RPCIF_PHYOFFSET1        0x0080  /* R/W */
 142 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
 143
 144 #define RPCIF_PHYOFFSET2        0x0084  /* R/W */
 145 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
 146
 147 #define RPCIF_PHYINT            0x0088  /* R/W */
 148 #define RPCIF_PHYINT_WPVAL      BIT(1)
 149
 150 static const struct regmap_range rpcif_volatile_ranges[] = {
 151         regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
 152         regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
 153         regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
 154 };
 155
 156 static const struct regmap_access_table rpcif_volatile_table = {
 157         .yes_ranges     = rpcif_volatile_ranges,
 158         .n_yes_ranges   = ARRAY_SIZE(rpcif_volatile_ranges),
 159 };
 160
 161
 162 /*
 163  * Custom accessor functions to ensure SMRDR0 and SMWDR0 are always accessed
 164  * with proper width. Requires SMENR_SPIDE to be correctly set before!
 165  */
 166 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
 167 {
 168         struct rpcif *rpc = context;
 169
 170         if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
 171                 u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
 172
 173                 if (spide == 0x8) {
 174                         *val = readb(rpc->base + reg);
 175                         return 0;
 176                 } else if (spide == 0xC) {
 177                         *val = readw(rpc->base + reg);
 178                         return 0;
 179                 } else if (spide != 0xF) {
 180                         return -EILSEQ;
 181                 }
 182         }
 183
 184         *val = readl(rpc->base + reg);
 185         return 0;
 186 }
 187
 188 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
 189 {
 190         struct rpcif *rpc = context;
 191
 192         if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
 193                 u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
 194
 195                 if (spide == 0x8) {
 196                         writeb(val, rpc->base + reg);
 197                         return 0;
 198                 } else if (spide == 0xC) {
 199                         writew(val, rpc->base + reg);
 200                         return 0;
 201                 } else if (spide != 0xF) {
 202                         return -EILSEQ;
 203                 }
 204         }
 205
 206         writel(val, rpc->base + reg);
 207         return 0;
 208 }
 209
 210 static const struct regmap_config rpcif_regmap_config = {
 211         .reg_bits       = 32,
 212         .val_bits       = 32,
 213         .reg_stride     = 4,
 214         .reg_read       = rpcif_reg_read,
 215         .reg_write      = rpcif_reg_write,
 216         .fast_io        = true,
 217         .max_register   = RPCIF_PHYINT,
 218         .volatile_table = &rpcif_volatile_table,
 219 };
 220
 221 int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
 222 {
 223         struct platform_device *pdev = to_platform_device(dev);
 224         struct resource *res;
 225
 226         rpc->dev = dev;
 227
 228         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 229         rpc->base = devm_ioremap_resource(&pdev->dev, res);
 230         if (IS_ERR(rpc->base))
 231                 return PTR_ERR(rpc->base);
 232
 233         rpc->regmap = devm_regmap_init(&pdev->dev, NULL, rpc, &rpcif_regmap_config);
 234         if (IS_ERR(rpc->regmap)) {
 235                 dev_err(&pdev->dev,
 236                         "failed to init regmap for rpcif, error %ld\n",
 237                         PTR_ERR(rpc->regmap));
 238                 return  PTR_ERR(rpc->regmap);
 239         }
 240
 241         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
 242         rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
 243         if (IS_ERR(rpc->dirmap))
 244                 return PTR_ERR(rpc->dirmap);
 245         rpc->size = resource_size(res);
 246
 247         rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 248
 249         return PTR_ERR_OR_ZERO(rpc->rstc);
 250 }
 251 EXPORT_SYMBOL(rpcif_sw_init);
 252
 253 void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
 254 {
 255         u32 dummy;
 256
 257         pm_runtime_get_sync(rpc->dev);
 258
 259         /*
 260          * NOTE: The 0x260 are undocumented bits, but they must be set.
 261          *       RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits,
 262          *       0x0 : the delay is biggest,
 263          *       0x1 : the delay is 2nd biggest,
 264          *       On H3 ES1.x, the value should be 0, while on others,
 265          *       the value should be 7.
 266          */
 267         regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
 268                      RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
 269
 270         /*
 271          * NOTE: The 0x1511144 are undocumented bits, but they must be set
 272          *       for RPCIF_PHYOFFSET1.
 273          *       The 0x31 are undocumented bits, but they must be set
 274          *       for RPCIF_PHYOFFSET2.
 275          */
 276         regmap_write(rpc->regmap, RPCIF_PHYOFFSET1, 0x1511144 |
 277                      RPCIF_PHYOFFSET1_DDRTMG(3));
 278         regmap_write(rpc->regmap, RPCIF_PHYOFFSET2, 0x31 |
 279                      RPCIF_PHYOFFSET2_OCTTMG(4));
 280
 281         if (hyperflash)
 282                 regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
 283                                    RPCIF_PHYINT_WPVAL, 0);
 284
 285         regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
 286                      RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ |
 287                      RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
 288         /* Set RCF after BSZ update */
 289         regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
 290         /* Dummy read according to spec */
 291         regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
 292         regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
 293                      RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
 294
 295         pm_runtime_put(rpc->dev);
 296
 297         rpc->bus_size = hyperflash ? 2 : 1;
 298 }
 299 EXPORT_SYMBOL(rpcif_hw_init);
 300
 301 static int wait_msg_xfer_end(struct rpcif *rpc)
 302 {
 303         u32 sts;
 304
 305         return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
 306                                         sts & RPCIF_CMNSR_TEND, 0,
 307                                         USEC_PER_SEC);
 308 }
 309
 310 static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes)
 311 {
 312         if (rpc->bus_size == 2)
 313                 nbytes /= 2;
 314         nbytes = clamp(nbytes, 1U, 4U);
 315         return GENMASK(3, 4 - nbytes);
 316 }
 317
 318 static u8 rpcif_bit_size(u8 buswidth)
 319 {
 320         return buswidth > 4 ? 2 : ilog2(buswidth);
 321 }
 322
 323 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
 324                    size_t *len)
 325 {
 326         rpc->smcr = 0;
 327         rpc->smadr = 0;
 328         rpc->enable = 0;
 329         rpc->command = 0;
 330         rpc->option = 0;
 331         rpc->dummy = 0;
 332         rpc->ddr = 0;
 333         rpc->xferlen = 0;
 334
 335         if (op->cmd.buswidth) {
 336                 rpc->enable  = RPCIF_SMENR_CDE |
 337                         RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
 338                 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
 339                 if (op->cmd.ddr)
 340                         rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
 341         }
 342         if (op->ocmd.buswidth) {
 343                 rpc->enable  |= RPCIF_SMENR_OCDE |
 344                         RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
 345                 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
 346         }
 347
 348         if (op->addr.buswidth) {
 349                 rpc->enable |=
 350                         RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
 351                 if (op->addr.nbytes == 4)
 352                         rpc->enable |= RPCIF_SMENR_ADE(0xF);
 353                 else
 354                         rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
 355                                                 2, 3 - op->addr.nbytes));
 356                 if (op->addr.ddr)
 357                         rpc->ddr |= RPCIF_SMDRENR_ADDRE;
 358
 359                 if (offs && len)
 360                         rpc->smadr = *offs;
 361                 else
 362                         rpc->smadr = op->addr.val;
 363         }
 364
 365         if (op->dummy.buswidth) {
 366                 rpc->enable |= RPCIF_SMENR_DME;
 367                 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
 368                                                 op->dummy.buswidth);
 369         }
 370
 371         if (op->option.buswidth) {
 372                 rpc->enable |= RPCIF_SMENR_OPDE(
 373                         rpcif_bits_set(rpc, op->option.nbytes)) |
 374                         RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
 375                 if (op->option.ddr)
 376                         rpc->ddr |= RPCIF_SMDRENR_OPDRE;
 377                 rpc->option = op->option.val;
 378         }
 379
 380         rpc->dir = op->data.dir;
 381         if (op->data.buswidth) {
 382                 u32 nbytes;
 383
 384                 rpc->buffer = op->data.buf.in;
 385                 switch (op->data.dir) {
 386                 case RPCIF_DATA_IN:
 387                         rpc->smcr = RPCIF_SMCR_SPIRE;
 388                         break;
 389                 case RPCIF_DATA_OUT:
 390                         rpc->smcr = RPCIF_SMCR_SPIWE;
 391                         break;
 392                 default:
 393                         break;
 394                 }
 395                 if (op->data.ddr)
 396                         rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
 397
 398                 if (offs && len)
 399                         nbytes = *len;
 400                 else
 401                         nbytes = op->data.nbytes;
 402                 rpc->xferlen = nbytes;
 403
 404                 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
 405         }
 406 }
 407 EXPORT_SYMBOL(rpcif_prepare);
 408
 409 int rpcif_manual_xfer(struct rpcif *rpc)
 410 {
 411         u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
 412         int ret = 0;
 413
 414         pm_runtime_get_sync(rpc->dev);
 415
 416         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
 417                            RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
 418         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 419                            RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
 420         regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
 421         regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
 422         regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
 423         regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
 424         regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
 425         smenr = rpc->enable;
 426
 427         switch (rpc->dir) {
 428         case RPCIF_DATA_OUT:
 429                 while (pos < rpc->xferlen) {
 430                         u32 bytes_left = rpc->xferlen - pos;
 431                         u32 nbytes, data[2];
 432
 433                         smcr = rpc->smcr | RPCIF_SMCR_SPIE;
 434
 435                         /* nbytes may only be 1, 2, 4, or 8 */
 436                         nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
 437                         if (bytes_left > nbytes)
 438                                 smcr |= RPCIF_SMCR_SSLKP;
 439
 440                         smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
 441                         regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
 442
 443                         memcpy(data, rpc->buffer + pos, nbytes);
 444                         if (nbytes == 8) {
 445                                 regmap_write(rpc->regmap, RPCIF_SMWDR1,
 446                                              data[0]);
 447                                 regmap_write(rpc->regmap, RPCIF_SMWDR0,
 448                                              data[1]);
 449                         } else {
 450                                 regmap_write(rpc->regmap, RPCIF_SMWDR0,
 451                                              data[0]);
 452                         }
 453
 454                         regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
 455                         ret = wait_msg_xfer_end(rpc);
 456                         if (ret)
 457                                 goto err_out;
 458
 459                         pos += nbytes;
 460                         smenr = rpc->enable &
 461                                 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
 462                 }
 463                 break;
 464         case RPCIF_DATA_IN:
 465                 /*
 466                  * RPC-IF spoils the data for the commands without an address
 467                  * phase (like RDID) in the manual mode, so we'll have to work
 468                  * around this issue by using the external address space read
 469                  * mode instead.
 470                  */
 471                 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
 472                         u32 dummy;
 473
 474                         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 475                                            RPCIF_CMNCR_MD, 0);
 476                         regmap_write(rpc->regmap, RPCIF_DRCR,
 477                                      RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
 478                         regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
 479                         regmap_write(rpc->regmap, RPCIF_DREAR,
 480                                      RPCIF_DREAR_EAC(1));
 481                         regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
 482                         regmap_write(rpc->regmap, RPCIF_DRENR,
 483                                      smenr & ~RPCIF_SMENR_SPIDE(0xF));
 484                         regmap_write(rpc->regmap, RPCIF_DRDMCR,  rpc->dummy);
 485                         regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
 486                         memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
 487                         regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
 488                         /* Dummy read according to spec */
 489                         regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
 490                         break;
 491                 }
 492                 while (pos < rpc->xferlen) {
 493                         u32 bytes_left = rpc->xferlen - pos;
 494                         u32 nbytes, data[2];
 495
 496                         /* nbytes may only be 1, 2, 4, or 8 */
 497                         nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
 498
 499                         regmap_write(rpc->regmap, RPCIF_SMADR,
 500                                      rpc->smadr + pos);
 501                         smenr &= ~RPCIF_SMENR_SPIDE(0xF);
 502                         smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
 503                         regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
 504                         regmap_write(rpc->regmap, RPCIF_SMCR,
 505                                      rpc->smcr | RPCIF_SMCR_SPIE);
 506                         ret = wait_msg_xfer_end(rpc);
 507                         if (ret)
 508                                 goto err_out;
 509
 510                         if (nbytes == 8) {
 511                                 regmap_read(rpc->regmap, RPCIF_SMRDR1,
 512                                             &data[0]);
 513                                 regmap_read(rpc->regmap, RPCIF_SMRDR0,
 514                                             &data[1]);
 515                         } else {
 516                                 regmap_read(rpc->regmap, RPCIF_SMRDR0,
 517                                             &data[0]);
 518                         }
 519                         memcpy(rpc->buffer + pos, data, nbytes);
 520
 521                         pos += nbytes;
 522                 }
 523                 break;
 524         default:
 525                 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
 526                 regmap_write(rpc->regmap, RPCIF_SMCR,
 527                              rpc->smcr | RPCIF_SMCR_SPIE);
 528                 ret = wait_msg_xfer_end(rpc);
 529                 if (ret)
 530                         goto err_out;
 531         }
 532
 533 exit:
 534         pm_runtime_put(rpc->dev);
 535         return ret;
 536
 537 err_out:
 538         if (reset_control_reset(rpc->rstc))
 539                 dev_err(rpc->dev, "Failed to reset HW\n");
 540         rpcif_hw_init(rpc, rpc->bus_size == 2);
 541         goto exit;
 542 }
 543 EXPORT_SYMBOL(rpcif_manual_xfer);
 544
 545 static void memcpy_fromio_readw(void *to,
 546                                 const void __iomem *from,
 547                                 size_t count)
 548 {
 549         const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4;
 550         u8 buf[2];
 551
 552         if (count && ((unsigned long)from & 1)) {
 553                 *(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1));
 554                 *(u8 *)to = buf[1];
 555                 from++;
 556                 to++;
 557                 count--;
 558         }
 559         while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) {
 560                 *(u16 *)to = __raw_readw(from);
 561                 from += 2;
 562                 to += 2;
 563                 count -= 2;
 564         }
 565         while (count >= maxw) {
 566 #ifdef CONFIG_64BIT
 567                 *(u64 *)to = __raw_readq(from);
 568 #else
 569                 *(u32 *)to = __raw_readl(from);
 570 #endif
 571                 from += maxw;
 572                 to += maxw;
 573                 count -= maxw;
 574         }
 575         while (count >= 2) {
 576                 *(u16 *)to = __raw_readw(from);
 577                 from += 2;
 578                 to += 2;
 579                 count -= 2;
 580         }
 581         if (count) {
 582                 *(u16 *)buf = __raw_readw(from);
 583                 *(u8 *)to = buf[0];
 584         }
 585 }
 586
 587 ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
 588 {
 589         loff_t from = offs & (rpc->size - 1);
 590         size_t size = rpc->size - from;
 591
 592         if (len > size)
 593                 len = size;
 594
 595         pm_runtime_get_sync(rpc->dev);
 596
 597         regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
 598         regmap_write(rpc->regmap, RPCIF_DRCR, 0);
 599         regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
 600         regmap_write(rpc->regmap, RPCIF_DREAR,
 601                      RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
 602         regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
 603         regmap_write(rpc->regmap, RPCIF_DRENR,
 604                      rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
 605         regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
 606         regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
 607
 608         if (rpc->bus_size == 2)
 609                 memcpy_fromio_readw(buf, rpc->dirmap + from, len);
 610         else
 611                 memcpy_fromio(buf, rpc->dirmap + from, len);
 612
 613         pm_runtime_put(rpc->dev);
 614
 615         return len;
 616 }
 617 EXPORT_SYMBOL(rpcif_dirmap_read);
 618
 619 static int rpcif_probe(struct platform_device *pdev)
 620 {
 621         struct platform_device *vdev;
 622         struct device_node *flash;
 623         const char *name;
 624
 625         flash = of_get_next_child(pdev->dev.of_node, NULL);
 626         if (!flash) {
 627                 dev_warn(&pdev->dev, "no flash node found\n");
 628                 return -ENODEV;
 629         }
 630
 631         if (of_device_is_compatible(flash, "jedec,spi-nor")) {
 632                 name = "rpc-if-spi";
 633         } else if (of_device_is_compatible(flash, "cfi-flash")) {
 634                 name = "rpc-if-hyperflash";
 635         } else  {
 636                 of_node_put(flash);
 637                 dev_warn(&pdev->dev, "unknown flash type\n");
 638                 return -ENODEV;
 639         }
 640         of_node_put(flash);
 641
 642         vdev = platform_device_alloc(name, pdev->id);
 643         if (!vdev)
 644                 return -ENOMEM;
 645         vdev->dev.parent = &pdev->dev;
 646         platform_set_drvdata(pdev, vdev);
 647         return platform_device_add(vdev);
 648 }
 649
 650 static int rpcif_remove(struct platform_device *pdev)
 651 {
 652         struct platform_device *vdev = platform_get_drvdata(pdev);
 653
 654         platform_device_unregister(vdev);
 655
 656         return 0;
 657 }
 658
 659 static const struct of_device_id rpcif_of_match[] = {
 660         { .compatible = "renesas,rcar-gen3-rpc-if", },
 661         {},
 662 };
 663 MODULE_DEVICE_TABLE(of, rpcif_of_match);
 664
 665 static struct platform_driver rpcif_driver = {
 666         .probe  = rpcif_probe,
 667         .remove = rpcif_remove,
 668         .driver = {
 669                 .name = "rpc-if",
 670                 .of_match_table = rpcif_of_match,
 671         },
 672 };
 673 module_platform_driver(rpcif_driver);
 674
 675 MODULE_DESCRIPTION("Renesas RPC-IF core driver");
 676 MODULE_LICENSE("GPL v2");