drivers/memory/omap-gpmc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * GPMC support functions
   4  *
   5  * Copyright (C) 2005-2006 Nokia Corporation
   6  *
   7  * Author: Juha Yrjola
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  */
  12 #include <linux/cpu_pm.h>
  13 #include <linux/irq.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/ioport.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/io.h>
  22 #include <linux/gpio/driver.h>
  23 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
  24 #include <linux/gpio/machine.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/irqdomain.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_device.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/omap-gpmc.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/sizes.h>
  35
  36 #include <linux/platform_data/mtd-nand-omap2.h>
  37
  38 #define DEVICE_NAME             "omap-gpmc"
  39
  40 /* GPMC register offsets */
  41 #define GPMC_REVISION           0x00
  42 #define GPMC_SYSCONFIG          0x10
  43 #define GPMC_SYSSTATUS          0x14
  44 #define GPMC_IRQSTATUS          0x18
  45 #define GPMC_IRQENABLE          0x1c
  46 #define GPMC_TIMEOUT_CONTROL    0x40
  47 #define GPMC_ERR_ADDRESS        0x44
  48 #define GPMC_ERR_TYPE           0x48
  49 #define GPMC_CONFIG             0x50
  50 #define GPMC_STATUS             0x54
  51 #define GPMC_PREFETCH_CONFIG1   0x1e0
  52 #define GPMC_PREFETCH_CONFIG2   0x1e4
  53 #define GPMC_PREFETCH_CONTROL   0x1ec
  54 #define GPMC_PREFETCH_STATUS    0x1f0
  55 #define GPMC_ECC_CONFIG         0x1f4
  56 #define GPMC_ECC_CONTROL        0x1f8
  57 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  58 #define GPMC_ECC1_RESULT        0x200
  59 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  60 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  61 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  66
  67 /* GPMC ECC control settings */
  68 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  69 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  70 #define GPMC_ECC_CTRL_ECCREG1           0x001
  71 #define GPMC_ECC_CTRL_ECCREG2           0x002
  72 #define GPMC_ECC_CTRL_ECCREG3           0x003
  73 #define GPMC_ECC_CTRL_ECCREG4           0x004
  74 #define GPMC_ECC_CTRL_ECCREG5           0x005
  75 #define GPMC_ECC_CTRL_ECCREG6           0x006
  76 #define GPMC_ECC_CTRL_ECCREG7           0x007
  77 #define GPMC_ECC_CTRL_ECCREG8           0x008
  78 #define GPMC_ECC_CTRL_ECCREG9           0x009
  79
  80 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  81
  82 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS      BIT(0)
  83
  84 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  85 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  86 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  87 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  90
  91 #define GPMC_CS0_OFFSET         0x60
  92 #define GPMC_CS_SIZE            0x30
  93 #define GPMC_BCH_SIZE           0x10
  94
  95 /*
  96  * The first 1MB of GPMC address space is typically mapped to
  97  * the internal ROM. Never allocate the first page, to
  98  * facilitate bug detection; even if we didn't boot from ROM.
  99  * As GPMC minimum partition size is 16MB we can only start from
 100  * there.
 101  */
 102 #define GPMC_MEM_START          0x1000000
 103 #define GPMC_MEM_END            0x3FFFFFFF
 104
 105 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 106 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 107
 108 #define CS_NUM_SHIFT            24
 109 #define ENABLE_PREFETCH         (0x1 << 7)
 110 #define DMA_MPU_MODE            2
 111
 112 #define GPMC_REVISION_MAJOR(l)          (((l) >> 4) & 0xf)
 113 #define GPMC_REVISION_MINOR(l)          ((l) & 0xf)
 114
 115 #define GPMC_HAS_WR_ACCESS              0x1
 116 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 117 #define GPMC_HAS_MUX_AAD                0x4
 118
 119 #define GPMC_NR_WAITPINS                4
 120
 121 #define GPMC_CS_CONFIG1         0x00
 122 #define GPMC_CS_CONFIG2         0x04
 123 #define GPMC_CS_CONFIG3         0x08
 124 #define GPMC_CS_CONFIG4         0x0c
 125 #define GPMC_CS_CONFIG5         0x10
 126 #define GPMC_CS_CONFIG6         0x14
 127 #define GPMC_CS_CONFIG7         0x18
 128 #define GPMC_CS_NAND_COMMAND    0x1c
 129 #define GPMC_CS_NAND_ADDRESS    0x20
 130 #define GPMC_CS_NAND_DATA       0x24
 131
 132 /* Control Commands */
 133 #define GPMC_CONFIG_RDY_BSY     0x00000001
 134 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 135 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 136
 137 #define GPMC_CONFIG_WAITPINPOLARITY(pin)        (BIT(pin) << 8)
 138 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 139 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 140 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 141 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 142 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 143 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 144 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 145 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
 146 /** CLKACTIVATIONTIME Max Ticks */
 147 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 148 #define GPMC_CONFIG1_PAGE_LEN(val)      (((val) & 3) << 23)
 149 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 150 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 151 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 152 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 153 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
 154 /** WAITMONITORINGTIME Max Ticks */
 155 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 156 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  (((val) & 3) << 16)
 157 #define GPMC_CONFIG1_DEVICESIZE(val)    (((val) & 3) << 12)
 158 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 159 /** DEVICESIZE Max Value */
 160 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 161 #define GPMC_CONFIG1_DEVICETYPE(val)    (((val) & 3) << 10)
 162 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 163 #define GPMC_CONFIG1_MUXTYPE(val)       (((val) & 3) << 8)
 164 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 165 #define GPMC_CONFIG1_FCLK_DIV(val)      ((val) & 3)
 166 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 167 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 168 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 169 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 170
 171 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 172 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 173 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 174 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 175 /* All CONFIG7 bits except reserved bits */
 176 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 177                                          GPMC_CONFIG7_CSVALID_MASK |     \
 178                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 179
 180 #define GPMC_DEVICETYPE_NOR             0
 181 #define GPMC_DEVICETYPE_NAND            2
 182 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 183 #define WR_RD_PIN_MONITORING            0x00600000
 184
 185 /* ECC commands */
 186 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 187 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 188 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 189
 190 #define GPMC_NR_NAND_IRQS       2 /* number of NAND specific IRQs */
 191
 192 enum gpmc_clk_domain {
 193         GPMC_CD_FCLK,
 194         GPMC_CD_CLK
 195 };
 196
 197 struct gpmc_cs_data {
 198         const char *name;
 199
 200 #define GPMC_CS_RESERVED        (1 << 0)
 201         u32 flags;
 202
 203         struct resource mem;
 204 };
 205
 206 /* Structure to save gpmc cs context */
 207 struct gpmc_cs_config {
 208         u32 config1;
 209         u32 config2;
 210         u32 config3;
 211         u32 config4;
 212         u32 config5;
 213         u32 config6;
 214         u32 config7;
 215         int is_valid;
 216 };
 217
 218 /*
 219  * Structure to save/restore gpmc context
 220  * to support core off on OMAP3
 221  */
 222 struct omap3_gpmc_regs {
 223         u32 sysconfig;
 224         u32 irqenable;
 225         u32 timeout_ctrl;
 226         u32 config;
 227         u32 prefetch_config1;
 228         u32 prefetch_config2;
 229         u32 prefetch_control;
 230         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 231 };
 232
 233 struct gpmc_waitpin {
 234         u32 pin;
 235         u32 polarity;
 236         struct gpio_desc *desc;
 237 };
 238
 239 struct gpmc_device {
 240         struct device *dev;
 241         int irq;
 242         struct irq_chip irq_chip;
 243         struct gpio_chip gpio_chip;
 244         struct notifier_block nb;
 245         struct omap3_gpmc_regs context;
 246         struct gpmc_waitpin *waitpins;
 247         int nirqs;
 248         unsigned int is_suspended:1;
 249         struct resource *data;
 250 };
 251
 252 static struct irq_domain *gpmc_irq_domain;
 253
 254 static struct resource  gpmc_mem_root;
 255 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 256 static DEFINE_SPINLOCK(gpmc_mem_lock);
 257 /* Define chip-selects as reserved by default until probe completes */
 258 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 259 static unsigned int gpmc_nr_waitpins;
 260 static unsigned int gpmc_capability;
 261 static void __iomem *gpmc_base;
 262
 263 static struct clk *gpmc_l3_clk;
 264
 265 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 266
 267 static void gpmc_write_reg(int idx, u32 val)
 268 {
 269         writel_relaxed(val, gpmc_base + idx);
 270 }
 271
 272 static u32 gpmc_read_reg(int idx)
 273 {
 274         return readl_relaxed(gpmc_base + idx);
 275 }
 276
 277 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 278 {
 279         void __iomem *reg_addr;
 280
 281         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 282         writel_relaxed(val, reg_addr);
 283 }
 284
 285 static u32 gpmc_cs_read_reg(int cs, int idx)
 286 {
 287         void __iomem *reg_addr;
 288
 289         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 290         return readl_relaxed(reg_addr);
 291 }
 292
 293 /* TODO: Add support for gpmc_fck to clock framework and use it */
 294 static unsigned long gpmc_get_fclk_period(void)
 295 {
 296         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 297
 298         rate /= 1000;
 299         rate = 1000000000 / rate;       /* In picoseconds */
 300
 301         return rate;
 302 }
 303
 304 /**
 305  * gpmc_get_clk_period - get period of selected clock domain in ps
 306  * @cs: Chip Select Region.
 307  * @cd: Clock Domain.
 308  *
 309  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 310  * prior to calling this function with GPMC_CD_CLK.
 311  */
 312 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 313 {
 314         unsigned long tick_ps = gpmc_get_fclk_period();
 315         u32 l;
 316         int div;
 317
 318         switch (cd) {
 319         case GPMC_CD_CLK:
 320                 /* get current clk divider */
 321                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 322                 div = (l & 0x03) + 1;
 323                 /* get GPMC_CLK period */
 324                 tick_ps *= div;
 325                 break;
 326         case GPMC_CD_FCLK:
 327         default:
 328                 break;
 329         }
 330
 331         return tick_ps;
 332 }
 333
 334 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 335                                          enum gpmc_clk_domain cd)
 336 {
 337         unsigned long tick_ps;
 338
 339         /* Calculate in picosecs to yield more exact results */
 340         tick_ps = gpmc_get_clk_period(cs, cd);
 341
 342         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 343 }
 344
 345 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 346 {
 347         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 348 }
 349
 350 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 351 {
 352         unsigned long tick_ps;
 353
 354         /* Calculate in picosecs to yield more exact results */
 355         tick_ps = gpmc_get_fclk_period();
 356
 357         return (time_ps + tick_ps - 1) / tick_ps;
 358 }
 359
 360 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
 361                                          enum gpmc_clk_domain cd)
 362 {
 363         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 364 }
 365
 366 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 367 {
 368         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 369 }
 370
 371 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 372 {
 373         return ticks * gpmc_get_fclk_period();
 374 }
 375
 376 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 377 {
 378         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 379
 380         return ticks * gpmc_get_fclk_period();
 381 }
 382
 383 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 384 {
 385         u32 l;
 386
 387         l = gpmc_cs_read_reg(cs, reg);
 388         if (value)
 389                 l |= mask;
 390         else
 391                 l &= ~mask;
 392         gpmc_cs_write_reg(cs, reg, l);
 393 }
 394
 395 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 396 {
 397         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 398                            GPMC_CONFIG1_TIME_PARA_GRAN,
 399                            p->time_para_granularity);
 400         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 401                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 402         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 403                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 404         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 405                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 406         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 407                            GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
 408         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 409                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 410                            p->cycle2cyclesamecsen);
 411         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 412                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 413                            p->cycle2cyclediffcsen);
 414 }
 415
 416 #ifdef CONFIG_OMAP_GPMC_DEBUG
 417 /**
 418  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 419  * @cs:      Chip Select Region
 420  * @reg:     GPMC_CS_CONFIGn register offset.
 421  * @st_bit:  Start Bit
 422  * @end_bit: End Bit. Must be >= @st_bit.
 423  * @max:     Maximum parameter value (before optional @shift).
 424  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 425  * @name:    DTS node name, w/o "gpmc,"
 426  * @cd:      Clock Domain of timing parameter.
 427  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 428  * @raw:     Raw Format Option.
 429  *           raw format:  gpmc,name = <value>
 430  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 431  *           Where x ns -- y ns result in the same tick value.
 432  *           When @max is exceeded, "invalid" is printed inside comment.
 433  * @noval:   Parameter values equal to 0 are not printed.
 434  * @return:  Specified timing parameter (after optional @shift).
 435  *
 436  */
 437 static int get_gpmc_timing_reg(
 438         /* timing specifiers */
 439         int cs, int reg, int st_bit, int end_bit, int max,
 440         const char *name, const enum gpmc_clk_domain cd,
 441         /* value transform */
 442         int shift,
 443         /* format specifiers */
 444         bool raw, bool noval)
 445 {
 446         u32 l;
 447         int nr_bits;
 448         int mask;
 449         bool invalid;
 450
 451         l = gpmc_cs_read_reg(cs, reg);
 452         nr_bits = end_bit - st_bit + 1;
 453         mask = (1 << nr_bits) - 1;
 454         l = (l >> st_bit) & mask;
 455         if (!max)
 456                 max = mask;
 457         invalid = l > max;
 458         if (shift)
 459                 l = (shift << l);
 460         if (noval && (l == 0))
 461                 return 0;
 462         if (!raw) {
 463                 /* DTS tick format for timings in ns */
 464                 unsigned int time_ns;
 465                 unsigned int time_ns_min = 0;
 466
 467                 if (l)
 468                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 469                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 470                 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
 471                         name, time_ns, time_ns_min, time_ns, l,
 472                         invalid ? "; invalid " : " ");
 473         } else {
 474                 /* raw format */
 475                 pr_info("gpmc,%s = <%u>;%s\n", name, l,
 476                         invalid ? " /* invalid */" : "");
 477         }
 478
 479         return l;
 480 }
 481
 482 #define GPMC_PRINT_CONFIG(cs, config) \
 483         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 484                 gpmc_cs_read_reg(cs, config))
 485 #define GPMC_GET_RAW(reg, st, end, field) \
 486         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 487 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 488         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 489 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 490         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 491 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 492         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 493 #define GPMC_GET_TICKS(reg, st, end, field) \
 494         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 495 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 496         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 497 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 498         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 499
 500 static void gpmc_show_regs(int cs, const char *desc)
 501 {
 502         pr_info("gpmc cs%i %s:\n", cs, desc);
 503         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 504         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 505         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 506         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 507         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 508         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 509 }
 510
 511 /*
 512  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 513  * see commit c9fb809.
 514  */
 515 static void gpmc_cs_show_timings(int cs, const char *desc)
 516 {
 517         gpmc_show_regs(cs, desc);
 518
 519         pr_info("gpmc cs%i access configuration:\n", cs);
 520         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 521         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 522         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
 523                                GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 524         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 525         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 527         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 528                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 529                                "burst-length");
 530         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 531         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 532         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 533         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 534         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 535
 536         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 537
 538         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 539
 540         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 541         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 542
 543         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 544         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 545
 546         pr_info("gpmc cs%i timings configuration:\n", cs);
 547         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 548         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 549         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 550
 551         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 552         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 553         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 554         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 555                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 556                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 557                                 "adv-aad-mux-rd-off-ns");
 558                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 559                                 "adv-aad-mux-wr-off-ns");
 560         }
 561
 562         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 563         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 564         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 565                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 566                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 567         }
 568         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 569         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 570
 571         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 572         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 573         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 574
 575         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 576
 577         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 578         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 579
 580         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 581                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 582                               "wait-monitoring-ns", GPMC_CD_CLK);
 583         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 584                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 585                               "clk-activation-ns", GPMC_CD_FCLK);
 586
 587         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 588         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 589 }
 590 #else
 591 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 592 {
 593 }
 594 #endif
 595
 596 /**
 597  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 598  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 599  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 600  *
 601  * @cs:      Chip Select Region.
 602  * @reg:     GPMC_CS_CONFIGn register offset.
 603  * @st_bit:  Start Bit
 604  * @end_bit: End Bit. Must be >= @st_bit.
 605  * @max:     Maximum parameter value.
 606  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 607  * @time:    Timing parameter in ns.
 608  * @cd:      Timing parameter clock domain.
 609  * @name:    Timing parameter name.
 610  * @return:  0 on success, -1 on error.
 611  */
 612 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 613                                int time, enum gpmc_clk_domain cd, const char *name)
 614 {
 615         u32 l;
 616         int ticks, mask, nr_bits;
 617
 618         if (time == 0)
 619                 ticks = 0;
 620         else
 621                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 622         nr_bits = end_bit - st_bit + 1;
 623         mask = (1 << nr_bits) - 1;
 624
 625         if (!max)
 626                 max = mask;
 627
 628         if (ticks > max) {
 629                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 630                        __func__, cs, name, time, ticks, max);
 631
 632                 return -1;
 633         }
 634
 635         l = gpmc_cs_read_reg(cs, reg);
 636 #ifdef CONFIG_OMAP_GPMC_DEBUG
 637         pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 638                 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 639                         (l >> st_bit) & mask, time);
 640 #endif
 641         l &= ~(mask << st_bit);
 642         l |= ticks << st_bit;
 643         gpmc_cs_write_reg(cs, reg, l);
 644
 645         return 0;
 646 }
 647
 648 /**
 649  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 650  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 651  * read  --> don't sample bus too early
 652  * write --> data is longer on bus
 653  *
 654  * Formula:
 655  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 656  *                    / waitmonitoring_ticks)
 657  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 658  * div <= 0 check.
 659  *
 660  * @wait_monitoring: WAITMONITORINGTIME in ns.
 661  * @return:          -1 on failure to scale, else proper divider > 0.
 662  */
 663 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 664 {
 665         int div = gpmc_ns_to_ticks(wait_monitoring);
 666
 667         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 668         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 669
 670         if (div > 4)
 671                 return -1;
 672         if (div <= 0)
 673                 div = 1;
 674
 675         return div;
 676 }
 677
 678 /**
 679  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 680  * @sync_clk: GPMC_CLK period in ps.
 681  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 682  *            Else, returns -1.
 683  */
 684 int gpmc_calc_divider(unsigned int sync_clk)
 685 {
 686         int div = gpmc_ps_to_ticks(sync_clk);
 687
 688         if (div > 4)
 689                 return -1;
 690         if (div <= 0)
 691                 div = 1;
 692
 693         return div;
 694 }
 695
 696 /**
 697  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 698  * @cs:     Chip Select Region.
 699  * @t:      GPMC timing parameters.
 700  * @s:      GPMC timing settings.
 701  * @return: 0 on success, -1 on error.
 702  */
 703 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 704                         const struct gpmc_settings *s)
 705 {
 706         int div, ret;
 707         u32 l;
 708
 709         div = gpmc_calc_divider(t->sync_clk);
 710         if (div < 0)
 711                 return -EINVAL;
 712
 713         /*
 714          * See if we need to change the divider for waitmonitoringtime.
 715          *
 716          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 717          * pure asynchronous accesses, i.e. both read and write asynchronous.
 718          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 719          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 720          *
 721          * This statement must not change div to scale async WAITMONITORINGTIME
 722          * to protect mixed synchronous and asynchronous accesses.
 723          *
 724          * We raise an error later if WAITMONITORINGTIME does not fit.
 725          */
 726         if (!s->sync_read && !s->sync_write &&
 727             (s->wait_on_read || s->wait_on_write)
 728            ) {
 729                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 730                 if (div < 0) {
 731                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 732                                __func__,
 733                                t->wait_monitoring
 734                                );
 735                         return -ENXIO;
 736                 }
 737         }
 738
 739         ret = 0;
 740         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
 741                                    GPMC_CD_FCLK, "cs_on");
 742         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
 743                                    GPMC_CD_FCLK, "cs_rd_off");
 744         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
 745                                    GPMC_CD_FCLK, "cs_wr_off");
 746         if (ret)
 747                 return -ENXIO;
 748
 749         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
 750                                    GPMC_CD_FCLK, "adv_on");
 751         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
 752                                    GPMC_CD_FCLK, "adv_rd_off");
 753         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
 754                                    GPMC_CD_FCLK, "adv_wr_off");
 755         if (ret)
 756                 return -ENXIO;
 757
 758         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 759                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
 760                                            t->adv_aad_mux_on, GPMC_CD_FCLK,
 761                                            "adv_aad_mux_on");
 762                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
 763                                            t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
 764                                            "adv_aad_mux_rd_off");
 765                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
 766                                            t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
 767                                            "adv_aad_mux_wr_off");
 768                 if (ret)
 769                         return -ENXIO;
 770         }
 771
 772         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
 773                                    GPMC_CD_FCLK, "oe_on");
 774         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
 775                                    GPMC_CD_FCLK, "oe_off");
 776         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 777                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
 778                                            t->oe_aad_mux_on, GPMC_CD_FCLK,
 779                                            "oe_aad_mux_on");
 780                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
 781                                            t->oe_aad_mux_off, GPMC_CD_FCLK,
 782                                            "oe_aad_mux_off");
 783         }
 784         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
 785                                    GPMC_CD_FCLK, "we_on");
 786         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
 787                                    GPMC_CD_FCLK, "we_off");
 788         if (ret)
 789                 return -ENXIO;
 790
 791         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
 792                                    GPMC_CD_FCLK, "rd_cycle");
 793         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
 794                                    GPMC_CD_FCLK, "wr_cycle");
 795         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
 796                                    GPMC_CD_FCLK, "access");
 797         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
 798                                    t->page_burst_access, GPMC_CD_FCLK,
 799                                    "page_burst_access");
 800         if (ret)
 801                 return -ENXIO;
 802
 803         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
 804                                    t->bus_turnaround, GPMC_CD_FCLK,
 805                                    "bus_turnaround");
 806         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
 807                                    t->cycle2cycle_delay, GPMC_CD_FCLK,
 808                                    "cycle2cycle_delay");
 809         if (ret)
 810                 return -ENXIO;
 811
 812         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
 813                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
 814                                            t->wr_data_mux_bus, GPMC_CD_FCLK,
 815                                            "wr_data_mux_bus");
 816                 if (ret)
 817                         return -ENXIO;
 818         }
 819         if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
 820                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
 821                                            t->wr_access, GPMC_CD_FCLK,
 822                                            "wr_access");
 823                 if (ret)
 824                         return -ENXIO;
 825         }
 826
 827         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 828         l &= ~0x03;
 829         l |= (div - 1);
 830         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 831
 832         ret = 0;
 833         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
 834                                    GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 835                                    t->wait_monitoring, GPMC_CD_CLK,
 836                                    "wait_monitoring");
 837         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
 838                                    GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 839                                    t->clk_activation, GPMC_CD_FCLK,
 840                                    "clk_activation");
 841         if (ret)
 842                 return -ENXIO;
 843
 844 #ifdef CONFIG_OMAP_GPMC_DEBUG
 845         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 846                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 847 #endif
 848
 849         gpmc_cs_bool_timings(cs, &t->bool_timings);
 850         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 851
 852         return 0;
 853 }
 854
 855 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 856 {
 857         u32 l;
 858         u32 mask;
 859
 860         /*
 861          * Ensure that base address is aligned on a
 862          * boundary equal to or greater than size.
 863          */
 864         if (base & (size - 1))
 865                 return -EINVAL;
 866
 867         base >>= GPMC_CHUNK_SHIFT;
 868         mask = (1 << GPMC_SECTION_SHIFT) - size;
 869         mask >>= GPMC_CHUNK_SHIFT;
 870         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 871
 872         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 873         l &= ~GPMC_CONFIG7_MASK;
 874         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 875         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 876         l |= GPMC_CONFIG7_CSVALID;
 877         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 878
 879         return 0;
 880 }
 881
 882 static void gpmc_cs_enable_mem(int cs)
 883 {
 884         u32 l;
 885
 886         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 887         l |= GPMC_CONFIG7_CSVALID;
 888         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 889 }
 890
 891 static void gpmc_cs_disable_mem(int cs)
 892 {
 893         u32 l;
 894
 895         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 896         l &= ~GPMC_CONFIG7_CSVALID;
 897         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 898 }
 899
 900 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 901 {
 902         u32 l;
 903         u32 mask;
 904
 905         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 906         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 907         mask = (l >> 8) & 0x0f;
 908         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 909 }
 910
 911 static int gpmc_cs_mem_enabled(int cs)
 912 {
 913         u32 l;
 914
 915         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 916         return l & GPMC_CONFIG7_CSVALID;
 917 }
 918
 919 static void gpmc_cs_set_reserved(int cs, int reserved)
 920 {
 921         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 922
 923         gpmc->flags |= GPMC_CS_RESERVED;
 924 }
 925
 926 static bool gpmc_cs_reserved(int cs)
 927 {
 928         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 929
 930         return gpmc->flags & GPMC_CS_RESERVED;
 931 }
 932
 933 static unsigned long gpmc_mem_align(unsigned long size)
 934 {
 935         int order;
 936
 937         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 938         order = GPMC_CHUNK_SHIFT - 1;
 939         do {
 940                 size >>= 1;
 941                 order++;
 942         } while (size);
 943         size = 1 << order;
 944         return size;
 945 }
 946
 947 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 948 {
 949         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 950         struct resource *res = &gpmc->mem;
 951         int r;
 952
 953         size = gpmc_mem_align(size);
 954         spin_lock(&gpmc_mem_lock);
 955         res->start = base;
 956         res->end = base + size - 1;
 957         r = request_resource(&gpmc_mem_root, res);
 958         spin_unlock(&gpmc_mem_lock);
 959
 960         return r;
 961 }
 962
 963 static int gpmc_cs_delete_mem(int cs)
 964 {
 965         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 966         struct resource *res = &gpmc->mem;
 967         int r;
 968
 969         spin_lock(&gpmc_mem_lock);
 970         r = release_resource(res);
 971         res->start = 0;
 972         res->end = 0;
 973         spin_unlock(&gpmc_mem_lock);
 974
 975         return r;
 976 }
 977
 978 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 979 {
 980         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 981         struct resource *res = &gpmc->mem;
 982         int r = -1;
 983
 984         if (cs >= gpmc_cs_num) {
 985                 pr_err("%s: requested chip-select is disabled\n", __func__);
 986                 return -ENODEV;
 987         }
 988         size = gpmc_mem_align(size);
 989         if (size > (1 << GPMC_SECTION_SHIFT))
 990                 return -ENOMEM;
 991
 992         spin_lock(&gpmc_mem_lock);
 993         if (gpmc_cs_reserved(cs)) {
 994                 r = -EBUSY;
 995                 goto out;
 996         }
 997         if (gpmc_cs_mem_enabled(cs))
 998                 r = adjust_resource(res, res->start & ~(size - 1), size);
 999         if (r < 0)
1000                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1001                                       size, NULL, NULL);
1002         if (r < 0)
1003                 goto out;
1004
1005         /* Disable CS while changing base address and size mask */
1006         gpmc_cs_disable_mem(cs);
1007
1008         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1009         if (r < 0) {
1010                 release_resource(res);
1011                 goto out;
1012         }
1013
1014         /* Enable CS */
1015         gpmc_cs_enable_mem(cs);
1016         *base = res->start;
1017         gpmc_cs_set_reserved(cs, 1);
1018 out:
1019         spin_unlock(&gpmc_mem_lock);
1020         return r;
1021 }
1022 EXPORT_SYMBOL(gpmc_cs_request);
1023
1024 void gpmc_cs_free(int cs)
1025 {
1026         struct gpmc_cs_data *gpmc;
1027         struct resource *res;
1028
1029         spin_lock(&gpmc_mem_lock);
1030         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1031                 WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
1032                 spin_unlock(&gpmc_mem_lock);
1033                 return;
1034         }
1035         gpmc = &gpmc_cs[cs];
1036         res = &gpmc->mem;
1037
1038         gpmc_cs_disable_mem(cs);
1039         if (res->flags)
1040                 release_resource(res);
1041         gpmc_cs_set_reserved(cs, 0);
1042         spin_unlock(&gpmc_mem_lock);
1043 }
1044 EXPORT_SYMBOL(gpmc_cs_free);
1045
1046 static bool gpmc_is_valid_waitpin(u32 waitpin)
1047 {
1048         return waitpin < gpmc_nr_waitpins;
1049 }
1050
1051 static int gpmc_alloc_waitpin(struct gpmc_device *gpmc,
1052                               struct gpmc_settings *p)
1053 {
1054         int ret;
1055         struct gpmc_waitpin *waitpin;
1056         struct gpio_desc *waitpin_desc;
1057
1058         if (!gpmc_is_valid_waitpin(p->wait_pin))
1059                 return -EINVAL;
1060
1061         waitpin = &gpmc->waitpins[p->wait_pin];
1062
1063         if (!waitpin->desc) {
1064                 /* Reserve the GPIO for wait pin usage.
1065                  * GPIO polarity doesn't matter here. Wait pin polarity
1066                  * is set in GPMC_CONFIG register.
1067                  */
1068                 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
1069                                                          p->wait_pin, "WAITPIN",
1070                                                          GPIO_ACTIVE_HIGH,
1071                                                          GPIOD_IN);
1072
1073                 ret = PTR_ERR(waitpin_desc);
1074                 if (IS_ERR(waitpin_desc) && ret != -EBUSY)
1075                         return ret;
1076
1077                 /* New wait pin */
1078                 waitpin->desc = waitpin_desc;
1079                 waitpin->pin = p->wait_pin;
1080                 waitpin->polarity = p->wait_pin_polarity;
1081         } else {
1082                 /* Shared wait pin */
1083                 if (p->wait_pin_polarity != waitpin->polarity ||
1084                     p->wait_pin != waitpin->pin) {
1085                         dev_err(gpmc->dev,
1086                                 "shared-wait-pin: invalid configuration\n");
1087                         return -EINVAL;
1088                 }
1089                 dev_info(gpmc->dev, "shared wait-pin: %d\n", waitpin->pin);
1090         }
1091
1092         return 0;
1093 }
1094
1095 static void gpmc_free_waitpin(struct gpmc_device *gpmc,
1096                               int wait_pin)
1097 {
1098         if (gpmc_is_valid_waitpin(wait_pin))
1099                 gpiochip_free_own_desc(gpmc->waitpins[wait_pin].desc);
1100 }
1101
1102 /**
1103  * gpmc_configure - write request to configure gpmc
1104  * @cmd: command type
1105  * @wval: value to write
1106  * @return status of the operation
1107  */
1108 int gpmc_configure(int cmd, int wval)
1109 {
1110         u32 regval;
1111
1112         switch (cmd) {
1113         case GPMC_CONFIG_WP:
1114                 regval = gpmc_read_reg(GPMC_CONFIG);
1115                 if (wval)
1116                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1117                 else
1118                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1119                 gpmc_write_reg(GPMC_CONFIG, regval);
1120                 break;
1121
1122         default:
1123                 pr_err("%s: command not supported\n", __func__);
1124                 return -EINVAL;
1125         }
1126
1127         return 0;
1128 }
1129 EXPORT_SYMBOL(gpmc_configure);
1130
1131 static bool gpmc_nand_writebuffer_empty(void)
1132 {
1133         if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1134                 return true;
1135
1136         return false;
1137 }
1138
1139 static struct gpmc_nand_ops nand_ops = {
1140         .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1141 };
1142
1143 /**
1144  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1145  * @reg: the GPMC NAND register map exclusive for NAND use.
1146  * @cs: GPMC chip select number on which the NAND sits. The
1147  *      register map returned will be specific to this chip select.
1148  *
1149  * Returns NULL on error e.g. invalid cs.
1150  */
1151 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1152 {
1153         int i;
1154
1155         if (cs >= gpmc_cs_num)
1156                 return NULL;
1157
1158         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1159                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1160         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1161                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1162         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1163                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1164         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1165         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1166         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1167         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1168         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1169         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1170         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1171         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1172
1173         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1174                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1175                                            GPMC_BCH_SIZE * i;
1176                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1177                                            GPMC_BCH_SIZE * i;
1178                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1179                                            GPMC_BCH_SIZE * i;
1180                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1181                                            GPMC_BCH_SIZE * i;
1182                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1183                                            i * GPMC_BCH_SIZE;
1184                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1185                                            i * GPMC_BCH_SIZE;
1186                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1187                                            i * GPMC_BCH_SIZE;
1188         }
1189
1190         return &nand_ops;
1191 }
1192 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1193
1194 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1195                                                 struct gpmc_settings *s,
1196                                                 int freq, int latency)
1197 {
1198         struct gpmc_device_timings dev_t;
1199         const int t_cer  = 15;
1200         const int t_avdp = 12;
1201         const int t_cez  = 20; /* max of t_cez, t_oez */
1202         const int t_wpl  = 40;
1203         const int t_wph  = 30;
1204         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1205
1206         switch (freq) {
1207         case 104:
1208                 min_gpmc_clk_period = 9600; /* 104 MHz */
1209                 t_ces   = 3;
1210                 t_avds  = 4;
1211                 t_avdh  = 2;
1212                 t_ach   = 3;
1213                 t_aavdh = 6;
1214                 t_rdyo  = 6;
1215                 break;
1216         case 83:
1217                 min_gpmc_clk_period = 12000; /* 83 MHz */
1218                 t_ces   = 5;
1219                 t_avds  = 4;
1220                 t_avdh  = 2;
1221                 t_ach   = 6;
1222                 t_aavdh = 6;
1223                 t_rdyo  = 9;
1224                 break;
1225         case 66:
1226                 min_gpmc_clk_period = 15000; /* 66 MHz */
1227                 t_ces   = 6;
1228                 t_avds  = 5;
1229                 t_avdh  = 2;
1230                 t_ach   = 6;
1231                 t_aavdh = 6;
1232                 t_rdyo  = 11;
1233                 break;
1234         default:
1235                 min_gpmc_clk_period = 18500; /* 54 MHz */
1236                 t_ces   = 7;
1237                 t_avds  = 7;
1238                 t_avdh  = 7;
1239                 t_ach   = 9;
1240                 t_aavdh = 7;
1241                 t_rdyo  = 15;
1242                 break;
1243         }
1244
1245         /* Set synchronous read timings */
1246         memset(&dev_t, 0, sizeof(dev_t));
1247
1248         if (!s->sync_write) {
1249                 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1250                 dev_t.t_wpl = t_wpl * 1000;
1251                 dev_t.t_wph = t_wph * 1000;
1252                 dev_t.t_aavdh = t_aavdh * 1000;
1253         }
1254         dev_t.ce_xdelay = true;
1255         dev_t.avd_xdelay = true;
1256         dev_t.oe_xdelay = true;
1257         dev_t.we_xdelay = true;
1258         dev_t.clk = min_gpmc_clk_period;
1259         dev_t.t_bacc = dev_t.clk;
1260         dev_t.t_ces = t_ces * 1000;
1261         dev_t.t_avds = t_avds * 1000;
1262         dev_t.t_avdh = t_avdh * 1000;
1263         dev_t.t_ach = t_ach * 1000;
1264         dev_t.cyc_iaa = (latency + 1);
1265         dev_t.t_cez_r = t_cez * 1000;
1266         dev_t.t_cez_w = dev_t.t_cez_r;
1267         dev_t.cyc_aavdh_oe = 1;
1268         dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1269
1270         gpmc_calc_timings(t, s, &dev_t);
1271 }
1272
1273 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1274                                   int latency,
1275                                   struct gpmc_onenand_info *info)
1276 {
1277         int ret;
1278         struct gpmc_timings gpmc_t;
1279         struct gpmc_settings gpmc_s;
1280
1281         gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1282
1283         info->sync_read = gpmc_s.sync_read;
1284         info->sync_write = gpmc_s.sync_write;
1285         info->burst_len = gpmc_s.burst_len;
1286
1287         if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1288                 return 0;
1289
1290         gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1291
1292         ret = gpmc_cs_program_settings(cs, &gpmc_s);
1293         if (ret < 0)
1294                 return ret;
1295
1296         return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1297 }
1298 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1299
1300 int gpmc_get_client_irq(unsigned int irq_config)
1301 {
1302         if (!gpmc_irq_domain) {
1303                 pr_warn("%s called before GPMC IRQ domain available\n",
1304                         __func__);
1305                 return 0;
1306         }
1307
1308         /* we restrict this to NAND IRQs only */
1309         if (irq_config >= GPMC_NR_NAND_IRQS)
1310                 return 0;
1311
1312         return irq_create_mapping(gpmc_irq_domain, irq_config);
1313 }
1314
1315 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1316 {
1317         u32 regval;
1318
1319         /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1320         if (hwirq >= GPMC_NR_NAND_IRQS)
1321                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1322
1323         regval = gpmc_read_reg(GPMC_IRQENABLE);
1324         if (endis)
1325                 regval |= BIT(hwirq);
1326         else
1327                 regval &= ~BIT(hwirq);
1328         gpmc_write_reg(GPMC_IRQENABLE, regval);
1329
1330         return 0;
1331 }
1332
1333 static void gpmc_irq_disable(struct irq_data *p)
1334 {
1335         gpmc_irq_endis(p->hwirq, false);
1336 }
1337
1338 static void gpmc_irq_enable(struct irq_data *p)
1339 {
1340         gpmc_irq_endis(p->hwirq, true);
1341 }
1342
1343 static void gpmc_irq_mask(struct irq_data *d)
1344 {
1345         gpmc_irq_endis(d->hwirq, false);
1346 }
1347
1348 static void gpmc_irq_unmask(struct irq_data *d)
1349 {
1350         gpmc_irq_endis(d->hwirq, true);
1351 }
1352
1353 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1354 {
1355         u32 regval;
1356
1357         /* NAND IRQs polarity is not configurable */
1358         if (hwirq < GPMC_NR_NAND_IRQS)
1359                 return;
1360
1361         /* WAITPIN starts at BIT 8 */
1362         hwirq += 8 - GPMC_NR_NAND_IRQS;
1363
1364         regval = gpmc_read_reg(GPMC_CONFIG);
1365         if (rising_edge)
1366                 regval &= ~BIT(hwirq);
1367         else
1368                 regval |= BIT(hwirq);
1369
1370         gpmc_write_reg(GPMC_CONFIG, regval);
1371 }
1372
1373 static void gpmc_irq_ack(struct irq_data *d)
1374 {
1375         unsigned int hwirq = d->hwirq;
1376
1377         /* skip reserved bits */
1378         if (hwirq >= GPMC_NR_NAND_IRQS)
1379                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1380
1381         /* Setting bit to 1 clears (or Acks) the interrupt */
1382         gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1383 }
1384
1385 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1386 {
1387         /* can't set type for NAND IRQs */
1388         if (d->hwirq < GPMC_NR_NAND_IRQS)
1389                 return -EINVAL;
1390
1391         /* We can support either rising or falling edge at a time */
1392         if (trigger == IRQ_TYPE_EDGE_FALLING)
1393                 gpmc_irq_edge_config(d->hwirq, false);
1394         else if (trigger == IRQ_TYPE_EDGE_RISING)
1395                 gpmc_irq_edge_config(d->hwirq, true);
1396         else
1397                 return -EINVAL;
1398
1399         return 0;
1400 }
1401
1402 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1403                         irq_hw_number_t hw)
1404 {
1405         struct gpmc_device *gpmc = d->host_data;
1406
1407         irq_set_chip_data(virq, gpmc);
1408         if (hw < GPMC_NR_NAND_IRQS) {
1409                 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1410                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1411                                          handle_simple_irq);
1412         } else {
1413                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1414                                          handle_edge_irq);
1415         }
1416
1417         return 0;
1418 }
1419
1420 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1421         .map    = gpmc_irq_map,
1422         .xlate  = irq_domain_xlate_twocell,
1423 };
1424
1425 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1426 {
1427         int hwirq, virq;
1428         u32 regval, regvalx;
1429         struct gpmc_device *gpmc = data;
1430
1431         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1432         regvalx = regval;
1433
1434         if (!regval)
1435                 return IRQ_NONE;
1436
1437         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1438                 /* skip reserved status bits */
1439                 if (hwirq == GPMC_NR_NAND_IRQS)
1440                         regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1441
1442                 if (regvalx & BIT(hwirq)) {
1443                         virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1444                         if (!virq) {
1445                                 dev_warn(gpmc->dev,
1446                                          "spurious irq detected hwirq %d, virq %d\n",
1447                                          hwirq, virq);
1448                         }
1449
1450                         generic_handle_irq(virq);
1451                 }
1452         }
1453
1454         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1455
1456         return IRQ_HANDLED;
1457 }
1458
1459 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1460 {
1461         u32 regval;
1462         int rc;
1463
1464         /* Disable interrupts */
1465         gpmc_write_reg(GPMC_IRQENABLE, 0);
1466
1467         /* clear interrupts */
1468         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1469         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1470
1471         gpmc->irq_chip.name = "gpmc";
1472         gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1473         gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1474         gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1475         gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1476         gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1477         gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1478
1479         gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1480                                                 gpmc->nirqs,
1481                                                 &gpmc_irq_domain_ops,
1482                                                 gpmc);
1483         if (!gpmc_irq_domain) {
1484                 dev_err(gpmc->dev, "IRQ domain add failed\n");
1485                 return -ENODEV;
1486         }
1487
1488         rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1489         if (rc) {
1490                 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1491                         gpmc->irq, rc);
1492                 irq_domain_remove(gpmc_irq_domain);
1493                 gpmc_irq_domain = NULL;
1494         }
1495
1496         return rc;
1497 }
1498
1499 static int gpmc_free_irq(struct gpmc_device *gpmc)
1500 {
1501         int hwirq;
1502
1503         free_irq(gpmc->irq, gpmc);
1504
1505         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1506                 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1507
1508         irq_domain_remove(gpmc_irq_domain);
1509         gpmc_irq_domain = NULL;
1510
1511         return 0;
1512 }
1513
1514 static void gpmc_mem_exit(void)
1515 {
1516         int cs;
1517
1518         for (cs = 0; cs < gpmc_cs_num; cs++) {
1519                 if (!gpmc_cs_mem_enabled(cs))
1520                         continue;
1521                 gpmc_cs_delete_mem(cs);
1522         }
1523 }
1524
1525 static void gpmc_mem_init(struct gpmc_device *gpmc)
1526 {
1527         int cs;
1528
1529         if (!gpmc->data) {
1530                 /* All legacy devices have same data IO window */
1531                 gpmc_mem_root.start = GPMC_MEM_START;
1532                 gpmc_mem_root.end = GPMC_MEM_END;
1533         } else {
1534                 gpmc_mem_root.start = gpmc->data->start;
1535                 gpmc_mem_root.end = gpmc->data->end;
1536         }
1537
1538         /* Reserve all regions that has been set up by bootloader */
1539         for (cs = 0; cs < gpmc_cs_num; cs++) {
1540                 u32 base, size;
1541
1542                 if (!gpmc_cs_mem_enabled(cs))
1543                         continue;
1544                 gpmc_cs_get_memconf(cs, &base, &size);
1545                 if (gpmc_cs_insert_mem(cs, base, size)) {
1546                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1547                                 __func__, cs, base, base + size);
1548                         gpmc_cs_disable_mem(cs);
1549                 }
1550         }
1551 }
1552
1553 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1554 {
1555         u32 temp;
1556         int div;
1557
1558         div = gpmc_calc_divider(sync_clk);
1559         temp = gpmc_ps_to_ticks(time_ps);
1560         temp = (temp + div - 1) / div;
1561         return gpmc_ticks_to_ps(temp * div);
1562 }
1563
1564 /* XXX: can the cycles be avoided ? */
1565 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1566                                        struct gpmc_device_timings *dev_t,
1567                                        bool mux)
1568 {
1569         u32 temp;
1570
1571         /* adv_rd_off */
1572         temp = dev_t->t_avdp_r;
1573         /* XXX: mux check required ? */
1574         if (mux) {
1575                 /* XXX: t_avdp not to be required for sync, only added for tusb
1576                  * this indirectly necessitates requirement of t_avdp_r and
1577                  * t_avdp_w instead of having a single t_avdp
1578                  */
1579                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1580                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1581         }
1582         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1583
1584         /* oe_on */
1585         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1586         if (mux) {
1587                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1588                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1589                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1590         }
1591         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1592
1593         /* access */
1594         /* XXX: any scope for improvement ?, by combining oe_on
1595          * and clk_activation, need to check whether
1596          * access = clk_activation + round to sync clk ?
1597          */
1598         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1599         temp += gpmc_t->clk_activation;
1600         if (dev_t->cyc_oe)
1601                 temp = max_t(u32, temp, gpmc_t->oe_on +
1602                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1603         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1604
1605         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1606         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1607
1608         /* rd_cycle */
1609         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1610         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1611                                                         gpmc_t->access;
1612         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1613         if (dev_t->t_ce_rdyz)
1614                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1615         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1616
1617         return 0;
1618 }
1619
1620 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1621                                         struct gpmc_device_timings *dev_t,
1622                                         bool mux)
1623 {
1624         u32 temp;
1625
1626         /* adv_wr_off */
1627         temp = dev_t->t_avdp_w;
1628         if (mux) {
1629                 temp = max_t(u32, temp,
1630                         gpmc_t->clk_activation + dev_t->t_avdh);
1631                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1632         }
1633         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1634
1635         /* wr_data_mux_bus */
1636         temp = max_t(u32, dev_t->t_weasu,
1637                         gpmc_t->clk_activation + dev_t->t_rdyo);
1638         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1639          * and in that case remember to handle we_on properly
1640          */
1641         if (mux) {
1642                 temp = max_t(u32, temp,
1643                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1644                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1645                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1646         }
1647         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1648
1649         /* we_on */
1650         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1651                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1652         else
1653                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1654
1655         /* wr_access */
1656         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1657         gpmc_t->wr_access = gpmc_t->access;
1658
1659         /* we_off */
1660         temp = gpmc_t->we_on + dev_t->t_wpl;
1661         temp = max_t(u32, temp,
1662                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1663         temp = max_t(u32, temp,
1664                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1665         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1666
1667         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1668                                                         dev_t->t_wph);
1669
1670         /* wr_cycle */
1671         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1672         temp += gpmc_t->wr_access;
1673         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1674         if (dev_t->t_ce_rdyz)
1675                 temp = max_t(u32, temp,
1676                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1677         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1678
1679         return 0;
1680 }
1681
1682 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1683                                         struct gpmc_device_timings *dev_t,
1684                                         bool mux)
1685 {
1686         u32 temp;
1687
1688         /* adv_rd_off */
1689         temp = dev_t->t_avdp_r;
1690         if (mux)
1691                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1692         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1693
1694         /* oe_on */
1695         temp = dev_t->t_oeasu;
1696         if (mux)
1697                 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
1698         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1699
1700         /* access */
1701         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1702                      gpmc_t->oe_on + dev_t->t_oe);
1703         temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1704         temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
1705         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1706
1707         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1708         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1709
1710         /* rd_cycle */
1711         temp = max_t(u32, dev_t->t_rd_cycle,
1712                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1713         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1714         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1715
1716         return 0;
1717 }
1718
1719 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1720                                          struct gpmc_device_timings *dev_t,
1721                                          bool mux)
1722 {
1723         u32 temp;
1724
1725         /* adv_wr_off */
1726         temp = dev_t->t_avdp_w;
1727         if (mux)
1728                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1729         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1730
1731         /* wr_data_mux_bus */
1732         temp = dev_t->t_weasu;
1733         if (mux) {
1734                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1735                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1736                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1737         }
1738         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1739
1740         /* we_on */
1741         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1742                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1743         else
1744                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1745
1746         /* we_off */
1747         temp = gpmc_t->we_on + dev_t->t_wpl;
1748         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1749
1750         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1751                                                         dev_t->t_wph);
1752
1753         /* wr_cycle */
1754         temp = max_t(u32, dev_t->t_wr_cycle,
1755                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1756         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1757
1758         return 0;
1759 }
1760
1761 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1762                         struct gpmc_device_timings *dev_t)
1763 {
1764         u32 temp;
1765
1766         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1767                                                 gpmc_get_fclk_period();
1768
1769         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1770                                         dev_t->t_bacc,
1771                                         gpmc_t->sync_clk);
1772
1773         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1774         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1775
1776         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1777                 return 0;
1778
1779         if (dev_t->ce_xdelay)
1780                 gpmc_t->bool_timings.cs_extra_delay = true;
1781         if (dev_t->avd_xdelay)
1782                 gpmc_t->bool_timings.adv_extra_delay = true;
1783         if (dev_t->oe_xdelay)
1784                 gpmc_t->bool_timings.oe_extra_delay = true;
1785         if (dev_t->we_xdelay)
1786                 gpmc_t->bool_timings.we_extra_delay = true;
1787
1788         return 0;
1789 }
1790
1791 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1792                                     struct gpmc_device_timings *dev_t,
1793                                     bool sync)
1794 {
1795         u32 temp;
1796
1797         /* cs_on */
1798         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1799
1800         /* adv_on */
1801         temp = dev_t->t_avdasu;
1802         if (dev_t->t_ce_avd)
1803                 temp = max_t(u32, temp,
1804                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1805         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1806
1807         if (sync)
1808                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1809
1810         return 0;
1811 }
1812
1813 /*
1814  * TODO: remove this function once all peripherals are confirmed to
1815  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1816  * has to be modified to handle timings in ps instead of ns
1817  */
1818 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1819 {
1820         t->cs_on /= 1000;
1821         t->cs_rd_off /= 1000;
1822         t->cs_wr_off /= 1000;
1823         t->adv_on /= 1000;
1824         t->adv_rd_off /= 1000;
1825         t->adv_wr_off /= 1000;
1826         t->we_on /= 1000;
1827         t->we_off /= 1000;
1828         t->oe_on /= 1000;
1829         t->oe_off /= 1000;
1830         t->page_burst_access /= 1000;
1831         t->access /= 1000;
1832         t->rd_cycle /= 1000;
1833         t->wr_cycle /= 1000;
1834         t->bus_turnaround /= 1000;
1835         t->cycle2cycle_delay /= 1000;
1836         t->wait_monitoring /= 1000;
1837         t->clk_activation /= 1000;
1838         t->wr_access /= 1000;
1839         t->wr_data_mux_bus /= 1000;
1840 }
1841
1842 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1843                       struct gpmc_settings *gpmc_s,
1844                       struct gpmc_device_timings *dev_t)
1845 {
1846         bool mux = false, sync = false;
1847
1848         if (gpmc_s) {
1849                 mux = gpmc_s->mux_add_data ? true : false;
1850                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1851         }
1852
1853         memset(gpmc_t, 0, sizeof(*gpmc_t));
1854
1855         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1856
1857         if (gpmc_s && gpmc_s->sync_read)
1858                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1859         else
1860                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1861
1862         if (gpmc_s && gpmc_s->sync_write)
1863                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1864         else
1865                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1866
1867         /* TODO: remove, see function definition */
1868         gpmc_convert_ps_to_ns(gpmc_t);
1869
1870         return 0;
1871 }
1872
1873 /**
1874  * gpmc_cs_program_settings - programs non-timing related settings
1875  * @cs:         GPMC chip-select to program
1876  * @p:          pointer to GPMC settings structure
1877  *
1878  * Programs non-timing related settings for a GPMC chip-select, such as
1879  * bus-width, burst configuration, etc. Function should be called once
1880  * for each chip-select that is being used and must be called before
1881  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1882  * register will be initialised to zero by this function. Returns 0 on
1883  * success and appropriate negative error code on failure.
1884  */
1885 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1886 {
1887         u32 config1;
1888
1889         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1890                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1891                 return -EINVAL;
1892         }
1893
1894         /* Address-data multiplexing not supported for NAND devices */
1895         if (p->device_nand && p->mux_add_data) {
1896                 pr_err("%s: invalid configuration!\n", __func__);
1897                 return -EINVAL;
1898         }
1899
1900         if ((p->mux_add_data > GPMC_MUX_AD) ||
1901             ((p->mux_add_data == GPMC_MUX_AAD) &&
1902              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1903                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1904                 return -EINVAL;
1905         }
1906
1907         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1908         if (p->burst_read || p->burst_write) {
1909                 switch (p->burst_len) {
1910                 case GPMC_BURST_4:
1911                 case GPMC_BURST_8:
1912                 case GPMC_BURST_16:
1913                         break;
1914                 default:
1915                         pr_err("%s: invalid page/burst-length (%d)\n",
1916                                __func__, p->burst_len);
1917                         return -EINVAL;
1918                 }
1919         }
1920
1921         if (p->wait_pin != GPMC_WAITPIN_INVALID &&
1922             p->wait_pin > gpmc_nr_waitpins) {
1923                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1924                 return -EINVAL;
1925         }
1926
1927         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1928
1929         if (p->sync_read)
1930                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1931         if (p->sync_write)
1932                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1933         if (p->wait_on_read)
1934                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1935         if (p->wait_on_write)
1936                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1937         if (p->wait_on_read || p->wait_on_write)
1938                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1939         if (p->device_nand)
1940                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1941         if (p->mux_add_data)
1942                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1943         if (p->burst_read)
1944                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1945         if (p->burst_write)
1946                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1947         if (p->burst_read || p->burst_write) {
1948                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1949                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1950         }
1951
1952         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1953
1954         if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_INVALID) {
1955                 config1 = gpmc_read_reg(GPMC_CONFIG);
1956
1957                 if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_LOW)
1958                         config1 &= ~GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin);
1959                 else if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_HIGH)
1960                         config1 |= GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin);
1961
1962                 gpmc_write_reg(GPMC_CONFIG, config1);
1963         }
1964
1965         return 0;
1966 }
1967
1968 #ifdef CONFIG_OF
1969 static void gpmc_cs_set_name(int cs, const char *name)
1970 {
1971         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1972
1973         gpmc->name = name;
1974 }
1975
1976 static const char *gpmc_cs_get_name(int cs)
1977 {
1978         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1979
1980         return gpmc->name;
1981 }
1982
1983 /**
1984  * gpmc_cs_remap - remaps a chip-select physical base address
1985  * @cs:         chip-select to remap
1986  * @base:       physical base address to re-map chip-select to
1987  *
1988  * Re-maps a chip-select to a new physical base address specified by
1989  * "base". Returns 0 on success and appropriate negative error code
1990  * on failure.
1991  */
1992 static int gpmc_cs_remap(int cs, u32 base)
1993 {
1994         int ret;
1995         u32 old_base, size;
1996
1997         if (cs >= gpmc_cs_num) {
1998                 pr_err("%s: requested chip-select is disabled\n", __func__);
1999                 return -ENODEV;
2000         }
2001
2002         /*
2003          * Make sure we ignore any device offsets from the GPMC partition
2004          * allocated for the chip select and that the new base confirms
2005          * to the GPMC 16MB minimum granularity.
2006          */
2007         base &= ~(SZ_16M - 1);
2008
2009         gpmc_cs_get_memconf(cs, &old_base, &size);
2010         if (base == old_base)
2011                 return 0;
2012
2013         ret = gpmc_cs_delete_mem(cs);
2014         if (ret < 0)
2015                 return ret;
2016
2017         ret = gpmc_cs_insert_mem(cs, base, size);
2018         if (ret < 0)
2019                 return ret;
2020
2021         ret = gpmc_cs_set_memconf(cs, base, size);
2022
2023         return ret;
2024 }
2025
2026 /**
2027  * gpmc_read_settings_dt - read gpmc settings from device-tree
2028  * @np:         pointer to device-tree node for a gpmc child device
2029  * @p:          pointer to gpmc settings structure
2030  *
2031  * Reads the GPMC settings for a GPMC child device from device-tree and
2032  * stores them in the GPMC settings structure passed. The GPMC settings
2033  * structure is initialised to zero by this function and so any
2034  * previously stored settings will be cleared.
2035  */
2036 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2037 {
2038         memset(p, 0, sizeof(struct gpmc_settings));
2039
2040         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
2041         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
2042         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
2043         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
2044
2045         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
2046                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
2047                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
2048                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
2049                 if (!p->burst_read && !p->burst_write)
2050                         pr_warn("%s: page/burst-length set but not used!\n",
2051                                 __func__);
2052         }
2053
2054         p->wait_pin = GPMC_WAITPIN_INVALID;
2055         p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID;
2056
2057         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
2058                 if (!gpmc_is_valid_waitpin(p->wait_pin)) {
2059                         pr_err("%s: Invalid wait-pin (%d)\n", __func__, p->wait_pin);
2060                         p->wait_pin = GPMC_WAITPIN_INVALID;
2061                 }
2062
2063                 if (!of_property_read_u32(np, "ti,wait-pin-polarity",
2064                                           &p->wait_pin_polarity)) {
2065                         if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_HIGH &&
2066                             p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_LOW) {
2067                                 pr_err("%s: Invalid wait-pin-polarity (%d)\n",
2068                                        __func__, p->wait_pin_polarity);
2069                                 p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID;
2070                                 }
2071                 }
2072
2073                 p->wait_on_read = of_property_read_bool(np,
2074                                                         "gpmc,wait-on-read");
2075                 p->wait_on_write = of_property_read_bool(np,
2076                                                          "gpmc,wait-on-write");
2077                 if (!p->wait_on_read && !p->wait_on_write)
2078                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
2079                                  __func__);
2080         }
2081 }
2082
2083 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
2084                                                 struct gpmc_timings *gpmc_t)
2085 {
2086         struct gpmc_bool_timings *p;
2087
2088         if (!np || !gpmc_t)
2089                 return;
2090
2091         memset(gpmc_t, 0, sizeof(*gpmc_t));
2092
2093         /* minimum clock period for syncronous mode */
2094         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
2095
2096         /* chip select timtings */
2097         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
2098         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
2099         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
2100
2101         /* ADV signal timings */
2102         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
2103         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
2104         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
2105         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
2106                              &gpmc_t->adv_aad_mux_on);
2107         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
2108                              &gpmc_t->adv_aad_mux_rd_off);
2109         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
2110                              &gpmc_t->adv_aad_mux_wr_off);
2111
2112         /* WE signal timings */
2113         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
2114         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
2115
2116         /* OE signal timings */
2117         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
2118         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
2119         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
2120                              &gpmc_t->oe_aad_mux_on);
2121         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
2122                              &gpmc_t->oe_aad_mux_off);
2123
2124         /* access and cycle timings */
2125         of_property_read_u32(np, "gpmc,page-burst-access-ns",
2126                              &gpmc_t->page_burst_access);
2127         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
2128         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
2129         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
2130         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
2131                              &gpmc_t->bus_turnaround);
2132         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
2133                              &gpmc_t->cycle2cycle_delay);
2134         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2135                              &gpmc_t->wait_monitoring);
2136         of_property_read_u32(np, "gpmc,clk-activation-ns",
2137                              &gpmc_t->clk_activation);
2138
2139         /* only applicable to OMAP3+ */
2140         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2141         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2142                              &gpmc_t->wr_data_mux_bus);
2143
2144         /* bool timing parameters */
2145         p = &gpmc_t->bool_timings;
2146
2147         p->cycle2cyclediffcsen =
2148                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2149         p->cycle2cyclesamecsen =
2150                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2151         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2152         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2153         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2154         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2155         p->time_para_granularity =
2156                 of_property_read_bool(np, "gpmc,time-para-granularity");
2157 }
2158
2159 /**
2160  * gpmc_probe_generic_child - configures the gpmc for a child device
2161  * @pdev:       pointer to gpmc platform device
2162  * @child:      pointer to device-tree node for child device
2163  *
2164  * Allocates and configures a GPMC chip-select for a child device.
2165  * Returns 0 on success and appropriate negative error code on failure.
2166  */
2167 static int gpmc_probe_generic_child(struct platform_device *pdev,
2168                                 struct device_node *child)
2169 {
2170         struct gpmc_settings gpmc_s;
2171         struct gpmc_timings gpmc_t;
2172         struct resource res;
2173         unsigned long base;
2174         const char *name;
2175         int ret, cs;
2176         u32 val;
2177         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2178
2179         if (of_property_read_u32(child, "reg", &cs) < 0) {
2180                 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2181                         child);
2182                 return -ENODEV;
2183         }
2184
2185         if (of_address_to_resource(child, 0, &res) < 0) {
2186                 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2187                         child);
2188                 return -ENODEV;
2189         }
2190
2191         /*
2192          * Check if we have multiple instances of the same device
2193          * on a single chip select. If so, use the already initialized
2194          * timings.
2195          */
2196         name = gpmc_cs_get_name(cs);
2197         if (name && of_node_name_eq(child, name))
2198                 goto no_timings;
2199
2200         ret = gpmc_cs_request(cs, resource_size(&res), &base);
2201         if (ret < 0) {
2202                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2203                 return ret;
2204         }
2205         gpmc_cs_set_name(cs, child->full_name);
2206
2207         gpmc_read_settings_dt(child, &gpmc_s);
2208         gpmc_read_timings_dt(child, &gpmc_t);
2209
2210         /*
2211          * For some GPMC devices we still need to rely on the bootloader
2212          * timings because the devices can be connected via FPGA.
2213          * REVISIT: Add timing support from slls644g.pdf.
2214          */
2215         if (!gpmc_t.cs_rd_off) {
2216                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2217                         cs);
2218                 gpmc_cs_show_timings(cs,
2219                                      "please add GPMC bootloader timings to .dts");
2220                 goto no_timings;
2221         }
2222
2223         /* CS must be disabled while making changes to gpmc configuration */
2224         gpmc_cs_disable_mem(cs);
2225
2226         /*
2227          * FIXME: gpmc_cs_request() will map the CS to an arbitrary
2228          * location in the gpmc address space. When booting with
2229          * device-tree we want the NOR flash to be mapped to the
2230          * location specified in the device-tree blob. So remap the
2231          * CS to this location. Once DT migration is complete should
2232          * just make gpmc_cs_request() map a specific address.
2233          */
2234         ret = gpmc_cs_remap(cs, res.start);
2235         if (ret < 0) {
2236                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2237                         cs, &res.start);
2238                 if (res.start < GPMC_MEM_START) {
2239                         dev_info(&pdev->dev,
2240                                  "GPMC CS %d start cannot be lesser than 0x%x\n",
2241                                  cs, GPMC_MEM_START);
2242                 } else if (res.end > GPMC_MEM_END) {
2243                         dev_info(&pdev->dev,
2244                                  "GPMC CS %d end cannot be greater than 0x%x\n",
2245                                  cs, GPMC_MEM_END);
2246                 }
2247                 goto err;
2248         }
2249
2250         if (of_node_name_eq(child, "nand")) {
2251                 /* Warn about older DT blobs with no compatible property */
2252                 if (!of_property_read_bool(child, "compatible")) {
2253                         dev_warn(&pdev->dev,
2254                                  "Incompatible NAND node: missing compatible");
2255                         ret = -EINVAL;
2256                         goto err;
2257                 }
2258         }
2259
2260         if (of_node_name_eq(child, "onenand")) {
2261                 /* Warn about older DT blobs with no compatible property */
2262                 if (!of_property_read_bool(child, "compatible")) {
2263                         dev_warn(&pdev->dev,
2264                                  "Incompatible OneNAND node: missing compatible");
2265                         ret = -EINVAL;
2266                         goto err;
2267                 }
2268         }
2269
2270         if (of_match_node(omap_nand_ids, child)) {
2271                 /* NAND specific setup */
2272                 val = 8;
2273                 of_property_read_u32(child, "nand-bus-width", &val);
2274                 switch (val) {
2275                 case 8:
2276                         gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2277                         break;
2278                 case 16:
2279                         gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2280                         break;
2281                 default:
2282                         dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2283                                 child);
2284                         ret = -EINVAL;
2285                         goto err;
2286                 }
2287
2288                 /* disable write protect */
2289                 gpmc_configure(GPMC_CONFIG_WP, 0);
2290                 gpmc_s.device_nand = true;
2291         } else {
2292                 ret = of_property_read_u32(child, "bank-width",
2293                                            &gpmc_s.device_width);
2294                 if (ret < 0 && !gpmc_s.device_width) {
2295                         dev_err(&pdev->dev,
2296                                 "%pOF has no 'gpmc,device-width' property\n",
2297                                 child);
2298                         goto err;
2299                 }
2300         }
2301
2302         /* Reserve wait pin if it is required and valid */
2303         if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2304                 ret = gpmc_alloc_waitpin(gpmc, &gpmc_s);
2305                 if (ret < 0)
2306                         goto err;
2307         }
2308
2309         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2310
2311         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2312         if (ret < 0)
2313                 goto err_cs;
2314
2315         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2316         if (ret) {
2317                 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2318                         child);
2319                 goto err_cs;
2320         }
2321
2322         /* Clear limited address i.e. enable A26-A11 */
2323         val = gpmc_read_reg(GPMC_CONFIG);
2324         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2325         gpmc_write_reg(GPMC_CONFIG, val);
2326
2327         /* Enable CS region */
2328         gpmc_cs_enable_mem(cs);
2329
2330 no_timings:
2331
2332         /* create platform device, NULL on error or when disabled */
2333         if (!of_platform_device_create(child, NULL, &pdev->dev))
2334                 goto err_child_fail;
2335
2336         /* create children and other common bus children */
2337         if (of_platform_default_populate(child, NULL, &pdev->dev))
2338                 goto err_child_fail;
2339
2340         return 0;
2341
2342 err_child_fail:
2343
2344         dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
2345         ret = -ENODEV;
2346
2347 err_cs:
2348         gpmc_free_waitpin(gpmc, gpmc_s.wait_pin);
2349 err:
2350         gpmc_cs_free(cs);
2351
2352         return ret;
2353 }
2354
2355 static const struct of_device_id gpmc_dt_ids[];
2356
2357 static int gpmc_probe_dt(struct platform_device *pdev)
2358 {
2359         int ret;
2360         const struct of_device_id *of_id =
2361                 of_match_device(gpmc_dt_ids, &pdev->dev);
2362
2363         if (!of_id)
2364                 return 0;
2365
2366         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2367                                    &gpmc_cs_num);
2368         if (ret < 0) {
2369                 pr_err("%s: number of chip-selects not defined\n", __func__);
2370                 return ret;
2371         } else if (gpmc_cs_num < 1) {
2372                 pr_err("%s: all chip-selects are disabled\n", __func__);
2373                 return -EINVAL;
2374         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2375                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2376                                          __func__, GPMC_CS_NUM);
2377                 return -EINVAL;
2378         }
2379
2380         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2381                                    &gpmc_nr_waitpins);
2382         if (ret < 0) {
2383                 pr_err("%s: number of wait pins not found!\n", __func__);
2384                 return ret;
2385         }
2386
2387         return 0;
2388 }
2389
2390 static void gpmc_probe_dt_children(struct platform_device *pdev)
2391 {
2392         int ret;
2393         struct device_node *child;
2394
2395         for_each_available_child_of_node(pdev->dev.of_node, child) {
2396                 ret = gpmc_probe_generic_child(pdev, child);
2397                 if (ret) {
2398                         dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2399                                 child, ret);
2400                 }
2401         }
2402 }
2403 #else
2404 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2405 {
2406         memset(p, 0, sizeof(*p));
2407 }
2408 static int gpmc_probe_dt(struct platform_device *pdev)
2409 {
2410         return 0;
2411 }
2412
2413 static void gpmc_probe_dt_children(struct platform_device *pdev)
2414 {
2415 }
2416 #endif /* CONFIG_OF */
2417
2418 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2419 {
2420         return 1;       /* we're input only */
2421 }
2422
2423 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2424                                      unsigned int offset)
2425 {
2426         return 0;       /* we're input only */
2427 }
2428
2429 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2430                                       unsigned int offset, int value)
2431 {
2432         return -EINVAL; /* we're input only */
2433 }
2434
2435 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2436                           int value)
2437 {
2438 }
2439
2440 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2441 {
2442         u32 reg;
2443
2444         offset += 8;
2445
2446         reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2447
2448         return !!reg;
2449 }
2450
2451 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2452 {
2453         int ret;
2454
2455         gpmc->gpio_chip.parent = gpmc->dev;
2456         gpmc->gpio_chip.owner = THIS_MODULE;
2457         gpmc->gpio_chip.label = DEVICE_NAME;
2458         gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2459         gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2460         gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2461         gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2462         gpmc->gpio_chip.set = gpmc_gpio_set;
2463         gpmc->gpio_chip.get = gpmc_gpio_get;
2464         gpmc->gpio_chip.base = -1;
2465
2466         ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2467         if (ret < 0) {
2468                 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2469                 return ret;
2470         }
2471
2472         return 0;
2473 }
2474
2475 static void omap3_gpmc_save_context(struct gpmc_device *gpmc)
2476 {
2477         struct omap3_gpmc_regs *gpmc_context;
2478         int i;
2479
2480         if (!gpmc || !gpmc_base)
2481                 return;
2482
2483         gpmc_context = &gpmc->context;
2484
2485         gpmc_context->sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2486         gpmc_context->irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2487         gpmc_context->timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2488         gpmc_context->config = gpmc_read_reg(GPMC_CONFIG);
2489         gpmc_context->prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2490         gpmc_context->prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2491         gpmc_context->prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2492         for (i = 0; i < gpmc_cs_num; i++) {
2493                 gpmc_context->cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2494                 if (gpmc_context->cs_context[i].is_valid) {
2495                         gpmc_context->cs_context[i].config1 =
2496                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2497                         gpmc_context->cs_context[i].config2 =
2498                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2499                         gpmc_context->cs_context[i].config3 =
2500                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2501                         gpmc_context->cs_context[i].config4 =
2502                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2503                         gpmc_context->cs_context[i].config5 =
2504                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2505                         gpmc_context->cs_context[i].config6 =
2506                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2507                         gpmc_context->cs_context[i].config7 =
2508                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2509                 }
2510         }
2511 }
2512
2513 static void omap3_gpmc_restore_context(struct gpmc_device *gpmc)
2514 {
2515         struct omap3_gpmc_regs *gpmc_context;
2516         int i;
2517
2518         if (!gpmc || !gpmc_base)
2519                 return;
2520
2521         gpmc_context = &gpmc->context;
2522
2523         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context->sysconfig);
2524         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context->irqenable);
2525         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context->timeout_ctrl);
2526         gpmc_write_reg(GPMC_CONFIG, gpmc_context->config);
2527         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context->prefetch_config1);
2528         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context->prefetch_config2);
2529         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context->prefetch_control);
2530         for (i = 0; i < gpmc_cs_num; i++) {
2531                 if (gpmc_context->cs_context[i].is_valid) {
2532                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2533                                           gpmc_context->cs_context[i].config1);
2534                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2535                                           gpmc_context->cs_context[i].config2);
2536                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2537                                           gpmc_context->cs_context[i].config3);
2538                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2539                                           gpmc_context->cs_context[i].config4);
2540                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2541                                           gpmc_context->cs_context[i].config5);
2542                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2543                                           gpmc_context->cs_context[i].config6);
2544                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2545                                           gpmc_context->cs_context[i].config7);
2546                 } else {
2547                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 0);
2548                 }
2549         }
2550 }
2551
2552 static int omap_gpmc_context_notifier(struct notifier_block *nb,
2553                                       unsigned long cmd, void *v)
2554 {
2555         struct gpmc_device *gpmc;
2556
2557         gpmc = container_of(nb, struct gpmc_device, nb);
2558         if (gpmc->is_suspended || pm_runtime_suspended(gpmc->dev))
2559                 return NOTIFY_OK;
2560
2561         switch (cmd) {
2562         case CPU_CLUSTER_PM_ENTER:
2563                 omap3_gpmc_save_context(gpmc);
2564                 break;
2565         case CPU_CLUSTER_PM_ENTER_FAILED:       /* No need to restore context */
2566                 break;
2567         case CPU_CLUSTER_PM_EXIT:
2568                 omap3_gpmc_restore_context(gpmc);
2569                 break;
2570         }
2571
2572         return NOTIFY_OK;
2573 }
2574
2575 static int gpmc_probe(struct platform_device *pdev)
2576 {
2577         int rc, i;
2578         u32 l;
2579         struct resource *res;
2580         struct gpmc_device *gpmc;
2581
2582         gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2583         if (!gpmc)
2584                 return -ENOMEM;
2585
2586         gpmc->dev = &pdev->dev;
2587         platform_set_drvdata(pdev, gpmc);
2588
2589         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
2590         if (!res) {
2591                 /* legacy DT */
2592                 gpmc_base = devm_platform_ioremap_resource(pdev, 0);
2593                 if (IS_ERR(gpmc_base))
2594                         return PTR_ERR(gpmc_base);
2595         } else {
2596                 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2597                 if (IS_ERR(gpmc_base))
2598                         return PTR_ERR(gpmc_base);
2599
2600                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "data");
2601                 if (!res) {
2602                         dev_err(&pdev->dev, "couldn't get data reg resource\n");
2603                         return -ENOENT;
2604                 }
2605
2606                 gpmc->data = res;
2607         }
2608
2609         gpmc->irq = platform_get_irq(pdev, 0);
2610         if (gpmc->irq < 0)
2611                 return gpmc->irq;
2612
2613         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2614         if (IS_ERR(gpmc_l3_clk)) {
2615                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2616                 return PTR_ERR(gpmc_l3_clk);
2617         }
2618
2619         if (!clk_get_rate(gpmc_l3_clk)) {
2620                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2621                 return -EINVAL;
2622         }
2623
2624         if (pdev->dev.of_node) {
2625                 rc = gpmc_probe_dt(pdev);
2626                 if (rc)
2627                         return rc;
2628         } else {
2629                 gpmc_cs_num = GPMC_CS_NUM;
2630                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2631         }
2632
2633         gpmc->waitpins = devm_kzalloc(&pdev->dev,
2634                                       gpmc_nr_waitpins * sizeof(struct gpmc_waitpin),
2635                                       GFP_KERNEL);
2636         if (!gpmc->waitpins)
2637                 return -ENOMEM;
2638
2639         for (i = 0; i < gpmc_nr_waitpins; i++)
2640                 gpmc->waitpins[i].pin = GPMC_WAITPIN_INVALID;
2641
2642         pm_runtime_enable(&pdev->dev);
2643         pm_runtime_get_sync(&pdev->dev);
2644
2645         l = gpmc_read_reg(GPMC_REVISION);
2646
2647         /*
2648          * FIXME: Once device-tree migration is complete the below flags
2649          * should be populated based upon the device-tree compatible
2650          * string. For now just use the IP revision. OMAP3+ devices have
2651          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2652          * devices support the addr-addr-data multiplex protocol.
2653          *
2654          * GPMC IP revisions:
2655          * - OMAP24xx                   = 2.0
2656          * - OMAP3xxx                   = 5.0
2657          * - OMAP44xx/54xx/AM335x       = 6.0
2658          */
2659         if (GPMC_REVISION_MAJOR(l) > 0x4)
2660                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2661         if (GPMC_REVISION_MAJOR(l) > 0x5)
2662                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2663         dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2664                  GPMC_REVISION_MINOR(l));
2665
2666         gpmc_mem_init(gpmc);
2667         rc = gpmc_gpio_init(gpmc);
2668         if (rc)
2669                 goto gpio_init_failed;
2670
2671         gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2672         rc = gpmc_setup_irq(gpmc);
2673         if (rc) {
2674                 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2675                 goto gpio_init_failed;
2676         }
2677
2678         gpmc_probe_dt_children(pdev);
2679
2680         gpmc->nb.notifier_call = omap_gpmc_context_notifier;
2681         cpu_pm_register_notifier(&gpmc->nb);
2682
2683         return 0;
2684
2685 gpio_init_failed:
2686         gpmc_mem_exit();
2687         pm_runtime_put_sync(&pdev->dev);
2688         pm_runtime_disable(&pdev->dev);
2689
2690         return rc;
2691 }
2692
2693 static int gpmc_remove(struct platform_device *pdev)
2694 {
2695         int i;
2696         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2697
2698         cpu_pm_unregister_notifier(&gpmc->nb);
2699         for (i = 0; i < gpmc_nr_waitpins; i++)
2700                 gpmc_free_waitpin(gpmc, i);
2701         gpmc_free_irq(gpmc);
2702         gpmc_mem_exit();
2703         pm_runtime_put_sync(&pdev->dev);
2704         pm_runtime_disable(&pdev->dev);
2705
2706         return 0;
2707 }
2708
2709 #ifdef CONFIG_PM_SLEEP
2710 static int gpmc_suspend(struct device *dev)
2711 {
2712         struct gpmc_device *gpmc = dev_get_drvdata(dev);
2713
2714         omap3_gpmc_save_context(gpmc);
2715         pm_runtime_put_sync(dev);
2716         gpmc->is_suspended = 1;
2717
2718         return 0;
2719 }
2720
2721 static int gpmc_resume(struct device *dev)
2722 {
2723         struct gpmc_device *gpmc = dev_get_drvdata(dev);
2724
2725         pm_runtime_get_sync(dev);
2726         omap3_gpmc_restore_context(gpmc);
2727         gpmc->is_suspended = 0;
2728
2729         return 0;
2730 }
2731 #endif
2732
2733 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2734
2735 #ifdef CONFIG_OF
2736 static const struct of_device_id gpmc_dt_ids[] = {
2737         { .compatible = "ti,omap2420-gpmc" },
2738         { .compatible = "ti,omap2430-gpmc" },
2739         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
2740         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
2741         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
2742         { .compatible = "ti,am64-gpmc" },
2743         { }
2744 };
2745 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
2746 #endif
2747
2748 static struct platform_driver gpmc_driver = {
2749         .probe          = gpmc_probe,
2750         .remove         = gpmc_remove,
2751         .driver         = {
2752                 .name   = DEVICE_NAME,
2753                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2754                 .pm     = &gpmc_pm_ops,
2755         },
2756 };
2757
2758 module_platform_driver(gpmc_driver);
2759
2760 MODULE_DESCRIPTION("Texas Instruments GPMC driver");
2761 MODULE_LICENSE("GPL");