1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPMC support functions
5 * Copyright (C) 2005-2006 Nokia Corporation
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 #include <linux/irq.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/ioport.h>
18 #include <linux/spinlock.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
22 #include <linux/gpio/machine.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/platform_device.h>
27 #include <linux/of_address.h>
28 #include <linux/of_device.h>
29 #include <linux/of_platform.h>
30 #include <linux/omap-gpmc.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/sizes.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #include <asm/mach-types.h>
38 #define DEVICE_NAME "omap-gpmc"
40 /* GPMC register offsets */
41 #define GPMC_REVISION 0x00
42 #define GPMC_SYSCONFIG 0x10
43 #define GPMC_SYSSTATUS 0x14
44 #define GPMC_IRQSTATUS 0x18
45 #define GPMC_IRQENABLE 0x1c
46 #define GPMC_TIMEOUT_CONTROL 0x40
47 #define GPMC_ERR_ADDRESS 0x44
48 #define GPMC_ERR_TYPE 0x48
49 #define GPMC_CONFIG 0x50
50 #define GPMC_STATUS 0x54
51 #define GPMC_PREFETCH_CONFIG1 0x1e0
52 #define GPMC_PREFETCH_CONFIG2 0x1e4
53 #define GPMC_PREFETCH_CONTROL 0x1ec
54 #define GPMC_PREFETCH_STATUS 0x1f0
55 #define GPMC_ECC_CONFIG 0x1f4
56 #define GPMC_ECC_CONTROL 0x1f8
57 #define GPMC_ECC_SIZE_CONFIG 0x1fc
58 #define GPMC_ECC1_RESULT 0x200
59 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
60 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
61 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
62 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
65 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
67 /* GPMC ECC control settings */
68 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
69 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
70 #define GPMC_ECC_CTRL_ECCREG1 0x001
71 #define GPMC_ECC_CTRL_ECCREG2 0x002
72 #define GPMC_ECC_CTRL_ECCREG3 0x003
73 #define GPMC_ECC_CTRL_ECCREG4 0x004
74 #define GPMC_ECC_CTRL_ECCREG5 0x005
75 #define GPMC_ECC_CTRL_ECCREG6 0x006
76 #define GPMC_ECC_CTRL_ECCREG7 0x007
77 #define GPMC_ECC_CTRL_ECCREG8 0x008
78 #define GPMC_ECC_CTRL_ECCREG9 0x009
80 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
82 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
84 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
85 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
87 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
91 #define GPMC_CS0_OFFSET 0x60
92 #define GPMC_CS_SIZE 0x30
93 #define GPMC_BCH_SIZE 0x10
96 * The first 1MB of GPMC address space is typically mapped to
97 * the internal ROM. Never allocate the first page, to
98 * facilitate bug detection; even if we didn't boot from ROM.
99 * As GPMC minimum partition size is 16MB we can only start from
102 #define GPMC_MEM_START 0x1000000
103 #define GPMC_MEM_END 0x3FFFFFFF
105 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
106 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
108 #define CS_NUM_SHIFT 24
109 #define ENABLE_PREFETCH (0x1 << 7)
110 #define DMA_MPU_MODE 2
112 #define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
113 #define GPMC_REVISION_MINOR(l) ((l) & 0xf)
115 #define GPMC_HAS_WR_ACCESS 0x1
116 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
117 #define GPMC_HAS_MUX_AAD 0x4
119 #define GPMC_NR_WAITPINS 4
121 #define GPMC_CS_CONFIG1 0x00
122 #define GPMC_CS_CONFIG2 0x04
123 #define GPMC_CS_CONFIG3 0x08
124 #define GPMC_CS_CONFIG4 0x0c
125 #define GPMC_CS_CONFIG5 0x10
126 #define GPMC_CS_CONFIG6 0x14
127 #define GPMC_CS_CONFIG7 0x18
128 #define GPMC_CS_NAND_COMMAND 0x1c
129 #define GPMC_CS_NAND_ADDRESS 0x20
130 #define GPMC_CS_NAND_DATA 0x24
132 /* Control Commands */
133 #define GPMC_CONFIG_RDY_BSY 0x00000001
134 #define GPMC_CONFIG_DEV_SIZE 0x00000002
135 #define GPMC_CONFIG_DEV_TYPE 0x00000003
137 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
138 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
139 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
140 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
141 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
142 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
143 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
144 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
145 /** CLKACTIVATIONTIME Max Ticks */
146 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
147 #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
148 /** ATTACHEDDEVICEPAGELENGTH Max Value */
149 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
150 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
151 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
152 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
153 /** WAITMONITORINGTIME Max Ticks */
154 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
155 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
156 #define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
157 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
158 /** DEVICESIZE Max Value */
159 #define GPMC_CONFIG1_DEVICESIZE_MAX 1
160 #define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
161 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
162 #define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
163 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
164 #define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
165 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
166 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
167 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
168 #define GPMC_CONFIG7_CSVALID (1 << 6)
170 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
171 #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
172 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
173 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
174 /* All CONFIG7 bits except reserved bits */
175 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
176 GPMC_CONFIG7_CSVALID_MASK | \
177 GPMC_CONFIG7_MASKADDRESS_MASK)
179 #define GPMC_DEVICETYPE_NOR 0
180 #define GPMC_DEVICETYPE_NAND 2
181 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
182 #define WR_RD_PIN_MONITORING 0x00600000
185 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
186 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
187 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
189 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
191 enum gpmc_clk_domain {
196 struct gpmc_cs_data {
199 #define GPMC_CS_RESERVED (1 << 0)
205 /* Structure to save gpmc cs context */
206 struct gpmc_cs_config {
218 * Structure to save/restore gpmc context
219 * to support core off on OMAP3
221 struct omap3_gpmc_regs {
226 u32 prefetch_config1;
227 u32 prefetch_config2;
228 u32 prefetch_control;
229 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
235 struct irq_chip irq_chip;
236 struct gpio_chip gpio_chip;
240 static struct irq_domain *gpmc_irq_domain;
242 static struct resource gpmc_mem_root;
243 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
244 static DEFINE_SPINLOCK(gpmc_mem_lock);
245 /* Define chip-selects as reserved by default until probe completes */
246 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
247 static unsigned int gpmc_nr_waitpins;
248 static resource_size_t phys_base, mem_size;
249 static unsigned int gpmc_capability;
250 static void __iomem *gpmc_base;
252 static struct clk *gpmc_l3_clk;
254 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
256 static void gpmc_write_reg(int idx, u32 val)
258 writel_relaxed(val, gpmc_base + idx);
261 static u32 gpmc_read_reg(int idx)
263 return readl_relaxed(gpmc_base + idx);
266 void gpmc_cs_write_reg(int cs, int idx, u32 val)
268 void __iomem *reg_addr;
270 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
271 writel_relaxed(val, reg_addr);
274 static u32 gpmc_cs_read_reg(int cs, int idx)
276 void __iomem *reg_addr;
278 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
279 return readl_relaxed(reg_addr);
282 /* TODO: Add support for gpmc_fck to clock framework and use it */
283 static unsigned long gpmc_get_fclk_period(void)
285 unsigned long rate = clk_get_rate(gpmc_l3_clk);
288 rate = 1000000000 / rate; /* In picoseconds */
294 * gpmc_get_clk_period - get period of selected clock domain in ps
295 * @cs: Chip Select Region.
298 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
299 * prior to calling this function with GPMC_CD_CLK.
301 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
303 unsigned long tick_ps = gpmc_get_fclk_period();
309 /* get current clk divider */
310 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
311 div = (l & 0x03) + 1;
312 /* get GPMC_CLK period */
324 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
325 enum gpmc_clk_domain cd)
327 unsigned long tick_ps;
329 /* Calculate in picosecs to yield more exact results */
330 tick_ps = gpmc_get_clk_period(cs, cd);
332 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
335 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
337 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
340 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
342 unsigned long tick_ps;
344 /* Calculate in picosecs to yield more exact results */
345 tick_ps = gpmc_get_fclk_period();
347 return (time_ps + tick_ps - 1) / tick_ps;
350 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
351 enum gpmc_clk_domain cd)
353 return ticks * gpmc_get_clk_period(cs, cd) / 1000;
356 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
358 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
361 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
363 return ticks * gpmc_get_fclk_period();
366 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
368 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
370 return ticks * gpmc_get_fclk_period();
373 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
377 l = gpmc_cs_read_reg(cs, reg);
382 gpmc_cs_write_reg(cs, reg, l);
385 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
387 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
388 GPMC_CONFIG1_TIME_PARA_GRAN,
389 p->time_para_granularity);
390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
391 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
392 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
393 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
394 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
395 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
396 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
397 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
399 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
400 p->cycle2cyclesamecsen);
401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
402 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
403 p->cycle2cyclediffcsen);
406 #ifdef CONFIG_OMAP_GPMC_DEBUG
408 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
409 * @cs: Chip Select Region
410 * @reg: GPMC_CS_CONFIGn register offset.
412 * @end_bit: End Bit. Must be >= @st_bit.
413 * @max: Maximum parameter value (before optional @shift).
414 * If 0, maximum is as high as @st_bit and @end_bit allow.
415 * @name: DTS node name, w/o "gpmc,"
416 * @cd: Clock Domain of timing parameter.
417 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
418 * @raw: Raw Format Option.
419 * raw format: gpmc,name = <value>
420 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
421 * Where x ns -- y ns result in the same tick value.
422 * When @max is exceeded, "invalid" is printed inside comment.
423 * @noval: Parameter values equal to 0 are not printed.
424 * @return: Specified timing parameter (after optional @shift).
427 static int get_gpmc_timing_reg(
428 /* timing specifiers */
429 int cs, int reg, int st_bit, int end_bit, int max,
430 const char *name, const enum gpmc_clk_domain cd,
431 /* value transform */
433 /* format specifiers */
434 bool raw, bool noval)
441 l = gpmc_cs_read_reg(cs, reg);
442 nr_bits = end_bit - st_bit + 1;
443 mask = (1 << nr_bits) - 1;
444 l = (l >> st_bit) & mask;
450 if (noval && (l == 0))
453 /* DTS tick format for timings in ns */
454 unsigned int time_ns;
455 unsigned int time_ns_min = 0;
458 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
459 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
460 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
461 name, time_ns, time_ns_min, time_ns, l,
462 invalid ? "; invalid " : " ");
465 pr_info("gpmc,%s = <%u>;%s\n", name, l,
466 invalid ? " /* invalid */" : "");
472 #define GPMC_PRINT_CONFIG(cs, config) \
473 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
474 gpmc_cs_read_reg(cs, config))
475 #define GPMC_GET_RAW(reg, st, end, field) \
476 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
477 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
478 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
479 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
480 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
481 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
482 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
483 #define GPMC_GET_TICKS(reg, st, end, field) \
484 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
485 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
486 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
487 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
488 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
490 static void gpmc_show_regs(int cs, const char *desc)
492 pr_info("gpmc cs%i %s:\n", cs, desc);
493 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
494 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
495 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
502 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
503 * see commit c9fb809.
505 static void gpmc_cs_show_timings(int cs, const char *desc)
507 gpmc_show_regs(cs, desc);
509 pr_info("gpmc cs%i access configuration:\n", cs);
510 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
511 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
512 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
513 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
514 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
515 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
516 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
517 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
518 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
520 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
521 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
522 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
528 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
530 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
536 pr_info("gpmc cs%i timings configuration:\n", cs);
537 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
538 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
539 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
541 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
542 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
543 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
544 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
545 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
546 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
547 "adv-aad-mux-rd-off-ns");
548 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
549 "adv-aad-mux-wr-off-ns");
552 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
553 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
554 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
555 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
558 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
561 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
562 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
563 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
565 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
567 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
568 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
570 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
571 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
572 "wait-monitoring-ns", GPMC_CD_CLK);
573 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
574 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
575 "clk-activation-ns", GPMC_CD_FCLK);
577 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
578 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
581 static inline void gpmc_cs_show_timings(int cs, const char *desc)
587 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
588 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
589 * prior to calling this function with @cd equal to GPMC_CD_CLK.
591 * @cs: Chip Select Region.
592 * @reg: GPMC_CS_CONFIGn register offset.
594 * @end_bit: End Bit. Must be >= @st_bit.
595 * @max: Maximum parameter value.
596 * If 0, maximum is as high as @st_bit and @end_bit allow.
597 * @time: Timing parameter in ns.
598 * @cd: Timing parameter clock domain.
599 * @name: Timing parameter name.
600 * @return: 0 on success, -1 on error.
602 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
603 int time, enum gpmc_clk_domain cd, const char *name)
606 int ticks, mask, nr_bits;
611 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
612 nr_bits = end_bit - st_bit + 1;
613 mask = (1 << nr_bits) - 1;
619 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
620 __func__, cs, name, time, ticks, max);
625 l = gpmc_cs_read_reg(cs, reg);
626 #ifdef CONFIG_OMAP_GPMC_DEBUG
627 pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
628 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
629 (l >> st_bit) & mask, time);
631 l &= ~(mask << st_bit);
632 l |= ticks << st_bit;
633 gpmc_cs_write_reg(cs, reg, l);
638 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \
639 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
640 t->field, (cd), #field) < 0) \
643 #define GPMC_SET_ONE(reg, st, end, field) \
644 GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
647 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
648 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
649 * read --> don't sample bus too early
650 * write --> data is longer on bus
653 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
654 * / waitmonitoring_ticks)
655 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
658 * @wait_monitoring: WAITMONITORINGTIME in ns.
659 * @return: -1 on failure to scale, else proper divider > 0.
661 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
663 int div = gpmc_ns_to_ticks(wait_monitoring);
665 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
666 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
677 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
678 * @sync_clk: GPMC_CLK period in ps.
679 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
682 int gpmc_calc_divider(unsigned int sync_clk)
684 int div = gpmc_ps_to_ticks(sync_clk);
695 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
696 * @cs: Chip Select Region.
697 * @t: GPMC timing parameters.
698 * @s: GPMC timing settings.
699 * @return: 0 on success, -1 on error.
701 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
702 const struct gpmc_settings *s)
707 div = gpmc_calc_divider(t->sync_clk);
712 * See if we need to change the divider for waitmonitoringtime.
714 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
715 * pure asynchronous accesses, i.e. both read and write asynchronous.
716 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
717 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
719 * This statement must not change div to scale async WAITMONITORINGTIME
720 * to protect mixed synchronous and asynchronous accesses.
722 * We raise an error later if WAITMONITORINGTIME does not fit.
724 if (!s->sync_read && !s->sync_write &&
725 (s->wait_on_read || s->wait_on_write)
727 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
729 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
737 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
738 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
739 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
741 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
742 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
743 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
744 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
745 GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on);
746 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
747 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
750 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
751 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
752 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
753 GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on);
754 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
756 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
757 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
759 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
760 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
761 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
763 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
765 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
766 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
768 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
769 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
770 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
771 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
773 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
776 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
778 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
779 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
780 wait_monitoring, GPMC_CD_CLK);
781 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
782 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
783 clk_activation, GPMC_CD_FCLK);
785 #ifdef CONFIG_OMAP_GPMC_DEBUG
786 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
787 cs, (div * gpmc_get_fclk_period()) / 1000, div);
790 gpmc_cs_bool_timings(cs, &t->bool_timings);
791 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
796 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
802 * Ensure that base address is aligned on a
803 * boundary equal to or greater than size.
805 if (base & (size - 1))
808 base >>= GPMC_CHUNK_SHIFT;
809 mask = (1 << GPMC_SECTION_SHIFT) - size;
810 mask >>= GPMC_CHUNK_SHIFT;
811 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
813 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
814 l &= ~GPMC_CONFIG7_MASK;
815 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
816 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
817 l |= GPMC_CONFIG7_CSVALID;
818 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
823 static void gpmc_cs_enable_mem(int cs)
827 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
828 l |= GPMC_CONFIG7_CSVALID;
829 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
832 static void gpmc_cs_disable_mem(int cs)
836 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
837 l &= ~GPMC_CONFIG7_CSVALID;
838 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
841 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
846 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
847 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
848 mask = (l >> 8) & 0x0f;
849 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
852 static int gpmc_cs_mem_enabled(int cs)
856 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
857 return l & GPMC_CONFIG7_CSVALID;
860 static void gpmc_cs_set_reserved(int cs, int reserved)
862 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
864 gpmc->flags |= GPMC_CS_RESERVED;
867 static bool gpmc_cs_reserved(int cs)
869 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
871 return gpmc->flags & GPMC_CS_RESERVED;
874 static void gpmc_cs_set_name(int cs, const char *name)
876 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
881 static const char *gpmc_cs_get_name(int cs)
883 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
888 static unsigned long gpmc_mem_align(unsigned long size)
892 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
893 order = GPMC_CHUNK_SHIFT - 1;
902 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
904 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
905 struct resource *res = &gpmc->mem;
908 size = gpmc_mem_align(size);
909 spin_lock(&gpmc_mem_lock);
911 res->end = base + size - 1;
912 r = request_resource(&gpmc_mem_root, res);
913 spin_unlock(&gpmc_mem_lock);
918 static int gpmc_cs_delete_mem(int cs)
920 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
921 struct resource *res = &gpmc->mem;
924 spin_lock(&gpmc_mem_lock);
925 r = release_resource(res);
928 spin_unlock(&gpmc_mem_lock);
934 * gpmc_cs_remap - remaps a chip-select physical base address
935 * @cs: chip-select to remap
936 * @base: physical base address to re-map chip-select to
938 * Re-maps a chip-select to a new physical base address specified by
939 * "base". Returns 0 on success and appropriate negative error code
942 static int gpmc_cs_remap(int cs, u32 base)
947 if (cs > gpmc_cs_num) {
948 pr_err("%s: requested chip-select is disabled\n", __func__);
953 * Make sure we ignore any device offsets from the GPMC partition
954 * allocated for the chip select and that the new base confirms
955 * to the GPMC 16MB minimum granularity.
957 base &= ~(SZ_16M - 1);
959 gpmc_cs_get_memconf(cs, &old_base, &size);
960 if (base == old_base)
963 ret = gpmc_cs_delete_mem(cs);
967 ret = gpmc_cs_insert_mem(cs, base, size);
971 ret = gpmc_cs_set_memconf(cs, base, size);
976 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
978 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
979 struct resource *res = &gpmc->mem;
982 if (cs > gpmc_cs_num) {
983 pr_err("%s: requested chip-select is disabled\n", __func__);
986 size = gpmc_mem_align(size);
987 if (size > (1 << GPMC_SECTION_SHIFT))
990 spin_lock(&gpmc_mem_lock);
991 if (gpmc_cs_reserved(cs)) {
995 if (gpmc_cs_mem_enabled(cs))
996 r = adjust_resource(res, res->start & ~(size - 1), size);
998 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1003 /* Disable CS while changing base address and size mask */
1004 gpmc_cs_disable_mem(cs);
1006 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1008 release_resource(res);
1013 gpmc_cs_enable_mem(cs);
1015 gpmc_cs_set_reserved(cs, 1);
1017 spin_unlock(&gpmc_mem_lock);
1020 EXPORT_SYMBOL(gpmc_cs_request);
1022 void gpmc_cs_free(int cs)
1024 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1025 struct resource *res = &gpmc->mem;
1027 spin_lock(&gpmc_mem_lock);
1028 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1029 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1031 spin_unlock(&gpmc_mem_lock);
1034 gpmc_cs_disable_mem(cs);
1036 release_resource(res);
1037 gpmc_cs_set_reserved(cs, 0);
1038 spin_unlock(&gpmc_mem_lock);
1040 EXPORT_SYMBOL(gpmc_cs_free);
1043 * gpmc_configure - write request to configure gpmc
1044 * @cmd: command type
1045 * @wval: value to write
1046 * @return status of the operation
1048 int gpmc_configure(int cmd, int wval)
1053 case GPMC_CONFIG_WP:
1054 regval = gpmc_read_reg(GPMC_CONFIG);
1056 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1058 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
1059 gpmc_write_reg(GPMC_CONFIG, regval);
1063 pr_err("%s: command not supported\n", __func__);
1069 EXPORT_SYMBOL(gpmc_configure);
1071 static bool gpmc_nand_writebuffer_empty(void)
1073 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1079 static struct gpmc_nand_ops nand_ops = {
1080 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1084 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1085 * @reg: the GPMC NAND register map exclusive for NAND use.
1086 * @cs: GPMC chip select number on which the NAND sits. The
1087 * register map returned will be specific to this chip select.
1089 * Returns NULL on error e.g. invalid cs.
1091 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1095 if (cs >= gpmc_cs_num)
1098 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1099 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1100 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1101 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1102 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1103 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1104 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1105 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1106 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1107 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1108 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1109 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1110 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1111 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1113 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1114 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1116 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1118 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1120 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1122 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1124 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1126 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1132 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1134 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1135 struct gpmc_settings *s,
1136 int freq, int latency)
1138 struct gpmc_device_timings dev_t;
1139 const int t_cer = 15;
1140 const int t_avdp = 12;
1141 const int t_cez = 20; /* max of t_cez, t_oez */
1142 const int t_wpl = 40;
1143 const int t_wph = 30;
1144 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1148 min_gpmc_clk_period = 9600; /* 104 MHz */
1157 min_gpmc_clk_period = 12000; /* 83 MHz */
1166 min_gpmc_clk_period = 15000; /* 66 MHz */
1175 min_gpmc_clk_period = 18500; /* 54 MHz */
1185 /* Set synchronous read timings */
1186 memset(&dev_t, 0, sizeof(dev_t));
1188 if (!s->sync_write) {
1189 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1190 dev_t.t_wpl = t_wpl * 1000;
1191 dev_t.t_wph = t_wph * 1000;
1192 dev_t.t_aavdh = t_aavdh * 1000;
1194 dev_t.ce_xdelay = true;
1195 dev_t.avd_xdelay = true;
1196 dev_t.oe_xdelay = true;
1197 dev_t.we_xdelay = true;
1198 dev_t.clk = min_gpmc_clk_period;
1199 dev_t.t_bacc = dev_t.clk;
1200 dev_t.t_ces = t_ces * 1000;
1201 dev_t.t_avds = t_avds * 1000;
1202 dev_t.t_avdh = t_avdh * 1000;
1203 dev_t.t_ach = t_ach * 1000;
1204 dev_t.cyc_iaa = (latency + 1);
1205 dev_t.t_cez_r = t_cez * 1000;
1206 dev_t.t_cez_w = dev_t.t_cez_r;
1207 dev_t.cyc_aavdh_oe = 1;
1208 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1210 gpmc_calc_timings(t, s, &dev_t);
1213 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1215 struct gpmc_onenand_info *info)
1218 struct gpmc_timings gpmc_t;
1219 struct gpmc_settings gpmc_s;
1221 gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1223 info->sync_read = gpmc_s.sync_read;
1224 info->sync_write = gpmc_s.sync_write;
1225 info->burst_len = gpmc_s.burst_len;
1227 if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1230 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1232 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1236 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1238 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1240 int gpmc_get_client_irq(unsigned int irq_config)
1242 if (!gpmc_irq_domain) {
1243 pr_warn("%s called before GPMC IRQ domain available\n",
1248 /* we restrict this to NAND IRQs only */
1249 if (irq_config >= GPMC_NR_NAND_IRQS)
1252 return irq_create_mapping(gpmc_irq_domain, irq_config);
1255 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1259 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1260 if (hwirq >= GPMC_NR_NAND_IRQS)
1261 hwirq += 8 - GPMC_NR_NAND_IRQS;
1263 regval = gpmc_read_reg(GPMC_IRQENABLE);
1265 regval |= BIT(hwirq);
1267 regval &= ~BIT(hwirq);
1268 gpmc_write_reg(GPMC_IRQENABLE, regval);
1273 static void gpmc_irq_disable(struct irq_data *p)
1275 gpmc_irq_endis(p->hwirq, false);
1278 static void gpmc_irq_enable(struct irq_data *p)
1280 gpmc_irq_endis(p->hwirq, true);
1283 static void gpmc_irq_mask(struct irq_data *d)
1285 gpmc_irq_endis(d->hwirq, false);
1288 static void gpmc_irq_unmask(struct irq_data *d)
1290 gpmc_irq_endis(d->hwirq, true);
1293 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1297 /* NAND IRQs polarity is not configurable */
1298 if (hwirq < GPMC_NR_NAND_IRQS)
1301 /* WAITPIN starts at BIT 8 */
1302 hwirq += 8 - GPMC_NR_NAND_IRQS;
1304 regval = gpmc_read_reg(GPMC_CONFIG);
1306 regval &= ~BIT(hwirq);
1308 regval |= BIT(hwirq);
1310 gpmc_write_reg(GPMC_CONFIG, regval);
1313 static void gpmc_irq_ack(struct irq_data *d)
1315 unsigned int hwirq = d->hwirq;
1317 /* skip reserved bits */
1318 if (hwirq >= GPMC_NR_NAND_IRQS)
1319 hwirq += 8 - GPMC_NR_NAND_IRQS;
1321 /* Setting bit to 1 clears (or Acks) the interrupt */
1322 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1325 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1327 /* can't set type for NAND IRQs */
1328 if (d->hwirq < GPMC_NR_NAND_IRQS)
1331 /* We can support either rising or falling edge at a time */
1332 if (trigger == IRQ_TYPE_EDGE_FALLING)
1333 gpmc_irq_edge_config(d->hwirq, false);
1334 else if (trigger == IRQ_TYPE_EDGE_RISING)
1335 gpmc_irq_edge_config(d->hwirq, true);
1342 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1345 struct gpmc_device *gpmc = d->host_data;
1347 irq_set_chip_data(virq, gpmc);
1348 if (hw < GPMC_NR_NAND_IRQS) {
1349 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1350 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1353 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1360 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1361 .map = gpmc_irq_map,
1362 .xlate = irq_domain_xlate_twocell,
1365 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1368 u32 regval, regvalx;
1369 struct gpmc_device *gpmc = data;
1371 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1377 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1378 /* skip reserved status bits */
1379 if (hwirq == GPMC_NR_NAND_IRQS)
1380 regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1382 if (regvalx & BIT(hwirq)) {
1383 virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1386 "spurious irq detected hwirq %d, virq %d\n",
1390 generic_handle_irq(virq);
1394 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1399 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1404 /* Disable interrupts */
1405 gpmc_write_reg(GPMC_IRQENABLE, 0);
1407 /* clear interrupts */
1408 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1409 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1411 gpmc->irq_chip.name = "gpmc";
1412 gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1413 gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1414 gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1415 gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1416 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1417 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1419 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1421 &gpmc_irq_domain_ops,
1423 if (!gpmc_irq_domain) {
1424 dev_err(gpmc->dev, "IRQ domain add failed\n");
1428 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1430 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1432 irq_domain_remove(gpmc_irq_domain);
1433 gpmc_irq_domain = NULL;
1439 static int gpmc_free_irq(struct gpmc_device *gpmc)
1443 free_irq(gpmc->irq, gpmc);
1445 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1446 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1448 irq_domain_remove(gpmc_irq_domain);
1449 gpmc_irq_domain = NULL;
1454 static void gpmc_mem_exit(void)
1458 for (cs = 0; cs < gpmc_cs_num; cs++) {
1459 if (!gpmc_cs_mem_enabled(cs))
1461 gpmc_cs_delete_mem(cs);
1465 static void gpmc_mem_init(void)
1469 gpmc_mem_root.start = GPMC_MEM_START;
1470 gpmc_mem_root.end = GPMC_MEM_END;
1472 /* Reserve all regions that has been set up by bootloader */
1473 for (cs = 0; cs < gpmc_cs_num; cs++) {
1476 if (!gpmc_cs_mem_enabled(cs))
1478 gpmc_cs_get_memconf(cs, &base, &size);
1479 if (gpmc_cs_insert_mem(cs, base, size)) {
1480 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1481 __func__, cs, base, base + size);
1482 gpmc_cs_disable_mem(cs);
1487 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1492 div = gpmc_calc_divider(sync_clk);
1493 temp = gpmc_ps_to_ticks(time_ps);
1494 temp = (temp + div - 1) / div;
1495 return gpmc_ticks_to_ps(temp * div);
1498 /* XXX: can the cycles be avoided ? */
1499 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1500 struct gpmc_device_timings *dev_t,
1506 temp = dev_t->t_avdp_r;
1507 /* XXX: mux check required ? */
1509 /* XXX: t_avdp not to be required for sync, only added for tusb
1510 * this indirectly necessitates requirement of t_avdp_r and
1511 * t_avdp_w instead of having a single t_avdp
1513 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1514 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1516 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1519 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1521 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1522 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1523 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1525 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1528 /* XXX: any scope for improvement ?, by combining oe_on
1529 * and clk_activation, need to check whether
1530 * access = clk_activation + round to sync clk ?
1532 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1533 temp += gpmc_t->clk_activation;
1535 temp = max_t(u32, temp, gpmc_t->oe_on +
1536 gpmc_ticks_to_ps(dev_t->cyc_oe));
1537 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1539 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1540 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1543 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1544 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1546 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1547 if (dev_t->t_ce_rdyz)
1548 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1549 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1554 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1555 struct gpmc_device_timings *dev_t,
1561 temp = dev_t->t_avdp_w;
1563 temp = max_t(u32, temp,
1564 gpmc_t->clk_activation + dev_t->t_avdh);
1565 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1567 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1569 /* wr_data_mux_bus */
1570 temp = max_t(u32, dev_t->t_weasu,
1571 gpmc_t->clk_activation + dev_t->t_rdyo);
1572 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1573 * and in that case remember to handle we_on properly
1576 temp = max_t(u32, temp,
1577 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1578 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1579 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1581 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1584 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1585 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1587 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1590 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1591 gpmc_t->wr_access = gpmc_t->access;
1594 temp = gpmc_t->we_on + dev_t->t_wpl;
1595 temp = max_t(u32, temp,
1596 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1597 temp = max_t(u32, temp,
1598 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1599 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1601 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1605 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1606 temp += gpmc_t->wr_access;
1607 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1608 if (dev_t->t_ce_rdyz)
1609 temp = max_t(u32, temp,
1610 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1611 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1616 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1617 struct gpmc_device_timings *dev_t,
1623 temp = dev_t->t_avdp_r;
1625 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1626 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1629 temp = dev_t->t_oeasu;
1631 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
1632 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1635 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1636 gpmc_t->oe_on + dev_t->t_oe);
1637 temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1638 temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
1639 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1641 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1642 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1645 temp = max_t(u32, dev_t->t_rd_cycle,
1646 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1647 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1648 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1653 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1654 struct gpmc_device_timings *dev_t,
1660 temp = dev_t->t_avdp_w;
1662 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1663 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1665 /* wr_data_mux_bus */
1666 temp = dev_t->t_weasu;
1668 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1669 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1670 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1672 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1675 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1676 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1678 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1681 temp = gpmc_t->we_on + dev_t->t_wpl;
1682 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1684 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1688 temp = max_t(u32, dev_t->t_wr_cycle,
1689 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1690 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1695 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1696 struct gpmc_device_timings *dev_t)
1700 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1701 gpmc_get_fclk_period();
1703 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1707 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1708 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1710 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1713 if (dev_t->ce_xdelay)
1714 gpmc_t->bool_timings.cs_extra_delay = true;
1715 if (dev_t->avd_xdelay)
1716 gpmc_t->bool_timings.adv_extra_delay = true;
1717 if (dev_t->oe_xdelay)
1718 gpmc_t->bool_timings.oe_extra_delay = true;
1719 if (dev_t->we_xdelay)
1720 gpmc_t->bool_timings.we_extra_delay = true;
1725 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1726 struct gpmc_device_timings *dev_t,
1732 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1735 temp = dev_t->t_avdasu;
1736 if (dev_t->t_ce_avd)
1737 temp = max_t(u32, temp,
1738 gpmc_t->cs_on + dev_t->t_ce_avd);
1739 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1742 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1748 * TODO: remove this function once all peripherals are confirmed to
1749 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1750 * has to be modified to handle timings in ps instead of ns
1752 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1755 t->cs_rd_off /= 1000;
1756 t->cs_wr_off /= 1000;
1758 t->adv_rd_off /= 1000;
1759 t->adv_wr_off /= 1000;
1764 t->page_burst_access /= 1000;
1766 t->rd_cycle /= 1000;
1767 t->wr_cycle /= 1000;
1768 t->bus_turnaround /= 1000;
1769 t->cycle2cycle_delay /= 1000;
1770 t->wait_monitoring /= 1000;
1771 t->clk_activation /= 1000;
1772 t->wr_access /= 1000;
1773 t->wr_data_mux_bus /= 1000;
1776 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1777 struct gpmc_settings *gpmc_s,
1778 struct gpmc_device_timings *dev_t)
1780 bool mux = false, sync = false;
1783 mux = gpmc_s->mux_add_data ? true : false;
1784 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1787 memset(gpmc_t, 0, sizeof(*gpmc_t));
1789 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1791 if (gpmc_s && gpmc_s->sync_read)
1792 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1794 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1796 if (gpmc_s && gpmc_s->sync_write)
1797 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1799 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1801 /* TODO: remove, see function definition */
1802 gpmc_convert_ps_to_ns(gpmc_t);
1808 * gpmc_cs_program_settings - programs non-timing related settings
1809 * @cs: GPMC chip-select to program
1810 * @p: pointer to GPMC settings structure
1812 * Programs non-timing related settings for a GPMC chip-select, such as
1813 * bus-width, burst configuration, etc. Function should be called once
1814 * for each chip-select that is being used and must be called before
1815 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1816 * register will be initialised to zero by this function. Returns 0 on
1817 * success and appropriate negative error code on failure.
1819 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1823 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1824 pr_err("%s: invalid width %d!", __func__, p->device_width);
1828 /* Address-data multiplexing not supported for NAND devices */
1829 if (p->device_nand && p->mux_add_data) {
1830 pr_err("%s: invalid configuration!\n", __func__);
1834 if ((p->mux_add_data > GPMC_MUX_AD) ||
1835 ((p->mux_add_data == GPMC_MUX_AAD) &&
1836 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1837 pr_err("%s: invalid multiplex configuration!\n", __func__);
1841 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1842 if (p->burst_read || p->burst_write) {
1843 switch (p->burst_len) {
1849 pr_err("%s: invalid page/burst-length (%d)\n",
1850 __func__, p->burst_len);
1855 if (p->wait_pin > gpmc_nr_waitpins) {
1856 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1860 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1863 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1865 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1866 if (p->wait_on_read)
1867 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1868 if (p->wait_on_write)
1869 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1870 if (p->wait_on_read || p->wait_on_write)
1871 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1873 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1874 if (p->mux_add_data)
1875 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1877 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1879 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1880 if (p->burst_read || p->burst_write) {
1881 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1882 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1885 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1891 static const struct of_device_id gpmc_dt_ids[] = {
1892 { .compatible = "ti,omap2420-gpmc" },
1893 { .compatible = "ti,omap2430-gpmc" },
1894 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1895 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1896 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1901 * gpmc_read_settings_dt - read gpmc settings from device-tree
1902 * @np: pointer to device-tree node for a gpmc child device
1903 * @p: pointer to gpmc settings structure
1905 * Reads the GPMC settings for a GPMC child device from device-tree and
1906 * stores them in the GPMC settings structure passed. The GPMC settings
1907 * structure is initialised to zero by this function and so any
1908 * previously stored settings will be cleared.
1910 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1912 memset(p, 0, sizeof(struct gpmc_settings));
1914 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1915 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1916 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1917 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1919 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1920 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1921 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1922 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1923 if (!p->burst_read && !p->burst_write)
1924 pr_warn("%s: page/burst-length set but not used!\n",
1928 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1929 p->wait_on_read = of_property_read_bool(np,
1930 "gpmc,wait-on-read");
1931 p->wait_on_write = of_property_read_bool(np,
1932 "gpmc,wait-on-write");
1933 if (!p->wait_on_read && !p->wait_on_write)
1934 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1939 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1940 struct gpmc_timings *gpmc_t)
1942 struct gpmc_bool_timings *p;
1947 memset(gpmc_t, 0, sizeof(*gpmc_t));
1949 /* minimum clock period for syncronous mode */
1950 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1952 /* chip select timtings */
1953 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1954 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1955 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1957 /* ADV signal timings */
1958 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1959 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1960 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1961 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1962 &gpmc_t->adv_aad_mux_on);
1963 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1964 &gpmc_t->adv_aad_mux_rd_off);
1965 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1966 &gpmc_t->adv_aad_mux_wr_off);
1968 /* WE signal timings */
1969 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1970 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1972 /* OE signal timings */
1973 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1974 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1975 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1976 &gpmc_t->oe_aad_mux_on);
1977 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1978 &gpmc_t->oe_aad_mux_off);
1980 /* access and cycle timings */
1981 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1982 &gpmc_t->page_burst_access);
1983 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1984 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1985 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1986 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1987 &gpmc_t->bus_turnaround);
1988 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1989 &gpmc_t->cycle2cycle_delay);
1990 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1991 &gpmc_t->wait_monitoring);
1992 of_property_read_u32(np, "gpmc,clk-activation-ns",
1993 &gpmc_t->clk_activation);
1995 /* only applicable to OMAP3+ */
1996 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1997 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1998 &gpmc_t->wr_data_mux_bus);
2000 /* bool timing parameters */
2001 p = &gpmc_t->bool_timings;
2003 p->cycle2cyclediffcsen =
2004 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2005 p->cycle2cyclesamecsen =
2006 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2007 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2008 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2009 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2010 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2011 p->time_para_granularity =
2012 of_property_read_bool(np, "gpmc,time-para-granularity");
2016 * gpmc_probe_generic_child - configures the gpmc for a child device
2017 * @pdev: pointer to gpmc platform device
2018 * @child: pointer to device-tree node for child device
2020 * Allocates and configures a GPMC chip-select for a child device.
2021 * Returns 0 on success and appropriate negative error code on failure.
2023 static int gpmc_probe_generic_child(struct platform_device *pdev,
2024 struct device_node *child)
2026 struct gpmc_settings gpmc_s;
2027 struct gpmc_timings gpmc_t;
2028 struct resource res;
2033 struct gpio_desc *waitpin_desc = NULL;
2034 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2036 if (of_property_read_u32(child, "reg", &cs) < 0) {
2037 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2042 if (of_address_to_resource(child, 0, &res) < 0) {
2043 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2049 * Check if we have multiple instances of the same device
2050 * on a single chip select. If so, use the already initialized
2053 name = gpmc_cs_get_name(cs);
2054 if (name && of_node_name_eq(child, name))
2057 ret = gpmc_cs_request(cs, resource_size(&res), &base);
2059 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2062 gpmc_cs_set_name(cs, child->full_name);
2064 gpmc_read_settings_dt(child, &gpmc_s);
2065 gpmc_read_timings_dt(child, &gpmc_t);
2068 * For some GPMC devices we still need to rely on the bootloader
2069 * timings because the devices can be connected via FPGA.
2070 * REVISIT: Add timing support from slls644g.pdf.
2072 if (!gpmc_t.cs_rd_off) {
2073 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2075 gpmc_cs_show_timings(cs,
2076 "please add GPMC bootloader timings to .dts");
2080 /* CS must be disabled while making changes to gpmc configuration */
2081 gpmc_cs_disable_mem(cs);
2084 * FIXME: gpmc_cs_request() will map the CS to an arbitrary
2085 * location in the gpmc address space. When booting with
2086 * device-tree we want the NOR flash to be mapped to the
2087 * location specified in the device-tree blob. So remap the
2088 * CS to this location. Once DT migration is complete should
2089 * just make gpmc_cs_request() map a specific address.
2091 ret = gpmc_cs_remap(cs, res.start);
2093 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2095 if (res.start < GPMC_MEM_START) {
2096 dev_info(&pdev->dev,
2097 "GPMC CS %d start cannot be lesser than 0x%x\n",
2098 cs, GPMC_MEM_START);
2099 } else if (res.end > GPMC_MEM_END) {
2100 dev_info(&pdev->dev,
2101 "GPMC CS %d end cannot be greater than 0x%x\n",
2107 if (of_node_name_eq(child, "nand")) {
2108 /* Warn about older DT blobs with no compatible property */
2109 if (!of_property_read_bool(child, "compatible")) {
2110 dev_warn(&pdev->dev,
2111 "Incompatible NAND node: missing compatible");
2117 if (of_node_name_eq(child, "onenand")) {
2118 /* Warn about older DT blobs with no compatible property */
2119 if (!of_property_read_bool(child, "compatible")) {
2120 dev_warn(&pdev->dev,
2121 "Incompatible OneNAND node: missing compatible");
2127 if (of_device_is_compatible(child, "ti,omap2-nand")) {
2128 /* NAND specific setup */
2130 of_property_read_u32(child, "nand-bus-width", &val);
2133 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2136 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2139 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2145 /* disable write protect */
2146 gpmc_configure(GPMC_CONFIG_WP, 0);
2147 gpmc_s.device_nand = true;
2149 ret = of_property_read_u32(child, "bank-width",
2150 &gpmc_s.device_width);
2151 if (ret < 0 && !gpmc_s.device_width) {
2153 "%pOF has no 'gpmc,device-width' property\n",
2159 /* Reserve wait pin if it is required and valid */
2160 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2161 unsigned int wait_pin = gpmc_s.wait_pin;
2163 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2164 wait_pin, "WAITPIN",
2167 if (IS_ERR(waitpin_desc)) {
2168 dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2169 ret = PTR_ERR(waitpin_desc);
2174 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2176 ret = gpmc_cs_program_settings(cs, &gpmc_s);
2180 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2182 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2187 /* Clear limited address i.e. enable A26-A11 */
2188 val = gpmc_read_reg(GPMC_CONFIG);
2189 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2190 gpmc_write_reg(GPMC_CONFIG, val);
2192 /* Enable CS region */
2193 gpmc_cs_enable_mem(cs);
2197 /* create platform device, NULL on error or when disabled */
2198 if (!of_platform_device_create(child, NULL, &pdev->dev))
2199 goto err_child_fail;
2201 /* is child a common bus? */
2202 if (of_match_node(of_default_bus_match_table, child))
2203 /* create children and other common bus children */
2204 if (of_platform_default_populate(child, NULL, &pdev->dev))
2205 goto err_child_fail;
2211 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
2215 gpiochip_free_own_desc(waitpin_desc);
2222 static int gpmc_probe_dt(struct platform_device *pdev)
2225 const struct of_device_id *of_id =
2226 of_match_device(gpmc_dt_ids, &pdev->dev);
2231 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2234 pr_err("%s: number of chip-selects not defined\n", __func__);
2236 } else if (gpmc_cs_num < 1) {
2237 pr_err("%s: all chip-selects are disabled\n", __func__);
2239 } else if (gpmc_cs_num > GPMC_CS_NUM) {
2240 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2241 __func__, GPMC_CS_NUM);
2245 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2248 pr_err("%s: number of wait pins not found!\n", __func__);
2255 static void gpmc_probe_dt_children(struct platform_device *pdev)
2258 struct device_node *child;
2260 for_each_available_child_of_node(pdev->dev.of_node, child) {
2261 ret = gpmc_probe_generic_child(pdev, child);
2263 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2269 static int gpmc_probe_dt(struct platform_device *pdev)
2274 static void gpmc_probe_dt_children(struct platform_device *pdev)
2277 #endif /* CONFIG_OF */
2279 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2281 return 1; /* we're input only */
2284 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2285 unsigned int offset)
2287 return 0; /* we're input only */
2290 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2291 unsigned int offset, int value)
2293 return -EINVAL; /* we're input only */
2296 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2301 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2307 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2312 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2316 gpmc->gpio_chip.parent = gpmc->dev;
2317 gpmc->gpio_chip.owner = THIS_MODULE;
2318 gpmc->gpio_chip.label = DEVICE_NAME;
2319 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2320 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2321 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2322 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2323 gpmc->gpio_chip.set = gpmc_gpio_set;
2324 gpmc->gpio_chip.get = gpmc_gpio_get;
2325 gpmc->gpio_chip.base = -1;
2327 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2329 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2336 static int gpmc_probe(struct platform_device *pdev)
2340 struct resource *res;
2341 struct gpmc_device *gpmc;
2343 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2347 gpmc->dev = &pdev->dev;
2348 platform_set_drvdata(pdev, gpmc);
2350 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2354 phys_base = res->start;
2355 mem_size = resource_size(res);
2357 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2358 if (IS_ERR(gpmc_base))
2359 return PTR_ERR(gpmc_base);
2361 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2363 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2367 gpmc->irq = res->start;
2369 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2370 if (IS_ERR(gpmc_l3_clk)) {
2371 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2372 return PTR_ERR(gpmc_l3_clk);
2375 if (!clk_get_rate(gpmc_l3_clk)) {
2376 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2380 if (pdev->dev.of_node) {
2381 rc = gpmc_probe_dt(pdev);
2385 gpmc_cs_num = GPMC_CS_NUM;
2386 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2389 pm_runtime_enable(&pdev->dev);
2390 pm_runtime_get_sync(&pdev->dev);
2392 l = gpmc_read_reg(GPMC_REVISION);
2395 * FIXME: Once device-tree migration is complete the below flags
2396 * should be populated based upon the device-tree compatible
2397 * string. For now just use the IP revision. OMAP3+ devices have
2398 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2399 * devices support the addr-addr-data multiplex protocol.
2401 * GPMC IP revisions:
2404 * - OMAP44xx/54xx/AM335x = 6.0
2406 if (GPMC_REVISION_MAJOR(l) > 0x4)
2407 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2408 if (GPMC_REVISION_MAJOR(l) > 0x5)
2409 gpmc_capability |= GPMC_HAS_MUX_AAD;
2410 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2411 GPMC_REVISION_MINOR(l));
2414 rc = gpmc_gpio_init(gpmc);
2416 goto gpio_init_failed;
2418 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2419 rc = gpmc_setup_irq(gpmc);
2421 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2422 goto gpio_init_failed;
2425 gpmc_probe_dt_children(pdev);
2431 pm_runtime_put_sync(&pdev->dev);
2432 pm_runtime_disable(&pdev->dev);
2437 static int gpmc_remove(struct platform_device *pdev)
2439 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2441 gpmc_free_irq(gpmc);
2443 pm_runtime_put_sync(&pdev->dev);
2444 pm_runtime_disable(&pdev->dev);
2449 #ifdef CONFIG_PM_SLEEP
2450 static int gpmc_suspend(struct device *dev)
2452 omap3_gpmc_save_context();
2453 pm_runtime_put_sync(dev);
2457 static int gpmc_resume(struct device *dev)
2459 pm_runtime_get_sync(dev);
2460 omap3_gpmc_restore_context();
2465 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2467 static struct platform_driver gpmc_driver = {
2468 .probe = gpmc_probe,
2469 .remove = gpmc_remove,
2471 .name = DEVICE_NAME,
2472 .of_match_table = of_match_ptr(gpmc_dt_ids),
2477 static __init int gpmc_init(void)
2479 return platform_driver_register(&gpmc_driver);
2481 postcore_initcall(gpmc_init);
2483 static struct omap3_gpmc_regs gpmc_context;
2485 void omap3_gpmc_save_context(void)
2492 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2493 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2494 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2495 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2496 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2497 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2498 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2499 for (i = 0; i < gpmc_cs_num; i++) {
2500 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2501 if (gpmc_context.cs_context[i].is_valid) {
2502 gpmc_context.cs_context[i].config1 =
2503 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2504 gpmc_context.cs_context[i].config2 =
2505 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2506 gpmc_context.cs_context[i].config3 =
2507 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2508 gpmc_context.cs_context[i].config4 =
2509 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2510 gpmc_context.cs_context[i].config5 =
2511 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2512 gpmc_context.cs_context[i].config6 =
2513 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2514 gpmc_context.cs_context[i].config7 =
2515 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2520 void omap3_gpmc_restore_context(void)
2527 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2528 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2529 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2530 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2531 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2532 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2533 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2534 for (i = 0; i < gpmc_cs_num; i++) {
2535 if (gpmc_context.cs_context[i].is_valid) {
2536 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2537 gpmc_context.cs_context[i].config1);
2538 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2539 gpmc_context.cs_context[i].config2);
2540 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2541 gpmc_context.cs_context[i].config3);
2542 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2543 gpmc_context.cs_context[i].config4);
2544 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2545 gpmc_context.cs_context[i].config5);
2546 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2547 gpmc_context.cs_context[i].config6);
2548 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2549 gpmc_context.cs_context[i].config7);