1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
7 #include <linux/component.h>
8 #include <linux/device.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <soc/mediatek/smi.h>
18 #include <dt-bindings/memory/mt2701-larb-port.h>
19 #include <dt-bindings/memory/mtk-memory-port.h>
22 #define SMI_L1LEN 0x100
24 #define SMI_BUS_SEL 0x220
25 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
26 /* All are MMU0 defaultly. Only specialize mmu1 here. */
27 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
29 #define SMI_M4U_TH 0x234
30 #define SMI_FIFO_TH1 0x238
31 #define SMI_FIFO_TH2 0x23c
33 #define SMI_DUMMY 0x444
36 #define SMI_LARB_SLP_CON 0xc
37 #define SLP_PROT_EN BIT(0)
38 #define SLP_PROT_RDY BIT(16)
40 #define SMI_LARB_CMD_THRT_CON 0x24
41 #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4)
42 #define SMI_LARB_THRT_RD_NU_LMT (5 << 4)
44 #define SMI_LARB_SW_FLAG 0x40
45 #define SMI_LARB_SW_FLAG_1 0x1
47 #define SMI_LARB_OSTDL_PORT 0x200
48 #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2))
50 /* Below are about mmu enable registers, they are different in SoCs */
52 #define REG_SMI_SECUR_CON_BASE 0x5c0
54 /* every register control 8 port, register offset 0x4 */
55 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
56 #define REG_SMI_SECUR_CON_ADDR(id) \
57 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
60 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
61 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
64 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
65 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
66 /* mt2701 domain should be set to 3 */
67 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
71 #define MT8167_SMI_LARB_MMU_EN 0xfc0
74 #define MT8173_SMI_LARB_MMU_EN 0xf00
77 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
78 #define F_MMU_EN BIT(0)
79 #define BANK_SEL(id) ({ \
80 u32 _id = (id) & 0x3; \
81 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
84 #define SMI_COMMON_INIT_REGS_NR 6
85 #define SMI_LARB_PORT_NR_MAX 32
87 #define MTK_SMI_FLAG_THRT_UPDATE BIT(0)
88 #define MTK_SMI_FLAG_SW_FLAG BIT(1)
89 #define MTK_SMI_FLAG_SLEEP_CTL BIT(2)
90 #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x)))
92 struct mtk_smi_reg_pair {
99 MTK_SMI_GEN2, /* gen2 smi common */
100 MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */
103 /* larbs: Require apb/smi clocks while gals is optional. */
104 static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"};
105 #define MTK_SMI_LARB_REQ_CLK_NR 2
106 #define MTK_SMI_LARB_OPT_CLK_NR 1
109 * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required.
110 * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required.
112 static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"};
113 #define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks)
114 #define MTK_SMI_COM_REQ_CLK_NR 2
115 #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX
116 #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3
118 struct mtk_smi_common_plat {
119 enum mtk_smi_type type;
121 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
123 const struct mtk_smi_reg_pair *init;
126 struct mtk_smi_larb_gen {
127 int port_in_larb[MTK_LARB_NR_MAX + 1];
128 void (*config_port)(struct device *dev);
129 unsigned int larb_direct_to_common_mask;
130 unsigned int flags_general;
131 const u8 (*ostd)[SMI_LARB_PORT_NR_MAX];
136 unsigned int clk_num;
137 struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX];
138 struct clk *clk_async; /*only needed by mt2701*/
140 void __iomem *smi_ao_base; /* only for gen1 */
141 void __iomem *base; /* only for gen2 */
143 struct device *smi_common_dev; /* for sub common */
144 const struct mtk_smi_common_plat *plat;
147 struct mtk_smi_larb { /* larb: local arbiter */
150 struct device *smi_common_dev; /* common or sub-common dev */
151 const struct mtk_smi_larb_gen *larb_gen;
158 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
160 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
161 struct mtk_smi_larb_iommu *larb_mmu = data;
164 for (i = 0; i < MTK_LARB_NR_MAX; i++) {
165 if (dev == larb_mmu[i].dev) {
167 larb->mmu = &larb_mmu[i].mmu;
168 larb->bank = larb_mmu[i].bank;
176 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
178 /* Do nothing as the iommu is always enabled. */
181 static const struct component_ops mtk_smi_larb_component_ops = {
182 .bind = mtk_smi_larb_bind,
183 .unbind = mtk_smi_larb_unbind,
186 static void mtk_smi_larb_config_port_gen1(struct device *dev)
188 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
189 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
190 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
191 int i, m4u_port_id, larb_port_num;
192 u32 sec_con_val, reg_val;
194 m4u_port_id = larb_gen->port_in_larb[larb->larbid];
195 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
196 - larb_gen->port_in_larb[larb->larbid];
198 for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
199 if (*larb->mmu & BIT(i)) {
200 /* bit[port + 3] controls the virtual or physical */
201 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
203 /* do not need to enable m4u for this port */
206 reg_val = readl(common->smi_ao_base
207 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
208 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
209 reg_val |= sec_con_val;
210 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
213 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
217 static void mtk_smi_larb_config_port_mt8167(struct device *dev)
219 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
221 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
224 static void mtk_smi_larb_config_port_mt8173(struct device *dev)
226 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
228 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
231 static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
233 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
234 u32 reg, flags_general = larb->larb_gen->flags_general;
235 const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL;
238 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
241 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) {
242 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON);
243 reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK;
244 reg |= SMI_LARB_THRT_RD_NU_LMT;
245 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON);
248 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG))
249 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);
251 for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)
252 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));
254 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
255 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
257 reg |= BANK_SEL(larb->bank[i]);
258 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
262 static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {
263 [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */
264 [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */
265 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */
266 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
267 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,},
268 [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,},
269 [6] = {0x06, 0x01, 0x06, 0x0a,},
270 [7] = {0x0c, 0x0c, 0x12,},
271 [8] = {0x0c, 0x0c, 0x12,},
272 [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a,
273 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,},
274 [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10,
275 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d,
276 0x0d, 0x06, 0x10, 0x10,},
277 [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,},
278 [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,},
279 [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,},
280 [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01,
281 0x01, 0x02, 0x02, 0x08, 0x02,},
283 [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
284 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,},
285 [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
286 [18] = {0x12, 0x06, 0x12, 0x06,},
287 [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
288 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
289 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
290 [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
291 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
292 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
293 [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
294 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
295 [23] = {0x18, 0x01,},
296 [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01,
298 [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
300 [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
302 [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
304 [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
307 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
309 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
310 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
312 .config_port = mtk_smi_larb_config_port_gen1,
315 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
316 .config_port = mtk_smi_larb_config_port_gen2_general,
317 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
320 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
321 .config_port = mtk_smi_larb_config_port_gen2_general,
322 .larb_direct_to_common_mask =
323 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
324 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
327 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
328 /* mt8167 do not need the port in larb */
329 .config_port = mtk_smi_larb_config_port_mt8167,
332 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
333 /* mt8173 do not need the port in larb */
334 .config_port = mtk_smi_larb_config_port_mt8173,
337 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
338 .config_port = mtk_smi_larb_config_port_gen2_general,
339 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
340 /* IPU0 | IPU1 | CCU */
343 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
344 .config_port = mtk_smi_larb_config_port_gen2_general,
345 .flags_general = MTK_SMI_FLAG_SLEEP_CTL,
348 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
349 .config_port = mtk_smi_larb_config_port_gen2_general,
352 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = {
353 .config_port = mtk_smi_larb_config_port_gen2_general,
354 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
355 MTK_SMI_FLAG_SLEEP_CTL,
356 .ostd = mtk_smi_larb_mt8195_ostd,
359 static const struct of_device_id mtk_smi_larb_of_ids[] = {
360 {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
361 {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
362 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779},
363 {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167},
364 {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
365 {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
366 {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186},
367 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
368 {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
372 static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb)
377 writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON);
378 ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON,
379 tmp, !!(tmp & SLP_PROT_RDY), 10, 1000);
381 /* TODO: Reset this larb if it fails here. */
382 dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp);
387 static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb)
389 writel_relaxed(0, larb->base + SMI_LARB_SLP_CON);
392 static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev)
394 struct platform_device *smi_com_pdev;
395 struct device_node *smi_com_node;
396 struct device *smi_com_dev;
397 struct device_link *link;
399 smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
403 smi_com_pdev = of_find_device_by_node(smi_com_node);
404 of_node_put(smi_com_node);
406 /* smi common is the supplier, Make sure it is ready before */
407 if (!platform_get_drvdata(smi_com_pdev))
408 return -EPROBE_DEFER;
409 smi_com_dev = &smi_com_pdev->dev;
410 link = device_link_add(dev, smi_com_dev,
411 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
413 dev_err(dev, "Unable to link smi-common dev\n");
416 *com_dev = smi_com_dev;
418 dev_err(dev, "Failed to get the smi_common device\n");
424 static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi,
425 const char * const clks[],
426 unsigned int clk_nr_required,
427 unsigned int clk_nr_optional)
431 for (i = 0; i < clk_nr_required; i++)
432 smi->clks[i].id = clks[i];
433 ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
437 for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++)
438 smi->clks[i].id = clks[i];
439 ret = devm_clk_bulk_get_optional(dev, clk_nr_optional,
440 smi->clks + clk_nr_required);
441 smi->clk_num = clk_nr_required + clk_nr_optional;
445 static int mtk_smi_larb_probe(struct platform_device *pdev)
447 struct mtk_smi_larb *larb;
448 struct device *dev = &pdev->dev;
451 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
455 larb->larb_gen = of_device_get_match_data(dev);
456 larb->base = devm_platform_ioremap_resource(pdev, 0);
457 if (IS_ERR(larb->base))
458 return PTR_ERR(larb->base);
460 ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks,
461 MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR);
467 ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev);
471 pm_runtime_enable(dev);
472 platform_set_drvdata(pdev, larb);
473 ret = component_add(dev, &mtk_smi_larb_component_ops);
479 pm_runtime_disable(dev);
480 device_link_remove(dev, larb->smi_common_dev);
484 static int mtk_smi_larb_remove(struct platform_device *pdev)
486 struct mtk_smi_larb *larb = platform_get_drvdata(pdev);
488 device_link_remove(&pdev->dev, larb->smi_common_dev);
489 pm_runtime_disable(&pdev->dev);
490 component_del(&pdev->dev, &mtk_smi_larb_component_ops);
494 static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
496 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
497 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
500 ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks);
504 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL))
505 mtk_smi_larb_sleep_ctrl_disable(larb);
507 /* Configure the basic setting for this larb */
508 larb_gen->config_port(dev);
513 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
515 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
518 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) {
519 ret = mtk_smi_larb_sleep_ctrl_enable(larb);
524 clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks);
528 static const struct dev_pm_ops smi_larb_pm_ops = {
529 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
530 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
531 pm_runtime_force_resume)
534 static struct platform_driver mtk_smi_larb_driver = {
535 .probe = mtk_smi_larb_probe,
536 .remove = mtk_smi_larb_remove,
538 .name = "mtk-smi-larb",
539 .of_match_table = mtk_smi_larb_of_ids,
540 .pm = &smi_larb_pm_ops,
544 static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
546 {SMI_M4U_TH, 0xe100e10},
547 {SMI_FIFO_TH1, 0x506090a},
548 {SMI_FIFO_TH2, 0x506090a},
553 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
554 .type = MTK_SMI_GEN1,
557 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
558 .type = MTK_SMI_GEN2,
561 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
562 .type = MTK_SMI_GEN2,
564 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
565 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
568 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
569 .type = MTK_SMI_GEN2,
571 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
575 static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = {
576 .type = MTK_SMI_GEN2,
578 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7),
581 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
582 .type = MTK_SMI_GEN2,
584 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
588 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {
589 .type = MTK_SMI_GEN2,
591 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
593 .init = mtk_smi_common_mt8195_init,
596 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {
597 .type = MTK_SMI_GEN2,
599 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
600 .init = mtk_smi_common_mt8195_init,
603 static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
604 .type = MTK_SMI_GEN2_SUB_COMM,
608 static const struct of_device_id mtk_smi_common_of_ids[] = {
609 {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
610 {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
611 {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779},
612 {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2},
613 {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
614 {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
615 {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
616 {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
617 {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
618 {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
619 {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195},
623 static int mtk_smi_common_probe(struct platform_device *pdev)
625 struct device *dev = &pdev->dev;
626 struct mtk_smi *common;
627 int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR;
629 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
633 common->plat = of_device_get_match_data(dev);
635 if (common->plat->has_gals) {
636 if (common->plat->type == MTK_SMI_GEN2)
637 clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
638 else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
639 clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR;
641 ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0);
646 * for mtk smi gen 1, we need to get the ao(always on) base to config
647 * m4u port, and we need to enable the aync clock for transform the smi
648 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
651 if (common->plat->type == MTK_SMI_GEN1) {
652 common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0);
653 if (IS_ERR(common->smi_ao_base))
654 return PTR_ERR(common->smi_ao_base);
656 common->clk_async = devm_clk_get(dev, "async");
657 if (IS_ERR(common->clk_async))
658 return PTR_ERR(common->clk_async);
660 ret = clk_prepare_enable(common->clk_async);
664 common->base = devm_platform_ioremap_resource(pdev, 0);
665 if (IS_ERR(common->base))
666 return PTR_ERR(common->base);
669 /* link its smi-common if this is smi-sub-common */
670 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
671 ret = mtk_smi_device_link_common(dev, &common->smi_common_dev);
676 pm_runtime_enable(dev);
677 platform_set_drvdata(pdev, common);
681 static int mtk_smi_common_remove(struct platform_device *pdev)
683 struct mtk_smi *common = dev_get_drvdata(&pdev->dev);
685 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
686 device_link_remove(&pdev->dev, common->smi_common_dev);
687 pm_runtime_disable(&pdev->dev);
691 static int __maybe_unused mtk_smi_common_resume(struct device *dev)
693 struct mtk_smi *common = dev_get_drvdata(dev);
694 const struct mtk_smi_reg_pair *init = common->plat->init;
695 u32 bus_sel = common->plat->bus_sel; /* default is 0 */
698 ret = clk_bulk_prepare_enable(common->clk_num, common->clks);
702 if (common->plat->type != MTK_SMI_GEN2)
705 for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)
706 writel_relaxed(init[i].value, common->base + init[i].offset);
708 writel(bus_sel, common->base + SMI_BUS_SEL);
712 static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
714 struct mtk_smi *common = dev_get_drvdata(dev);
716 clk_bulk_disable_unprepare(common->clk_num, common->clks);
720 static const struct dev_pm_ops smi_common_pm_ops = {
721 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
722 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
723 pm_runtime_force_resume)
726 static struct platform_driver mtk_smi_common_driver = {
727 .probe = mtk_smi_common_probe,
728 .remove = mtk_smi_common_remove,
730 .name = "mtk-smi-common",
731 .of_match_table = mtk_smi_common_of_ids,
732 .pm = &smi_common_pm_ops,
736 static struct platform_driver * const smidrivers[] = {
737 &mtk_smi_common_driver,
738 &mtk_smi_larb_driver,
741 static int __init mtk_smi_init(void)
743 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers));
745 module_init(mtk_smi_init);
747 static void __exit mtk_smi_exit(void)
749 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers));
751 module_exit(mtk_smi_exit);
753 MODULE_DESCRIPTION("MediaTek SMI driver");
754 MODULE_LICENSE("GPL v2");