drivers/memory/emif.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * EMIF driver
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * Aneesh V <aneesh@ti.com>
   8  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  */
  10 #include <linux/err.h>
  11 #include <linux/kernel.h>
  12 #include <linux/reboot.h>
  13 #include <linux/platform_data/emif_plat.h>
  14 #include <linux/io.h>
  15 #include <linux/device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/slab.h>
  19 #include <linux/of.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/module.h>
  23 #include <linux/list.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/pm.h>
  26
  27 #include "emif.h"
  28 #include "jedec_ddr.h"
  29 #include "of_memory.h"
  30
  31 /**
  32  * struct emif_data - Per device static data for driver's use
  33  * @duplicate:                  Whether the DDR devices attached to this EMIF
  34  *                              instance are exactly same as that on EMIF1. In
  35  *                              this case we can save some memory and processing
  36  * @temperature_level:          Maximum temperature of LPDDR2 devices attached
  37  *                              to this EMIF - read from MR4 register. If there
  38  *                              are two devices attached to this EMIF, this
  39  *                              value is the maximum of the two temperature
  40  *                              levels.
  41  * @node:                       node in the device list
  42  * @base:                       base address of memory-mapped IO registers.
  43  * @dev:                        device pointer.
  44  * @addressing                  table with addressing information from the spec
  45  * @regs_cache:                 An array of 'struct emif_regs' that stores
  46  *                              calculated register values for different
  47  *                              frequencies, to avoid re-calculating them on
  48  *                              each DVFS transition.
  49  * @curr_regs:                  The set of register values used in the last
  50  *                              frequency change (i.e. corresponding to the
  51  *                              frequency in effect at the moment)
  52  * @plat_data:                  Pointer to saved platform data.
  53  * @debugfs_root:               dentry to the root folder for EMIF in debugfs
  54  * @np_ddr:                     Pointer to ddr device tree node
  55  */
  56 struct emif_data {
  57         u8                              duplicate;
  58         u8                              temperature_level;
  59         u8                              lpmode;
  60         struct list_head                node;
  61         unsigned long                   irq_state;
  62         void __iomem                    *base;
  63         struct device                   *dev;
  64         const struct lpddr2_addressing  *addressing;
  65         struct emif_regs                *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
  66         struct emif_regs                *curr_regs;
  67         struct emif_platform_data       *plat_data;
  68         struct dentry                   *debugfs_root;
  69         struct device_node              *np_ddr;
  70 };
  71
  72 static struct emif_data *emif1;
  73 static spinlock_t       emif_lock;
  74 static unsigned long    irq_state;
  75 static u32              t_ck; /* DDR clock period in ps */
  76 static LIST_HEAD(device_list);
  77
  78 #ifdef CONFIG_DEBUG_FS
  79 static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
  80         struct emif_regs *regs)
  81 {
  82         u32 type = emif->plat_data->device_info->type;
  83         u32 ip_rev = emif->plat_data->ip_rev;
  84
  85         seq_printf(s, "EMIF register cache dump for %dMHz\n",
  86                 regs->freq/1000000);
  87
  88         seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
  89         seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
  90         seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
  91         seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
  92
  93         if (ip_rev == EMIF_4D) {
  94                 seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
  95                         regs->read_idle_ctrl_shdw_normal);
  96                 seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
  97                         regs->read_idle_ctrl_shdw_volt_ramp);
  98         } else if (ip_rev == EMIF_4D5) {
  99                 seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
 100                         regs->dll_calib_ctrl_shdw_normal);
 101                 seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
 102                         regs->dll_calib_ctrl_shdw_volt_ramp);
 103         }
 104
 105         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
 106                 seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
 107                         regs->ref_ctrl_shdw_derated);
 108                 seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
 109                         regs->sdram_tim1_shdw_derated);
 110                 seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
 111                         regs->sdram_tim3_shdw_derated);
 112         }
 113 }
 114
 115 static int emif_regdump_show(struct seq_file *s, void *unused)
 116 {
 117         struct emif_data        *emif   = s->private;
 118         struct emif_regs        **regs_cache;
 119         int                     i;
 120
 121         if (emif->duplicate)
 122                 regs_cache = emif1->regs_cache;
 123         else
 124                 regs_cache = emif->regs_cache;
 125
 126         for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
 127                 do_emif_regdump_show(s, emif, regs_cache[i]);
 128                 seq_putc(s, '\n');
 129         }
 130
 131         return 0;
 132 }
 133
 134 static int emif_regdump_open(struct inode *inode, struct file *file)
 135 {
 136         return single_open(file, emif_regdump_show, inode->i_private);
 137 }
 138
 139 static const struct file_operations emif_regdump_fops = {
 140         .open                   = emif_regdump_open,
 141         .read                   = seq_read,
 142         .release                = single_release,
 143 };
 144
 145 static int emif_mr4_show(struct seq_file *s, void *unused)
 146 {
 147         struct emif_data *emif = s->private;
 148
 149         seq_printf(s, "MR4=%d\n", emif->temperature_level);
 150         return 0;
 151 }
 152
 153 static int emif_mr4_open(struct inode *inode, struct file *file)
 154 {
 155         return single_open(file, emif_mr4_show, inode->i_private);
 156 }
 157
 158 static const struct file_operations emif_mr4_fops = {
 159         .open                   = emif_mr4_open,
 160         .read                   = seq_read,
 161         .release                = single_release,
 162 };
 163
 164 static int __init_or_module emif_debugfs_init(struct emif_data *emif)
 165 {
 166         emif->debugfs_root = debugfs_create_dir(dev_name(emif->dev), NULL);
 167         debugfs_create_file("regcache_dump", S_IRUGO, emif->debugfs_root, emif,
 168                             &emif_regdump_fops);
 169         debugfs_create_file("mr4", S_IRUGO, emif->debugfs_root, emif,
 170                             &emif_mr4_fops);
 171         return 0;
 172 }
 173
 174 static void __exit emif_debugfs_exit(struct emif_data *emif)
 175 {
 176         debugfs_remove_recursive(emif->debugfs_root);
 177         emif->debugfs_root = NULL;
 178 }
 179 #else
 180 static inline int __init_or_module emif_debugfs_init(struct emif_data *emif)
 181 {
 182         return 0;
 183 }
 184
 185 static inline void __exit emif_debugfs_exit(struct emif_data *emif)
 186 {
 187 }
 188 #endif
 189
 190 /*
 191  * Calculate the period of DDR clock from frequency value
 192  */
 193 static void set_ddr_clk_period(u32 freq)
 194 {
 195         /* Divide 10^12 by frequency to get period in ps */
 196         t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
 197 }
 198
 199 /*
 200  * Get bus width used by EMIF. Note that this may be different from the
 201  * bus width of the DDR devices used. For instance two 16-bit DDR devices
 202  * may be connected to a given CS of EMIF. In this case bus width as far
 203  * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
 204  */
 205 static u32 get_emif_bus_width(struct emif_data *emif)
 206 {
 207         u32             width;
 208         void __iomem    *base = emif->base;
 209
 210         width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
 211                         >> NARROW_MODE_SHIFT;
 212         width = width == 0 ? 32 : 16;
 213
 214         return width;
 215 }
 216
 217 /*
 218  * Get the CL from SDRAM_CONFIG register
 219  */
 220 static u32 get_cl(struct emif_data *emif)
 221 {
 222         u32             cl;
 223         void __iomem    *base = emif->base;
 224
 225         cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
 226
 227         return cl;
 228 }
 229
 230 static void set_lpmode(struct emif_data *emif, u8 lpmode)
 231 {
 232         u32 temp;
 233         void __iomem *base = emif->base;
 234
 235         /*
 236          * Workaround for errata i743 - LPDDR2 Power-Down State is Not
 237          * Efficient
 238          *
 239          * i743 DESCRIPTION:
 240          * The EMIF supports power-down state for low power. The EMIF
 241          * automatically puts the SDRAM into power-down after the memory is
 242          * not accessed for a defined number of cycles and the
 243          * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4.
 244          * As the EMIF supports automatic output impedance calibration, a ZQ
 245          * calibration long command is issued every time it exits active
 246          * power-down and precharge power-down modes. The EMIF waits and
 247          * blocks any other command during this calibration.
 248          * The EMIF does not allow selective disabling of ZQ calibration upon
 249          * exit of power-down mode. Due to very short periods of power-down
 250          * cycles, ZQ calibration overhead creates bandwidth issues and
 251          * increases overall system power consumption. On the other hand,
 252          * issuing ZQ calibration long commands when exiting self-refresh is
 253          * still required.
 254          *
 255          * WORKAROUND
 256          * Because there is no power consumption benefit of the power-down due
 257          * to the calibration and there is a performance risk, the guideline
 258          * is to not allow power-down state and, therefore, to not have set
 259          * the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4.
 260          */
 261         if ((emif->plat_data->ip_rev == EMIF_4D) &&
 262             (lpmode == EMIF_LP_MODE_PWR_DN)) {
 263                 WARN_ONCE(1,
 264                           "REG_LP_MODE = LP_MODE_PWR_DN(4) is prohibited by erratum i743 switch to LP_MODE_SELF_REFRESH(2)\n");
 265                 /* rollback LP_MODE to Self-refresh mode */
 266                 lpmode = EMIF_LP_MODE_SELF_REFRESH;
 267         }
 268
 269         temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
 270         temp &= ~LP_MODE_MASK;
 271         temp |= (lpmode << LP_MODE_SHIFT);
 272         writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
 273 }
 274
 275 static void do_freq_update(void)
 276 {
 277         struct emif_data *emif;
 278
 279         /*
 280          * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
 281          *
 282          * i728 DESCRIPTION:
 283          * The EMIF automatically puts the SDRAM into self-refresh mode
 284          * after the EMIF has not performed accesses during
 285          * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
 286          * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
 287          * to 0x2. If during a small window the following three events
 288          * occur:
 289          * - The SR_TIMING counter expires
 290          * - And frequency change is requested
 291          * - And OCP access is requested
 292          * Then it causes instable clock on the DDR interface.
 293          *
 294          * WORKAROUND
 295          * To avoid the occurrence of the three events, the workaround
 296          * is to disable the self-refresh when requesting a frequency
 297          * change. Before requesting a frequency change the software must
 298          * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
 299          * frequency change has been done, the software can reprogram
 300          * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
 301          */
 302         list_for_each_entry(emif, &device_list, node) {
 303                 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
 304                         set_lpmode(emif, EMIF_LP_MODE_DISABLE);
 305         }
 306
 307         /*
 308          * TODO: Do FREQ_UPDATE here when an API
 309          * is available for this as part of the new
 310          * clock framework
 311          */
 312
 313         list_for_each_entry(emif, &device_list, node) {
 314                 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
 315                         set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
 316         }
 317 }
 318
 319 /* Find addressing table entry based on the device's type and density */
 320 static const struct lpddr2_addressing *get_addressing_table(
 321         const struct ddr_device_info *device_info)
 322 {
 323         u32             index, type, density;
 324
 325         type = device_info->type;
 326         density = device_info->density;
 327
 328         switch (type) {
 329         case DDR_TYPE_LPDDR2_S4:
 330                 index = density - 1;
 331                 break;
 332         case DDR_TYPE_LPDDR2_S2:
 333                 switch (density) {
 334                 case DDR_DENSITY_1Gb:
 335                 case DDR_DENSITY_2Gb:
 336                         index = density + 3;
 337                         break;
 338                 default:
 339                         index = density - 1;
 340                 }
 341                 break;
 342         default:
 343                 return NULL;
 344         }
 345
 346         return &lpddr2_jedec_addressing_table[index];
 347 }
 348
 349 /*
 350  * Find the the right timing table from the array of timing
 351  * tables of the device using DDR clock frequency
 352  */
 353 static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
 354                 u32 freq)
 355 {
 356         u32                             i, min, max, freq_nearest;
 357         const struct lpddr2_timings     *timings = NULL;
 358         const struct lpddr2_timings     *timings_arr = emif->plat_data->timings;
 359         struct                          device *dev = emif->dev;
 360
 361         /* Start with a very high frequency - 1GHz */
 362         freq_nearest = 1000000000;
 363
 364         /*
 365          * Find the timings table such that:
 366          *  1. the frequency range covers the required frequency(safe) AND
 367          *  2. the max_freq is closest to the required frequency(optimal)
 368          */
 369         for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
 370                 max = timings_arr[i].max_freq;
 371                 min = timings_arr[i].min_freq;
 372                 if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
 373                         freq_nearest = max;
 374                         timings = &timings_arr[i];
 375                 }
 376         }
 377
 378         if (!timings)
 379                 dev_err(dev, "%s: couldn't find timings for - %dHz\n",
 380                         __func__, freq);
 381
 382         dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
 383                 __func__, freq, freq_nearest);
 384
 385         return timings;
 386 }
 387
 388 static u32 get_sdram_ref_ctrl_shdw(u32 freq,
 389                 const struct lpddr2_addressing *addressing)
 390 {
 391         u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
 392
 393         /* Scale down frequency and t_refi to avoid overflow */
 394         freq_khz = freq / 1000;
 395         t_refi = addressing->tREFI_ns / 100;
 396
 397         /*
 398          * refresh rate to be set is 'tREFI(in us) * freq in MHz
 399          * division by 10000 to account for change in units
 400          */
 401         val = t_refi * freq_khz / 10000;
 402         ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
 403
 404         return ref_ctrl_shdw;
 405 }
 406
 407 static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,
 408                 const struct lpddr2_min_tck *min_tck,
 409                 const struct lpddr2_addressing *addressing)
 410 {
 411         u32 tim1 = 0, val = 0;
 412
 413         val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
 414         tim1 |= val << T_WTR_SHIFT;
 415
 416         if (addressing->num_banks == B8)
 417                 val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
 418         else
 419                 val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
 420         tim1 |= (val - 1) << T_RRD_SHIFT;
 421
 422         val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
 423         tim1 |= val << T_RC_SHIFT;
 424
 425         val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
 426         tim1 |= (val - 1) << T_RAS_SHIFT;
 427
 428         val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
 429         tim1 |= val << T_WR_SHIFT;
 430
 431         val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
 432         tim1 |= val << T_RCD_SHIFT;
 433
 434         val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
 435         tim1 |= val << T_RP_SHIFT;
 436
 437         return tim1;
 438 }
 439
 440 static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,
 441                 const struct lpddr2_min_tck *min_tck,
 442                 const struct lpddr2_addressing *addressing)
 443 {
 444         u32 tim1 = 0, val = 0;
 445
 446         val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
 447         tim1 = val << T_WTR_SHIFT;
 448
 449         /*
 450          * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
 451          * to tFAW for de-rating
 452          */
 453         if (addressing->num_banks == B8) {
 454                 val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
 455         } else {
 456                 val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
 457                 val = max(min_tck->tRRD, val) - 1;
 458         }
 459         tim1 |= val << T_RRD_SHIFT;
 460
 461         val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
 462         tim1 |= (val - 1) << T_RC_SHIFT;
 463
 464         val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
 465         val = max(min_tck->tRASmin, val) - 1;
 466         tim1 |= val << T_RAS_SHIFT;
 467
 468         val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
 469         tim1 |= val << T_WR_SHIFT;
 470
 471         val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
 472         tim1 |= (val - 1) << T_RCD_SHIFT;
 473
 474         val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
 475         tim1 |= (val - 1) << T_RP_SHIFT;
 476
 477         return tim1;
 478 }
 479
 480 static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings,
 481                 const struct lpddr2_min_tck *min_tck,
 482                 const struct lpddr2_addressing *addressing,
 483                 u32 type)
 484 {
 485         u32 tim2 = 0, val = 0;
 486
 487         val = min_tck->tCKE - 1;
 488         tim2 |= val << T_CKE_SHIFT;
 489
 490         val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
 491         tim2 |= val << T_RTP_SHIFT;
 492
 493         /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
 494         val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
 495         tim2 |= val << T_XSNR_SHIFT;
 496
 497         /* XSRD same as XSNR for LPDDR2 */
 498         tim2 |= val << T_XSRD_SHIFT;
 499
 500         val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
 501         tim2 |= val << T_XP_SHIFT;
 502
 503         return tim2;
 504 }
 505
 506 static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
 507                 const struct lpddr2_min_tck *min_tck,
 508                 const struct lpddr2_addressing *addressing,
 509                 u32 type, u32 ip_rev, u32 derated)
 510 {
 511         u32 tim3 = 0, val = 0, t_dqsck;
 512
 513         val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
 514         val = val > 0xF ? 0xF : val;
 515         tim3 |= val << T_RAS_MAX_SHIFT;
 516
 517         val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
 518         tim3 |= val << T_RFC_SHIFT;
 519
 520         t_dqsck = (derated == EMIF_DERATED_TIMINGS) ?
 521                 timings->tDQSCK_max_derated : timings->tDQSCK_max;
 522         if (ip_rev == EMIF_4D5)
 523                 val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
 524         else
 525                 val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
 526
 527         tim3 |= val << T_TDQSCKMAX_SHIFT;
 528
 529         val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
 530         tim3 |= val << ZQ_ZQCS_SHIFT;
 531
 532         val = DIV_ROUND_UP(timings->tCKESR, t_ck);
 533         val = max(min_tck->tCKESR, val) - 1;
 534         tim3 |= val << T_CKESR_SHIFT;
 535
 536         if (ip_rev == EMIF_4D5) {
 537                 tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
 538
 539                 val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
 540                 tim3 |= val << T_PDLL_UL_SHIFT;
 541         }
 542
 543         return tim3;
 544 }
 545
 546 static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
 547                 bool cs1_used, bool cal_resistors_per_cs)
 548 {
 549         u32 zq = 0, val = 0;
 550
 551         val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
 552         zq |= val << ZQ_REFINTERVAL_SHIFT;
 553
 554         val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
 555         zq |= val << ZQ_ZQCL_MULT_SHIFT;
 556
 557         val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
 558         zq |= val << ZQ_ZQINIT_MULT_SHIFT;
 559
 560         zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
 561
 562         if (cal_resistors_per_cs)
 563                 zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
 564         else
 565                 zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
 566
 567         zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
 568
 569         val = cs1_used ? 1 : 0;
 570         zq |= val << ZQ_CS1EN_SHIFT;
 571
 572         return zq;
 573 }
 574
 575 static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
 576                 const struct emif_custom_configs *custom_configs, bool cs1_used,
 577                 u32 sdram_io_width, u32 emif_bus_width)
 578 {
 579         u32 alert = 0, interval, devcnt;
 580
 581         if (custom_configs && (custom_configs->mask &
 582                                 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
 583                 interval = custom_configs->temp_alert_poll_interval_ms;
 584         else
 585                 interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
 586
 587         interval *= 1000000;                    /* Convert to ns */
 588         interval /= addressing->tREFI_ns;       /* Convert to refresh cycles */
 589         alert |= (interval << TA_REFINTERVAL_SHIFT);
 590
 591         /*
 592          * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
 593          * also to this form and subtract to get TA_DEVCNT, which is
 594          * in log2(x) form.
 595          */
 596         emif_bus_width = __fls(emif_bus_width) - 1;
 597         devcnt = emif_bus_width - sdram_io_width;
 598         alert |= devcnt << TA_DEVCNT_SHIFT;
 599
 600         /* DEVWDT is in 'log2(x) - 3' form */
 601         alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
 602
 603         alert |= 1 << TA_SFEXITEN_SHIFT;
 604         alert |= 1 << TA_CS0EN_SHIFT;
 605         alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
 606
 607         return alert;
 608 }
 609
 610 static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
 611 {
 612         u32 idle = 0, val = 0;
 613
 614         /*
 615          * Maximum value in normal conditions and increased frequency
 616          * when voltage is ramping
 617          */
 618         if (volt_ramp)
 619                 val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
 620         else
 621                 val = 0x1FF;
 622
 623         /*
 624          * READ_IDLE_CTRL register in EMIF4D has same offset and fields
 625          * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
 626          */
 627         idle |= val << DLL_CALIB_INTERVAL_SHIFT;
 628         idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT;
 629
 630         return idle;
 631 }
 632
 633 static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp)
 634 {
 635         u32 calib = 0, val = 0;
 636
 637         if (volt_ramp == DDR_VOLTAGE_RAMPING)
 638                 val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
 639         else
 640                 val = 0; /* Disabled when voltage is stable */
 641
 642         calib |= val << DLL_CALIB_INTERVAL_SHIFT;
 643         calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT;
 644
 645         return calib;
 646 }
 647
 648 static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings,
 649         u32 freq, u8 RL)
 650 {
 651         u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
 652
 653         val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
 654         phy |= val << READ_LATENCY_SHIFT_4D;
 655
 656         if (freq <= 100000000)
 657                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
 658         else if (freq <= 200000000)
 659                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
 660         else
 661                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
 662
 663         phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;
 664
 665         return phy;
 666 }
 667
 668 static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl)
 669 {
 670         u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay;
 671
 672         /*
 673          * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
 674          * half-delay is not needed else set half-delay
 675          */
 676         if (freq >= 265000000 && freq < 267000000)
 677                 half_delay = 0;
 678         else
 679                 half_delay = 1;
 680
 681         phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5;
 682         phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS,
 683                         t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
 684
 685         return phy;
 686 }
 687
 688 static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void)
 689 {
 690         u32 fifo_we_slave_ratio;
 691
 692         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 693                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck);
 694
 695         return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 |
 696                 fifo_we_slave_ratio << 22;
 697 }
 698
 699 static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void)
 700 {
 701         u32 fifo_we_slave_ratio;
 702
 703         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 704                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck);
 705
 706         return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 |
 707                 fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23;
 708 }
 709
 710 static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void)
 711 {
 712         u32 fifo_we_slave_ratio;
 713
 714         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 715                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck);
 716
 717         return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 |
 718                 fifo_we_slave_ratio << 13;
 719 }
 720
 721 static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
 722 {
 723         u32 pwr_mgmt_ctrl       = 0, timeout;
 724         u32 lpmode              = EMIF_LP_MODE_SELF_REFRESH;
 725         u32 timeout_perf        = EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
 726         u32 timeout_pwr         = EMIF_LP_MODE_TIMEOUT_POWER;
 727         u32 freq_threshold      = EMIF_LP_MODE_FREQ_THRESHOLD;
 728         u32 mask;
 729         u8 shift;
 730
 731         struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
 732
 733         if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
 734                 lpmode          = cust_cfgs->lpmode;
 735                 timeout_perf    = cust_cfgs->lpmode_timeout_performance;
 736                 timeout_pwr     = cust_cfgs->lpmode_timeout_power;
 737                 freq_threshold  = cust_cfgs->lpmode_freq_threshold;
 738         }
 739
 740         /* Timeout based on DDR frequency */
 741         timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
 742
 743         /*
 744          * The value to be set in register is "log2(timeout) - 3"
 745          * if timeout < 16 load 0 in register
 746          * if timeout is not a power of 2, round to next highest power of 2
 747          */
 748         if (timeout < 16) {
 749                 timeout = 0;
 750         } else {
 751                 if (timeout & (timeout - 1))
 752                         timeout <<= 1;
 753                 timeout = __fls(timeout) - 3;
 754         }
 755
 756         switch (lpmode) {
 757         case EMIF_LP_MODE_CLOCK_STOP:
 758                 shift = CS_TIM_SHIFT;
 759                 mask = CS_TIM_MASK;
 760                 break;
 761         case EMIF_LP_MODE_SELF_REFRESH:
 762                 /* Workaround for errata i735 */
 763                 if (timeout < 6)
 764                         timeout = 6;
 765
 766                 shift = SR_TIM_SHIFT;
 767                 mask = SR_TIM_MASK;
 768                 break;
 769         case EMIF_LP_MODE_PWR_DN:
 770                 shift = PD_TIM_SHIFT;
 771                 mask = PD_TIM_MASK;
 772                 break;
 773         case EMIF_LP_MODE_DISABLE:
 774         default:
 775                 mask = 0;
 776                 shift = 0;
 777                 break;
 778         }
 779         /* Round to maximum in case of overflow, BUT warn! */
 780         if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) {
 781                 pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n",
 782                        lpmode,
 783                        timeout_perf,
 784                        timeout_pwr,
 785                        freq_threshold);
 786                 WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n",
 787                      timeout, mask >> shift);
 788                 timeout = mask >> shift;
 789         }
 790
 791         /* Setup required timing */
 792         pwr_mgmt_ctrl = (timeout << shift) & mask;
 793         /* setup a default mask for rest of the modes */
 794         pwr_mgmt_ctrl |= (SR_TIM_MASK | CS_TIM_MASK | PD_TIM_MASK) &
 795                           ~mask;
 796
 797         /* No CS_TIM in EMIF_4D5 */
 798         if (ip_rev == EMIF_4D5)
 799                 pwr_mgmt_ctrl &= ~CS_TIM_MASK;
 800
 801         pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
 802
 803         return pwr_mgmt_ctrl;
 804 }
 805
 806 /*
 807  * Get the temperature level of the EMIF instance:
 808  * Reads the MR4 register of attached SDRAM parts to find out the temperature
 809  * level. If there are two parts attached(one on each CS), then the temperature
 810  * level for the EMIF instance is the higher of the two temperatures.
 811  */
 812 static void get_temperature_level(struct emif_data *emif)
 813 {
 814         u32             temp, temperature_level;
 815         void __iomem    *base;
 816
 817         base = emif->base;
 818
 819         /* Read mode register 4 */
 820         writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
 821         temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 822         temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
 823                                 MR4_SDRAM_REF_RATE_SHIFT;
 824
 825         if (emif->plat_data->device_info->cs1_used) {
 826                 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
 827                 temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 828                 temp = (temp & MR4_SDRAM_REF_RATE_MASK)
 829                                 >> MR4_SDRAM_REF_RATE_SHIFT;
 830                 temperature_level = max(temp, temperature_level);
 831         }
 832
 833         /* treat everything less than nominal(3) in MR4 as nominal */
 834         if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
 835                 temperature_level = SDRAM_TEMP_NOMINAL;
 836
 837         /* if we get reserved value in MR4 persist with the existing value */
 838         if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
 839                 emif->temperature_level = temperature_level;
 840 }
 841
 842 /*
 843  * Program EMIF shadow registers that are not dependent on temperature
 844  * or voltage
 845  */
 846 static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
 847 {
 848         void __iomem    *base = emif->base;
 849
 850         writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
 851         writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
 852         writel(regs->pwr_mgmt_ctrl_shdw,
 853                base + EMIF_POWER_MANAGEMENT_CTRL_SHDW);
 854
 855         /* Settings specific for EMIF4D5 */
 856         if (emif->plat_data->ip_rev != EMIF_4D5)
 857                 return;
 858         writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
 859         writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
 860         writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
 861 }
 862
 863 /*
 864  * When voltage ramps dll calibration and forced read idle should
 865  * happen more often
 866  */
 867 static void setup_volt_sensitive_regs(struct emif_data *emif,
 868                 struct emif_regs *regs, u32 volt_state)
 869 {
 870         u32             calib_ctrl;
 871         void __iomem    *base = emif->base;
 872
 873         /*
 874          * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
 875          * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
 876          * is an alias of the respective read_idle_ctrl_shdw_* (members of
 877          * a union). So, the below code takes care of both cases
 878          */
 879         if (volt_state == DDR_VOLTAGE_RAMPING)
 880                 calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp;
 881         else
 882                 calib_ctrl = regs->dll_calib_ctrl_shdw_normal;
 883
 884         writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
 885 }
 886
 887 /*
 888  * setup_temperature_sensitive_regs() - set the timings for temperature
 889  * sensitive registers. This happens once at initialisation time based
 890  * on the temperature at boot time and subsequently based on the temperature
 891  * alert interrupt. Temperature alert can happen when the temperature
 892  * increases or drops. So this function can have the effect of either
 893  * derating the timings or going back to nominal values.
 894  */
 895 static void setup_temperature_sensitive_regs(struct emif_data *emif,
 896                 struct emif_regs *regs)
 897 {
 898         u32             tim1, tim3, ref_ctrl, type;
 899         void __iomem    *base = emif->base;
 900         u32             temperature;
 901
 902         type = emif->plat_data->device_info->type;
 903
 904         tim1 = regs->sdram_tim1_shdw;
 905         tim3 = regs->sdram_tim3_shdw;
 906         ref_ctrl = regs->ref_ctrl_shdw;
 907
 908         /* No de-rating for non-lpddr2 devices */
 909         if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
 910                 goto out;
 911
 912         temperature = emif->temperature_level;
 913         if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
 914                 ref_ctrl = regs->ref_ctrl_shdw_derated;
 915         } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
 916                 tim1 = regs->sdram_tim1_shdw_derated;
 917                 tim3 = regs->sdram_tim3_shdw_derated;
 918                 ref_ctrl = regs->ref_ctrl_shdw_derated;
 919         }
 920
 921 out:
 922         writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
 923         writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
 924         writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
 925 }
 926
 927 static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
 928 {
 929         u32             old_temp_level;
 930         irqreturn_t     ret = IRQ_HANDLED;
 931         struct emif_custom_configs *custom_configs;
 932
 933         spin_lock_irqsave(&emif_lock, irq_state);
 934         old_temp_level = emif->temperature_level;
 935         get_temperature_level(emif);
 936
 937         if (unlikely(emif->temperature_level == old_temp_level)) {
 938                 goto out;
 939         } else if (!emif->curr_regs) {
 940                 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
 941                 goto out;
 942         }
 943
 944         custom_configs = emif->plat_data->custom_configs;
 945
 946         /*
 947          * IF we detect higher than "nominal rating" from DDR sensor
 948          * on an unsupported DDR part, shutdown system
 949          */
 950         if (custom_configs && !(custom_configs->mask &
 951                                 EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART)) {
 952                 if (emif->temperature_level >= SDRAM_TEMP_HIGH_DERATE_REFRESH) {
 953                         dev_err(emif->dev,
 954                                 "%s:NOT Extended temperature capable memory. Converting MR4=0x%02x as shutdown event\n",
 955                                 __func__, emif->temperature_level);
 956                         /*
 957                          * Temperature far too high - do kernel_power_off()
 958                          * from thread context
 959                          */
 960                         emif->temperature_level = SDRAM_TEMP_VERY_HIGH_SHUTDOWN;
 961                         ret = IRQ_WAKE_THREAD;
 962                         goto out;
 963                 }
 964         }
 965
 966         if (emif->temperature_level < old_temp_level ||
 967                 emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
 968                 /*
 969                  * Temperature coming down - defer handling to thread OR
 970                  * Temperature far too high - do kernel_power_off() from
 971                  * thread context
 972                  */
 973                 ret = IRQ_WAKE_THREAD;
 974         } else {
 975                 /* Temperature is going up - handle immediately */
 976                 setup_temperature_sensitive_regs(emif, emif->curr_regs);
 977                 do_freq_update();
 978         }
 979
 980 out:
 981         spin_unlock_irqrestore(&emif_lock, irq_state);
 982         return ret;
 983 }
 984
 985 static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
 986 {
 987         u32                     interrupts;
 988         struct emif_data        *emif = dev_id;
 989         void __iomem            *base = emif->base;
 990         struct device           *dev = emif->dev;
 991         irqreturn_t             ret = IRQ_HANDLED;
 992
 993         /* Save the status and clear it */
 994         interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
 995         writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
 996
 997         /*
 998          * Handle temperature alert
 999          * Temperature alert should be same for all ports
1000          * So, it's enough to process it only for one of the ports
1001          */
1002         if (interrupts & TA_SYS_MASK)
1003                 ret = handle_temp_alert(base, emif);
1004
1005         if (interrupts & ERR_SYS_MASK)
1006                 dev_err(dev, "Access error from SYS port - %x\n", interrupts);
1007
1008         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1009                 /* Save the status and clear it */
1010                 interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
1011                 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
1012
1013                 if (interrupts & ERR_LL_MASK)
1014                         dev_err(dev, "Access error from LL port - %x\n",
1015                                 interrupts);
1016         }
1017
1018         return ret;
1019 }
1020
1021 static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
1022 {
1023         struct emif_data        *emif = dev_id;
1024
1025         if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
1026                 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1027
1028                 /* If we have Power OFF ability, use it, else try restarting */
1029                 if (pm_power_off) {
1030                         kernel_power_off();
1031                 } else {
1032                         WARN(1, "FIXME: NO pm_power_off!!! trying restart\n");
1033                         kernel_restart("SDRAM Over-temp Emergency restart");
1034                 }
1035                 return IRQ_HANDLED;
1036         }
1037
1038         spin_lock_irqsave(&emif_lock, irq_state);
1039
1040         if (emif->curr_regs) {
1041                 setup_temperature_sensitive_regs(emif, emif->curr_regs);
1042                 do_freq_update();
1043         } else {
1044                 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
1045         }
1046
1047         spin_unlock_irqrestore(&emif_lock, irq_state);
1048
1049         return IRQ_HANDLED;
1050 }
1051
1052 static void clear_all_interrupts(struct emif_data *emif)
1053 {
1054         void __iomem    *base = emif->base;
1055
1056         writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
1057                 base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
1058         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
1059                 writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
1060                         base + EMIF_LL_OCP_INTERRUPT_STATUS);
1061 }
1062
1063 static void disable_and_clear_all_interrupts(struct emif_data *emif)
1064 {
1065         void __iomem            *base = emif->base;
1066
1067         /* Disable all interrupts */
1068         writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
1069                 base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
1070         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
1071                 writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
1072                         base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
1073
1074         /* Clear all interrupts */
1075         clear_all_interrupts(emif);
1076 }
1077
1078 static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
1079 {
1080         u32             interrupts, type;
1081         void __iomem    *base = emif->base;
1082
1083         type = emif->plat_data->device_info->type;
1084
1085         clear_all_interrupts(emif);
1086
1087         /* Enable interrupts for SYS interface */
1088         interrupts = EN_ERR_SYS_MASK;
1089         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
1090                 interrupts |= EN_TA_SYS_MASK;
1091         writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
1092
1093         /* Enable interrupts for LL interface */
1094         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1095                 /* TA need not be enabled for LL */
1096                 interrupts = EN_ERR_LL_MASK;
1097                 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
1098         }
1099
1100         /* setup IRQ handlers */
1101         return devm_request_threaded_irq(emif->dev, irq,
1102                                     emif_interrupt_handler,
1103                                     emif_threaded_isr,
1104                                     0, dev_name(emif->dev),
1105                                     emif);
1106
1107 }
1108
1109 static void __init_or_module emif_onetime_settings(struct emif_data *emif)
1110 {
1111         u32                             pwr_mgmt_ctrl, zq, temp_alert_cfg;
1112         void __iomem                    *base = emif->base;
1113         const struct lpddr2_addressing  *addressing;
1114         const struct ddr_device_info    *device_info;
1115
1116         device_info = emif->plat_data->device_info;
1117         addressing = get_addressing_table(device_info);
1118
1119         /*
1120          * Init power management settings
1121          * We don't know the frequency yet. Use a high frequency
1122          * value for a conservative timeout setting
1123          */
1124         pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
1125                         emif->plat_data->ip_rev);
1126         emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
1127         writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
1128
1129         /* Init ZQ calibration settings */
1130         zq = get_zq_config_reg(addressing, device_info->cs1_used,
1131                 device_info->cal_resistors_per_cs);
1132         writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
1133
1134         /* Check temperature level temperature level*/
1135         get_temperature_level(emif);
1136         if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
1137                 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1138
1139         /* Init temperature polling */
1140         temp_alert_cfg = get_temp_alert_config(addressing,
1141                 emif->plat_data->custom_configs, device_info->cs1_used,
1142                 device_info->io_width, get_emif_bus_width(emif));
1143         writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
1144
1145         /*
1146          * Program external PHY control registers that are not frequency
1147          * dependent
1148          */
1149         if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
1150                 return;
1151         writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
1152         writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
1153         writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
1154         writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
1155         writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
1156         writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
1157         writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
1158         writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
1159         writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
1160         writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
1161         writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
1162         writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
1163         writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
1164         writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
1165         writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
1166         writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
1167         writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
1168         writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
1169         writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
1170         writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
1171         writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
1172 }
1173
1174 static void get_default_timings(struct emif_data *emif)
1175 {
1176         struct emif_platform_data *pd = emif->plat_data;
1177
1178         pd->timings             = lpddr2_jedec_timings;
1179         pd->timings_arr_size    = ARRAY_SIZE(lpddr2_jedec_timings);
1180
1181         dev_warn(emif->dev, "%s: using default timings\n", __func__);
1182 }
1183
1184 static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
1185                 u32 ip_rev, struct device *dev)
1186 {
1187         int valid;
1188
1189         valid = (type == DDR_TYPE_LPDDR2_S4 ||
1190                         type == DDR_TYPE_LPDDR2_S2)
1191                 && (density >= DDR_DENSITY_64Mb
1192                         && density <= DDR_DENSITY_8Gb)
1193                 && (io_width >= DDR_IO_WIDTH_8
1194                         && io_width <= DDR_IO_WIDTH_32);
1195
1196         /* Combinations of EMIF and PHY revisions that we support today */
1197         switch (ip_rev) {
1198         case EMIF_4D:
1199                 valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
1200                 break;
1201         case EMIF_4D5:
1202                 valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
1203                 break;
1204         default:
1205                 valid = 0;
1206         }
1207
1208         if (!valid)
1209                 dev_err(dev, "%s: invalid DDR details\n", __func__);
1210         return valid;
1211 }
1212
1213 static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
1214                 struct device *dev)
1215 {
1216         int valid = 1;
1217
1218         if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
1219                 (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
1220                 valid = cust_cfgs->lpmode_freq_threshold &&
1221                         cust_cfgs->lpmode_timeout_performance &&
1222                         cust_cfgs->lpmode_timeout_power;
1223
1224         if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
1225                 valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
1226
1227         if (!valid)
1228                 dev_warn(dev, "%s: invalid custom configs\n", __func__);
1229
1230         return valid;
1231 }
1232
1233 #if defined(CONFIG_OF)
1234 static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
1235                 struct emif_data *emif)
1236 {
1237         struct emif_custom_configs      *cust_cfgs = NULL;
1238         int                             len;
1239         const __be32                    *lpmode, *poll_intvl;
1240
1241         lpmode = of_get_property(np_emif, "low-power-mode", &len);
1242         poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
1243
1244         if (lpmode || poll_intvl)
1245                 cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
1246                         GFP_KERNEL);
1247
1248         if (!cust_cfgs)
1249                 return;
1250
1251         if (lpmode) {
1252                 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
1253                 cust_cfgs->lpmode = be32_to_cpup(lpmode);
1254                 of_property_read_u32(np_emif,
1255                                 "low-power-mode-timeout-performance",
1256                                 &cust_cfgs->lpmode_timeout_performance);
1257                 of_property_read_u32(np_emif,
1258                                 "low-power-mode-timeout-power",
1259                                 &cust_cfgs->lpmode_timeout_power);
1260                 of_property_read_u32(np_emif,
1261                                 "low-power-mode-freq-threshold",
1262                                 &cust_cfgs->lpmode_freq_threshold);
1263         }
1264
1265         if (poll_intvl) {
1266                 cust_cfgs->mask |=
1267                                 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
1268                 cust_cfgs->temp_alert_poll_interval_ms =
1269                                                 be32_to_cpup(poll_intvl);
1270         }
1271
1272         if (of_find_property(np_emif, "extended-temp-part", &len))
1273                 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART;
1274
1275         if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
1276                 devm_kfree(emif->dev, cust_cfgs);
1277                 return;
1278         }
1279
1280         emif->plat_data->custom_configs = cust_cfgs;
1281 }
1282
1283 static void __init_or_module of_get_ddr_info(struct device_node *np_emif,
1284                 struct device_node *np_ddr,
1285                 struct ddr_device_info *dev_info)
1286 {
1287         u32 density = 0, io_width = 0;
1288         int len;
1289
1290         if (of_find_property(np_emif, "cs1-used", &len))
1291                 dev_info->cs1_used = true;
1292
1293         if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
1294                 dev_info->cal_resistors_per_cs = true;
1295
1296         if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s4"))
1297                 dev_info->type = DDR_TYPE_LPDDR2_S4;
1298         else if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s2"))
1299                 dev_info->type = DDR_TYPE_LPDDR2_S2;
1300
1301         of_property_read_u32(np_ddr, "density", &density);
1302         of_property_read_u32(np_ddr, "io-width", &io_width);
1303
1304         /* Convert from density in Mb to the density encoding in jedc_ddr.h */
1305         if (density & (density - 1))
1306                 dev_info->density = 0;
1307         else
1308                 dev_info->density = __fls(density) - 5;
1309
1310         /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
1311         if (io_width & (io_width - 1))
1312                 dev_info->io_width = 0;
1313         else
1314                 dev_info->io_width = __fls(io_width) - 1;
1315 }
1316
1317 static struct emif_data * __init_or_module of_get_memory_device_details(
1318                 struct device_node *np_emif, struct device *dev)
1319 {
1320         struct emif_data                *emif = NULL;
1321         struct ddr_device_info          *dev_info = NULL;
1322         struct emif_platform_data       *pd = NULL;
1323         struct device_node              *np_ddr;
1324         int                             len;
1325
1326         np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
1327         if (!np_ddr)
1328                 goto error;
1329         emif    = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
1330         pd      = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1331         dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1332
1333         if (!emif || !pd || !dev_info) {
1334                 dev_err(dev, "%s: Out of memory!!\n",
1335                         __func__);
1336                 goto error;
1337         }
1338
1339         emif->plat_data         = pd;
1340         pd->device_info         = dev_info;
1341         emif->dev               = dev;
1342         emif->np_ddr            = np_ddr;
1343         emif->temperature_level = SDRAM_TEMP_NOMINAL;
1344
1345         if (of_device_is_compatible(np_emif, "ti,emif-4d"))
1346                 emif->plat_data->ip_rev = EMIF_4D;
1347         else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
1348                 emif->plat_data->ip_rev = EMIF_4D5;
1349
1350         of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
1351
1352         if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
1353                 pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
1354
1355         of_get_ddr_info(np_emif, np_ddr, dev_info);
1356         if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
1357                         pd->device_info->io_width, pd->phy_type, pd->ip_rev,
1358                         emif->dev)) {
1359                 dev_err(dev, "%s: invalid device data!!\n", __func__);
1360                 goto error;
1361         }
1362         /*
1363          * For EMIF instances other than EMIF1 see if the devices connected
1364          * are exactly same as on EMIF1(which is typically the case). If so,
1365          * mark it as a duplicate of EMIF1. This will save some memory and
1366          * computation.
1367          */
1368         if (emif1 && emif1->np_ddr == np_ddr) {
1369                 emif->duplicate = true;
1370                 goto out;
1371         } else if (emif1) {
1372                 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1373                         __func__);
1374         }
1375
1376         of_get_custom_configs(np_emif, emif);
1377         emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev,
1378                                         emif->plat_data->device_info->type,
1379                                         &emif->plat_data->timings_arr_size);
1380
1381         emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev);
1382         goto out;
1383
1384 error:
1385         return NULL;
1386 out:
1387         return emif;
1388 }
1389
1390 #else
1391
1392 static struct emif_data * __init_or_module of_get_memory_device_details(
1393                 struct device_node *np_emif, struct device *dev)
1394 {
1395         return NULL;
1396 }
1397 #endif
1398
1399 static struct emif_data *__init_or_module get_device_details(
1400                 struct platform_device *pdev)
1401 {
1402         u32                             size;
1403         struct emif_data                *emif = NULL;
1404         struct ddr_device_info          *dev_info;
1405         struct emif_custom_configs      *cust_cfgs;
1406         struct emif_platform_data       *pd;
1407         struct device                   *dev;
1408         void                            *temp;
1409
1410         pd = pdev->dev.platform_data;
1411         dev = &pdev->dev;
1412
1413         if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
1414                         pd->device_info->density, pd->device_info->io_width,
1415                         pd->phy_type, pd->ip_rev, dev))) {
1416                 dev_err(dev, "%s: invalid device data\n", __func__);
1417                 goto error;
1418         }
1419
1420         emif    = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
1421         temp    = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1422         dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1423
1424         if (!emif || !pd || !dev_info) {
1425                 dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__);
1426                 goto error;
1427         }
1428
1429         memcpy(temp, pd, sizeof(*pd));
1430         pd = temp;
1431         memcpy(dev_info, pd->device_info, sizeof(*dev_info));
1432
1433         pd->device_info         = dev_info;
1434         emif->plat_data         = pd;
1435         emif->dev               = dev;
1436         emif->temperature_level = SDRAM_TEMP_NOMINAL;
1437
1438         /*
1439          * For EMIF instances other than EMIF1 see if the devices connected
1440          * are exactly same as on EMIF1(which is typically the case). If so,
1441          * mark it as a duplicate of EMIF1 and skip copying timings data.
1442          * This will save some memory and some computation later.
1443          */
1444         emif->duplicate = emif1 && (memcmp(dev_info,
1445                 emif1->plat_data->device_info,
1446                 sizeof(struct ddr_device_info)) == 0);
1447
1448         if (emif->duplicate) {
1449                 pd->timings = NULL;
1450                 pd->min_tck = NULL;
1451                 goto out;
1452         } else if (emif1) {
1453                 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1454                         __func__);
1455         }
1456
1457         /*
1458          * Copy custom configs - ignore allocation error, if any, as
1459          * custom_configs is not very critical
1460          */
1461         cust_cfgs = pd->custom_configs;
1462         if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
1463                 temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
1464                 if (temp)
1465                         memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
1466                 else
1467                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1468                                 __LINE__);
1469                 pd->custom_configs = temp;
1470         }
1471
1472         /*
1473          * Copy timings and min-tck values from platform data. If it is not
1474          * available or if memory allocation fails, use JEDEC defaults
1475          */
1476         size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
1477         if (pd->timings) {
1478                 temp = devm_kzalloc(dev, size, GFP_KERNEL);
1479                 if (temp) {
1480                         memcpy(temp, pd->timings, size);
1481                         pd->timings = temp;
1482                 } else {
1483                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1484                                 __LINE__);
1485                         get_default_timings(emif);
1486                 }
1487         } else {
1488                 get_default_timings(emif);
1489         }
1490
1491         if (pd->min_tck) {
1492                 temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
1493                 if (temp) {
1494                         memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
1495                         pd->min_tck = temp;
1496                 } else {
1497                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1498                                 __LINE__);
1499                         pd->min_tck = &lpddr2_jedec_min_tck;
1500                 }
1501         } else {
1502                 pd->min_tck = &lpddr2_jedec_min_tck;
1503         }
1504
1505 out:
1506         return emif;
1507
1508 error:
1509         return NULL;
1510 }
1511
1512 static int __init_or_module emif_probe(struct platform_device *pdev)
1513 {
1514         struct emif_data        *emif;
1515         struct resource         *res;
1516         int                     irq;
1517
1518         if (pdev->dev.of_node)
1519                 emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev);
1520         else
1521                 emif = get_device_details(pdev);
1522
1523         if (!emif) {
1524                 pr_err("%s: error getting device data\n", __func__);
1525                 goto error;
1526         }
1527
1528         list_add(&emif->node, &device_list);
1529         emif->addressing = get_addressing_table(emif->plat_data->device_info);
1530
1531         /* Save pointers to each other in emif and device structures */
1532         emif->dev = &pdev->dev;
1533         platform_set_drvdata(pdev, emif);
1534
1535         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1536         emif->base = devm_ioremap_resource(emif->dev, res);
1537         if (IS_ERR(emif->base))
1538                 goto error;
1539
1540         irq = platform_get_irq(pdev, 0);
1541         if (irq < 0)
1542                 goto error;
1543
1544         emif_onetime_settings(emif);
1545         emif_debugfs_init(emif);
1546         disable_and_clear_all_interrupts(emif);
1547         setup_interrupts(emif, irq);
1548
1549         /* One-time actions taken on probing the first device */
1550         if (!emif1) {
1551                 emif1 = emif;
1552                 spin_lock_init(&emif_lock);
1553
1554                 /*
1555                  * TODO: register notifiers for frequency and voltage
1556                  * change here once the respective frameworks are
1557                  * available
1558                  */
1559         }
1560
1561         dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
1562                 __func__, emif->base, irq);
1563
1564         return 0;
1565 error:
1566         return -ENODEV;
1567 }
1568
1569 static int __exit emif_remove(struct platform_device *pdev)
1570 {
1571         struct emif_data *emif = platform_get_drvdata(pdev);
1572
1573         emif_debugfs_exit(emif);
1574
1575         return 0;
1576 }
1577
1578 static void emif_shutdown(struct platform_device *pdev)
1579 {
1580         struct emif_data        *emif = platform_get_drvdata(pdev);
1581
1582         disable_and_clear_all_interrupts(emif);
1583 }
1584
1585 static int get_emif_reg_values(struct emif_data *emif, u32 freq,
1586                 struct emif_regs *regs)
1587 {
1588         u32                             ip_rev, phy_type;
1589         u32                             cl, type;
1590         const struct lpddr2_timings     *timings;
1591         const struct lpddr2_min_tck     *min_tck;
1592         const struct ddr_device_info    *device_info;
1593         const struct lpddr2_addressing  *addressing;
1594         struct emif_data                *emif_for_calc;
1595         struct device                   *dev;
1596
1597         dev = emif->dev;
1598         /*
1599          * If the devices on this EMIF instance is duplicate of EMIF1,
1600          * use EMIF1 details for the calculation
1601          */
1602         emif_for_calc   = emif->duplicate ? emif1 : emif;
1603         timings         = get_timings_table(emif_for_calc, freq);
1604         addressing      = emif_for_calc->addressing;
1605         if (!timings || !addressing) {
1606                 dev_err(dev, "%s: not enough data available for %dHz",
1607                         __func__, freq);
1608                 return -1;
1609         }
1610
1611         device_info     = emif_for_calc->plat_data->device_info;
1612         type            = device_info->type;
1613         ip_rev          = emif_for_calc->plat_data->ip_rev;
1614         phy_type        = emif_for_calc->plat_data->phy_type;
1615
1616         min_tck         = emif_for_calc->plat_data->min_tck;
1617
1618         set_ddr_clk_period(freq);
1619
1620         regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing);
1621         regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck,
1622                         addressing);
1623         regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck,
1624                         addressing, type);
1625         regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck,
1626                 addressing, type, ip_rev, EMIF_NORMAL_TIMINGS);
1627
1628         cl = get_cl(emif);
1629
1630         if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) {
1631                 regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
1632                         timings, freq, cl);
1633         } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) {
1634                 regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
1635                 regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5();
1636                 regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5();
1637                 regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5();
1638         } else {
1639                 return -1;
1640         }
1641
1642         /* Only timeout values in pwr_mgmt_ctrl_shdw register */
1643         regs->pwr_mgmt_ctrl_shdw =
1644                 get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) &
1645                 (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK);
1646
1647         if (ip_rev & EMIF_4D) {
1648                 regs->read_idle_ctrl_shdw_normal =
1649                         get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE);
1650
1651                 regs->read_idle_ctrl_shdw_volt_ramp =
1652                         get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1653         } else if (ip_rev & EMIF_4D5) {
1654                 regs->dll_calib_ctrl_shdw_normal =
1655                         get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE);
1656
1657                 regs->dll_calib_ctrl_shdw_volt_ramp =
1658                         get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1659         }
1660
1661         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
1662                 regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4,
1663                         addressing);
1664
1665                 regs->sdram_tim1_shdw_derated =
1666                         get_sdram_tim_1_shdw_derated(timings, min_tck,
1667                                 addressing);
1668
1669                 regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings,
1670                         min_tck, addressing, type, ip_rev,
1671                         EMIF_DERATED_TIMINGS);
1672         }
1673
1674         regs->freq = freq;
1675
1676         return 0;
1677 }
1678
1679 /*
1680  * get_regs() - gets the cached emif_regs structure for a given EMIF instance
1681  * given frequency(freq):
1682  *
1683  * As an optimisation, every EMIF instance other than EMIF1 shares the
1684  * register cache with EMIF1 if the devices connected on this instance
1685  * are same as that on EMIF1(indicated by the duplicate flag)
1686  *
1687  * If we do not have an entry corresponding to the frequency given, we
1688  * allocate a new entry and calculate the values
1689  *
1690  * Upon finding the right reg dump, save it in curr_regs. It can be
1691  * directly used for thermal de-rating and voltage ramping changes.
1692  */
1693 static struct emif_regs *get_regs(struct emif_data *emif, u32 freq)
1694 {
1695         int                     i;
1696         struct emif_regs        **regs_cache;
1697         struct emif_regs        *regs = NULL;
1698         struct device           *dev;
1699
1700         dev = emif->dev;
1701         if (emif->curr_regs && emif->curr_regs->freq == freq) {
1702                 dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq);
1703                 return emif->curr_regs;
1704         }
1705
1706         if (emif->duplicate)
1707                 regs_cache = emif1->regs_cache;
1708         else
1709                 regs_cache = emif->regs_cache;
1710
1711         for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
1712                 if (regs_cache[i]->freq == freq) {
1713                         regs = regs_cache[i];
1714                         dev_dbg(dev,
1715                                 "%s: reg dump found in reg cache for %u Hz\n",
1716                                 __func__, freq);
1717                         break;
1718                 }
1719         }
1720
1721         /*
1722          * If we don't have an entry for this frequency in the cache create one
1723          * and calculate the values
1724          */
1725         if (!regs) {
1726                 regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC);
1727                 if (!regs)
1728                         return NULL;
1729
1730                 if (get_emif_reg_values(emif, freq, regs)) {
1731                         devm_kfree(emif->dev, regs);
1732                         return NULL;
1733                 }
1734
1735                 /*
1736                  * Now look for an un-used entry in the cache and save the
1737                  * newly created struct. If there are no free entries
1738                  * over-write the last entry
1739                  */
1740                 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++)
1741                         ;
1742
1743                 if (i >= EMIF_MAX_NUM_FREQUENCIES) {
1744                         dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n",
1745                                 __func__);
1746                         i = EMIF_MAX_NUM_FREQUENCIES - 1;
1747                         devm_kfree(emif->dev, regs_cache[i]);
1748                 }
1749                 regs_cache[i] = regs;
1750         }
1751
1752         return regs;
1753 }
1754
1755 static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state)
1756 {
1757         dev_dbg(emif->dev, "%s: voltage notification : %d", __func__,
1758                 volt_state);
1759
1760         if (!emif->curr_regs) {
1761                 dev_err(emif->dev,
1762                         "%s: volt-notify before registers are ready: %d\n",
1763                         __func__, volt_state);
1764                 return;
1765         }
1766
1767         setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state);
1768 }
1769
1770 /*
1771  * TODO: voltage notify handling should be hooked up to
1772  * regulator framework as soon as the necessary support
1773  * is available in mainline kernel. This function is un-used
1774  * right now.
1775  */
1776 static void __attribute__((unused)) volt_notify_handling(u32 volt_state)
1777 {
1778         struct emif_data *emif;
1779
1780         spin_lock_irqsave(&emif_lock, irq_state);
1781
1782         list_for_each_entry(emif, &device_list, node)
1783                 do_volt_notify_handling(emif, volt_state);
1784         do_freq_update();
1785
1786         spin_unlock_irqrestore(&emif_lock, irq_state);
1787 }
1788
1789 static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq)
1790 {
1791         struct emif_regs *regs;
1792
1793         regs = get_regs(emif, new_freq);
1794         if (!regs)
1795                 return;
1796
1797         emif->curr_regs = regs;
1798
1799         /*
1800          * Update the shadow registers:
1801          * Temperature and voltage-ramp sensitive settings are also configured
1802          * in terms of DDR cycles. So, we need to update them too when there
1803          * is a freq change
1804          */
1805         dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz",
1806                 __func__, new_freq);
1807         setup_registers(emif, regs);
1808         setup_temperature_sensitive_regs(emif, regs);
1809         setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE);
1810
1811         /*
1812          * Part of workaround for errata i728. See do_freq_update()
1813          * for more details
1814          */
1815         if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1816                 set_lpmode(emif, EMIF_LP_MODE_DISABLE);
1817 }
1818
1819 /*
1820  * TODO: frequency notify handling should be hooked up to
1821  * clock framework as soon as the necessary support is
1822  * available in mainline kernel. This function is un-used
1823  * right now.
1824  */
1825 static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq)
1826 {
1827         struct emif_data *emif;
1828
1829         /*
1830          * NOTE: we are taking the spin-lock here and releases it
1831          * only in post-notifier. This doesn't look good and
1832          * Sparse complains about it, but this seems to be
1833          * un-avoidable. We need to lock a sequence of events
1834          * that is split between EMIF and clock framework.
1835          *
1836          * 1. EMIF driver updates EMIF timings in shadow registers in the
1837          *    frequency pre-notify callback from clock framework
1838          * 2. clock framework sets up the registers for the new frequency
1839          * 3. clock framework initiates a hw-sequence that updates
1840          *    the frequency EMIF timings synchronously.
1841          *
1842          * All these 3 steps should be performed as an atomic operation
1843          * vis-a-vis similar sequence in the EMIF interrupt handler
1844          * for temperature events. Otherwise, there could be race
1845          * conditions that could result in incorrect EMIF timings for
1846          * a given frequency
1847          */
1848         spin_lock_irqsave(&emif_lock, irq_state);
1849
1850         list_for_each_entry(emif, &device_list, node)
1851                 do_freq_pre_notify_handling(emif, new_freq);
1852 }
1853
1854 static void do_freq_post_notify_handling(struct emif_data *emif)
1855 {
1856         /*
1857          * Part of workaround for errata i728. See do_freq_update()
1858          * for more details
1859          */
1860         if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1861                 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
1862 }
1863
1864 /*
1865  * TODO: frequency notify handling should be hooked up to
1866  * clock framework as soon as the necessary support is
1867  * available in mainline kernel. This function is un-used
1868  * right now.
1869  */
1870 static void __attribute__((unused)) freq_post_notify_handling(void)
1871 {
1872         struct emif_data *emif;
1873
1874         list_for_each_entry(emif, &device_list, node)
1875                 do_freq_post_notify_handling(emif);
1876
1877         /*
1878          * Lock is done in pre-notify handler. See freq_pre_notify_handling()
1879          * for more details
1880          */
1881         spin_unlock_irqrestore(&emif_lock, irq_state);
1882 }
1883
1884 #if defined(CONFIG_OF)
1885 static const struct of_device_id emif_of_match[] = {
1886                 { .compatible = "ti,emif-4d" },
1887                 { .compatible = "ti,emif-4d5" },
1888                 {},
1889 };
1890 MODULE_DEVICE_TABLE(of, emif_of_match);
1891 #endif
1892
1893 static struct platform_driver emif_driver = {
1894         .remove         = __exit_p(emif_remove),
1895         .shutdown       = emif_shutdown,
1896         .driver = {
1897                 .name = "emif",
1898                 .of_match_table = of_match_ptr(emif_of_match),
1899         },
1900 };
1901
1902 module_platform_driver_probe(emif_driver, emif_probe);
1903
1904 MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
1905 MODULE_LICENSE("GPL");
1906 MODULE_ALIAS("platform:emif");
1907 MODULE_AUTHOR("Texas Instruments Inc");