1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "Memory Controller drivers"
9 This option allows to enable specific memory controller drivers,
10 useful mostly on embedded systems. These could be controllers
11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
12 vary from memory tuning and frequency scaling to enabling
13 access to attached peripherals through memory bus.
20 Data from JEDEC specs for DDR SDRAM memories,
21 particularly the AC timing parameters and addressing
22 information. This data is useful for drivers handling
23 DDR SDRAM controllers.
26 tristate "ARM PL172 MPMC driver"
27 depends on ARM_AMBA && OF
29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
30 If you have an embedded system with an AMBA bus and a PL172
31 controller, say Y or M here.
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
36 depends on ARCH_AT91 && OF
38 This driver is for Atmel SDRAM Controller or Atmel Multi-port
39 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
40 Starting with the at91sam9g45, this controller supports SDR, DDR and
44 bool "Atmel EBI driver"
46 depends on ARCH_AT91 && OF
50 Driver for Atmel EBI controller.
51 Used to configure the EBI (external bus interface) when the device-
52 tree is used. This bus supports NANDs, external ethernet controller,
53 SRAMs, ATA devices, etc.
56 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
57 depends on MIPS_BAIKAL_T1 || COMPILE_TEST
60 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
61 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
62 possible to tune the L2 cache performance up by setting the data,
63 tags and way-select latencies of RAM access. This driver provides a
64 dt properties-based and sysfs interface for it.
67 tristate "Texas Instruments AEMIF driver"
68 depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
70 This driver is for the AEMIF module available in Texas Instruments
71 SoCs. AEMIF stands for Asynchronous External Memory Interface and
72 is intended to provide a glue-less interface to a variety of
73 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
74 of 256M bytes of any of these memories can be accessed at a given
75 time via four chip selects with 64M byte access per chip select.
78 tristate "Texas Instruments EMIF driver"
79 depends on ARCH_OMAP2PLUS
82 This driver is for the EMIF module available in Texas Instruments
83 SoCs. EMIF is an SDRAM controller that, based on its revision,
84 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
85 This driver takes care of only LPDDR2 memories presently. The
86 functions of the driver includes re-configuring AC timing
87 parameters and other settings during frequency, voltage and
94 This driver is for the General Purpose Memory Controller (GPMC)
95 present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
96 interfacing to a variety of asynchronous as well as synchronous
97 memory drives like NOR, NAND, OneNAND, SRAM.
99 config OMAP_GPMC_DEBUG
100 bool "Enable GPMC debug output and skip reset of GPMC during init"
103 Enables verbose debugging mostly to decode the bootloader provided
104 timings. To preserve the bootloader provided timings, the reset
105 of GPMC is skipped during init. Enable this during development to
106 configure devices connected to the GPMC bus.
108 NOTE: In addition to matching the register setup with the bootloader
109 you also need to match the GPMC FCLK frequency used by the
110 bootloader or else the GPMC timings won't be identical with the
114 tristate "Texas Instruments EMIF SRAM driver"
115 depends on (SOC_AM33XX || SOC_AM43XX) && SRAM
117 This driver is for the EMIF module available on Texas Instruments
118 AM33XX and AM43XX SoCs and is required for PM. Certain parts of
119 the EMIF PM code must run from on-chip SRAM late in the suspend
120 sequence so this driver provides several relocatable PM functions
121 for the SoC PM code to use.
124 bool "Marvell EBU Device Bus Controller"
126 depends on PLAT_ORION && OF
128 This driver is for the Device Bus controller available in some
129 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
130 Armada 370 and Armada XP. This controller allows to handle flash
131 devices such as NOR, NAND, SRAM, and FPGA.
133 config FSL_CORENET_CF
134 tristate "Freescale CoreNet Error Reporting"
135 depends on FSL_SOC_BOOKE
137 Say Y for reporting of errors from the Freescale CoreNet
138 Coherency Fabric. Errors reported include accesses to
139 physical addresses that mapped by no local access window
140 (LAW) or an invalid LAW, as well as bad cache state that
141 represents a coherency violation.
145 depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
149 bool "Ingenic JZ4780 SoC NEMC driver"
151 depends on MIPS || COMPILE_TEST
152 depends on HAS_IOMEM && OF
154 This driver is for the NAND/External Memory Controller (NEMC) in
155 the Ingenic JZ4780. This controller is used to handle external
156 memory devices such as NAND and SRAM.
160 depends on ARCH_MEDIATEK || COMPILE_TEST
162 This driver is for the Memory Controller module in MediaTek SoCs,
163 mainly help enable/disable iommu and control the power domain and
164 clocks for each local arbiter.
167 bool "Texas Instruments da8xx DDR2/mDDR driver"
168 depends on ARCH_DAVINCI_DA8XX
170 This driver is for the DDR2/mDDR Memory Controller present on
171 Texas Instruments da8xx SoCs. It's used to tweak various memory
172 controller configuration options.
175 tristate "ARM PL35X Static Memory Controller(SMC) driver"
180 This driver is for the ARM PL351/PL353 Static Memory
181 Controller(SMC) module.
184 tristate "Renesas RPC-IF driver"
185 depends on ARCH_RENESAS
188 This supports Renesas R-Car Gen3 RPC-IF which provides either SPI
189 host or HyperFlash. You'll have to select individual components
190 under the corresponding menu.
192 source "drivers/memory/samsung/Kconfig"
193 source "drivers/memory/tegra/Kconfig"