drivers/media/usb/pvrusb2/pvrusb2-hdw.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  */
   6
   7 #include <linux/errno.h>
   8 #include <linux/string.h>
   9 #include <linux/slab.h>
  10 #include <linux/module.h>
  11 #include <linux/firmware.h>
  12 #include <linux/videodev2.h>
  13 #include <media/v4l2-common.h>
  14 #include <media/tuner.h>
  15 #include "pvrusb2.h"
  16 #include "pvrusb2-std.h"
  17 #include "pvrusb2-util.h"
  18 #include "pvrusb2-hdw.h"
  19 #include "pvrusb2-i2c-core.h"
  20 #include "pvrusb2-eeprom.h"
  21 #include "pvrusb2-hdw-internal.h"
  22 #include "pvrusb2-encoder.h"
  23 #include "pvrusb2-debug.h"
  24 #include "pvrusb2-fx2-cmd.h"
  25 #include "pvrusb2-wm8775.h"
  26 #include "pvrusb2-video-v4l.h"
  27 #include "pvrusb2-cx2584x-v4l.h"
  28 #include "pvrusb2-cs53l32a.h"
  29 #include "pvrusb2-audio.h"
  30
  31 #define TV_MIN_FREQ     55250000L
  32 #define TV_MAX_FREQ    850000000L
  33
  34 /* This defines a minimum interval that the decoder must remain quiet
  35    before we are allowed to start it running. */
  36 #define TIME_MSEC_DECODER_WAIT 50
  37
  38 /* This defines a minimum interval that the decoder must be allowed to run
  39    before we can safely begin using its streaming output. */
  40 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
  41
  42 /* This defines a minimum interval that the encoder must remain quiet
  43    before we are allowed to configure it. */
  44 #define TIME_MSEC_ENCODER_WAIT 50
  45
  46 /* This defines the minimum interval that the encoder must successfully run
  47    before we consider that the encoder has run at least once since its
  48    firmware has been loaded.  This measurement is in important for cases
  49    where we can't do something until we know that the encoder has been run
  50    at least once. */
  51 #define TIME_MSEC_ENCODER_OK 250
  52
  53 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  54 static DEFINE_MUTEX(pvr2_unit_mtx);
  55
  56 static int ctlchg;
  57 static int procreload;
  58 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  59 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  60 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  61 static int init_pause_msec;
  62
  63 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  64 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  65 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  66 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  67 module_param(procreload, int, S_IRUGO|S_IWUSR);
  68 MODULE_PARM_DESC(procreload,
  69                  "Attempt init failure recovery with firmware reload");
  70 module_param_array(tuner,    int, NULL, 0444);
  71 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  72 module_param_array(video_std,    int, NULL, 0444);
  73 MODULE_PARM_DESC(video_std,"specify initial video standard");
  74 module_param_array(tolerance,    int, NULL, 0444);
  75 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  76
  77 /* US Broadcast channel 3 (61.25 MHz), to help with testing */
  78 static int default_tv_freq    = 61250000L;
  79 /* 104.3 MHz, a usable FM station for my area */
  80 static int default_radio_freq = 104300000L;
  81
  82 module_param_named(tv_freq, default_tv_freq, int, 0444);
  83 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  84 module_param_named(radio_freq, default_radio_freq, int, 0444);
  85 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  86
  87 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  88 #define PVR2_CTL_READ_ENDPOINT   0x81
  89
  90 #define PVR2_GPIO_IN 0x9008
  91 #define PVR2_GPIO_OUT 0x900c
  92 #define PVR2_GPIO_DIR 0x9020
  93
  94 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
  95
  96 #define PVR2_FIRMWARE_ENDPOINT   0x02
  97
  98 /* size of a firmware chunk */
  99 #define FIRMWARE_CHUNK_SIZE 0x2000
 100
 101 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 102                                         struct v4l2_subdev *);
 103
 104 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 105         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 106         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 107         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 108         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 109         [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 110 };
 111
 112 static const char *module_names[] = {
 113         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 114         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 115         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 116         [PVR2_CLIENT_ID_TUNER] = "tuner",
 117         [PVR2_CLIENT_ID_DEMOD] = "tuner",
 118         [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 119         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 120 };
 121
 122
 123 static const unsigned char *module_i2c_addresses[] = {
 124         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 125         [PVR2_CLIENT_ID_DEMOD] = "\x43",
 126         [PVR2_CLIENT_ID_MSP3400] = "\x40",
 127         [PVR2_CLIENT_ID_SAA7115] = "\x21",
 128         [PVR2_CLIENT_ID_WM8775] = "\x1b",
 129         [PVR2_CLIENT_ID_CX25840] = "\x44",
 130         [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 131 };
 132
 133
 134 static const char *ir_scheme_names[] = {
 135         [PVR2_IR_SCHEME_NONE] = "none",
 136         [PVR2_IR_SCHEME_29XXX] = "29xxx",
 137         [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 138         [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 139         [PVR2_IR_SCHEME_ZILOG] = "Zilog",
 140 };
 141
 142
 143 /* Define the list of additional controls we'll dynamically construct based
 144    on query of the cx2341x module. */
 145 struct pvr2_mpeg_ids {
 146         const char *strid;
 147         int id;
 148 };
 149 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 150         {
 151                 .strid = "audio_layer",
 152                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 153         },{
 154                 .strid = "audio_bitrate",
 155                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 156         },{
 157                 /* Already using audio_mode elsewhere :-( */
 158                 .strid = "mpeg_audio_mode",
 159                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 160         },{
 161                 .strid = "mpeg_audio_mode_extension",
 162                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 163         },{
 164                 .strid = "audio_emphasis",
 165                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 166         },{
 167                 .strid = "audio_crc",
 168                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 169         },{
 170                 .strid = "video_aspect",
 171                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 172         },{
 173                 .strid = "video_b_frames",
 174                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 175         },{
 176                 .strid = "video_gop_size",
 177                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 178         },{
 179                 .strid = "video_gop_closure",
 180                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 181         },{
 182                 .strid = "video_bitrate_mode",
 183                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 184         },{
 185                 .strid = "video_bitrate",
 186                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 187         },{
 188                 .strid = "video_bitrate_peak",
 189                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 190         },{
 191                 .strid = "video_temporal_decimation",
 192                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 193         },{
 194                 .strid = "stream_type",
 195                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 196         },{
 197                 .strid = "video_spatial_filter_mode",
 198                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 199         },{
 200                 .strid = "video_spatial_filter",
 201                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 202         },{
 203                 .strid = "video_luma_spatial_filter_type",
 204                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 205         },{
 206                 .strid = "video_chroma_spatial_filter_type",
 207                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 208         },{
 209                 .strid = "video_temporal_filter_mode",
 210                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 211         },{
 212                 .strid = "video_temporal_filter",
 213                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 214         },{
 215                 .strid = "video_median_filter_type",
 216                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 217         },{
 218                 .strid = "video_luma_median_filter_top",
 219                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 220         },{
 221                 .strid = "video_luma_median_filter_bottom",
 222                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 223         },{
 224                 .strid = "video_chroma_median_filter_top",
 225                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 226         },{
 227                 .strid = "video_chroma_median_filter_bottom",
 228                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 229         }
 230 };
 231 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 232
 233
 234 static const char *control_values_srate[] = {
 235         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 236         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 237         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 238 };
 239
 240
 241
 242 static const char *control_values_input[] = {
 243         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 244         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 245         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 246         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 247         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 248 };
 249
 250
 251 static const char *control_values_audiomode[] = {
 252         [V4L2_TUNER_MODE_MONO]   = "Mono",
 253         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 254         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 255         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 256         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 257 };
 258
 259
 260 static const char *control_values_hsm[] = {
 261         [PVR2_CVAL_HSM_FAIL] = "Fail",
 262         [PVR2_CVAL_HSM_HIGH] = "High",
 263         [PVR2_CVAL_HSM_FULL] = "Full",
 264 };
 265
 266
 267 static const char *pvr2_state_names[] = {
 268         [PVR2_STATE_NONE] =    "none",
 269         [PVR2_STATE_DEAD] =    "dead",
 270         [PVR2_STATE_COLD] =    "cold",
 271         [PVR2_STATE_WARM] =    "warm",
 272         [PVR2_STATE_ERROR] =   "error",
 273         [PVR2_STATE_READY] =   "ready",
 274         [PVR2_STATE_RUN] =     "run",
 275 };
 276
 277
 278 struct pvr2_fx2cmd_descdef {
 279         unsigned char id;
 280         unsigned char *desc;
 281 };
 282
 283 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 284         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 285         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 286         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 287         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 288         {FX2CMD_REG_WRITE, "write encoder register"},
 289         {FX2CMD_REG_READ, "read encoder register"},
 290         {FX2CMD_MEMSEL, "encoder memsel"},
 291         {FX2CMD_I2C_WRITE, "i2c write"},
 292         {FX2CMD_I2C_READ, "i2c read"},
 293         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 294         {FX2CMD_STREAMING_ON, "stream on"},
 295         {FX2CMD_STREAMING_OFF, "stream off"},
 296         {FX2CMD_FWPOST1, "fwpost1"},
 297         {FX2CMD_POWER_OFF, "power off"},
 298         {FX2CMD_POWER_ON, "power on"},
 299         {FX2CMD_DEEP_RESET, "deep reset"},
 300         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 301         {FX2CMD_GET_IR_CODE, "get IR code"},
 302         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 303         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 304         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 305         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 306         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 307         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 308         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 309 };
 310
 311
 312 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 313 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 314 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 315 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 316 static void pvr2_hdw_worker_poll(struct work_struct *work);
 317 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 318 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 319 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 320 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 321 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 322 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 323 static void pvr2_hdw_quiescent_timeout(struct timer_list *);
 324 static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *);
 325 static void pvr2_hdw_encoder_wait_timeout(struct timer_list *);
 326 static void pvr2_hdw_encoder_run_timeout(struct timer_list *);
 327 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 328 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 329                                 unsigned int timeout,int probe_fl,
 330                                 void *write_data,unsigned int write_len,
 331                                 void *read_data,unsigned int read_len);
 332 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 333 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
 334
 335 static void trace_stbit(const char *name,int val)
 336 {
 337         pvr2_trace(PVR2_TRACE_STBITS,
 338                    "State bit %s <-- %s",
 339                    name,(val ? "true" : "false"));
 340 }
 341
 342 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 343 {
 344         struct pvr2_hdw *hdw = cptr->hdw;
 345         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 346                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 347         } else {
 348                 *vp = 0;
 349         }
 350         return 0;
 351 }
 352
 353 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 354 {
 355         struct pvr2_hdw *hdw = cptr->hdw;
 356         unsigned int slotId = hdw->freqProgSlot;
 357         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 358                 hdw->freqTable[slotId-1] = v;
 359                 /* Handle side effects correctly - if we're tuned to this
 360                    slot, then forgot the slot id relation since the stored
 361                    frequency has been changed. */
 362                 if (hdw->freqSelector) {
 363                         if (hdw->freqSlotRadio == slotId) {
 364                                 hdw->freqSlotRadio = 0;
 365                         }
 366                 } else {
 367                         if (hdw->freqSlotTelevision == slotId) {
 368                                 hdw->freqSlotTelevision = 0;
 369                         }
 370                 }
 371         }
 372         return 0;
 373 }
 374
 375 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 376 {
 377         *vp = cptr->hdw->freqProgSlot;
 378         return 0;
 379 }
 380
 381 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 382 {
 383         struct pvr2_hdw *hdw = cptr->hdw;
 384         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 385                 hdw->freqProgSlot = v;
 386         }
 387         return 0;
 388 }
 389
 390 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 391 {
 392         struct pvr2_hdw *hdw = cptr->hdw;
 393         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 394         return 0;
 395 }
 396
 397 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 398 {
 399         unsigned freq = 0;
 400         struct pvr2_hdw *hdw = cptr->hdw;
 401         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 402         if (slotId > 0) {
 403                 freq = hdw->freqTable[slotId-1];
 404                 if (!freq) return 0;
 405                 pvr2_hdw_set_cur_freq(hdw,freq);
 406         }
 407         if (hdw->freqSelector) {
 408                 hdw->freqSlotRadio = slotId;
 409         } else {
 410                 hdw->freqSlotTelevision = slotId;
 411         }
 412         return 0;
 413 }
 414
 415 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 416 {
 417         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 418         return 0;
 419 }
 420
 421 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 422 {
 423         return cptr->hdw->freqDirty != 0;
 424 }
 425
 426 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 427 {
 428         cptr->hdw->freqDirty = 0;
 429 }
 430
 431 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 432 {
 433         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 434         return 0;
 435 }
 436
 437 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 438 {
 439         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 440         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 441         if (stat != 0) {
 442                 return stat;
 443         }
 444         *left = cap->bounds.left;
 445         return 0;
 446 }
 447
 448 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 449 {
 450         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 451         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 452         if (stat != 0) {
 453                 return stat;
 454         }
 455         *left = cap->bounds.left;
 456         if (cap->bounds.width > cptr->hdw->cropw_val) {
 457                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 458         }
 459         return 0;
 460 }
 461
 462 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 463 {
 464         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 465         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 466         if (stat != 0) {
 467                 return stat;
 468         }
 469         *top = cap->bounds.top;
 470         return 0;
 471 }
 472
 473 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 474 {
 475         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 476         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 477         if (stat != 0) {
 478                 return stat;
 479         }
 480         *top = cap->bounds.top;
 481         if (cap->bounds.height > cptr->hdw->croph_val) {
 482                 *top += cap->bounds.height - cptr->hdw->croph_val;
 483         }
 484         return 0;
 485 }
 486
 487 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
 488 {
 489         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 490         int stat, bleftend, cleft;
 491
 492         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 493         if (stat != 0) {
 494                 return stat;
 495         }
 496         bleftend = cap->bounds.left+cap->bounds.width;
 497         cleft = cptr->hdw->cropl_val;
 498
 499         *width = cleft < bleftend ? bleftend-cleft : 0;
 500         return 0;
 501 }
 502
 503 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
 504 {
 505         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 506         int stat, btopend, ctop;
 507
 508         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 509         if (stat != 0) {
 510                 return stat;
 511         }
 512         btopend = cap->bounds.top+cap->bounds.height;
 513         ctop = cptr->hdw->cropt_val;
 514
 515         *height = ctop < btopend ? btopend-ctop : 0;
 516         return 0;
 517 }
 518
 519 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 520 {
 521         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 522         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 523         if (stat != 0) {
 524                 return stat;
 525         }
 526         *val = cap->bounds.left;
 527         return 0;
 528 }
 529
 530 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 531 {
 532         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 533         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 534         if (stat != 0) {
 535                 return stat;
 536         }
 537         *val = cap->bounds.top;
 538         return 0;
 539 }
 540
 541 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 542 {
 543         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 544         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 545         if (stat != 0) {
 546                 return stat;
 547         }
 548         *val = cap->bounds.width;
 549         return 0;
 550 }
 551
 552 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 553 {
 554         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 555         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 556         if (stat != 0) {
 557                 return stat;
 558         }
 559         *val = cap->bounds.height;
 560         return 0;
 561 }
 562
 563 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 564 {
 565         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 566         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 567         if (stat != 0) {
 568                 return stat;
 569         }
 570         *val = cap->defrect.left;
 571         return 0;
 572 }
 573
 574 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 575 {
 576         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 577         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 578         if (stat != 0) {
 579                 return stat;
 580         }
 581         *val = cap->defrect.top;
 582         return 0;
 583 }
 584
 585 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 586 {
 587         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 588         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 589         if (stat != 0) {
 590                 return stat;
 591         }
 592         *val = cap->defrect.width;
 593         return 0;
 594 }
 595
 596 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 597 {
 598         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 599         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 600         if (stat != 0) {
 601                 return stat;
 602         }
 603         *val = cap->defrect.height;
 604         return 0;
 605 }
 606
 607 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 608 {
 609         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 610         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 611         if (stat != 0) {
 612                 return stat;
 613         }
 614         *val = cap->pixelaspect.numerator;
 615         return 0;
 616 }
 617
 618 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 619 {
 620         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 621         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 622         if (stat != 0) {
 623                 return stat;
 624         }
 625         *val = cap->pixelaspect.denominator;
 626         return 0;
 627 }
 628
 629 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 630 {
 631         /* Actual maximum depends on the video standard in effect. */
 632         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 633                 *vp = 480;
 634         } else {
 635                 *vp = 576;
 636         }
 637         return 0;
 638 }
 639
 640 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 641 {
 642         /* Actual minimum depends on device digitizer type. */
 643         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 644                 *vp = 75;
 645         } else {
 646                 *vp = 17;
 647         }
 648         return 0;
 649 }
 650
 651 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 652 {
 653         *vp = cptr->hdw->input_val;
 654         return 0;
 655 }
 656
 657 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 658 {
 659         if (v < 0 || v > PVR2_CVAL_INPUT_MAX)
 660                 return 0;
 661         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 662 }
 663
 664 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 665 {
 666         return pvr2_hdw_set_input(cptr->hdw,v);
 667 }
 668
 669 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 670 {
 671         return cptr->hdw->input_dirty != 0;
 672 }
 673
 674 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 675 {
 676         cptr->hdw->input_dirty = 0;
 677 }
 678
 679
 680 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 681 {
 682         unsigned long fv;
 683         struct pvr2_hdw *hdw = cptr->hdw;
 684         if (hdw->tuner_signal_stale) {
 685                 pvr2_hdw_status_poll(hdw);
 686         }
 687         fv = hdw->tuner_signal_info.rangehigh;
 688         if (!fv) {
 689                 /* Safety fallback */
 690                 *vp = TV_MAX_FREQ;
 691                 return 0;
 692         }
 693         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 694                 fv = (fv * 125) / 2;
 695         } else {
 696                 fv = fv * 62500;
 697         }
 698         *vp = fv;
 699         return 0;
 700 }
 701
 702 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 703 {
 704         unsigned long fv;
 705         struct pvr2_hdw *hdw = cptr->hdw;
 706         if (hdw->tuner_signal_stale) {
 707                 pvr2_hdw_status_poll(hdw);
 708         }
 709         fv = hdw->tuner_signal_info.rangelow;
 710         if (!fv) {
 711                 /* Safety fallback */
 712                 *vp = TV_MIN_FREQ;
 713                 return 0;
 714         }
 715         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 716                 fv = (fv * 125) / 2;
 717         } else {
 718                 fv = fv * 62500;
 719         }
 720         *vp = fv;
 721         return 0;
 722 }
 723
 724 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 725 {
 726         return cptr->hdw->enc_stale != 0;
 727 }
 728
 729 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 730 {
 731         cptr->hdw->enc_stale = 0;
 732         cptr->hdw->enc_unsafe_stale = 0;
 733 }
 734
 735 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 736 {
 737         int ret;
 738         struct v4l2_ext_controls cs;
 739         struct v4l2_ext_control c1;
 740         memset(&cs,0,sizeof(cs));
 741         memset(&c1,0,sizeof(c1));
 742         cs.controls = &c1;
 743         cs.count = 1;
 744         c1.id = cptr->info->v4l_id;
 745         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 746                                 VIDIOC_G_EXT_CTRLS);
 747         if (ret) return ret;
 748         *vp = c1.value;
 749         return 0;
 750 }
 751
 752 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 753 {
 754         int ret;
 755         struct pvr2_hdw *hdw = cptr->hdw;
 756         struct v4l2_ext_controls cs;
 757         struct v4l2_ext_control c1;
 758         memset(&cs,0,sizeof(cs));
 759         memset(&c1,0,sizeof(c1));
 760         cs.controls = &c1;
 761         cs.count = 1;
 762         c1.id = cptr->info->v4l_id;
 763         c1.value = v;
 764         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 765                                 hdw->state_encoder_run, &cs,
 766                                 VIDIOC_S_EXT_CTRLS);
 767         if (ret == -EBUSY) {
 768                 /* Oops.  cx2341x is telling us it's not safe to change
 769                    this control while we're capturing.  Make a note of this
 770                    fact so that the pipeline will be stopped the next time
 771                    controls are committed.  Then go on ahead and store this
 772                    change anyway. */
 773                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 774                                         0, &cs,
 775                                         VIDIOC_S_EXT_CTRLS);
 776                 if (!ret) hdw->enc_unsafe_stale = !0;
 777         }
 778         if (ret) return ret;
 779         hdw->enc_stale = !0;
 780         return 0;
 781 }
 782
 783 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 784 {
 785         struct v4l2_queryctrl qctrl;
 786         struct pvr2_ctl_info *info;
 787         qctrl.id = cptr->info->v4l_id;
 788         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 789         /* Strip out the const so we can adjust a function pointer.  It's
 790            OK to do this here because we know this is a dynamically created
 791            control, so the underlying storage for the info pointer is (a)
 792            private to us, and (b) not in read-only storage.  Either we do
 793            this or we significantly complicate the underlying control
 794            implementation. */
 795         info = (struct pvr2_ctl_info *)(cptr->info);
 796         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 797                 if (info->set_value) {
 798                         info->set_value = NULL;
 799                 }
 800         } else {
 801                 if (!(info->set_value)) {
 802                         info->set_value = ctrl_cx2341x_set;
 803                 }
 804         }
 805         return qctrl.flags;
 806 }
 807
 808 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 809 {
 810         *vp = cptr->hdw->state_pipeline_req;
 811         return 0;
 812 }
 813
 814 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 815 {
 816         *vp = cptr->hdw->master_state;
 817         return 0;
 818 }
 819
 820 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 821 {
 822         int result = pvr2_hdw_is_hsm(cptr->hdw);
 823         *vp = PVR2_CVAL_HSM_FULL;
 824         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 825         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 826         return 0;
 827 }
 828
 829 static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
 830 {
 831         *vp = pvr2_hdw_get_detected_std(cptr->hdw);
 832         return 0;
 833 }
 834
 835 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 836 {
 837         *vp = cptr->hdw->std_mask_avail;
 838         return 0;
 839 }
 840
 841 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 842 {
 843         struct pvr2_hdw *hdw = cptr->hdw;
 844         v4l2_std_id ns;
 845         ns = hdw->std_mask_avail;
 846         ns = (ns & ~m) | (v & m);
 847         if (ns == hdw->std_mask_avail) return 0;
 848         hdw->std_mask_avail = ns;
 849         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
 850         return 0;
 851 }
 852
 853 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 854                                char *bufPtr,unsigned int bufSize,
 855                                unsigned int *len)
 856 {
 857         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 858         return 0;
 859 }
 860
 861 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 862                                const char *bufPtr,unsigned int bufSize,
 863                                int *mskp,int *valp)
 864 {
 865         int ret;
 866         v4l2_std_id id;
 867         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 868         if (ret < 0) return ret;
 869         if (mskp) *mskp = id;
 870         if (valp) *valp = id;
 871         return 0;
 872 }
 873
 874 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 875 {
 876         *vp = cptr->hdw->std_mask_cur;
 877         return 0;
 878 }
 879
 880 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 881 {
 882         struct pvr2_hdw *hdw = cptr->hdw;
 883         v4l2_std_id ns;
 884         ns = hdw->std_mask_cur;
 885         ns = (ns & ~m) | (v & m);
 886         if (ns == hdw->std_mask_cur) return 0;
 887         hdw->std_mask_cur = ns;
 888         hdw->std_dirty = !0;
 889         return 0;
 890 }
 891
 892 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 893 {
 894         return cptr->hdw->std_dirty != 0;
 895 }
 896
 897 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 898 {
 899         cptr->hdw->std_dirty = 0;
 900 }
 901
 902 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 903 {
 904         struct pvr2_hdw *hdw = cptr->hdw;
 905         pvr2_hdw_status_poll(hdw);
 906         *vp = hdw->tuner_signal_info.signal;
 907         return 0;
 908 }
 909
 910 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 911 {
 912         int val = 0;
 913         unsigned int subchan;
 914         struct pvr2_hdw *hdw = cptr->hdw;
 915         pvr2_hdw_status_poll(hdw);
 916         subchan = hdw->tuner_signal_info.rxsubchans;
 917         if (subchan & V4L2_TUNER_SUB_MONO) {
 918                 val |= (1 << V4L2_TUNER_MODE_MONO);
 919         }
 920         if (subchan & V4L2_TUNER_SUB_STEREO) {
 921                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 922         }
 923         if (subchan & V4L2_TUNER_SUB_LANG1) {
 924                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 925         }
 926         if (subchan & V4L2_TUNER_SUB_LANG2) {
 927                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 928         }
 929         *vp = val;
 930         return 0;
 931 }
 932
 933
 934 #define DEFINT(vmin,vmax) \
 935         .type = pvr2_ctl_int, \
 936         .def.type_int.min_value = vmin, \
 937         .def.type_int.max_value = vmax
 938
 939 #define DEFENUM(tab) \
 940         .type = pvr2_ctl_enum, \
 941         .def.type_enum.count = ARRAY_SIZE(tab), \
 942         .def.type_enum.value_names = tab
 943
 944 #define DEFBOOL \
 945         .type = pvr2_ctl_bool
 946
 947 #define DEFMASK(msk,tab) \
 948         .type = pvr2_ctl_bitmask, \
 949         .def.type_bitmask.valid_bits = msk, \
 950         .def.type_bitmask.bit_names = tab
 951
 952 #define DEFREF(vname) \
 953         .set_value = ctrl_set_##vname, \
 954         .get_value = ctrl_get_##vname, \
 955         .is_dirty = ctrl_isdirty_##vname, \
 956         .clear_dirty = ctrl_cleardirty_##vname
 957
 958
 959 #define VCREATE_FUNCS(vname) \
 960 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 961 {*vp = cptr->hdw->vname##_val; return 0;} \
 962 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 963 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 964 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 965 {return cptr->hdw->vname##_dirty != 0;} \
 966 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 967 {cptr->hdw->vname##_dirty = 0;}
 968
 969 VCREATE_FUNCS(brightness)
 970 VCREATE_FUNCS(contrast)
 971 VCREATE_FUNCS(saturation)
 972 VCREATE_FUNCS(hue)
 973 VCREATE_FUNCS(volume)
 974 VCREATE_FUNCS(balance)
 975 VCREATE_FUNCS(bass)
 976 VCREATE_FUNCS(treble)
 977 VCREATE_FUNCS(mute)
 978 VCREATE_FUNCS(cropl)
 979 VCREATE_FUNCS(cropt)
 980 VCREATE_FUNCS(cropw)
 981 VCREATE_FUNCS(croph)
 982 VCREATE_FUNCS(audiomode)
 983 VCREATE_FUNCS(res_hor)
 984 VCREATE_FUNCS(res_ver)
 985 VCREATE_FUNCS(srate)
 986
 987 /* Table definition of all controls which can be manipulated */
 988 static const struct pvr2_ctl_info control_defs[] = {
 989         {
 990                 .v4l_id = V4L2_CID_BRIGHTNESS,
 991                 .desc = "Brightness",
 992                 .name = "brightness",
 993                 .default_value = 128,
 994                 DEFREF(brightness),
 995                 DEFINT(0,255),
 996         },{
 997                 .v4l_id = V4L2_CID_CONTRAST,
 998                 .desc = "Contrast",
 999                 .name = "contrast",
1000                 .default_value = 68,
1001                 DEFREF(contrast),
1002                 DEFINT(0,127),
1003         },{
1004                 .v4l_id = V4L2_CID_SATURATION,
1005                 .desc = "Saturation",
1006                 .name = "saturation",
1007                 .default_value = 64,
1008                 DEFREF(saturation),
1009                 DEFINT(0,127),
1010         },{
1011                 .v4l_id = V4L2_CID_HUE,
1012                 .desc = "Hue",
1013                 .name = "hue",
1014                 .default_value = 0,
1015                 DEFREF(hue),
1016                 DEFINT(-128,127),
1017         },{
1018                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1019                 .desc = "Volume",
1020                 .name = "volume",
1021                 .default_value = 62000,
1022                 DEFREF(volume),
1023                 DEFINT(0,65535),
1024         },{
1025                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1026                 .desc = "Balance",
1027                 .name = "balance",
1028                 .default_value = 0,
1029                 DEFREF(balance),
1030                 DEFINT(-32768,32767),
1031         },{
1032                 .v4l_id = V4L2_CID_AUDIO_BASS,
1033                 .desc = "Bass",
1034                 .name = "bass",
1035                 .default_value = 0,
1036                 DEFREF(bass),
1037                 DEFINT(-32768,32767),
1038         },{
1039                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1040                 .desc = "Treble",
1041                 .name = "treble",
1042                 .default_value = 0,
1043                 DEFREF(treble),
1044                 DEFINT(-32768,32767),
1045         },{
1046                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1047                 .desc = "Mute",
1048                 .name = "mute",
1049                 .default_value = 0,
1050                 DEFREF(mute),
1051                 DEFBOOL,
1052         }, {
1053                 .desc = "Capture crop left margin",
1054                 .name = "crop_left",
1055                 .internal_id = PVR2_CID_CROPL,
1056                 .default_value = 0,
1057                 DEFREF(cropl),
1058                 DEFINT(-129, 340),
1059                 .get_min_value = ctrl_cropl_min_get,
1060                 .get_max_value = ctrl_cropl_max_get,
1061                 .get_def_value = ctrl_get_cropcapdl,
1062         }, {
1063                 .desc = "Capture crop top margin",
1064                 .name = "crop_top",
1065                 .internal_id = PVR2_CID_CROPT,
1066                 .default_value = 0,
1067                 DEFREF(cropt),
1068                 DEFINT(-35, 544),
1069                 .get_min_value = ctrl_cropt_min_get,
1070                 .get_max_value = ctrl_cropt_max_get,
1071                 .get_def_value = ctrl_get_cropcapdt,
1072         }, {
1073                 .desc = "Capture crop width",
1074                 .name = "crop_width",
1075                 .internal_id = PVR2_CID_CROPW,
1076                 .default_value = 720,
1077                 DEFREF(cropw),
1078                 DEFINT(0, 864),
1079                 .get_max_value = ctrl_cropw_max_get,
1080                 .get_def_value = ctrl_get_cropcapdw,
1081         }, {
1082                 .desc = "Capture crop height",
1083                 .name = "crop_height",
1084                 .internal_id = PVR2_CID_CROPH,
1085                 .default_value = 480,
1086                 DEFREF(croph),
1087                 DEFINT(0, 576),
1088                 .get_max_value = ctrl_croph_max_get,
1089                 .get_def_value = ctrl_get_cropcapdh,
1090         }, {
1091                 .desc = "Capture capability pixel aspect numerator",
1092                 .name = "cropcap_pixel_numerator",
1093                 .internal_id = PVR2_CID_CROPCAPPAN,
1094                 .get_value = ctrl_get_cropcappan,
1095         }, {
1096                 .desc = "Capture capability pixel aspect denominator",
1097                 .name = "cropcap_pixel_denominator",
1098                 .internal_id = PVR2_CID_CROPCAPPAD,
1099                 .get_value = ctrl_get_cropcappad,
1100         }, {
1101                 .desc = "Capture capability bounds top",
1102                 .name = "cropcap_bounds_top",
1103                 .internal_id = PVR2_CID_CROPCAPBT,
1104                 .get_value = ctrl_get_cropcapbt,
1105         }, {
1106                 .desc = "Capture capability bounds left",
1107                 .name = "cropcap_bounds_left",
1108                 .internal_id = PVR2_CID_CROPCAPBL,
1109                 .get_value = ctrl_get_cropcapbl,
1110         }, {
1111                 .desc = "Capture capability bounds width",
1112                 .name = "cropcap_bounds_width",
1113                 .internal_id = PVR2_CID_CROPCAPBW,
1114                 .get_value = ctrl_get_cropcapbw,
1115         }, {
1116                 .desc = "Capture capability bounds height",
1117                 .name = "cropcap_bounds_height",
1118                 .internal_id = PVR2_CID_CROPCAPBH,
1119                 .get_value = ctrl_get_cropcapbh,
1120         },{
1121                 .desc = "Video Source",
1122                 .name = "input",
1123                 .internal_id = PVR2_CID_INPUT,
1124                 .default_value = PVR2_CVAL_INPUT_TV,
1125                 .check_value = ctrl_check_input,
1126                 DEFREF(input),
1127                 DEFENUM(control_values_input),
1128         },{
1129                 .desc = "Audio Mode",
1130                 .name = "audio_mode",
1131                 .internal_id = PVR2_CID_AUDIOMODE,
1132                 .default_value = V4L2_TUNER_MODE_STEREO,
1133                 DEFREF(audiomode),
1134                 DEFENUM(control_values_audiomode),
1135         },{
1136                 .desc = "Horizontal capture resolution",
1137                 .name = "resolution_hor",
1138                 .internal_id = PVR2_CID_HRES,
1139                 .default_value = 720,
1140                 DEFREF(res_hor),
1141                 DEFINT(19,720),
1142         },{
1143                 .desc = "Vertical capture resolution",
1144                 .name = "resolution_ver",
1145                 .internal_id = PVR2_CID_VRES,
1146                 .default_value = 480,
1147                 DEFREF(res_ver),
1148                 DEFINT(17,576),
1149                 /* Hook in check for video standard and adjust maximum
1150                    depending on the standard. */
1151                 .get_max_value = ctrl_vres_max_get,
1152                 .get_min_value = ctrl_vres_min_get,
1153         },{
1154                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1155                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1156                 .desc = "Audio Sampling Frequency",
1157                 .name = "srate",
1158                 DEFREF(srate),
1159                 DEFENUM(control_values_srate),
1160         },{
1161                 .desc = "Tuner Frequency (Hz)",
1162                 .name = "frequency",
1163                 .internal_id = PVR2_CID_FREQUENCY,
1164                 .default_value = 0,
1165                 .set_value = ctrl_freq_set,
1166                 .get_value = ctrl_freq_get,
1167                 .is_dirty = ctrl_freq_is_dirty,
1168                 .clear_dirty = ctrl_freq_clear_dirty,
1169                 DEFINT(0,0),
1170                 /* Hook in check for input value (tv/radio) and adjust
1171                    max/min values accordingly */
1172                 .get_max_value = ctrl_freq_max_get,
1173                 .get_min_value = ctrl_freq_min_get,
1174         },{
1175                 .desc = "Channel",
1176                 .name = "channel",
1177                 .set_value = ctrl_channel_set,
1178                 .get_value = ctrl_channel_get,
1179                 DEFINT(0,FREQTABLE_SIZE),
1180         },{
1181                 .desc = "Channel Program Frequency",
1182                 .name = "freq_table_value",
1183                 .set_value = ctrl_channelfreq_set,
1184                 .get_value = ctrl_channelfreq_get,
1185                 DEFINT(0,0),
1186                 /* Hook in check for input value (tv/radio) and adjust
1187                    max/min values accordingly */
1188                 .get_max_value = ctrl_freq_max_get,
1189                 .get_min_value = ctrl_freq_min_get,
1190         },{
1191                 .desc = "Channel Program ID",
1192                 .name = "freq_table_channel",
1193                 .set_value = ctrl_channelprog_set,
1194                 .get_value = ctrl_channelprog_get,
1195                 DEFINT(0,FREQTABLE_SIZE),
1196         },{
1197                 .desc = "Streaming Enabled",
1198                 .name = "streaming_enabled",
1199                 .get_value = ctrl_streamingenabled_get,
1200                 DEFBOOL,
1201         },{
1202                 .desc = "USB Speed",
1203                 .name = "usb_speed",
1204                 .get_value = ctrl_hsm_get,
1205                 DEFENUM(control_values_hsm),
1206         },{
1207                 .desc = "Master State",
1208                 .name = "master_state",
1209                 .get_value = ctrl_masterstate_get,
1210                 DEFENUM(pvr2_state_names),
1211         },{
1212                 .desc = "Signal Present",
1213                 .name = "signal_present",
1214                 .get_value = ctrl_signal_get,
1215                 DEFINT(0,65535),
1216         },{
1217                 .desc = "Audio Modes Present",
1218                 .name = "audio_modes_present",
1219                 .get_value = ctrl_audio_modes_present_get,
1220                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1221                    v4l.  Nothing outside of this module cares about this,
1222                    but I reuse it in order to also reuse the
1223                    control_values_audiomode string table. */
1224                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1225                          (1 << V4L2_TUNER_MODE_STEREO)|
1226                          (1 << V4L2_TUNER_MODE_LANG1)|
1227                          (1 << V4L2_TUNER_MODE_LANG2)),
1228                         control_values_audiomode),
1229         },{
1230                 .desc = "Video Standards Available Mask",
1231                 .name = "video_standard_mask_available",
1232                 .internal_id = PVR2_CID_STDAVAIL,
1233                 .skip_init = !0,
1234                 .get_value = ctrl_stdavail_get,
1235                 .set_value = ctrl_stdavail_set,
1236                 .val_to_sym = ctrl_std_val_to_sym,
1237                 .sym_to_val = ctrl_std_sym_to_val,
1238                 .type = pvr2_ctl_bitmask,
1239         },{
1240                 .desc = "Video Standards In Use Mask",
1241                 .name = "video_standard_mask_active",
1242                 .internal_id = PVR2_CID_STDCUR,
1243                 .skip_init = !0,
1244                 .get_value = ctrl_stdcur_get,
1245                 .set_value = ctrl_stdcur_set,
1246                 .is_dirty = ctrl_stdcur_is_dirty,
1247                 .clear_dirty = ctrl_stdcur_clear_dirty,
1248                 .val_to_sym = ctrl_std_val_to_sym,
1249                 .sym_to_val = ctrl_std_sym_to_val,
1250                 .type = pvr2_ctl_bitmask,
1251         },{
1252                 .desc = "Video Standards Detected Mask",
1253                 .name = "video_standard_mask_detected",
1254                 .internal_id = PVR2_CID_STDDETECT,
1255                 .skip_init = !0,
1256                 .get_value = ctrl_stddetect_get,
1257                 .val_to_sym = ctrl_std_val_to_sym,
1258                 .sym_to_val = ctrl_std_sym_to_val,
1259                 .type = pvr2_ctl_bitmask,
1260         }
1261 };
1262
1263 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1264
1265
1266 const char *pvr2_config_get_name(enum pvr2_config cfg)
1267 {
1268         switch (cfg) {
1269         case pvr2_config_empty: return "empty";
1270         case pvr2_config_mpeg: return "mpeg";
1271         case pvr2_config_vbi: return "vbi";
1272         case pvr2_config_pcm: return "pcm";
1273         case pvr2_config_rawvideo: return "raw video";
1274         }
1275         return "<unknown>";
1276 }
1277
1278
1279 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1280 {
1281         return hdw->usb_dev;
1282 }
1283
1284
1285 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1286 {
1287         return hdw->serial_number;
1288 }
1289
1290
1291 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1292 {
1293         return hdw->bus_info;
1294 }
1295
1296
1297 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1298 {
1299         return hdw->identifier;
1300 }
1301
1302
1303 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1304 {
1305         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1306 }
1307
1308 /* Set the currently tuned frequency and account for all possible
1309    driver-core side effects of this action. */
1310 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1311 {
1312         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1313                 if (hdw->freqSelector) {
1314                         /* Swing over to radio frequency selection */
1315                         hdw->freqSelector = 0;
1316                         hdw->freqDirty = !0;
1317                 }
1318                 if (hdw->freqValRadio != val) {
1319                         hdw->freqValRadio = val;
1320                         hdw->freqSlotRadio = 0;
1321                         hdw->freqDirty = !0;
1322                 }
1323         } else {
1324                 if (!(hdw->freqSelector)) {
1325                         /* Swing over to television frequency selection */
1326                         hdw->freqSelector = 1;
1327                         hdw->freqDirty = !0;
1328                 }
1329                 if (hdw->freqValTelevision != val) {
1330                         hdw->freqValTelevision = val;
1331                         hdw->freqSlotTelevision = 0;
1332                         hdw->freqDirty = !0;
1333                 }
1334         }
1335 }
1336
1337 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1338 {
1339         return hdw->unit_number;
1340 }
1341
1342
1343 /* Attempt to locate one of the given set of files.  Messages are logged
1344    appropriate to what has been found.  The return value will be 0 or
1345    greater on success (it will be the index of the file name found) and
1346    fw_entry will be filled in.  Otherwise a negative error is returned on
1347    failure.  If the return value is -ENOENT then no viable firmware file
1348    could be located. */
1349 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1350                                 const struct firmware **fw_entry,
1351                                 const char *fwtypename,
1352                                 unsigned int fwcount,
1353                                 const char *fwnames[])
1354 {
1355         unsigned int idx;
1356         int ret = -EINVAL;
1357         for (idx = 0; idx < fwcount; idx++) {
1358                 ret = request_firmware(fw_entry,
1359                                        fwnames[idx],
1360                                        &hdw->usb_dev->dev);
1361                 if (!ret) {
1362                         trace_firmware("Located %s firmware: %s; uploading...",
1363                                        fwtypename,
1364                                        fwnames[idx]);
1365                         return idx;
1366                 }
1367                 if (ret == -ENOENT) continue;
1368                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1369                            "request_firmware fatal error with code=%d",ret);
1370                 return ret;
1371         }
1372         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1373                    "***WARNING*** Device %s firmware seems to be missing.",
1374                    fwtypename);
1375         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1376                    "Did you install the pvrusb2 firmware files in their proper location?");
1377         if (fwcount == 1) {
1378                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1379                            "request_firmware unable to locate %s file %s",
1380                            fwtypename,fwnames[0]);
1381         } else {
1382                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1383                            "request_firmware unable to locate one of the following %s files:",
1384                            fwtypename);
1385                 for (idx = 0; idx < fwcount; idx++) {
1386                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1387                                    "request_firmware: Failed to find %s",
1388                                    fwnames[idx]);
1389                 }
1390         }
1391         return ret;
1392 }
1393
1394
1395 /*
1396  * pvr2_upload_firmware1().
1397  *
1398  * Send the 8051 firmware to the device.  After the upload, arrange for
1399  * device to re-enumerate.
1400  *
1401  * NOTE : the pointer to the firmware data given by request_firmware()
1402  * is not suitable for an usb transaction.
1403  *
1404  */
1405 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1406 {
1407         const struct firmware *fw_entry = NULL;
1408         void  *fw_ptr;
1409         unsigned int pipe;
1410         unsigned int fwsize;
1411         int ret;
1412         u16 address;
1413
1414         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1415                 hdw->fw1_state = FW1_STATE_OK;
1416                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1417                            "Connected device type defines no firmware to upload; ignoring firmware");
1418                 return -ENOTTY;
1419         }
1420
1421         hdw->fw1_state = FW1_STATE_FAILED; // default result
1422
1423         trace_firmware("pvr2_upload_firmware1");
1424
1425         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1426                                    hdw->hdw_desc->fx2_firmware.cnt,
1427                                    hdw->hdw_desc->fx2_firmware.lst);
1428         if (ret < 0) {
1429                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1430                 return ret;
1431         }
1432
1433         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1434
1435         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1436         fwsize = fw_entry->size;
1437
1438         if ((fwsize != 0x2000) &&
1439             (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1440                 if (hdw->hdw_desc->flag_fx2_16kb) {
1441                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1442                                    "Wrong fx2 firmware size (expected 8192 or 16384, got %u)",
1443                                    fwsize);
1444                 } else {
1445                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1446                                    "Wrong fx2 firmware size (expected 8192, got %u)",
1447                                    fwsize);
1448                 }
1449                 release_firmware(fw_entry);
1450                 return -ENOMEM;
1451         }
1452
1453         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1454         if (fw_ptr == NULL){
1455                 release_firmware(fw_entry);
1456                 return -ENOMEM;
1457         }
1458
1459         /* We have to hold the CPU during firmware upload. */
1460         pvr2_hdw_cpureset_assert(hdw,1);
1461
1462         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1463            chunk. */
1464
1465         ret = 0;
1466         for (address = 0; address < fwsize; address += 0x800) {
1467                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1468                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1469                                        0, fw_ptr, 0x800, HZ);
1470         }
1471
1472         trace_firmware("Upload done, releasing device's CPU");
1473
1474         /* Now release the CPU.  It will disconnect and reconnect later. */
1475         pvr2_hdw_cpureset_assert(hdw,0);
1476
1477         kfree(fw_ptr);
1478         release_firmware(fw_entry);
1479
1480         trace_firmware("Upload done (%d bytes sent)",ret);
1481
1482         /* We should have written fwsize bytes */
1483         if (ret == fwsize) {
1484                 hdw->fw1_state = FW1_STATE_RELOAD;
1485                 return 0;
1486         }
1487
1488         return -EIO;
1489 }
1490
1491
1492 /*
1493  * pvr2_upload_firmware2()
1494  *
1495  * This uploads encoder firmware on endpoint 2.
1496  *
1497  */
1498
1499 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1500 {
1501         const struct firmware *fw_entry = NULL;
1502         void  *fw_ptr;
1503         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1504         int actual_length;
1505         int ret = 0;
1506         int fwidx;
1507         static const char *fw_files[] = {
1508                 CX2341X_FIRM_ENC_FILENAME,
1509         };
1510
1511         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1512                 return 0;
1513         }
1514
1515         trace_firmware("pvr2_upload_firmware2");
1516
1517         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1518                                    ARRAY_SIZE(fw_files), fw_files);
1519         if (ret < 0) return ret;
1520         fwidx = ret;
1521         ret = 0;
1522         /* Since we're about to completely reinitialize the encoder,
1523            invalidate our cached copy of its configuration state.  Next
1524            time we configure the encoder, then we'll fully configure it. */
1525         hdw->enc_cur_valid = 0;
1526
1527         /* Encoder is about to be reset so note that as far as we're
1528            concerned now, the encoder has never been run. */
1529         del_timer_sync(&hdw->encoder_run_timer);
1530         if (hdw->state_encoder_runok) {
1531                 hdw->state_encoder_runok = 0;
1532                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1533         }
1534
1535         /* First prepare firmware loading */
1536         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1537         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1538         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1539         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1540         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1541         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1542         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1543         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1544         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1545         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1546         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1547         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1548         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1549         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1550         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1551         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1552         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1553         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1554
1555         if (ret) {
1556                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1557                            "firmware2 upload prep failed, ret=%d",ret);
1558                 release_firmware(fw_entry);
1559                 goto done;
1560         }
1561
1562         /* Now send firmware */
1563
1564         fw_len = fw_entry->size;
1565
1566         if (fw_len % sizeof(u32)) {
1567                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1568                            "size of %s firmware must be a multiple of %zu bytes",
1569                            fw_files[fwidx],sizeof(u32));
1570                 release_firmware(fw_entry);
1571                 ret = -EINVAL;
1572                 goto done;
1573         }
1574
1575         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1576         if (fw_ptr == NULL){
1577                 release_firmware(fw_entry);
1578                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1579                            "failed to allocate memory for firmware2 upload");
1580                 ret = -ENOMEM;
1581                 goto done;
1582         }
1583
1584         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1585
1586         fw_done = 0;
1587         for (fw_done = 0; fw_done < fw_len;) {
1588                 bcnt = fw_len - fw_done;
1589                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1590                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1591                 /* Usbsnoop log shows that we must swap bytes... */
1592                 /* Some background info: The data being swapped here is a
1593                    firmware image destined for the mpeg encoder chip that
1594                    lives at the other end of a USB endpoint.  The encoder
1595                    chip always talks in 32 bit chunks and its storage is
1596                    organized into 32 bit words.  However from the file
1597                    system to the encoder chip everything is purely a byte
1598                    stream.  The firmware file's contents are always 32 bit
1599                    swapped from what the encoder expects.  Thus the need
1600                    always exists to swap the bytes regardless of the endian
1601                    type of the host processor and therefore swab32() makes
1602                    the most sense. */
1603                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1604                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1605
1606                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1607                                     &actual_length, HZ);
1608                 ret |= (actual_length != bcnt);
1609                 if (ret) break;
1610                 fw_done += bcnt;
1611         }
1612
1613         trace_firmware("upload of %s : %i / %i ",
1614                        fw_files[fwidx],fw_done,fw_len);
1615
1616         kfree(fw_ptr);
1617         release_firmware(fw_entry);
1618
1619         if (ret) {
1620                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1621                            "firmware2 upload transfer failure");
1622                 goto done;
1623         }
1624
1625         /* Finish upload */
1626
1627         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1628         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1629         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1630
1631         if (ret) {
1632                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1633                            "firmware2 upload post-proc failure");
1634         }
1635
1636  done:
1637         if (hdw->hdw_desc->signal_routing_scheme ==
1638             PVR2_ROUTING_SCHEME_GOTVIEW) {
1639                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1640                    hardware. */
1641                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1642         }
1643         return ret;
1644 }
1645
1646
1647 static const char *pvr2_get_state_name(unsigned int st)
1648 {
1649         if (st < ARRAY_SIZE(pvr2_state_names)) {
1650                 return pvr2_state_names[st];
1651         }
1652         return "???";
1653 }
1654
1655 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1656 {
1657         /* Even though we really only care about the video decoder chip at
1658            this point, we'll broadcast stream on/off to all sub-devices
1659            anyway, just in case somebody else wants to hear the
1660            command... */
1661         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1662                    (enablefl ? "on" : "off"));
1663         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1664         v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1665         if (hdw->decoder_client_id) {
1666                 /* We get here if the encoder has been noticed.  Otherwise
1667                    we'll issue a warning to the user (which should
1668                    normally never happen). */
1669                 return 0;
1670         }
1671         if (!hdw->flag_decoder_missed) {
1672                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1673                            "WARNING: No decoder present");
1674                 hdw->flag_decoder_missed = !0;
1675                 trace_stbit("flag_decoder_missed",
1676                             hdw->flag_decoder_missed);
1677         }
1678         return -EIO;
1679 }
1680
1681
1682 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1683 {
1684         return hdw->master_state;
1685 }
1686
1687
1688 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1689 {
1690         if (!hdw->flag_tripped) return 0;
1691         hdw->flag_tripped = 0;
1692         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1693                    "Clearing driver error status");
1694         return !0;
1695 }
1696
1697
1698 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1699 {
1700         int fl;
1701         LOCK_TAKE(hdw->big_lock); do {
1702                 fl = pvr2_hdw_untrip_unlocked(hdw);
1703         } while (0); LOCK_GIVE(hdw->big_lock);
1704         if (fl) pvr2_hdw_state_sched(hdw);
1705         return 0;
1706 }
1707
1708
1709
1710
1711 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1712 {
1713         return hdw->state_pipeline_req != 0;
1714 }
1715
1716
1717 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1718 {
1719         int ret,st;
1720         LOCK_TAKE(hdw->big_lock); do {
1721                 pvr2_hdw_untrip_unlocked(hdw);
1722                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1723                         hdw->state_pipeline_req = enable_flag != 0;
1724                         pvr2_trace(PVR2_TRACE_START_STOP,
1725                                    "/*--TRACE_STREAM--*/ %s",
1726                                    enable_flag ? "enable" : "disable");
1727                 }
1728                 pvr2_hdw_state_sched(hdw);
1729         } while (0); LOCK_GIVE(hdw->big_lock);
1730         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1731         if (enable_flag) {
1732                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1733                         if (st != PVR2_STATE_READY) return -EIO;
1734                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1735                 }
1736         }
1737         return 0;
1738 }
1739
1740
1741 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1742 {
1743         int fl;
1744         LOCK_TAKE(hdw->big_lock);
1745         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1746                 hdw->desired_stream_type = config;
1747                 hdw->state_pipeline_config = 0;
1748                 trace_stbit("state_pipeline_config",
1749                             hdw->state_pipeline_config);
1750                 pvr2_hdw_state_sched(hdw);
1751         }
1752         LOCK_GIVE(hdw->big_lock);
1753         if (fl) return 0;
1754         return pvr2_hdw_wait(hdw,0);
1755 }
1756
1757
1758 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1759 {
1760         int unit_number = hdw->unit_number;
1761         int tp = -1;
1762         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1763                 tp = tuner[unit_number];
1764         }
1765         if (tp < 0) return -EINVAL;
1766         hdw->tuner_type = tp;
1767         hdw->tuner_updated = !0;
1768         return 0;
1769 }
1770
1771
1772 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1773 {
1774         int unit_number = hdw->unit_number;
1775         int tp = 0;
1776         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1777                 tp = video_std[unit_number];
1778                 if (tp) return tp;
1779         }
1780         return 0;
1781 }
1782
1783
1784 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1785 {
1786         int unit_number = hdw->unit_number;
1787         int tp = 0;
1788         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1789                 tp = tolerance[unit_number];
1790         }
1791         return tp;
1792 }
1793
1794
1795 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1796 {
1797         /* Try a harmless request to fetch the eeprom's address over
1798            endpoint 1.  See what happens.  Only the full FX2 image can
1799            respond to this.  If this probe fails then likely the FX2
1800            firmware needs be loaded. */
1801         int result;
1802         LOCK_TAKE(hdw->ctl_lock); do {
1803                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1804                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1805                                            hdw->cmd_buffer,1,
1806                                            hdw->cmd_buffer,1);
1807                 if (result < 0) break;
1808         } while(0); LOCK_GIVE(hdw->ctl_lock);
1809         if (result) {
1810                 pvr2_trace(PVR2_TRACE_INIT,
1811                            "Probe of device endpoint 1 result status %d",
1812                            result);
1813         } else {
1814                 pvr2_trace(PVR2_TRACE_INIT,
1815                            "Probe of device endpoint 1 succeeded");
1816         }
1817         return result == 0;
1818 }
1819
1820 struct pvr2_std_hack {
1821         v4l2_std_id pat;  /* Pattern to match */
1822         v4l2_std_id msk;  /* Which bits we care about */
1823         v4l2_std_id std;  /* What additional standards or default to set */
1824 };
1825
1826 /* This data structure labels specific combinations of standards from
1827    tveeprom that we'll try to recognize.  If we recognize one, then assume
1828    a specified default standard to use.  This is here because tveeprom only
1829    tells us about available standards not the intended default standard (if
1830    any) for the device in question.  We guess the default based on what has
1831    been reported as available.  Note that this is only for guessing a
1832    default - which can always be overridden explicitly - and if the user
1833    has otherwise named a default then that default will always be used in
1834    place of this table. */
1835 static const struct pvr2_std_hack std_eeprom_maps[] = {
1836         {       /* PAL(B/G) */
1837                 .pat = V4L2_STD_B|V4L2_STD_GH,
1838                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1839         },
1840         {       /* NTSC(M) */
1841                 .pat = V4L2_STD_MN,
1842                 .std = V4L2_STD_NTSC_M,
1843         },
1844         {       /* PAL(I) */
1845                 .pat = V4L2_STD_PAL_I,
1846                 .std = V4L2_STD_PAL_I,
1847         },
1848         {       /* SECAM(L/L') */
1849                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1850                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1851         },
1852         {       /* PAL(D/D1/K) */
1853                 .pat = V4L2_STD_DK,
1854                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1855         },
1856 };
1857
1858 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1859 {
1860         char buf[40];
1861         unsigned int bcnt;
1862         v4l2_std_id std1,std2,std3;
1863
1864         std1 = get_default_standard(hdw);
1865         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1866
1867         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1868         pvr2_trace(PVR2_TRACE_STD,
1869                    "Supported video standard(s) reported available in hardware: %.*s",
1870                    bcnt,buf);
1871
1872         hdw->std_mask_avail = hdw->std_mask_eeprom;
1873
1874         std2 = (std1|std3) & ~hdw->std_mask_avail;
1875         if (std2) {
1876                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1877                 pvr2_trace(PVR2_TRACE_STD,
1878                            "Expanding supported video standards to include: %.*s",
1879                            bcnt,buf);
1880                 hdw->std_mask_avail |= std2;
1881         }
1882
1883         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1884
1885         if (std1) {
1886                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1887                 pvr2_trace(PVR2_TRACE_STD,
1888                            "Initial video standard forced to %.*s",
1889                            bcnt,buf);
1890                 hdw->std_mask_cur = std1;
1891                 hdw->std_dirty = !0;
1892                 return;
1893         }
1894         if (std3) {
1895                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1896                 pvr2_trace(PVR2_TRACE_STD,
1897                            "Initial video standard (determined by device type): %.*s",
1898                            bcnt, buf);
1899                 hdw->std_mask_cur = std3;
1900                 hdw->std_dirty = !0;
1901                 return;
1902         }
1903
1904         {
1905                 unsigned int idx;
1906                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1907                         if (std_eeprom_maps[idx].msk ?
1908                             ((std_eeprom_maps[idx].pat ^
1909                              hdw->std_mask_eeprom) &
1910                              std_eeprom_maps[idx].msk) :
1911                             (std_eeprom_maps[idx].pat !=
1912                              hdw->std_mask_eeprom)) continue;
1913                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1914                                                   std_eeprom_maps[idx].std);
1915                         pvr2_trace(PVR2_TRACE_STD,
1916                                    "Initial video standard guessed as %.*s",
1917                                    bcnt,buf);
1918                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1919                         hdw->std_dirty = !0;
1920                         return;
1921                 }
1922         }
1923
1924 }
1925
1926
1927 static unsigned int pvr2_copy_i2c_addr_list(
1928         unsigned short *dst, const unsigned char *src,
1929         unsigned int dst_max)
1930 {
1931         unsigned int cnt = 0;
1932         if (!src) return 0;
1933         while (src[cnt] && (cnt + 1) < dst_max) {
1934                 dst[cnt] = src[cnt];
1935                 cnt++;
1936         }
1937         dst[cnt] = I2C_CLIENT_END;
1938         return cnt;
1939 }
1940
1941
1942 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1943 {
1944         /*
1945           Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1946           for cx25840 causes that module to correctly set up its video
1947           scaling.  This is really a problem in the cx25840 module itself,
1948           but we work around it here.  The problem has not been seen in
1949           ivtv because there VBI is supported and set up.  We don't do VBI
1950           here (at least not yet) and thus we never attempted to even set
1951           it up.
1952         */
1953         struct v4l2_format fmt;
1954         if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1955                 /* We're not using a cx25840 so don't enable the hack */
1956                 return;
1957         }
1958
1959         pvr2_trace(PVR2_TRACE_INIT,
1960                    "Module ID %u: Executing cx25840 VBI hack",
1961                    hdw->decoder_client_id);
1962         memset(&fmt, 0, sizeof(fmt));
1963         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
1964         fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
1965         fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
1966         v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
1967                              vbi, s_sliced_fmt, &fmt.fmt.sliced);
1968 }
1969
1970
1971 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1972                                 const struct pvr2_device_client_desc *cd)
1973 {
1974         const char *fname;
1975         unsigned char mid;
1976         struct v4l2_subdev *sd;
1977         unsigned int i2ccnt;
1978         const unsigned char *p;
1979         /* Arbitrary count - max # i2c addresses we will probe */
1980         unsigned short i2caddr[25];
1981
1982         mid = cd->module_id;
1983         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1984         if (!fname) {
1985                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1986                            "Module ID %u for device %s has no name?  The driver might have a configuration problem.",
1987                            mid,
1988                            hdw->hdw_desc->description);
1989                 return -EINVAL;
1990         }
1991         pvr2_trace(PVR2_TRACE_INIT,
1992                    "Module ID %u (%s) for device %s being loaded...",
1993                    mid, fname,
1994                    hdw->hdw_desc->description);
1995
1996         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
1997                                          ARRAY_SIZE(i2caddr));
1998         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
1999                          module_i2c_addresses[mid] : NULL) != NULL)) {
2000                 /* Second chance: Try default i2c address list */
2001                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2002                                                  ARRAY_SIZE(i2caddr));
2003                 if (i2ccnt) {
2004                         pvr2_trace(PVR2_TRACE_INIT,
2005                                    "Module ID %u: Using default i2c address list",
2006                                    mid);
2007                 }
2008         }
2009
2010         if (!i2ccnt) {
2011                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2012                            "Module ID %u (%s) for device %s: No i2c addresses.  The driver might have a configuration problem.",
2013                            mid, fname, hdw->hdw_desc->description);
2014                 return -EINVAL;
2015         }
2016
2017         if (i2ccnt == 1) {
2018                 pvr2_trace(PVR2_TRACE_INIT,
2019                            "Module ID %u: Setting up with specified i2c address 0x%x",
2020                            mid, i2caddr[0]);
2021                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2022                                          fname, i2caddr[0], NULL);
2023         } else {
2024                 pvr2_trace(PVR2_TRACE_INIT,
2025                            "Module ID %u: Setting up with address probe list",
2026                            mid);
2027                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2028                                          fname, 0, i2caddr);
2029         }
2030
2031         if (!sd) {
2032                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2033                            "Module ID %u (%s) for device %s failed to load.  Possible missing sub-device kernel module or initialization failure within module.",
2034                            mid, fname, hdw->hdw_desc->description);
2035                 return -EIO;
2036         }
2037
2038         /* Tag this sub-device instance with the module ID we know about.
2039            In other places we'll use that tag to determine if the instance
2040            requires special handling. */
2041         sd->grp_id = mid;
2042
2043         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2044
2045
2046         /* client-specific setup... */
2047         switch (mid) {
2048         case PVR2_CLIENT_ID_CX25840:
2049         case PVR2_CLIENT_ID_SAA7115:
2050                 hdw->decoder_client_id = mid;
2051                 break;
2052         default: break;
2053         }
2054
2055         return 0;
2056 }
2057
2058
2059 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2060 {
2061         unsigned int idx;
2062         const struct pvr2_string_table *cm;
2063         const struct pvr2_device_client_table *ct;
2064         int okFl = !0;
2065
2066         cm = &hdw->hdw_desc->client_modules;
2067         for (idx = 0; idx < cm->cnt; idx++) {
2068                 request_module(cm->lst[idx]);
2069         }
2070
2071         ct = &hdw->hdw_desc->client_table;
2072         for (idx = 0; idx < ct->cnt; idx++) {
2073                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2074         }
2075         if (!okFl) {
2076                 hdw->flag_modulefail = !0;
2077                 pvr2_hdw_render_useless(hdw);
2078         }
2079 }
2080
2081
2082 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2083 {
2084         int ret;
2085         unsigned int idx;
2086         struct pvr2_ctrl *cptr;
2087         int reloadFl = 0;
2088         if (hdw->hdw_desc->fx2_firmware.cnt) {
2089                 if (!reloadFl) {
2090                         reloadFl =
2091                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2092                                  == 0);
2093                         if (reloadFl) {
2094                                 pvr2_trace(PVR2_TRACE_INIT,
2095                                            "USB endpoint config looks strange; possibly firmware needs to be loaded");
2096                         }
2097                 }
2098                 if (!reloadFl) {
2099                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2100                         if (reloadFl) {
2101                                 pvr2_trace(PVR2_TRACE_INIT,
2102                                            "Check for FX2 firmware failed; possibly firmware needs to be loaded");
2103                         }
2104                 }
2105                 if (reloadFl) {
2106                         if (pvr2_upload_firmware1(hdw) != 0) {
2107                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2108                                            "Failure uploading firmware1");
2109                         }
2110                         return;
2111                 }
2112         }
2113         hdw->fw1_state = FW1_STATE_OK;
2114
2115         if (!pvr2_hdw_dev_ok(hdw)) return;
2116
2117         hdw->force_dirty = !0;
2118
2119         if (!hdw->hdw_desc->flag_no_powerup) {
2120                 pvr2_hdw_cmd_powerup(hdw);
2121                 if (!pvr2_hdw_dev_ok(hdw)) return;
2122         }
2123
2124         /* Take the IR chip out of reset, if appropriate */
2125         if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2126                 pvr2_issue_simple_cmd(hdw,
2127                                       FX2CMD_HCW_ZILOG_RESET |
2128                                       (1 << 8) |
2129                                       ((0) << 16));
2130         }
2131
2132         // This step MUST happen after the earlier powerup step.
2133         pvr2_i2c_core_init(hdw);
2134         if (!pvr2_hdw_dev_ok(hdw)) return;
2135
2136         pvr2_hdw_load_modules(hdw);
2137         if (!pvr2_hdw_dev_ok(hdw)) return;
2138
2139         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2140
2141         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2142                 cptr = hdw->controls + idx;
2143                 if (cptr->info->skip_init) continue;
2144                 if (!cptr->info->set_value) continue;
2145                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2146         }
2147
2148         pvr2_hdw_cx25840_vbi_hack(hdw);
2149
2150         /* Set up special default values for the television and radio
2151            frequencies here.  It's not really important what these defaults
2152            are, but I set them to something usable in the Chicago area just
2153            to make driver testing a little easier. */
2154
2155         hdw->freqValTelevision = default_tv_freq;
2156         hdw->freqValRadio = default_radio_freq;
2157
2158         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2159         // thread-safe against the normal pvr2_send_request() mechanism.
2160         // (We should make it thread safe).
2161
2162         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2163                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2164                 if (!pvr2_hdw_dev_ok(hdw)) return;
2165                 if (ret < 0) {
2166                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2167                                    "Unable to determine location of eeprom, skipping");
2168                 } else {
2169                         hdw->eeprom_addr = ret;
2170                         pvr2_eeprom_analyze(hdw);
2171                         if (!pvr2_hdw_dev_ok(hdw)) return;
2172                 }
2173         } else {
2174                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2175                 hdw->tuner_updated = !0;
2176                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2177         }
2178
2179         if (hdw->serial_number) {
2180                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2181                                 "sn-%lu", hdw->serial_number);
2182         } else if (hdw->unit_number >= 0) {
2183                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2184                                 "unit-%c",
2185                                 hdw->unit_number + 'a');
2186         } else {
2187                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2188                                 "unit-??");
2189         }
2190         hdw->identifier[idx] = 0;
2191
2192         pvr2_hdw_setup_std(hdw);
2193
2194         if (!get_default_tuner_type(hdw)) {
2195                 pvr2_trace(PVR2_TRACE_INIT,
2196                            "pvr2_hdw_setup: Tuner type overridden to %d",
2197                            hdw->tuner_type);
2198         }
2199
2200
2201         if (!pvr2_hdw_dev_ok(hdw)) return;
2202
2203         if (hdw->hdw_desc->signal_routing_scheme ==
2204             PVR2_ROUTING_SCHEME_GOTVIEW) {
2205                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2206                    hardware. */
2207                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2208         }
2209
2210         pvr2_hdw_commit_setup(hdw);
2211
2212         hdw->vid_stream = pvr2_stream_create();
2213         if (!pvr2_hdw_dev_ok(hdw)) return;
2214         pvr2_trace(PVR2_TRACE_INIT,
2215                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2216         if (hdw->vid_stream) {
2217                 idx = get_default_error_tolerance(hdw);
2218                 if (idx) {
2219                         pvr2_trace(PVR2_TRACE_INIT,
2220                                    "pvr2_hdw_setup: video stream %p setting tolerance %u",
2221                                    hdw->vid_stream,idx);
2222                 }
2223                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2224                                   PVR2_VID_ENDPOINT,idx);
2225         }
2226
2227         if (!pvr2_hdw_dev_ok(hdw)) return;
2228
2229         hdw->flag_init_ok = !0;
2230
2231         pvr2_hdw_state_sched(hdw);
2232 }
2233
2234
2235 /* Set up the structure and attempt to put the device into a usable state.
2236    This can be a time-consuming operation, which is why it is not done
2237    internally as part of the create() step. */
2238 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2239 {
2240         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2241         do {
2242                 pvr2_hdw_setup_low(hdw);
2243                 pvr2_trace(PVR2_TRACE_INIT,
2244                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2245                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2246                 if (pvr2_hdw_dev_ok(hdw)) {
2247                         if (hdw->flag_init_ok) {
2248                                 pvr2_trace(
2249                                         PVR2_TRACE_INFO,
2250                                         "Device initialization completed successfully.");
2251                                 break;
2252                         }
2253                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2254                                 pvr2_trace(
2255                                         PVR2_TRACE_INFO,
2256                                         "Device microcontroller firmware (re)loaded; it should now reset and reconnect.");
2257                                 break;
2258                         }
2259                         pvr2_trace(
2260                                 PVR2_TRACE_ERROR_LEGS,
2261                                 "Device initialization was not successful.");
2262                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2263                                 pvr2_trace(
2264                                         PVR2_TRACE_ERROR_LEGS,
2265                                         "Giving up since device microcontroller firmware appears to be missing.");
2266                                 break;
2267                         }
2268                 }
2269                 if (hdw->flag_modulefail) {
2270                         pvr2_trace(
2271                                 PVR2_TRACE_ERROR_LEGS,
2272                                 "***WARNING*** pvrusb2 driver initialization failed due to the failure of one or more sub-device kernel modules.");
2273                         pvr2_trace(
2274                                 PVR2_TRACE_ERROR_LEGS,
2275                                 "You need to resolve the failing condition before this driver can function.  There should be some earlier messages giving more information about the problem.");
2276                         break;
2277                 }
2278                 if (procreload) {
2279                         pvr2_trace(
2280                                 PVR2_TRACE_ERROR_LEGS,
2281                                 "Attempting pvrusb2 recovery by reloading primary firmware.");
2282                         pvr2_trace(
2283                                 PVR2_TRACE_ERROR_LEGS,
2284                                 "If this works, device should disconnect and reconnect in a sane state.");
2285                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2286                         pvr2_upload_firmware1(hdw);
2287                 } else {
2288                         pvr2_trace(
2289                                 PVR2_TRACE_ERROR_LEGS,
2290                                 "***WARNING*** pvrusb2 device hardware appears to be jammed and I can't clear it.");
2291                         pvr2_trace(
2292                                 PVR2_TRACE_ERROR_LEGS,
2293                                 "You might need to power cycle the pvrusb2 device in order to recover.");
2294                 }
2295         } while (0);
2296         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2297 }
2298
2299
2300 /* Perform second stage initialization.  Set callback pointer first so that
2301    we can avoid a possible initialization race (if the kernel thread runs
2302    before the callback has been set). */
2303 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2304                         void (*callback_func)(void *),
2305                         void *callback_data)
2306 {
2307         LOCK_TAKE(hdw->big_lock); do {
2308                 if (hdw->flag_disconnected) {
2309                         /* Handle a race here: If we're already
2310                            disconnected by this point, then give up.  If we
2311                            get past this then we'll remain connected for
2312                            the duration of initialization since the entire
2313                            initialization sequence is now protected by the
2314                            big_lock. */
2315                         break;
2316                 }
2317                 hdw->state_data = callback_data;
2318                 hdw->state_func = callback_func;
2319                 pvr2_hdw_setup(hdw);
2320         } while (0); LOCK_GIVE(hdw->big_lock);
2321         return hdw->flag_init_ok;
2322 }
2323
2324
2325 /* Create, set up, and return a structure for interacting with the
2326    underlying hardware.  */
2327 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2328                                  const struct usb_device_id *devid)
2329 {
2330         unsigned int idx,cnt1,cnt2,m;
2331         struct pvr2_hdw *hdw = NULL;
2332         int valid_std_mask;
2333         struct pvr2_ctrl *cptr;
2334         struct usb_device *usb_dev;
2335         const struct pvr2_device_desc *hdw_desc;
2336         __u8 ifnum;
2337         struct v4l2_queryctrl qctrl;
2338         struct pvr2_ctl_info *ciptr;
2339
2340         usb_dev = interface_to_usbdev(intf);
2341
2342         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2343
2344         if (hdw_desc == NULL) {
2345                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create: No device description pointer, unable to continue.");
2346                 pvr2_trace(PVR2_TRACE_INIT,
2347                            "If you have a new device type, please contact Mike Isely <isely@pobox.com> to get it included in the driver");
2348                 goto fail;
2349         }
2350
2351         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2352         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2353                    hdw,hdw_desc->description);
2354         pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2355                 hdw_desc->description);
2356         if (hdw_desc->flag_is_experimental) {
2357                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2358                 pvr2_trace(PVR2_TRACE_INFO,
2359                            "WARNING: Support for this device (%s) is experimental.",
2360                                                               hdw_desc->description);
2361                 pvr2_trace(PVR2_TRACE_INFO,
2362                            "Important functionality might not be entirely working.");
2363                 pvr2_trace(PVR2_TRACE_INFO,
2364                            "Please consider contacting the driver author to help with further stabilization of the driver.");
2365                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2366         }
2367         if (!hdw) goto fail;
2368
2369         timer_setup(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout, 0);
2370
2371         timer_setup(&hdw->decoder_stabilization_timer,
2372                     pvr2_hdw_decoder_stabilization_timeout, 0);
2373
2374         timer_setup(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
2375                     0);
2376
2377         timer_setup(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout, 0);
2378
2379         hdw->master_state = PVR2_STATE_DEAD;
2380
2381         init_waitqueue_head(&hdw->state_wait_data);
2382
2383         hdw->tuner_signal_stale = !0;
2384         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2385
2386         /* Calculate which inputs are OK */
2387         m = 0;
2388         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2389         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2390                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2391         }
2392         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2393         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2394         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2395         hdw->input_avail_mask = m;
2396         hdw->input_allowed_mask = hdw->input_avail_mask;
2397
2398         /* If not a hybrid device, pathway_state never changes.  So
2399            initialize it here to what it should forever be. */
2400         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2401                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2402         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2403                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2404         }
2405
2406         hdw->control_cnt = CTRLDEF_COUNT;
2407         hdw->control_cnt += MPEGDEF_COUNT;
2408         hdw->controls = kcalloc(hdw->control_cnt, sizeof(struct pvr2_ctrl),
2409                                 GFP_KERNEL);
2410         if (!hdw->controls) goto fail;
2411         hdw->hdw_desc = hdw_desc;
2412         hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2413         for (idx = 0; idx < hdw->control_cnt; idx++) {
2414                 cptr = hdw->controls + idx;
2415                 cptr->hdw = hdw;
2416         }
2417         for (idx = 0; idx < 32; idx++) {
2418                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2419         }
2420         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2421                 cptr = hdw->controls + idx;
2422                 cptr->info = control_defs+idx;
2423         }
2424
2425         /* Ensure that default input choice is a valid one. */
2426         m = hdw->input_avail_mask;
2427         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2428                 if (!((1 << idx) & m)) continue;
2429                 hdw->input_val = idx;
2430                 break;
2431         }
2432
2433         /* Define and configure additional controls from cx2341x module. */
2434         hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2435                                       sizeof(*(hdw->mpeg_ctrl_info)),
2436                                       GFP_KERNEL);
2437         if (!hdw->mpeg_ctrl_info) goto fail;
2438         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2439                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2440                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2441                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2442                 ciptr->name = mpeg_ids[idx].strid;
2443                 ciptr->v4l_id = mpeg_ids[idx].id;
2444                 ciptr->skip_init = !0;
2445                 ciptr->get_value = ctrl_cx2341x_get;
2446                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2447                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2448                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2449                 qctrl.id = ciptr->v4l_id;
2450                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2451                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2452                         ciptr->set_value = ctrl_cx2341x_set;
2453                 }
2454                 strscpy(hdw->mpeg_ctrl_info[idx].desc, qctrl.name,
2455                         sizeof(hdw->mpeg_ctrl_info[idx].desc));
2456                 ciptr->default_value = qctrl.default_value;
2457                 switch (qctrl.type) {
2458                 default:
2459                 case V4L2_CTRL_TYPE_INTEGER:
2460                         ciptr->type = pvr2_ctl_int;
2461                         ciptr->def.type_int.min_value = qctrl.minimum;
2462                         ciptr->def.type_int.max_value = qctrl.maximum;
2463                         break;
2464                 case V4L2_CTRL_TYPE_BOOLEAN:
2465                         ciptr->type = pvr2_ctl_bool;
2466                         break;
2467                 case V4L2_CTRL_TYPE_MENU:
2468                         ciptr->type = pvr2_ctl_enum;
2469                         ciptr->def.type_enum.value_names =
2470                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2471                                                                 ciptr->v4l_id);
2472                         for (cnt1 = 0;
2473                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2474                              cnt1++) { }
2475                         ciptr->def.type_enum.count = cnt1;
2476                         break;
2477                 }
2478                 cptr->info = ciptr;
2479         }
2480
2481         // Initialize control data regarding video standard masks
2482         valid_std_mask = pvr2_std_get_usable();
2483         for (idx = 0; idx < 32; idx++) {
2484                 if (!(valid_std_mask & (1 << idx))) continue;
2485                 cnt1 = pvr2_std_id_to_str(
2486                         hdw->std_mask_names[idx],
2487                         sizeof(hdw->std_mask_names[idx])-1,
2488                         1 << idx);
2489                 hdw->std_mask_names[idx][cnt1] = 0;
2490         }
2491         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2492         if (cptr) {
2493                 memcpy(&hdw->std_info_avail,cptr->info,
2494                        sizeof(hdw->std_info_avail));
2495                 cptr->info = &hdw->std_info_avail;
2496                 hdw->std_info_avail.def.type_bitmask.bit_names =
2497                         hdw->std_mask_ptrs;
2498                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2499                         valid_std_mask;
2500         }
2501         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2502         if (cptr) {
2503                 memcpy(&hdw->std_info_cur,cptr->info,
2504                        sizeof(hdw->std_info_cur));
2505                 cptr->info = &hdw->std_info_cur;
2506                 hdw->std_info_cur.def.type_bitmask.bit_names =
2507                         hdw->std_mask_ptrs;
2508                 hdw->std_info_cur.def.type_bitmask.valid_bits =
2509                         valid_std_mask;
2510         }
2511         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2512         if (cptr) {
2513                 memcpy(&hdw->std_info_detect,cptr->info,
2514                        sizeof(hdw->std_info_detect));
2515                 cptr->info = &hdw->std_info_detect;
2516                 hdw->std_info_detect.def.type_bitmask.bit_names =
2517                         hdw->std_mask_ptrs;
2518                 hdw->std_info_detect.def.type_bitmask.valid_bits =
2519                         valid_std_mask;
2520         }
2521
2522         hdw->cropcap_stale = !0;
2523         hdw->eeprom_addr = -1;
2524         hdw->unit_number = -1;
2525         hdw->v4l_minor_number_video = -1;
2526         hdw->v4l_minor_number_vbi = -1;
2527         hdw->v4l_minor_number_radio = -1;
2528         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2529         if (!hdw->ctl_write_buffer) goto fail;
2530         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2531         if (!hdw->ctl_read_buffer) goto fail;
2532         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2533         if (!hdw->ctl_write_urb) goto fail;
2534         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2535         if (!hdw->ctl_read_urb) goto fail;
2536
2537         if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2538                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2539                            "Error registering with v4l core, giving up");
2540                 goto fail;
2541         }
2542         mutex_lock(&pvr2_unit_mtx);
2543         do {
2544                 for (idx = 0; idx < PVR_NUM; idx++) {
2545                         if (unit_pointers[idx]) continue;
2546                         hdw->unit_number = idx;
2547                         unit_pointers[idx] = hdw;
2548                         break;
2549                 }
2550         } while (0);
2551         mutex_unlock(&pvr2_unit_mtx);
2552
2553         cnt1 = 0;
2554         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2555         cnt1 += cnt2;
2556         if (hdw->unit_number >= 0) {
2557                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2558                                  ('a' + hdw->unit_number));
2559                 cnt1 += cnt2;
2560         }
2561         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2562         hdw->name[cnt1] = 0;
2563
2564         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2565
2566         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2567                    hdw->unit_number,hdw->name);
2568
2569         hdw->tuner_type = -1;
2570         hdw->flag_ok = !0;
2571
2572         hdw->usb_intf = intf;
2573         hdw->usb_dev = usb_dev;
2574
2575         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2576
2577         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2578         usb_set_interface(hdw->usb_dev,ifnum,0);
2579
2580         mutex_init(&hdw->ctl_lock_mutex);
2581         mutex_init(&hdw->big_lock_mutex);
2582
2583         return hdw;
2584  fail:
2585         if (hdw) {
2586                 del_timer_sync(&hdw->quiescent_timer);
2587                 del_timer_sync(&hdw->decoder_stabilization_timer);
2588                 del_timer_sync(&hdw->encoder_run_timer);
2589                 del_timer_sync(&hdw->encoder_wait_timer);
2590                 flush_work(&hdw->workpoll);
2591                 usb_free_urb(hdw->ctl_read_urb);
2592                 usb_free_urb(hdw->ctl_write_urb);
2593                 kfree(hdw->ctl_read_buffer);
2594                 kfree(hdw->ctl_write_buffer);
2595                 kfree(hdw->controls);
2596                 kfree(hdw->mpeg_ctrl_info);
2597                 kfree(hdw);
2598         }
2599         return NULL;
2600 }
2601
2602
2603 /* Remove _all_ associations between this driver and the underlying USB
2604    layer. */
2605 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2606 {
2607         if (hdw->flag_disconnected) return;
2608         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2609         if (hdw->ctl_read_urb) {
2610                 usb_kill_urb(hdw->ctl_read_urb);
2611                 usb_free_urb(hdw->ctl_read_urb);
2612                 hdw->ctl_read_urb = NULL;
2613         }
2614         if (hdw->ctl_write_urb) {
2615                 usb_kill_urb(hdw->ctl_write_urb);
2616                 usb_free_urb(hdw->ctl_write_urb);
2617                 hdw->ctl_write_urb = NULL;
2618         }
2619         if (hdw->ctl_read_buffer) {
2620                 kfree(hdw->ctl_read_buffer);
2621                 hdw->ctl_read_buffer = NULL;
2622         }
2623         if (hdw->ctl_write_buffer) {
2624                 kfree(hdw->ctl_write_buffer);
2625                 hdw->ctl_write_buffer = NULL;
2626         }
2627         hdw->flag_disconnected = !0;
2628         /* If we don't do this, then there will be a dangling struct device
2629            reference to our disappearing device persisting inside the V4L
2630            core... */
2631         v4l2_device_disconnect(&hdw->v4l2_dev);
2632         hdw->usb_dev = NULL;
2633         hdw->usb_intf = NULL;
2634         pvr2_hdw_render_useless(hdw);
2635 }
2636
2637 void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2638 {
2639         vdev->v4l2_dev = &hdw->v4l2_dev;
2640 }
2641
2642 /* Destroy hardware interaction structure */
2643 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2644 {
2645         if (!hdw) return;
2646         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2647         flush_work(&hdw->workpoll);
2648         del_timer_sync(&hdw->quiescent_timer);
2649         del_timer_sync(&hdw->decoder_stabilization_timer);
2650         del_timer_sync(&hdw->encoder_run_timer);
2651         del_timer_sync(&hdw->encoder_wait_timer);
2652         if (hdw->fw_buffer) {
2653                 kfree(hdw->fw_buffer);
2654                 hdw->fw_buffer = NULL;
2655         }
2656         if (hdw->vid_stream) {
2657                 pvr2_stream_destroy(hdw->vid_stream);
2658                 hdw->vid_stream = NULL;
2659         }
2660         pvr2_i2c_core_done(hdw);
2661         v4l2_device_unregister(&hdw->v4l2_dev);
2662         pvr2_hdw_remove_usb_stuff(hdw);
2663         mutex_lock(&pvr2_unit_mtx);
2664         do {
2665                 if ((hdw->unit_number >= 0) &&
2666                     (hdw->unit_number < PVR_NUM) &&
2667                     (unit_pointers[hdw->unit_number] == hdw)) {
2668                         unit_pointers[hdw->unit_number] = NULL;
2669                 }
2670         } while (0);
2671         mutex_unlock(&pvr2_unit_mtx);
2672         kfree(hdw->controls);
2673         kfree(hdw->mpeg_ctrl_info);
2674         kfree(hdw);
2675 }
2676
2677
2678 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2679 {
2680         return (hdw && hdw->flag_ok);
2681 }
2682
2683
2684 /* Called when hardware has been unplugged */
2685 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2686 {
2687         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2688         LOCK_TAKE(hdw->big_lock);
2689         LOCK_TAKE(hdw->ctl_lock);
2690         pvr2_hdw_remove_usb_stuff(hdw);
2691         LOCK_GIVE(hdw->ctl_lock);
2692         LOCK_GIVE(hdw->big_lock);
2693 }
2694
2695
2696 /* Get the number of defined controls */
2697 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2698 {
2699         return hdw->control_cnt;
2700 }
2701
2702
2703 /* Retrieve a control handle given its index (0..count-1) */
2704 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2705                                              unsigned int idx)
2706 {
2707         if (idx >= hdw->control_cnt) return NULL;
2708         return hdw->controls + idx;
2709 }
2710
2711
2712 /* Retrieve a control handle given its index (0..count-1) */
2713 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2714                                           unsigned int ctl_id)
2715 {
2716         struct pvr2_ctrl *cptr;
2717         unsigned int idx;
2718         int i;
2719
2720         /* This could be made a lot more efficient, but for now... */
2721         for (idx = 0; idx < hdw->control_cnt; idx++) {
2722                 cptr = hdw->controls + idx;
2723                 i = cptr->info->internal_id;
2724                 if (i && (i == ctl_id)) return cptr;
2725         }
2726         return NULL;
2727 }
2728
2729
2730 /* Given a V4L ID, retrieve the control structure associated with it. */
2731 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2732 {
2733         struct pvr2_ctrl *cptr;
2734         unsigned int idx;
2735         int i;
2736
2737         /* This could be made a lot more efficient, but for now... */
2738         for (idx = 0; idx < hdw->control_cnt; idx++) {
2739                 cptr = hdw->controls + idx;
2740                 i = cptr->info->v4l_id;
2741                 if (i && (i == ctl_id)) return cptr;
2742         }
2743         return NULL;
2744 }
2745
2746
2747 /* Given a V4L ID for its immediate predecessor, retrieve the control
2748    structure associated with it. */
2749 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2750                                             unsigned int ctl_id)
2751 {
2752         struct pvr2_ctrl *cptr,*cp2;
2753         unsigned int idx;
2754         int i;
2755
2756         /* This could be made a lot more efficient, but for now... */
2757         cp2 = NULL;
2758         for (idx = 0; idx < hdw->control_cnt; idx++) {
2759                 cptr = hdw->controls + idx;
2760                 i = cptr->info->v4l_id;
2761                 if (!i) continue;
2762                 if (i <= ctl_id) continue;
2763                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2764                 cp2 = cptr;
2765         }
2766         return cp2;
2767         return NULL;
2768 }
2769
2770
2771 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2772 {
2773         switch (tp) {
2774         case pvr2_ctl_int: return "integer";
2775         case pvr2_ctl_enum: return "enum";
2776         case pvr2_ctl_bool: return "boolean";
2777         case pvr2_ctl_bitmask: return "bitmask";
2778         }
2779         return "";
2780 }
2781
2782
2783 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2784                                     const char *name, int val)
2785 {
2786         struct v4l2_control ctrl;
2787         struct v4l2_subdev *sd;
2788
2789         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2790         memset(&ctrl, 0, sizeof(ctrl));
2791         ctrl.id = id;
2792         ctrl.value = val;
2793
2794         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev)
2795                 v4l2_s_ctrl(NULL, sd->ctrl_handler, &ctrl);
2796 }
2797
2798 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2799         if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2800                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2801         }
2802
2803 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
2804 {
2805         v4l2_std_id std;
2806         std = (v4l2_std_id)hdw->std_mask_avail;
2807         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2808                              video, querystd, &std);
2809         return std;
2810 }
2811
2812 /* Execute whatever commands are required to update the state of all the
2813    sub-devices so that they match our current control values. */
2814 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2815 {
2816         struct v4l2_subdev *sd;
2817         unsigned int id;
2818         pvr2_subdev_update_func fp;
2819
2820         pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2821
2822         if (hdw->tuner_updated || hdw->force_dirty) {
2823                 struct tuner_setup setup;
2824                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2825                            hdw->tuner_type);
2826                 if (((int)(hdw->tuner_type)) >= 0) {
2827                         memset(&setup, 0, sizeof(setup));
2828                         setup.addr = ADDR_UNSET;
2829                         setup.type = hdw->tuner_type;
2830                         setup.mode_mask = T_RADIO | T_ANALOG_TV;
2831                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2832                                              tuner, s_type_addr, &setup);
2833                 }
2834         }
2835
2836         if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2837                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2838                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2839                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2840                                              tuner, s_radio);
2841                 } else {
2842                         v4l2_std_id vs;
2843                         vs = hdw->std_mask_cur;
2844                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2845                                              video, s_std, vs);
2846                         pvr2_hdw_cx25840_vbi_hack(hdw);
2847                 }
2848                 hdw->tuner_signal_stale = !0;
2849                 hdw->cropcap_stale = !0;
2850         }
2851
2852         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2853         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2854         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2855         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2856         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2857         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2858         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2859         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2860         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2861
2862         if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2863                 struct v4l2_tuner vt;
2864                 memset(&vt, 0, sizeof(vt));
2865                 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2866                         V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2867                 vt.audmode = hdw->audiomode_val;
2868                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2869         }
2870
2871         if (hdw->freqDirty || hdw->force_dirty) {
2872                 unsigned long fv;
2873                 struct v4l2_frequency freq;
2874                 fv = pvr2_hdw_get_cur_freq(hdw);
2875                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2876                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2877                 memset(&freq, 0, sizeof(freq));
2878                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2879                         /* ((fv * 1000) / 62500) */
2880                         freq.frequency = (fv * 2) / 125;
2881                 } else {
2882                         freq.frequency = fv / 62500;
2883                 }
2884                 /* tuner-core currently doesn't seem to care about this, but
2885                    let's set it anyway for completeness. */
2886                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2887                         freq.type = V4L2_TUNER_RADIO;
2888                 } else {
2889                         freq.type = V4L2_TUNER_ANALOG_TV;
2890                 }
2891                 freq.tuner = 0;
2892                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2893                                      s_frequency, &freq);
2894         }
2895
2896         if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2897                 struct v4l2_subdev_format format = {
2898                         .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2899                 };
2900
2901                 format.format.width = hdw->res_hor_val;
2902                 format.format.height = hdw->res_ver_val;
2903                 format.format.code = MEDIA_BUS_FMT_FIXED;
2904                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2905                            format.format.width, format.format.height);
2906                 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
2907                                      NULL, &format);
2908         }
2909
2910         if (hdw->srate_dirty || hdw->force_dirty) {
2911                 u32 val;
2912                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2913                            hdw->srate_val);
2914                 switch (hdw->srate_val) {
2915                 default:
2916                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2917                         val = 48000;
2918                         break;
2919                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2920                         val = 44100;
2921                         break;
2922                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2923                         val = 32000;
2924                         break;
2925                 }
2926                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2927                                      audio, s_clock_freq, val);
2928         }
2929
2930         /* Unable to set crop parameters; there is apparently no equivalent
2931            for VIDIOC_S_CROP */
2932
2933         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2934                 id = sd->grp_id;
2935                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
2936                 fp = pvr2_module_update_functions[id];
2937                 if (!fp) continue;
2938                 (*fp)(hdw, sd);
2939         }
2940
2941         if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2942                 pvr2_hdw_status_poll(hdw);
2943         }
2944 }
2945
2946
2947 /* Figure out if we need to commit control changes.  If so, mark internal
2948    state flags to indicate this fact and return true.  Otherwise do nothing
2949    else and return false. */
2950 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2951 {
2952         unsigned int idx;
2953         struct pvr2_ctrl *cptr;
2954         int value;
2955         int commit_flag = hdw->force_dirty;
2956         char buf[100];
2957         unsigned int bcnt,ccnt;
2958
2959         for (idx = 0; idx < hdw->control_cnt; idx++) {
2960                 cptr = hdw->controls + idx;
2961                 if (!cptr->info->is_dirty) continue;
2962                 if (!cptr->info->is_dirty(cptr)) continue;
2963                 commit_flag = !0;
2964
2965                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2966                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2967                                  cptr->info->name);
2968                 value = 0;
2969                 cptr->info->get_value(cptr,&value);
2970                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2971                                                 buf+bcnt,
2972                                                 sizeof(buf)-bcnt,&ccnt);
2973                 bcnt += ccnt;
2974                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2975                                   get_ctrl_typename(cptr->info->type));
2976                 pvr2_trace(PVR2_TRACE_CTL,
2977                            "/*--TRACE_COMMIT--*/ %.*s",
2978                            bcnt,buf);
2979         }
2980
2981         if (!commit_flag) {
2982                 /* Nothing has changed */
2983                 return 0;
2984         }
2985
2986         hdw->state_pipeline_config = 0;
2987         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2988         pvr2_hdw_state_sched(hdw);
2989
2990         return !0;
2991 }
2992
2993
2994 /* Perform all operations needed to commit all control changes.  This must
2995    be performed in synchronization with the pipeline state and is thus
2996    expected to be called as part of the driver's worker thread.  Return
2997    true if commit successful, otherwise return false to indicate that
2998    commit isn't possible at this time. */
2999 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3000 {
3001         unsigned int idx;
3002         struct pvr2_ctrl *cptr;
3003         int disruptive_change;
3004
3005         if (hdw->input_dirty && hdw->state_pathway_ok &&
3006             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3007               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3008              hdw->pathway_state)) {
3009                 /* Change of mode being asked for... */
3010                 hdw->state_pathway_ok = 0;
3011                 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3012         }
3013         if (!hdw->state_pathway_ok) {
3014                 /* Can't commit anything until pathway is ok. */
3015                 return 0;
3016         }
3017
3018         /* Handle some required side effects when the video standard is
3019            changed.... */
3020         if (hdw->std_dirty) {
3021                 int nvres;
3022                 int gop_size;
3023                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3024                         nvres = 480;
3025                         gop_size = 15;
3026                 } else {
3027                         nvres = 576;
3028                         gop_size = 12;
3029                 }
3030                 /* Rewrite the vertical resolution to be appropriate to the
3031                    video standard that has been selected. */
3032                 if (nvres != hdw->res_ver_val) {
3033                         hdw->res_ver_val = nvres;
3034                         hdw->res_ver_dirty = !0;
3035                 }
3036                 /* Rewrite the GOP size to be appropriate to the video
3037                    standard that has been selected. */
3038                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3039                         struct v4l2_ext_controls cs;
3040                         struct v4l2_ext_control c1;
3041                         memset(&cs, 0, sizeof(cs));
3042                         memset(&c1, 0, sizeof(c1));
3043                         cs.controls = &c1;
3044                         cs.count = 1;
3045                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3046                         c1.value = gop_size;
3047                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3048                                           VIDIOC_S_EXT_CTRLS);
3049                 }
3050         }
3051
3052         /* The broadcast decoder can only scale down, so if
3053          * res_*_dirty && crop window < output format ==> enlarge crop.
3054          *
3055          * The mpeg encoder receives fields of res_hor_val dots and
3056          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3057          */
3058         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3059                 hdw->cropw_val = hdw->res_hor_val;
3060                 hdw->cropw_dirty = !0;
3061         } else if (hdw->cropw_dirty) {
3062                 hdw->res_hor_dirty = !0;           /* must rescale */
3063                 hdw->res_hor_val = min(720, hdw->cropw_val);
3064         }
3065         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3066                 hdw->croph_val = hdw->res_ver_val;
3067                 hdw->croph_dirty = !0;
3068         } else if (hdw->croph_dirty) {
3069                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3070                 hdw->res_ver_dirty = !0;
3071                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3072         }
3073
3074         /* If any of the below has changed, then we can't do the update
3075            while the pipeline is running.  Pipeline must be paused first
3076            and decoder -> encoder connection be made quiescent before we
3077            can proceed. */
3078         disruptive_change =
3079                 (hdw->std_dirty ||
3080                  hdw->enc_unsafe_stale ||
3081                  hdw->srate_dirty ||
3082                  hdw->res_ver_dirty ||
3083                  hdw->res_hor_dirty ||
3084                  hdw->cropw_dirty ||
3085                  hdw->croph_dirty ||
3086                  hdw->input_dirty ||
3087                  (hdw->active_stream_type != hdw->desired_stream_type));
3088         if (disruptive_change && !hdw->state_pipeline_idle) {
3089                 /* Pipeline is not idle; we can't proceed.  Arrange to
3090                    cause pipeline to stop so that we can try this again
3091                    later.... */
3092                 hdw->state_pipeline_pause = !0;
3093                 return 0;
3094         }
3095
3096         if (hdw->srate_dirty) {
3097                 /* Write new sample rate into control structure since
3098                  * the master copy is stale.  We must track srate
3099                  * separate from the mpeg control structure because
3100                  * other logic also uses this value. */
3101                 struct v4l2_ext_controls cs;
3102                 struct v4l2_ext_control c1;
3103                 memset(&cs,0,sizeof(cs));
3104                 memset(&c1,0,sizeof(c1));
3105                 cs.controls = &c1;
3106                 cs.count = 1;
3107                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3108                 c1.value = hdw->srate_val;
3109                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3110         }
3111
3112         if (hdw->active_stream_type != hdw->desired_stream_type) {
3113                 /* Handle any side effects of stream config here */
3114                 hdw->active_stream_type = hdw->desired_stream_type;
3115         }
3116
3117         if (hdw->hdw_desc->signal_routing_scheme ==
3118             PVR2_ROUTING_SCHEME_GOTVIEW) {
3119                 u32 b;
3120                 /* Handle GOTVIEW audio switching */
3121                 pvr2_hdw_gpio_get_out(hdw,&b);
3122                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3123                         /* Set GPIO 11 */
3124                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3125                 } else {
3126                         /* Clear GPIO 11 */
3127                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3128                 }
3129         }
3130
3131         /* Check and update state for all sub-devices. */
3132         pvr2_subdev_update(hdw);
3133
3134         hdw->tuner_updated = 0;
3135         hdw->force_dirty = 0;
3136         for (idx = 0; idx < hdw->control_cnt; idx++) {
3137                 cptr = hdw->controls + idx;
3138                 if (!cptr->info->clear_dirty) continue;
3139                 cptr->info->clear_dirty(cptr);
3140         }
3141
3142         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3143             hdw->state_encoder_run) {
3144                 /* If encoder isn't running or it can't be touched, then
3145                    this will get worked out later when we start the
3146                    encoder. */
3147                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3148         }
3149
3150         hdw->state_pipeline_config = !0;
3151         /* Hardware state may have changed in a way to cause the cropping
3152            capabilities to have changed.  So mark it stale, which will
3153            cause a later re-fetch. */
3154         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3155         return !0;
3156 }
3157
3158
3159 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3160 {
3161         int fl;
3162         LOCK_TAKE(hdw->big_lock);
3163         fl = pvr2_hdw_commit_setup(hdw);
3164         LOCK_GIVE(hdw->big_lock);
3165         if (!fl) return 0;
3166         return pvr2_hdw_wait(hdw,0);
3167 }
3168
3169
3170 static void pvr2_hdw_worker_poll(struct work_struct *work)
3171 {
3172         int fl = 0;
3173         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3174         LOCK_TAKE(hdw->big_lock); do {
3175                 fl = pvr2_hdw_state_eval(hdw);
3176         } while (0); LOCK_GIVE(hdw->big_lock);
3177         if (fl && hdw->state_func) {
3178                 hdw->state_func(hdw->state_data);
3179         }
3180 }
3181
3182
3183 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3184 {
3185         return wait_event_interruptible(
3186                 hdw->state_wait_data,
3187                 (hdw->state_stale == 0) &&
3188                 (!state || (hdw->master_state != state)));
3189 }
3190
3191
3192 /* Return name for this driver instance */
3193 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3194 {
3195         return hdw->name;
3196 }
3197
3198
3199 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3200 {
3201         return hdw->hdw_desc->description;
3202 }
3203
3204
3205 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3206 {
3207         return hdw->hdw_desc->shortname;
3208 }
3209
3210
3211 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3212 {
3213         int result;
3214         LOCK_TAKE(hdw->ctl_lock); do {
3215                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3216                 result = pvr2_send_request(hdw,
3217                                            hdw->cmd_buffer,1,
3218                                            hdw->cmd_buffer,1);
3219                 if (result < 0) break;
3220                 result = (hdw->cmd_buffer[0] != 0);
3221         } while(0); LOCK_GIVE(hdw->ctl_lock);
3222         return result;
3223 }
3224
3225
3226 /* Execute poll of tuner status */
3227 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3228 {
3229         LOCK_TAKE(hdw->big_lock); do {
3230                 pvr2_hdw_status_poll(hdw);
3231         } while (0); LOCK_GIVE(hdw->big_lock);
3232 }
3233
3234
3235 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3236 {
3237         if (!hdw->cropcap_stale) {
3238                 return 0;
3239         }
3240         pvr2_hdw_status_poll(hdw);
3241         if (hdw->cropcap_stale) {
3242                 return -EIO;
3243         }
3244         return 0;
3245 }
3246
3247
3248 /* Return information about cropping capabilities */
3249 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3250 {
3251         int stat = 0;
3252         LOCK_TAKE(hdw->big_lock);
3253         stat = pvr2_hdw_check_cropcap(hdw);
3254         if (!stat) {
3255                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3256         }
3257         LOCK_GIVE(hdw->big_lock);
3258         return stat;
3259 }
3260
3261
3262 /* Return information about the tuner */
3263 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3264 {
3265         LOCK_TAKE(hdw->big_lock); do {
3266                 if (hdw->tuner_signal_stale) {
3267                         pvr2_hdw_status_poll(hdw);
3268                 }
3269                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3270         } while (0); LOCK_GIVE(hdw->big_lock);
3271         return 0;
3272 }
3273
3274
3275 /* Get handle to video output stream */
3276 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3277 {
3278         return hp->vid_stream;
3279 }
3280
3281
3282 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3283 {
3284         int nr = pvr2_hdw_get_unit_number(hdw);
3285         LOCK_TAKE(hdw->big_lock);
3286         do {
3287                 pr_info("pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3288                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3289                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3290                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3291                 pvr2_hdw_state_log_state(hdw);
3292                 pr_info("pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3293         } while (0);
3294         LOCK_GIVE(hdw->big_lock);
3295 }
3296
3297
3298 /* Grab EEPROM contents, needed for direct method. */
3299 #define EEPROM_SIZE 8192
3300 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3301 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3302 {
3303         struct i2c_msg msg[2];
3304         u8 *eeprom;
3305         u8 iadd[2];
3306         u8 addr;
3307         u16 eepromSize;
3308         unsigned int offs;
3309         int ret;
3310         int mode16 = 0;
3311         unsigned pcnt,tcnt;
3312         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3313         if (!eeprom) {
3314                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3315                            "Failed to allocate memory required to read eeprom");
3316                 return NULL;
3317         }
3318
3319         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3320                      hdw->eeprom_addr);
3321         addr = hdw->eeprom_addr;
3322         /* Seems that if the high bit is set, then the *real* eeprom
3323            address is shifted right now bit position (noticed this in
3324            newer PVR USB2 hardware) */
3325         if (addr & 0x80) addr >>= 1;
3326
3327         /* FX2 documentation states that a 16bit-addressed eeprom is
3328            expected if the I2C address is an odd number (yeah, this is
3329            strange but it's what they do) */
3330         mode16 = (addr & 1);
3331         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3332         trace_eeprom("Examining %d byte eeprom at location 0x%x using %d bit addressing",
3333                      eepromSize, addr,
3334                      mode16 ? 16 : 8);
3335
3336         msg[0].addr = addr;
3337         msg[0].flags = 0;
3338         msg[0].len = mode16 ? 2 : 1;
3339         msg[0].buf = iadd;
3340         msg[1].addr = addr;
3341         msg[1].flags = I2C_M_RD;
3342
3343         /* We have to do the actual eeprom data fetch ourselves, because
3344            (1) we're only fetching part of the eeprom, and (2) if we were
3345            getting the whole thing our I2C driver can't grab it in one
3346            pass - which is what tveeprom is otherwise going to attempt */
3347         memset(eeprom,0,EEPROM_SIZE);
3348         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3349                 pcnt = 16;
3350                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3351                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3352                 if (mode16) {
3353                         iadd[0] = offs >> 8;
3354                         iadd[1] = offs;
3355                 } else {
3356                         iadd[0] = offs;
3357                 }
3358                 msg[1].len = pcnt;
3359                 msg[1].buf = eeprom+tcnt;
3360                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3361                                         msg,ARRAY_SIZE(msg))) != 2) {
3362                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3363                                    "eeprom fetch set offs err=%d",ret);
3364                         kfree(eeprom);
3365                         return NULL;
3366                 }
3367         }
3368         return eeprom;
3369 }
3370
3371
3372 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3373                                 int mode,
3374                                 int enable_flag)
3375 {
3376         int ret;
3377         u16 address;
3378         unsigned int pipe;
3379         LOCK_TAKE(hdw->big_lock); do {
3380                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3381
3382                 if (!enable_flag) {
3383                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3384                                    "Cleaning up after CPU firmware fetch");
3385                         kfree(hdw->fw_buffer);
3386                         hdw->fw_buffer = NULL;
3387                         hdw->fw_size = 0;
3388                         if (hdw->fw_cpu_flag) {
3389                                 /* Now release the CPU.  It will disconnect
3390                                    and reconnect later. */
3391                                 pvr2_hdw_cpureset_assert(hdw,0);
3392                         }
3393                         break;
3394                 }
3395
3396                 hdw->fw_cpu_flag = (mode != 2);
3397                 if (hdw->fw_cpu_flag) {
3398                         hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3399                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3400                                    "Preparing to suck out CPU firmware (size=%u)",
3401                                    hdw->fw_size);
3402                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3403                         if (!hdw->fw_buffer) {
3404                                 hdw->fw_size = 0;
3405                                 break;
3406                         }
3407
3408                         /* We have to hold the CPU during firmware upload. */
3409                         pvr2_hdw_cpureset_assert(hdw,1);
3410
3411                         /* download the firmware from address 0000-1fff in 2048
3412                            (=0x800) bytes chunk. */
3413
3414                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3415                                    "Grabbing CPU firmware");
3416                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3417                         for(address = 0; address < hdw->fw_size;
3418                             address += 0x800) {
3419                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3420                                                       0xa0,0xc0,
3421                                                       address,0,
3422                                                       hdw->fw_buffer+address,
3423                                                       0x800,HZ);
3424                                 if (ret < 0) break;
3425                         }
3426
3427                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3428                                    "Done grabbing CPU firmware");
3429                 } else {
3430                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3431                                    "Sucking down EEPROM contents");
3432                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3433                         if (!hdw->fw_buffer) {
3434                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3435                                            "EEPROM content suck failed.");
3436                                 break;
3437                         }
3438                         hdw->fw_size = EEPROM_SIZE;
3439                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3440                                    "Done sucking down EEPROM contents");
3441                 }
3442
3443         } while (0); LOCK_GIVE(hdw->big_lock);
3444 }
3445
3446
3447 /* Return true if we're in a mode for retrieval CPU firmware */
3448 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3449 {
3450         return hdw->fw_buffer != NULL;
3451 }
3452
3453
3454 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3455                        char *buf,unsigned int cnt)
3456 {
3457         int ret = -EINVAL;
3458         LOCK_TAKE(hdw->big_lock); do {
3459                 if (!buf) break;
3460                 if (!cnt) break;
3461
3462                 if (!hdw->fw_buffer) {
3463                         ret = -EIO;
3464                         break;
3465                 }
3466
3467                 if (offs >= hdw->fw_size) {
3468                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3469                                    "Read firmware data offs=%d EOF",
3470                                    offs);
3471                         ret = 0;
3472                         break;
3473                 }
3474
3475                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3476
3477                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3478
3479                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3480                            "Read firmware data offs=%d cnt=%d",
3481                            offs,cnt);
3482                 ret = cnt;
3483         } while (0); LOCK_GIVE(hdw->big_lock);
3484
3485         return ret;
3486 }
3487
3488
3489 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3490                                   enum pvr2_v4l_type index)
3491 {
3492         switch (index) {
3493         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3494         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3495         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3496         default: return -1;
3497         }
3498 }
3499
3500
3501 /* Store a v4l minor device number */
3502 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3503                                      enum pvr2_v4l_type index,int v)
3504 {
3505         switch (index) {
3506         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3507         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3508         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
3509         default: break;
3510         }
3511 }
3512
3513
3514 static void pvr2_ctl_write_complete(struct urb *urb)
3515 {
3516         struct pvr2_hdw *hdw = urb->context;
3517         hdw->ctl_write_pend_flag = 0;
3518         if (hdw->ctl_read_pend_flag) return;
3519         complete(&hdw->ctl_done);
3520 }
3521
3522
3523 static void pvr2_ctl_read_complete(struct urb *urb)
3524 {
3525         struct pvr2_hdw *hdw = urb->context;
3526         hdw->ctl_read_pend_flag = 0;
3527         if (hdw->ctl_write_pend_flag) return;
3528         complete(&hdw->ctl_done);
3529 }
3530
3531 struct hdw_timer {
3532         struct timer_list timer;
3533         struct pvr2_hdw *hdw;
3534 };
3535
3536 static void pvr2_ctl_timeout(struct timer_list *t)
3537 {
3538         struct hdw_timer *timer = from_timer(timer, t, timer);
3539         struct pvr2_hdw *hdw = timer->hdw;
3540
3541         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3542                 hdw->ctl_timeout_flag = !0;
3543                 if (hdw->ctl_write_pend_flag)
3544                         usb_unlink_urb(hdw->ctl_write_urb);
3545                 if (hdw->ctl_read_pend_flag)
3546                         usb_unlink_urb(hdw->ctl_read_urb);
3547         }
3548 }
3549
3550
3551 /* Issue a command and get a response from the device.  This extended
3552    version includes a probe flag (which if set means that device errors
3553    should not be logged or treated as fatal) and a timeout in jiffies.
3554    This can be used to non-lethally probe the health of endpoint 1. */
3555 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3556                                 unsigned int timeout,int probe_fl,
3557                                 void *write_data,unsigned int write_len,
3558                                 void *read_data,unsigned int read_len)
3559 {
3560         unsigned int idx;
3561         int status = 0;
3562         struct hdw_timer timer = {
3563                 .hdw = hdw,
3564         };
3565
3566         if (!hdw->ctl_lock_held) {
3567                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3568                            "Attempted to execute control transfer without lock!!");
3569                 return -EDEADLK;
3570         }
3571         if (!hdw->flag_ok && !probe_fl) {
3572                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3573                            "Attempted to execute control transfer when device not ok");
3574                 return -EIO;
3575         }
3576         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3577                 if (!probe_fl) {
3578                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3579                                    "Attempted to execute control transfer when USB is disconnected");
3580                 }
3581                 return -ENOTTY;
3582         }
3583
3584         /* Ensure that we have sane parameters */
3585         if (!write_data) write_len = 0;
3586         if (!read_data) read_len = 0;
3587         if (write_len > PVR2_CTL_BUFFSIZE) {
3588                 pvr2_trace(
3589                         PVR2_TRACE_ERROR_LEGS,
3590                         "Attempted to execute %d byte control-write transfer (limit=%d)",
3591                         write_len,PVR2_CTL_BUFFSIZE);
3592                 return -EINVAL;
3593         }
3594         if (read_len > PVR2_CTL_BUFFSIZE) {
3595                 pvr2_trace(
3596                         PVR2_TRACE_ERROR_LEGS,
3597                         "Attempted to execute %d byte control-read transfer (limit=%d)",
3598                         write_len,PVR2_CTL_BUFFSIZE);
3599                 return -EINVAL;
3600         }
3601         if ((!write_len) && (!read_len)) {
3602                 pvr2_trace(
3603                         PVR2_TRACE_ERROR_LEGS,
3604                         "Attempted to execute null control transfer?");
3605                 return -EINVAL;
3606         }
3607
3608
3609         hdw->cmd_debug_state = 1;
3610         if (write_len && write_data)
3611                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3612         else
3613                 hdw->cmd_debug_code = 0;
3614         hdw->cmd_debug_write_len = write_len;
3615         hdw->cmd_debug_read_len = read_len;
3616
3617         /* Initialize common stuff */
3618         init_completion(&hdw->ctl_done);
3619         hdw->ctl_timeout_flag = 0;
3620         hdw->ctl_write_pend_flag = 0;
3621         hdw->ctl_read_pend_flag = 0;
3622         timer_setup_on_stack(&timer.timer, pvr2_ctl_timeout, 0);
3623         timer.timer.expires = jiffies + timeout;
3624
3625         if (write_len && write_data) {
3626                 hdw->cmd_debug_state = 2;
3627                 /* Transfer write data to internal buffer */
3628                 for (idx = 0; idx < write_len; idx++) {
3629                         hdw->ctl_write_buffer[idx] =
3630                                 ((unsigned char *)write_data)[idx];
3631                 }
3632                 /* Initiate a write request */
3633                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3634                                   hdw->usb_dev,
3635                                   usb_sndbulkpipe(hdw->usb_dev,
3636                                                   PVR2_CTL_WRITE_ENDPOINT),
3637                                   hdw->ctl_write_buffer,
3638                                   write_len,
3639                                   pvr2_ctl_write_complete,
3640                                   hdw);
3641                 hdw->ctl_write_urb->actual_length = 0;
3642                 hdw->ctl_write_pend_flag = !0;
3643                 if (usb_urb_ep_type_check(hdw->ctl_write_urb)) {
3644                         pvr2_trace(
3645                                 PVR2_TRACE_ERROR_LEGS,
3646                                 "Invalid write control endpoint");
3647                         return -EINVAL;
3648                 }
3649                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3650                 if (status < 0) {
3651                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3652                                    "Failed to submit write-control URB status=%d",
3653 status);
3654                         hdw->ctl_write_pend_flag = 0;
3655                         goto done;
3656                 }
3657         }
3658
3659         if (read_len) {
3660                 hdw->cmd_debug_state = 3;
3661                 memset(hdw->ctl_read_buffer,0x43,read_len);
3662                 /* Initiate a read request */
3663                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3664                                   hdw->usb_dev,
3665                                   usb_rcvbulkpipe(hdw->usb_dev,
3666                                                   PVR2_CTL_READ_ENDPOINT),
3667                                   hdw->ctl_read_buffer,
3668                                   read_len,
3669                                   pvr2_ctl_read_complete,
3670                                   hdw);
3671                 hdw->ctl_read_urb->actual_length = 0;
3672                 hdw->ctl_read_pend_flag = !0;
3673                 if (usb_urb_ep_type_check(hdw->ctl_read_urb)) {
3674                         pvr2_trace(
3675                                 PVR2_TRACE_ERROR_LEGS,
3676                                 "Invalid read control endpoint");
3677                         return -EINVAL;
3678                 }
3679                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3680                 if (status < 0) {
3681                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3682                                    "Failed to submit read-control URB status=%d",
3683 status);
3684                         hdw->ctl_read_pend_flag = 0;
3685                         goto done;
3686                 }
3687         }
3688
3689         /* Start timer */
3690         add_timer(&timer.timer);
3691
3692         /* Now wait for all I/O to complete */
3693         hdw->cmd_debug_state = 4;
3694         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3695                 wait_for_completion(&hdw->ctl_done);
3696         }
3697         hdw->cmd_debug_state = 5;
3698
3699         /* Stop timer */
3700         del_timer_sync(&timer.timer);
3701
3702         hdw->cmd_debug_state = 6;
3703         status = 0;
3704
3705         if (hdw->ctl_timeout_flag) {
3706                 status = -ETIMEDOUT;
3707                 if (!probe_fl) {
3708                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3709                                    "Timed out control-write");
3710                 }
3711                 goto done;
3712         }
3713
3714         if (write_len) {
3715                 /* Validate results of write request */
3716                 if ((hdw->ctl_write_urb->status != 0) &&
3717                     (hdw->ctl_write_urb->status != -ENOENT) &&
3718                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3719                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3720                         /* USB subsystem is reporting some kind of failure
3721                            on the write */
3722                         status = hdw->ctl_write_urb->status;
3723                         if (!probe_fl) {
3724                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3725                                            "control-write URB failure, status=%d",
3726                                            status);
3727                         }
3728                         goto done;
3729                 }
3730                 if (hdw->ctl_write_urb->actual_length < write_len) {
3731                         /* Failed to write enough data */
3732                         status = -EIO;
3733                         if (!probe_fl) {
3734                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3735                                            "control-write URB short, expected=%d got=%d",
3736                                            write_len,
3737                                            hdw->ctl_write_urb->actual_length);
3738                         }
3739                         goto done;
3740                 }
3741         }
3742         if (read_len && read_data) {
3743                 /* Validate results of read request */
3744                 if ((hdw->ctl_read_urb->status != 0) &&
3745                     (hdw->ctl_read_urb->status != -ENOENT) &&
3746                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3747                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3748                         /* USB subsystem is reporting some kind of failure
3749                            on the read */
3750                         status = hdw->ctl_read_urb->status;
3751                         if (!probe_fl) {
3752                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3753                                            "control-read URB failure, status=%d",
3754                                            status);
3755                         }
3756                         goto done;
3757                 }
3758                 if (hdw->ctl_read_urb->actual_length < read_len) {
3759                         /* Failed to read enough data */
3760                         status = -EIO;
3761                         if (!probe_fl) {
3762                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3763                                            "control-read URB short, expected=%d got=%d",
3764                                            read_len,
3765                                            hdw->ctl_read_urb->actual_length);
3766                         }
3767                         goto done;
3768                 }
3769                 /* Transfer retrieved data out from internal buffer */
3770                 for (idx = 0; idx < read_len; idx++) {
3771                         ((unsigned char *)read_data)[idx] =
3772                                 hdw->ctl_read_buffer[idx];
3773                 }
3774         }
3775
3776  done:
3777
3778         hdw->cmd_debug_state = 0;
3779         if ((status < 0) && (!probe_fl)) {
3780                 pvr2_hdw_render_useless(hdw);
3781         }
3782         destroy_timer_on_stack(&timer.timer);
3783
3784         return status;
3785 }
3786
3787
3788 int pvr2_send_request(struct pvr2_hdw *hdw,
3789                       void *write_data,unsigned int write_len,
3790                       void *read_data,unsigned int read_len)
3791 {
3792         return pvr2_send_request_ex(hdw,HZ*4,0,
3793                                     write_data,write_len,
3794                                     read_data,read_len);
3795 }
3796
3797
3798 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3799 {
3800         int ret;
3801         unsigned int cnt = 1;
3802         unsigned int args = 0;
3803         LOCK_TAKE(hdw->ctl_lock);
3804         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3805         args = (cmdcode >> 8) & 0xffu;
3806         args = (args > 2) ? 2 : args;
3807         if (args) {
3808                 cnt += args;
3809                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3810                 if (args > 1) {
3811                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3812                 }
3813         }
3814         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3815                 unsigned int idx;
3816                 unsigned int ccnt,bcnt;
3817                 char tbuf[50];
3818                 cmdcode &= 0xffu;
3819                 bcnt = 0;
3820                 ccnt = scnprintf(tbuf+bcnt,
3821                                  sizeof(tbuf)-bcnt,
3822                                  "Sending FX2 command 0x%x",cmdcode);
3823                 bcnt += ccnt;
3824                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3825                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3826                                 ccnt = scnprintf(tbuf+bcnt,
3827                                                  sizeof(tbuf)-bcnt,
3828                                                  " \"%s\"",
3829                                                  pvr2_fx2cmd_desc[idx].desc);
3830                                 bcnt += ccnt;
3831                                 break;
3832                         }
3833                 }
3834                 if (args) {
3835                         ccnt = scnprintf(tbuf+bcnt,
3836                                          sizeof(tbuf)-bcnt,
3837                                          " (%u",hdw->cmd_buffer[1]);
3838                         bcnt += ccnt;
3839                         if (args > 1) {
3840                                 ccnt = scnprintf(tbuf+bcnt,
3841                                                  sizeof(tbuf)-bcnt,
3842                                                  ",%u",hdw->cmd_buffer[2]);
3843                                 bcnt += ccnt;
3844                         }
3845                         ccnt = scnprintf(tbuf+bcnt,
3846                                          sizeof(tbuf)-bcnt,
3847                                          ")");
3848                         bcnt += ccnt;
3849                 }
3850                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3851         }
3852         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3853         LOCK_GIVE(hdw->ctl_lock);
3854         return ret;
3855 }
3856
3857
3858 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3859 {
3860         int ret;
3861
3862         LOCK_TAKE(hdw->ctl_lock);
3863
3864         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3865         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3866         hdw->cmd_buffer[5] = 0;
3867         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3868         hdw->cmd_buffer[7] = reg & 0xff;
3869
3870
3871         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3872
3873         LOCK_GIVE(hdw->ctl_lock);
3874
3875         return ret;
3876 }
3877
3878
3879 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3880 {
3881         int ret = 0;
3882
3883         LOCK_TAKE(hdw->ctl_lock);
3884
3885         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3886         hdw->cmd_buffer[1] = 0;
3887         hdw->cmd_buffer[2] = 0;
3888         hdw->cmd_buffer[3] = 0;
3889         hdw->cmd_buffer[4] = 0;
3890         hdw->cmd_buffer[5] = 0;
3891         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3892         hdw->cmd_buffer[7] = reg & 0xff;
3893
3894         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3895         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3896
3897         LOCK_GIVE(hdw->ctl_lock);
3898
3899         return ret;
3900 }
3901
3902
3903 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3904 {
3905         if (!hdw->flag_ok) return;
3906         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3907                    "Device being rendered inoperable");
3908         if (hdw->vid_stream) {
3909                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3910         }
3911         hdw->flag_ok = 0;
3912         trace_stbit("flag_ok",hdw->flag_ok);
3913         pvr2_hdw_state_sched(hdw);
3914 }
3915
3916
3917 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3918 {
3919         int ret;
3920         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3921         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3922         if (ret == 0) {
3923                 ret = usb_reset_device(hdw->usb_dev);
3924                 usb_unlock_device(hdw->usb_dev);
3925         } else {
3926                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3927                            "Failed to lock USB device ret=%d",ret);
3928         }
3929         if (init_pause_msec) {
3930                 pvr2_trace(PVR2_TRACE_INFO,
3931                            "Waiting %u msec for hardware to settle",
3932                            init_pause_msec);
3933                 msleep(init_pause_msec);
3934         }
3935
3936 }
3937
3938
3939 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3940 {
3941         char *da;
3942         unsigned int pipe;
3943         int ret;
3944
3945         if (!hdw->usb_dev) return;
3946
3947         da = kmalloc(16, GFP_KERNEL);
3948
3949         if (da == NULL) {
3950                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3951                            "Unable to allocate memory to control CPU reset");
3952                 return;
3953         }
3954
3955         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3956
3957         da[0] = val ? 0x01 : 0x00;
3958
3959         /* Write the CPUCS register on the 8051.  The lsb of the register
3960            is the reset bit; a 1 asserts reset while a 0 clears it. */
3961         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3962         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3963         if (ret < 0) {
3964                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3965                            "cpureset_assert(%d) error=%d",val,ret);
3966                 pvr2_hdw_render_useless(hdw);
3967         }
3968
3969         kfree(da);
3970 }
3971
3972
3973 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3974 {
3975         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3976 }
3977
3978
3979 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3980 {
3981         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3982 }
3983
3984
3985
3986 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3987 {
3988         pvr2_trace(PVR2_TRACE_INIT,
3989                    "Requesting decoder reset");
3990         if (hdw->decoder_client_id) {
3991                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
3992                                      core, reset, 0);
3993                 pvr2_hdw_cx25840_vbi_hack(hdw);
3994                 return 0;
3995         }
3996         pvr2_trace(PVR2_TRACE_INIT,
3997                    "Unable to reset decoder: nothing attached");
3998         return -ENOTTY;
3999 }
4000
4001
4002 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4003 {
4004         hdw->flag_ok = !0;
4005         return pvr2_issue_simple_cmd(hdw,
4006                                      FX2CMD_HCW_DEMOD_RESETIN |
4007                                      (1 << 8) |
4008                                      ((onoff ? 1 : 0) << 16));
4009 }
4010
4011
4012 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4013 {
4014         hdw->flag_ok = !0;
4015         return pvr2_issue_simple_cmd(hdw,(onoff ?
4016                                           FX2CMD_ONAIR_DTV_POWER_ON :
4017                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4018 }
4019
4020
4021 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4022                                                 int onoff)
4023 {
4024         return pvr2_issue_simple_cmd(hdw,(onoff ?
4025                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4026                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4027 }
4028
4029
4030 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4031 {
4032         int cmode;
4033         /* Compare digital/analog desired setting with current setting.  If
4034            they don't match, fix it... */
4035         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4036         if (cmode == hdw->pathway_state) {
4037                 /* They match; nothing to do */
4038                 return;
4039         }
4040
4041         switch (hdw->hdw_desc->digital_control_scheme) {
4042         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4043                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4044                 if (cmode == PVR2_PATHWAY_ANALOG) {
4045                         /* If moving to analog mode, also force the decoder
4046                            to reset.  If no decoder is attached, then it's
4047                            ok to ignore this because if/when the decoder
4048                            attaches, it will reset itself at that time. */
4049                         pvr2_hdw_cmd_decoder_reset(hdw);
4050                 }
4051                 break;
4052         case PVR2_DIGITAL_SCHEME_ONAIR:
4053                 /* Supposedly we should always have the power on whether in
4054                    digital or analog mode.  But for now do what appears to
4055                    work... */
4056                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4057                 break;
4058         default: break;
4059         }
4060
4061         pvr2_hdw_untrip_unlocked(hdw);
4062         hdw->pathway_state = cmode;
4063 }
4064
4065
4066 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4067 {
4068         /* change some GPIO data
4069          *
4070          * note: bit d7 of dir appears to control the LED,
4071          * so we shut it off here.
4072          *
4073          */
4074         if (onoff) {
4075                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4076         } else {
4077                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4078         }
4079         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4080 }
4081
4082
4083 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4084
4085 static led_method_func led_methods[] = {
4086         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4087 };
4088
4089
4090 /* Toggle LED */
4091 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4092 {
4093         unsigned int scheme_id;
4094         led_method_func fp;
4095
4096         if ((!onoff) == (!hdw->led_on)) return;
4097
4098         hdw->led_on = onoff != 0;
4099
4100         scheme_id = hdw->hdw_desc->led_scheme;
4101         if (scheme_id < ARRAY_SIZE(led_methods)) {
4102                 fp = led_methods[scheme_id];
4103         } else {
4104                 fp = NULL;
4105         }
4106
4107         if (fp) (*fp)(hdw,onoff);
4108 }
4109
4110
4111 /* Stop / start video stream transport */
4112 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4113 {
4114         int ret;
4115
4116         /* If we're in analog mode, then just issue the usual analog
4117            command. */
4118         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4119                 return pvr2_issue_simple_cmd(hdw,
4120                                              (runFl ?
4121                                               FX2CMD_STREAMING_ON :
4122                                               FX2CMD_STREAMING_OFF));
4123                 /*Note: Not reached */
4124         }
4125
4126         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4127                 /* Whoops, we don't know what mode we're in... */
4128                 return -EINVAL;
4129         }
4130
4131         /* To get here we have to be in digital mode.  The mechanism here
4132            is unfortunately different for different vendors.  So we switch
4133            on the device's digital scheme attribute in order to figure out
4134            what to do. */
4135         switch (hdw->hdw_desc->digital_control_scheme) {
4136         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4137                 return pvr2_issue_simple_cmd(hdw,
4138                                              (runFl ?
4139                                               FX2CMD_HCW_DTV_STREAMING_ON :
4140                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4141         case PVR2_DIGITAL_SCHEME_ONAIR:
4142                 ret = pvr2_issue_simple_cmd(hdw,
4143                                             (runFl ?
4144                                              FX2CMD_STREAMING_ON :
4145                                              FX2CMD_STREAMING_OFF));
4146                 if (ret) return ret;
4147                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4148         default:
4149                 return -EINVAL;
4150         }
4151 }
4152
4153
4154 /* Evaluate whether or not state_pathway_ok can change */
4155 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4156 {
4157         if (hdw->state_pathway_ok) {
4158                 /* Nothing to do if pathway is already ok */
4159                 return 0;
4160         }
4161         if (!hdw->state_pipeline_idle) {
4162                 /* Not allowed to change anything if pipeline is not idle */
4163                 return 0;
4164         }
4165         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4166         hdw->state_pathway_ok = !0;
4167         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4168         return !0;
4169 }
4170
4171
4172 /* Evaluate whether or not state_encoder_ok can change */
4173 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4174 {
4175         if (hdw->state_encoder_ok) return 0;
4176         if (hdw->flag_tripped) return 0;
4177         if (hdw->state_encoder_run) return 0;
4178         if (hdw->state_encoder_config) return 0;
4179         if (hdw->state_decoder_run) return 0;
4180         if (hdw->state_usbstream_run) return 0;
4181         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4182                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4183         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4184                 return 0;
4185         }
4186
4187         if (pvr2_upload_firmware2(hdw) < 0) {
4188                 hdw->flag_tripped = !0;
4189                 trace_stbit("flag_tripped",hdw->flag_tripped);
4190                 return !0;
4191         }
4192         hdw->state_encoder_ok = !0;
4193         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4194         return !0;
4195 }
4196
4197
4198 /* Evaluate whether or not state_encoder_config can change */
4199 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4200 {
4201         if (hdw->state_encoder_config) {
4202                 if (hdw->state_encoder_ok) {
4203                         if (hdw->state_pipeline_req &&
4204                             !hdw->state_pipeline_pause) return 0;
4205                 }
4206                 hdw->state_encoder_config = 0;
4207                 hdw->state_encoder_waitok = 0;
4208                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4209                 /* paranoia - solve race if timer just completed */
4210                 del_timer_sync(&hdw->encoder_wait_timer);
4211         } else {
4212                 if (!hdw->state_pathway_ok ||
4213                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4214                     !hdw->state_encoder_ok ||
4215                     !hdw->state_pipeline_idle ||
4216                     hdw->state_pipeline_pause ||
4217                     !hdw->state_pipeline_req ||
4218                     !hdw->state_pipeline_config) {
4219                         /* We must reset the enforced wait interval if
4220                            anything has happened that might have disturbed
4221                            the encoder.  This should be a rare case. */
4222                         if (timer_pending(&hdw->encoder_wait_timer)) {
4223                                 del_timer_sync(&hdw->encoder_wait_timer);
4224                         }
4225                         if (hdw->state_encoder_waitok) {
4226                                 /* Must clear the state - therefore we did
4227                                    something to a state bit and must also
4228                                    return true. */
4229                                 hdw->state_encoder_waitok = 0;
4230                                 trace_stbit("state_encoder_waitok",
4231                                             hdw->state_encoder_waitok);
4232                                 return !0;
4233                         }
4234                         return 0;
4235                 }
4236                 if (!hdw->state_encoder_waitok) {
4237                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4238                                 /* waitok flag wasn't set and timer isn't
4239                                    running.  Check flag once more to avoid
4240                                    a race then start the timer.  This is
4241                                    the point when we measure out a minimal
4242                                    quiet interval before doing something to
4243                                    the encoder. */
4244                                 if (!hdw->state_encoder_waitok) {
4245                                         hdw->encoder_wait_timer.expires =
4246                                                 jiffies + msecs_to_jiffies(
4247                                                 TIME_MSEC_ENCODER_WAIT);
4248                                         add_timer(&hdw->encoder_wait_timer);
4249                                 }
4250                         }
4251                         /* We can't continue until we know we have been
4252                            quiet for the interval measured by this
4253                            timer. */
4254                         return 0;
4255                 }
4256                 pvr2_encoder_configure(hdw);
4257                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4258         }
4259         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4260         return !0;
4261 }
4262
4263
4264 /* Return true if the encoder should not be running. */
4265 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4266 {
4267         if (!hdw->state_encoder_ok) {
4268                 /* Encoder isn't healthy at the moment, so stop it. */
4269                 return !0;
4270         }
4271         if (!hdw->state_pathway_ok) {
4272                 /* Mode is not understood at the moment (i.e. it wants to
4273                    change), so encoder must be stopped. */
4274                 return !0;
4275         }
4276
4277         switch (hdw->pathway_state) {
4278         case PVR2_PATHWAY_ANALOG:
4279                 if (!hdw->state_decoder_run) {
4280                         /* We're in analog mode and the decoder is not
4281                            running; thus the encoder should be stopped as
4282                            well. */
4283                         return !0;
4284                 }
4285                 break;
4286         case PVR2_PATHWAY_DIGITAL:
4287                 if (hdw->state_encoder_runok) {
4288                         /* This is a funny case.  We're in digital mode so
4289                            really the encoder should be stopped.  However
4290                            if it really is running, only kill it after
4291                            runok has been set.  This gives a chance for the
4292                            onair quirk to function (encoder must run
4293                            briefly first, at least once, before onair
4294                            digital streaming can work). */
4295                         return !0;
4296                 }
4297                 break;
4298         default:
4299                 /* Unknown mode; so encoder should be stopped. */
4300                 return !0;
4301         }
4302
4303         /* If we get here, we haven't found a reason to stop the
4304            encoder. */
4305         return 0;
4306 }
4307
4308
4309 /* Return true if the encoder should be running. */
4310 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4311 {
4312         if (!hdw->state_encoder_ok) {
4313                 /* Don't run the encoder if it isn't healthy... */
4314                 return 0;
4315         }
4316         if (!hdw->state_pathway_ok) {
4317                 /* Don't run the encoder if we don't (yet) know what mode
4318                    we need to be in... */
4319                 return 0;
4320         }
4321
4322         switch (hdw->pathway_state) {
4323         case PVR2_PATHWAY_ANALOG:
4324                 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4325                         /* In analog mode, if the decoder is running, then
4326                            run the encoder. */
4327                         return !0;
4328                 }
4329                 break;
4330         case PVR2_PATHWAY_DIGITAL:
4331                 if ((hdw->hdw_desc->digital_control_scheme ==
4332                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4333                     !hdw->state_encoder_runok) {
4334                         /* This is a quirk.  OnAir hardware won't stream
4335                            digital until the encoder has been run at least
4336                            once, for a minimal period of time (empiricially
4337                            measured to be 1/4 second).  So if we're on
4338                            OnAir hardware and the encoder has never been
4339                            run at all, then start the encoder.  Normal
4340                            state machine logic in the driver will
4341                            automatically handle the remaining bits. */
4342                         return !0;
4343                 }
4344                 break;
4345         default:
4346                 /* For completeness (unknown mode; encoder won't run ever) */
4347                 break;
4348         }
4349         /* If we get here, then we haven't found any reason to run the
4350            encoder, so don't run it. */
4351         return 0;
4352 }
4353
4354
4355 /* Evaluate whether or not state_encoder_run can change */
4356 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4357 {
4358         if (hdw->state_encoder_run) {
4359                 if (!state_check_disable_encoder_run(hdw)) return 0;
4360                 if (hdw->state_encoder_ok) {
4361                         del_timer_sync(&hdw->encoder_run_timer);
4362                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4363                 }
4364                 hdw->state_encoder_run = 0;
4365         } else {
4366                 if (!state_check_enable_encoder_run(hdw)) return 0;
4367                 if (pvr2_encoder_start(hdw) < 0) return !0;
4368                 hdw->state_encoder_run = !0;
4369                 if (!hdw->state_encoder_runok) {
4370                         hdw->encoder_run_timer.expires = jiffies +
4371                                  msecs_to_jiffies(TIME_MSEC_ENCODER_OK);
4372                         add_timer(&hdw->encoder_run_timer);
4373                 }
4374         }
4375         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4376         return !0;
4377 }
4378
4379
4380 /* Timeout function for quiescent timer. */
4381 static void pvr2_hdw_quiescent_timeout(struct timer_list *t)
4382 {
4383         struct pvr2_hdw *hdw = from_timer(hdw, t, quiescent_timer);
4384         hdw->state_decoder_quiescent = !0;
4385         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4386         hdw->state_stale = !0;
4387         schedule_work(&hdw->workpoll);
4388 }
4389
4390
4391 /* Timeout function for decoder stabilization timer. */
4392 static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *t)
4393 {
4394         struct pvr2_hdw *hdw = from_timer(hdw, t, decoder_stabilization_timer);
4395         hdw->state_decoder_ready = !0;
4396         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4397         hdw->state_stale = !0;
4398         schedule_work(&hdw->workpoll);
4399 }
4400
4401
4402 /* Timeout function for encoder wait timer. */
4403 static void pvr2_hdw_encoder_wait_timeout(struct timer_list *t)
4404 {
4405         struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_wait_timer);
4406         hdw->state_encoder_waitok = !0;
4407         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4408         hdw->state_stale = !0;
4409         schedule_work(&hdw->workpoll);
4410 }
4411
4412
4413 /* Timeout function for encoder run timer. */
4414 static void pvr2_hdw_encoder_run_timeout(struct timer_list *t)
4415 {
4416         struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_run_timer);
4417         if (!hdw->state_encoder_runok) {
4418                 hdw->state_encoder_runok = !0;
4419                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4420                 hdw->state_stale = !0;
4421                 schedule_work(&hdw->workpoll);
4422         }
4423 }
4424
4425
4426 /* Evaluate whether or not state_decoder_run can change */
4427 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4428 {
4429         if (hdw->state_decoder_run) {
4430                 if (hdw->state_encoder_ok) {
4431                         if (hdw->state_pipeline_req &&
4432                             !hdw->state_pipeline_pause &&
4433                             hdw->state_pathway_ok) return 0;
4434                 }
4435                 if (!hdw->flag_decoder_missed) {
4436                         pvr2_decoder_enable(hdw,0);
4437                 }
4438                 hdw->state_decoder_quiescent = 0;
4439                 hdw->state_decoder_run = 0;
4440                 /* paranoia - solve race if timer(s) just completed */
4441                 del_timer_sync(&hdw->quiescent_timer);
4442                 /* Kill the stabilization timer, in case we're killing the
4443                    encoder before the previous stabilization interval has
4444                    been properly timed. */
4445                 del_timer_sync(&hdw->decoder_stabilization_timer);
4446                 hdw->state_decoder_ready = 0;
4447         } else {
4448                 if (!hdw->state_decoder_quiescent) {
4449                         if (!timer_pending(&hdw->quiescent_timer)) {
4450                                 /* We don't do something about the
4451                                    quiescent timer until right here because
4452                                    we also want to catch cases where the
4453                                    decoder was already not running (like
4454                                    after initialization) as opposed to
4455                                    knowing that we had just stopped it.
4456                                    The second flag check is here to cover a
4457                                    race - the timer could have run and set
4458                                    this flag just after the previous check
4459                                    but before we did the pending check. */
4460                                 if (!hdw->state_decoder_quiescent) {
4461                                         hdw->quiescent_timer.expires =
4462                                                 jiffies + msecs_to_jiffies(
4463                                                 TIME_MSEC_DECODER_WAIT);
4464                                         add_timer(&hdw->quiescent_timer);
4465                                 }
4466                         }
4467                         /* Don't allow decoder to start again until it has
4468                            been quiesced first.  This little detail should
4469                            hopefully further stabilize the encoder. */
4470                         return 0;
4471                 }
4472                 if (!hdw->state_pathway_ok ||
4473                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4474                     !hdw->state_pipeline_req ||
4475                     hdw->state_pipeline_pause ||
4476                     !hdw->state_pipeline_config ||
4477                     !hdw->state_encoder_config ||
4478                     !hdw->state_encoder_ok) return 0;
4479                 del_timer_sync(&hdw->quiescent_timer);
4480                 if (hdw->flag_decoder_missed) return 0;
4481                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4482                 hdw->state_decoder_quiescent = 0;
4483                 hdw->state_decoder_ready = 0;
4484                 hdw->state_decoder_run = !0;
4485                 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4486                         hdw->decoder_stabilization_timer.expires =
4487                                 jiffies + msecs_to_jiffies(
4488                                 TIME_MSEC_DECODER_STABILIZATION_WAIT);
4489                         add_timer(&hdw->decoder_stabilization_timer);
4490                 } else {
4491                         hdw->state_decoder_ready = !0;
4492                 }
4493         }
4494         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4495         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4496         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4497         return !0;
4498 }
4499
4500
4501 /* Evaluate whether or not state_usbstream_run can change */
4502 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4503 {
4504         if (hdw->state_usbstream_run) {
4505                 int fl = !0;
4506                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4507                         fl = (hdw->state_encoder_ok &&
4508                               hdw->state_encoder_run);
4509                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4510                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4511                         fl = hdw->state_encoder_ok;
4512                 }
4513                 if (fl &&
4514                     hdw->state_pipeline_req &&
4515                     !hdw->state_pipeline_pause &&
4516                     hdw->state_pathway_ok) {
4517                         return 0;
4518                 }
4519                 pvr2_hdw_cmd_usbstream(hdw,0);
4520                 hdw->state_usbstream_run = 0;
4521         } else {
4522                 if (!hdw->state_pipeline_req ||
4523                     hdw->state_pipeline_pause ||
4524                     !hdw->state_pathway_ok) return 0;
4525                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4526                         if (!hdw->state_encoder_ok ||
4527                             !hdw->state_encoder_run) return 0;
4528                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4529                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4530                         if (!hdw->state_encoder_ok) return 0;
4531                         if (hdw->state_encoder_run) return 0;
4532                         if (hdw->hdw_desc->digital_control_scheme ==
4533                             PVR2_DIGITAL_SCHEME_ONAIR) {
4534                                 /* OnAir digital receivers won't stream
4535                                    unless the analog encoder has run first.
4536                                    Why?  I have no idea.  But don't even
4537                                    try until we know the analog side is
4538                                    known to have run. */
4539                                 if (!hdw->state_encoder_runok) return 0;
4540                         }
4541                 }
4542                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4543                 hdw->state_usbstream_run = !0;
4544         }
4545         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4546         return !0;
4547 }
4548
4549
4550 /* Attempt to configure pipeline, if needed */
4551 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4552 {
4553         if (hdw->state_pipeline_config ||
4554             hdw->state_pipeline_pause) return 0;
4555         pvr2_hdw_commit_execute(hdw);
4556         return !0;
4557 }
4558
4559
4560 /* Update pipeline idle and pipeline pause tracking states based on other
4561    inputs.  This must be called whenever the other relevant inputs have
4562    changed. */
4563 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4564 {
4565         unsigned int st;
4566         int updatedFl = 0;
4567         /* Update pipeline state */
4568         st = !(hdw->state_encoder_run ||
4569                hdw->state_decoder_run ||
4570                hdw->state_usbstream_run ||
4571                (!hdw->state_decoder_quiescent));
4572         if (!st != !hdw->state_pipeline_idle) {
4573                 hdw->state_pipeline_idle = st;
4574                 updatedFl = !0;
4575         }
4576         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4577                 hdw->state_pipeline_pause = 0;
4578                 updatedFl = !0;
4579         }
4580         return updatedFl;
4581 }
4582
4583
4584 typedef int (*state_eval_func)(struct pvr2_hdw *);
4585
4586 /* Set of functions to be run to evaluate various states in the driver. */
4587 static const state_eval_func eval_funcs[] = {
4588         state_eval_pathway_ok,
4589         state_eval_pipeline_config,
4590         state_eval_encoder_ok,
4591         state_eval_encoder_config,
4592         state_eval_decoder_run,
4593         state_eval_encoder_run,
4594         state_eval_usbstream_run,
4595 };
4596
4597
4598 /* Process various states and return true if we did anything interesting. */
4599 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4600 {
4601         unsigned int i;
4602         int state_updated = 0;
4603         int check_flag;
4604
4605         if (!hdw->state_stale) return 0;
4606         if ((hdw->fw1_state != FW1_STATE_OK) ||
4607             !hdw->flag_ok) {
4608                 hdw->state_stale = 0;
4609                 return !0;
4610         }
4611         /* This loop is the heart of the entire driver.  It keeps trying to
4612            evaluate various bits of driver state until nothing changes for
4613            one full iteration.  Each "bit of state" tracks some global
4614            aspect of the driver, e.g. whether decoder should run, if
4615            pipeline is configured, usb streaming is on, etc.  We separately
4616            evaluate each of those questions based on other driver state to
4617            arrive at the correct running configuration. */
4618         do {
4619                 check_flag = 0;
4620                 state_update_pipeline_state(hdw);
4621                 /* Iterate over each bit of state */
4622                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4623                         if ((*eval_funcs[i])(hdw)) {
4624                                 check_flag = !0;
4625                                 state_updated = !0;
4626                                 state_update_pipeline_state(hdw);
4627                         }
4628                 }
4629         } while (check_flag && hdw->flag_ok);
4630         hdw->state_stale = 0;
4631         trace_stbit("state_stale",hdw->state_stale);
4632         return state_updated;
4633 }
4634
4635
4636 static unsigned int print_input_mask(unsigned int msk,
4637                                      char *buf,unsigned int acnt)
4638 {
4639         unsigned int idx,ccnt;
4640         unsigned int tcnt = 0;
4641         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4642                 if (!((1 << idx) & msk)) continue;
4643                 ccnt = scnprintf(buf+tcnt,
4644                                  acnt-tcnt,
4645                                  "%s%s",
4646                                  (tcnt ? ", " : ""),
4647                                  control_values_input[idx]);
4648                 tcnt += ccnt;
4649         }
4650         return tcnt;
4651 }
4652
4653
4654 static const char *pvr2_pathway_state_name(int id)
4655 {
4656         switch (id) {
4657         case PVR2_PATHWAY_ANALOG: return "analog";
4658         case PVR2_PATHWAY_DIGITAL: return "digital";
4659         default: return "unknown";
4660         }
4661 }
4662
4663
4664 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4665                                              char *buf,unsigned int acnt)
4666 {
4667         switch (which) {
4668         case 0:
4669                 return scnprintf(
4670                         buf,acnt,
4671                         "driver:%s%s%s%s%s <mode=%s>",
4672                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4673                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4674                         (hdw->flag_disconnected ? " <disconnected>" :
4675                          " <connected>"),
4676                         (hdw->flag_tripped ? " <tripped>" : ""),
4677                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4678                         pvr2_pathway_state_name(hdw->pathway_state));
4679
4680         case 1:
4681                 return scnprintf(
4682                         buf,acnt,
4683                         "pipeline:%s%s%s%s",
4684                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4685                         (hdw->state_pipeline_config ?
4686                          " <configok>" : " <stale>"),
4687                         (hdw->state_pipeline_req ? " <req>" : ""),
4688                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4689         case 2:
4690                 return scnprintf(
4691                         buf,acnt,
4692                         "worker:%s%s%s%s%s%s%s",
4693                         (hdw->state_decoder_run ?
4694                          (hdw->state_decoder_ready ?
4695                           "<decode:run>" : " <decode:start>") :
4696                          (hdw->state_decoder_quiescent ?
4697                           "" : " <decode:stop>")),
4698                         (hdw->state_decoder_quiescent ?
4699                          " <decode:quiescent>" : ""),
4700                         (hdw->state_encoder_ok ?
4701                          "" : " <encode:init>"),
4702                         (hdw->state_encoder_run ?
4703                          (hdw->state_encoder_runok ?
4704                           " <encode:run>" :
4705                           " <encode:firstrun>") :
4706                          (hdw->state_encoder_runok ?
4707                           " <encode:stop>" :
4708                           " <encode:virgin>")),
4709                         (hdw->state_encoder_config ?
4710                          " <encode:configok>" :
4711                          (hdw->state_encoder_waitok ?
4712                           "" : " <encode:waitok>")),
4713                         (hdw->state_usbstream_run ?
4714                          " <usb:run>" : " <usb:stop>"),
4715                         (hdw->state_pathway_ok ?
4716                          " <pathway:ok>" : ""));
4717         case 3:
4718                 return scnprintf(
4719                         buf,acnt,
4720                         "state: %s",
4721                         pvr2_get_state_name(hdw->master_state));
4722         case 4: {
4723                 unsigned int tcnt = 0;
4724                 unsigned int ccnt;
4725
4726                 ccnt = scnprintf(buf,
4727                                  acnt,
4728                                  "Hardware supported inputs: ");
4729                 tcnt += ccnt;
4730                 tcnt += print_input_mask(hdw->input_avail_mask,
4731                                          buf+tcnt,
4732                                          acnt-tcnt);
4733                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4734                         ccnt = scnprintf(buf+tcnt,
4735                                          acnt-tcnt,
4736                                          "; allowed inputs: ");
4737                         tcnt += ccnt;
4738                         tcnt += print_input_mask(hdw->input_allowed_mask,
4739                                                  buf+tcnt,
4740                                                  acnt-tcnt);
4741                 }
4742                 return tcnt;
4743         }
4744         case 5: {
4745                 struct pvr2_stream_stats stats;
4746                 if (!hdw->vid_stream) break;
4747                 pvr2_stream_get_stats(hdw->vid_stream,
4748                                       &stats,
4749                                       0);
4750                 return scnprintf(
4751                         buf,acnt,
4752                         "Bytes streamed=%u URBs: queued=%u idle=%u ready=%u processed=%u failed=%u",
4753                         stats.bytes_processed,
4754                         stats.buffers_in_queue,
4755                         stats.buffers_in_idle,
4756                         stats.buffers_in_ready,
4757                         stats.buffers_processed,
4758                         stats.buffers_failed);
4759         }
4760         case 6: {
4761                 unsigned int id = hdw->ir_scheme_active;
4762                 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4763                                  (id >= ARRAY_SIZE(ir_scheme_names) ?
4764                                   "?" : ir_scheme_names[id]));
4765         }
4766         default: break;
4767         }
4768         return 0;
4769 }
4770
4771
4772 /* Generate report containing info about attached sub-devices and attached
4773    i2c clients, including an indication of which attached i2c clients are
4774    actually sub-devices. */
4775 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4776                                             char *buf, unsigned int acnt)
4777 {
4778         struct v4l2_subdev *sd;
4779         unsigned int tcnt = 0;
4780         unsigned int ccnt;
4781         struct i2c_client *client;
4782         const char *p;
4783         unsigned int id;
4784
4785         ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4786         tcnt += ccnt;
4787         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4788                 id = sd->grp_id;
4789                 p = NULL;
4790                 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4791                 if (p) {
4792                         ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4793                         tcnt += ccnt;
4794                 } else {
4795                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4796                                          "  (unknown id=%u):", id);
4797                         tcnt += ccnt;
4798                 }
4799                 client = v4l2_get_subdevdata(sd);
4800                 if (client) {
4801                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4802                                          " %s @ %02x\n", client->name,
4803                                          client->addr);
4804                         tcnt += ccnt;
4805                 } else {
4806                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4807                                          " no i2c client\n");
4808                         tcnt += ccnt;
4809                 }
4810         }
4811         return tcnt;
4812 }
4813
4814
4815 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4816                                    char *buf,unsigned int acnt)
4817 {
4818         unsigned int bcnt,ccnt,idx;
4819         bcnt = 0;
4820         LOCK_TAKE(hdw->big_lock);
4821         for (idx = 0; ; idx++) {
4822                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4823                 if (!ccnt) break;
4824                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4825                 if (!acnt) break;
4826                 buf[0] = '\n'; ccnt = 1;
4827                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4828         }
4829         ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4830         bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4831         LOCK_GIVE(hdw->big_lock);
4832         return bcnt;
4833 }
4834
4835
4836 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4837 {
4838         char buf[256];
4839         unsigned int idx, ccnt;
4840         unsigned int lcnt, ucnt;
4841
4842         for (idx = 0; ; idx++) {
4843                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4844                 if (!ccnt) break;
4845                 pr_info("%s %.*s\n", hdw->name, ccnt, buf);
4846         }
4847         ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4848         if (ccnt >= sizeof(buf))
4849                 ccnt = sizeof(buf);
4850
4851         ucnt = 0;
4852         while (ucnt < ccnt) {
4853                 lcnt = 0;
4854                 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4855                         lcnt++;
4856                 }
4857                 pr_info("%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4858                 ucnt += lcnt + 1;
4859         }
4860 }
4861
4862
4863 /* Evaluate and update the driver's current state, taking various actions
4864    as appropriate for the update. */
4865 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4866 {
4867         unsigned int st;
4868         int state_updated = 0;
4869         int callback_flag = 0;
4870         int analog_mode;
4871
4872         pvr2_trace(PVR2_TRACE_STBITS,
4873                    "Drive state check START");
4874         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4875                 pvr2_hdw_state_log_state(hdw);
4876         }
4877
4878         /* Process all state and get back over disposition */
4879         state_updated = pvr2_hdw_state_update(hdw);
4880
4881         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4882
4883         /* Update master state based upon all other states. */
4884         if (!hdw->flag_ok) {
4885                 st = PVR2_STATE_DEAD;
4886         } else if (hdw->fw1_state != FW1_STATE_OK) {
4887                 st = PVR2_STATE_COLD;
4888         } else if ((analog_mode ||
4889                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4890                    !hdw->state_encoder_ok) {
4891                 st = PVR2_STATE_WARM;
4892         } else if (hdw->flag_tripped ||
4893                    (analog_mode && hdw->flag_decoder_missed)) {
4894                 st = PVR2_STATE_ERROR;
4895         } else if (hdw->state_usbstream_run &&
4896                    (!analog_mode ||
4897                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4898                 st = PVR2_STATE_RUN;
4899         } else {
4900                 st = PVR2_STATE_READY;
4901         }
4902         if (hdw->master_state != st) {
4903                 pvr2_trace(PVR2_TRACE_STATE,
4904                            "Device state change from %s to %s",
4905                            pvr2_get_state_name(hdw->master_state),
4906                            pvr2_get_state_name(st));
4907                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4908                 hdw->master_state = st;
4909                 state_updated = !0;
4910                 callback_flag = !0;
4911         }
4912         if (state_updated) {
4913                 /* Trigger anyone waiting on any state changes here. */
4914                 wake_up(&hdw->state_wait_data);
4915         }
4916
4917         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4918                 pvr2_hdw_state_log_state(hdw);
4919         }
4920         pvr2_trace(PVR2_TRACE_STBITS,
4921                    "Drive state check DONE callback=%d",callback_flag);
4922
4923         return callback_flag;
4924 }
4925
4926
4927 /* Cause kernel thread to check / update driver state */
4928 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4929 {
4930         if (hdw->state_stale) return;
4931         hdw->state_stale = !0;
4932         trace_stbit("state_stale",hdw->state_stale);
4933         schedule_work(&hdw->workpoll);
4934 }
4935
4936
4937 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4938 {
4939         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4940 }
4941
4942
4943 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4944 {
4945         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4946 }
4947
4948
4949 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4950 {
4951         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4952 }
4953
4954
4955 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4956 {
4957         u32 cval,nval;
4958         int ret;
4959         if (~msk) {
4960                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4961                 if (ret) return ret;
4962                 nval = (cval & ~msk) | (val & msk);
4963                 pvr2_trace(PVR2_TRACE_GPIO,
4964                            "GPIO direction changing 0x%x:0x%x from 0x%x to 0x%x",
4965                            msk,val,cval,nval);
4966         } else {
4967                 nval = val;
4968                 pvr2_trace(PVR2_TRACE_GPIO,
4969                            "GPIO direction changing to 0x%x",nval);
4970         }
4971         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4972 }
4973
4974
4975 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4976 {
4977         u32 cval,nval;
4978         int ret;
4979         if (~msk) {
4980                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4981                 if (ret) return ret;
4982                 nval = (cval & ~msk) | (val & msk);
4983                 pvr2_trace(PVR2_TRACE_GPIO,
4984                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4985                            msk,val,cval,nval);
4986         } else {
4987                 nval = val;
4988                 pvr2_trace(PVR2_TRACE_GPIO,
4989                            "GPIO output changing to 0x%x",nval);
4990         }
4991         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4992 }
4993
4994
4995 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
4996 {
4997         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
4998         memset(vtp, 0, sizeof(*vtp));
4999         vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5000                 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
5001         hdw->tuner_signal_stale = 0;
5002         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5003            using v4l2-subdev - therefore we can't support that AT ALL right
5004            now.  (Of course, no sub-drivers seem to implement it either.
5005            But now it's a a chicken and egg problem...) */
5006         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5007         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll type=%u strength=%u audio=0x%x cap=0x%x low=%u hi=%u",
5008                    vtp->type,
5009                    vtp->signal, vtp->rxsubchans, vtp->capability,
5010                    vtp->rangelow, vtp->rangehigh);
5011
5012         /* We have to do this to avoid getting into constant polling if
5013            there's nobody to answer a poll of cropcap info. */
5014         hdw->cropcap_stale = 0;
5015 }
5016
5017
5018 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5019 {
5020         return hdw->input_avail_mask;
5021 }
5022
5023
5024 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5025 {
5026         return hdw->input_allowed_mask;
5027 }
5028
5029
5030 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5031 {
5032         if (hdw->input_val != v) {
5033                 hdw->input_val = v;
5034                 hdw->input_dirty = !0;
5035         }
5036
5037         /* Handle side effects - if we switch to a mode that needs the RF
5038            tuner, then select the right frequency choice as well and mark
5039            it dirty. */
5040         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5041                 hdw->freqSelector = 0;
5042                 hdw->freqDirty = !0;
5043         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5044                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5045                 hdw->freqSelector = 1;
5046                 hdw->freqDirty = !0;
5047         }
5048         return 0;
5049 }
5050
5051
5052 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5053                                unsigned int change_mask,
5054                                unsigned int change_val)
5055 {
5056         int ret = 0;
5057         unsigned int nv,m,idx;
5058         LOCK_TAKE(hdw->big_lock);
5059         do {
5060                 nv = hdw->input_allowed_mask & ~change_mask;
5061                 nv |= (change_val & change_mask);
5062                 nv &= hdw->input_avail_mask;
5063                 if (!nv) {
5064                         /* No legal modes left; return error instead. */
5065                         ret = -EPERM;
5066                         break;
5067                 }
5068                 hdw->input_allowed_mask = nv;
5069                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5070                         /* Current mode is still in the allowed mask, so
5071                            we're done. */
5072                         break;
5073                 }
5074                 /* Select and switch to a mode that is still in the allowed
5075                    mask */
5076                 if (!hdw->input_allowed_mask) {
5077                         /* Nothing legal; give up */
5078                         break;
5079                 }
5080                 m = hdw->input_allowed_mask;
5081                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5082                         if (!((1 << idx) & m)) continue;
5083                         pvr2_hdw_set_input(hdw,idx);
5084                         break;
5085                 }
5086         } while (0);
5087         LOCK_GIVE(hdw->big_lock);
5088         return ret;
5089 }
5090
5091
5092 /* Find I2C address of eeprom */
5093 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5094 {
5095         int result;
5096         LOCK_TAKE(hdw->ctl_lock); do {
5097                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5098                 result = pvr2_send_request(hdw,
5099                                            hdw->cmd_buffer,1,
5100                                            hdw->cmd_buffer,1);
5101                 if (result < 0) break;
5102                 result = hdw->cmd_buffer[0];
5103         } while(0); LOCK_GIVE(hdw->ctl_lock);
5104         return result;
5105 }