2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28 #include <linux/spinlock.h>
29 #include <linux/ioctl.h>
31 /* platform driver name to register */
32 #define NVT_DRIVER_NAME "nuvoton-cir"
34 /* debugging module parameter */
38 #define nvt_dbg(text, ...) \
41 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
43 #define nvt_dbg_verbose(text, ...) \
46 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
48 #define nvt_dbg_wake(text, ...) \
51 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
55 * Original lirc driver said min value of 76, and recommended value of 256
56 * for the buffer length, but then used 2048. Never mind that the size of the
57 * RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm
58 * not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes),
59 * and I don't have TX-capable hardware to test/debug on...
61 #define TX_BUF_LEN 256
64 #define SIO_ID_MASK 0xfff0
68 NVT_W83667HG = 0xa510,
77 enum nvt_chip_ver chip_ver;
93 unsigned int buf_count;
94 unsigned int cur_buf_num;
95 wait_queue_head_t queue;
99 /* EFER Config register index/data pair */
103 /* hardware I/O settings */
104 unsigned long cir_addr;
105 unsigned long cir_wake_addr;
109 enum nvt_chip_ver chip_ver;
114 /* hardware features */
115 bool hw_learning_capable;
119 bool learning_enabled;
121 /* track cir wake state */
125 /* carrier period = 1 / frequency */
130 #define ST_STUDY_NONE 0x0
131 #define ST_STUDY_START 0x1
132 #define ST_STUDY_CARRIER 0x2
133 #define ST_STUDY_ALL_RECV 0x4
136 #define ST_WAKE_NONE 0x0
137 #define ST_WAKE_START 0x1
138 #define ST_WAKE_FINISH 0x2
141 #define ST_RX_WAIT_7F 0x1
142 #define ST_RX_WAIT_HEAD 0x2
143 #define ST_RX_WAIT_SILENT_END 0x4
146 #define ST_TX_NONE 0x0
147 #define ST_TX_REQUEST 0x2
148 #define ST_TX_REPLY 0x4
150 /* buffer packet constants */
151 #define BUF_PULSE_BIT 0x80
152 #define BUF_LEN_MASK 0x7f
153 #define BUF_REPEAT_BYTE 0x70
154 #define BUF_REPEAT_MASK 0xf0
158 /* total length of CIR and CIR WAKE */
159 #define CIR_IOREG_LENGTH 0x0f
161 /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */
162 #define CIR_RX_LIMIT_COUNT (IR_DEFAULT_TIMEOUT / US_TO_NS(SAMPLE_PERIOD))
165 #define CIR_IRCON 0x00
166 #define CIR_IRSTS 0x01
167 #define CIR_IREN 0x02
168 #define CIR_RXFCONT 0x03
171 #define CIR_SLCH 0x06
172 #define CIR_SLCL 0x07
173 #define CIR_FIFOCON 0x08
174 #define CIR_IRFIFOSTS 0x09
175 #define CIR_SRXFIFO 0x0a
176 #define CIR_TXFCONT 0x0b
177 #define CIR_STXFIFO 0x0c
178 #define CIR_FCCH 0x0d
179 #define CIR_FCCL 0x0e
180 #define CIR_IRFSM 0x0f
182 /* CIR IRCON settings */
183 #define CIR_IRCON_RECV 0x80
184 #define CIR_IRCON_WIREN 0x40
185 #define CIR_IRCON_TXEN 0x20
186 #define CIR_IRCON_RXEN 0x10
187 #define CIR_IRCON_WRXINV 0x08
188 #define CIR_IRCON_RXINV 0x04
190 #define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00
191 #define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01
192 #define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02
193 #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03
195 /* FIXME: make this a runtime option */
196 /* select sample period as 50us */
197 #define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
199 /* CIR IRSTS settings */
200 #define CIR_IRSTS_RDR 0x80
201 #define CIR_IRSTS_RTR 0x40
202 #define CIR_IRSTS_PE 0x20
203 #define CIR_IRSTS_RFO 0x10
204 #define CIR_IRSTS_TE 0x08
205 #define CIR_IRSTS_TTR 0x04
206 #define CIR_IRSTS_TFU 0x02
207 #define CIR_IRSTS_GH 0x01
209 /* CIR IREN settings */
210 #define CIR_IREN_RDR 0x80
211 #define CIR_IREN_RTR 0x40
212 #define CIR_IREN_PE 0x20
213 #define CIR_IREN_RFO 0x10
214 #define CIR_IREN_TE 0x08
215 #define CIR_IREN_TTR 0x04
216 #define CIR_IREN_TFU 0x02
217 #define CIR_IREN_GH 0x01
219 /* CIR FIFOCON settings */
220 #define CIR_FIFOCON_TXFIFOCLR 0x80
222 #define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00
223 #define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10
224 #define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20
225 #define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30
227 /* FIXME: make this a runtime option */
228 /* select TX trigger level as 16 */
229 #define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16
231 #define CIR_FIFOCON_RXFIFOCLR 0x08
233 #define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00
234 #define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01
235 #define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02
236 #define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03
238 /* FIXME: make this a runtime option */
239 /* select RX trigger level as 24 */
240 #define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24
242 /* CIR IRFIFOSTS settings */
243 #define CIR_IRFIFOSTS_IR_PENDING 0x80
244 #define CIR_IRFIFOSTS_RX_GS 0x40
245 #define CIR_IRFIFOSTS_RX_FTA 0x20
246 #define CIR_IRFIFOSTS_RX_EMPTY 0x10
247 #define CIR_IRFIFOSTS_RX_FULL 0x08
248 #define CIR_IRFIFOSTS_TX_FTA 0x04
249 #define CIR_IRFIFOSTS_TX_EMPTY 0x02
250 #define CIR_IRFIFOSTS_TX_FULL 0x01
253 /* CIR WAKE UP Regs */
254 #define CIR_WAKE_IRCON 0x00
255 #define CIR_WAKE_IRSTS 0x01
256 #define CIR_WAKE_IREN 0x02
257 #define CIR_WAKE_FIFO_CMP_DEEP 0x03
258 #define CIR_WAKE_FIFO_CMP_TOL 0x04
259 #define CIR_WAKE_FIFO_COUNT 0x05
260 #define CIR_WAKE_SLCH 0x06
261 #define CIR_WAKE_SLCL 0x07
262 #define CIR_WAKE_FIFOCON 0x08
263 #define CIR_WAKE_SRXFSTS 0x09
264 #define CIR_WAKE_SAMPLE_RX_FIFO 0x0a
265 #define CIR_WAKE_WR_FIFO_DATA 0x0b
266 #define CIR_WAKE_RD_FIFO_ONLY 0x0c
267 #define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d
268 #define CIR_WAKE_FIFO_IGNORE 0x0e
269 #define CIR_WAKE_IRFSM 0x0f
271 /* CIR WAKE UP IRCON settings */
272 #define CIR_WAKE_IRCON_DEC_RST 0x80
273 #define CIR_WAKE_IRCON_MODE1 0x40
274 #define CIR_WAKE_IRCON_MODE0 0x20
275 #define CIR_WAKE_IRCON_RXEN 0x10
276 #define CIR_WAKE_IRCON_R 0x08
277 #define CIR_WAKE_IRCON_RXINV 0x04
279 /* FIXME/jarod: make this a runtime option */
280 /* select a same sample period like cir register */
281 #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
283 /* CIR WAKE IRSTS Bits */
284 #define CIR_WAKE_IRSTS_RDR 0x80
285 #define CIR_WAKE_IRSTS_RTR 0x40
286 #define CIR_WAKE_IRSTS_PE 0x20
287 #define CIR_WAKE_IRSTS_RFO 0x10
288 #define CIR_WAKE_IRSTS_GH 0x08
289 #define CIR_WAKE_IRSTS_IR_PENDING 0x01
291 /* CIR WAKE UP IREN Bits */
292 #define CIR_WAKE_IREN_RDR 0x80
293 #define CIR_WAKE_IREN_RTR 0x40
294 #define CIR_WAKE_IREN_PE 0x20
295 #define CIR_WAKE_IREN_RFO 0x10
296 #define CIR_WAKE_IREN_GH 0x08
298 /* CIR WAKE FIFOCON settings */
299 #define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08
301 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00
302 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01
303 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02
304 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03
306 /* FIXME: make this a runtime option */
307 /* select WAKE UP RX trigger level as 67 */
308 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67
310 /* CIR WAKE SRXFSTS settings */
311 #define CIR_WAKE_IRFIFOSTS_RX_GS 0x80
312 #define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40
313 #define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20
314 #define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10
317 * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes
318 * the system comparing only 65 bytes (fails with this set to 67)
320 #define CIR_WAKE_FIFO_CMP_BYTES 65
321 /* CIR Wake byte comparison tolerance */
322 #define CIR_WAKE_CMP_TOLERANCE 5
325 * Extended Function Enable Registers:
326 * Extended Function Index Register
327 * Extended Function Data Register
332 /* Possible alternate EFER values, depends on how the chip is wired */
333 #define CR_EFIR2 0x4e
334 #define CR_EFDR2 0x4f
336 /* Extended Function Mode enable/disable magic values */
337 #define EFER_EFM_ENABLE 0x87
338 #define EFER_EFM_DISABLE 0xaa
340 /* Config regs we need to care about */
341 #define CR_SOFTWARE_RESET 0x02
342 #define CR_LOGICAL_DEV_SEL 0x07
343 #define CR_CHIP_ID_HI 0x20
344 #define CR_CHIP_ID_LO 0x21
345 #define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */
346 #define CR_OUTPUT_PIN_SEL 0x27
347 #define CR_MULTIFUNC_PIN_SEL 0x2c
348 #define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */
349 /* next three regs valid for both the CIR and CIR_WAKE logical devices */
350 #define CR_CIR_BASE_ADDR_HI 0x60
351 #define CR_CIR_BASE_ADDR_LO 0x61
352 #define CR_CIR_IRQ_RSRC 0x70
353 /* next three regs valid only for ACPI logical dev */
354 #define CR_ACPI_CIR_WAKE 0xe0
355 #define CR_ACPI_IRQ_EVENTS 0xf6
356 #define CR_ACPI_IRQ_EVENTS2 0xf7
358 /* Logical devices that we need to care about */
359 #define LOGICAL_DEV_LPT 0x01
360 #define LOGICAL_DEV_CIR 0x06
361 #define LOGICAL_DEV_ACPI 0x0a
362 #define LOGICAL_DEV_CIR_WAKE 0x0e
364 #define LOGICAL_DEV_DISABLE 0x00
365 #define LOGICAL_DEV_ENABLE 0x01
367 #define CIR_WAKE_ENABLE_BIT 0x08
368 #define PME_INTR_CIR_PASS_BIT 0x08
370 /* w83677hg CIR pin config */
371 #define OUTPUT_PIN_SEL_MASK 0xbc
372 #define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
373 #define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */
375 /* w83667hg CIR pin config */
376 #define MULTIFUNC_PIN_SEL_MASK 0x1f
377 #define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
378 #define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */
380 /* MCE CIR signal length, related on sample period */
382 /* MCE CIR controller signal length: about 43ms
383 * 43ms / 50us (sample period) * 0.85 (inaccuracy)
385 #define CONTROLLER_BUF_LEN_MIN 830
387 /* MCE CIR keyboard signal length: about 26ms
388 * 26ms / 50us (sample period) * 0.85 (inaccuracy)
390 #define KEYBOARD_BUF_LEN_MAX 650
391 #define KEYBOARD_BUF_LEN_MIN 610
393 /* MCE CIR mouse signal length: about 24ms
394 * 24ms / 50us (sample period) * 0.85 (inaccuracy)
396 #define MOUSE_BUF_LEN_MIN 565
398 #define CIR_SAMPLE_PERIOD 50
399 #define CIR_SAMPLE_LOW_INACCURACY 0.85
401 /* MAX silence time that driver will sent to lirc */
402 #define MAX_SILENCE_TIME 60000
404 #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100
405 #define SAMPLE_PERIOD 100
407 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50
408 #define SAMPLE_PERIOD 50
410 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25
411 #define SAMPLE_PERIOD 25
414 #define SAMPLE_PERIOD 1
417 /* as VISTA MCE definition, valid carrier value */
418 #define MAX_CARRIER 60000
419 #define MIN_CARRIER 30000
421 /* max wakeup sequence length */
422 #define WAKEUP_MAX_SIZE 65