1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Xilinx MIPI CSI-2 Rx Subsystem
5 * Copyright (C) 2016 - 2020 Xilinx, Inc.
7 * Contacts: Vishal Sagar <vishal.sagar@xilinx.com>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
17 #include <linux/of_irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/v4l2-subdev.h>
20 #include <media/media-entity.h>
21 #include <media/v4l2-common.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-fwnode.h>
24 #include <media/v4l2-subdev.h>
25 #include "xilinx-vip.h"
27 /* Register register map */
28 #define XCSI_CCR_OFFSET 0x00
29 #define XCSI_CCR_SOFTRESET BIT(1)
30 #define XCSI_CCR_ENABLE BIT(0)
32 #define XCSI_PCR_OFFSET 0x04
33 #define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3)
34 #define XCSI_PCR_ACTLANES_MASK GENMASK(1, 0)
36 #define XCSI_CSR_OFFSET 0x10
37 #define XCSI_CSR_PKTCNT GENMASK(31, 16)
38 #define XCSI_CSR_SPFIFOFULL BIT(3)
39 #define XCSI_CSR_SPFIFONE BIT(2)
40 #define XCSI_CSR_SLBF BIT(1)
41 #define XCSI_CSR_RIPCD BIT(0)
43 #define XCSI_GIER_OFFSET 0x20
44 #define XCSI_GIER_GIE BIT(0)
46 #define XCSI_ISR_OFFSET 0x24
47 #define XCSI_IER_OFFSET 0x28
49 #define XCSI_ISR_FR BIT(31)
50 #define XCSI_ISR_VCXFE BIT(30)
51 #define XCSI_ISR_WCC BIT(22)
52 #define XCSI_ISR_ILC BIT(21)
53 #define XCSI_ISR_SPFIFOF BIT(20)
54 #define XCSI_ISR_SPFIFONE BIT(19)
55 #define XCSI_ISR_SLBF BIT(18)
56 #define XCSI_ISR_STOP BIT(17)
57 #define XCSI_ISR_SOTERR BIT(13)
58 #define XCSI_ISR_SOTSYNCERR BIT(12)
59 #define XCSI_ISR_ECC2BERR BIT(11)
60 #define XCSI_ISR_ECC1BERR BIT(10)
61 #define XCSI_ISR_CRCERR BIT(9)
62 #define XCSI_ISR_DATAIDERR BIT(8)
63 #define XCSI_ISR_VC3FSYNCERR BIT(7)
64 #define XCSI_ISR_VC3FLVLERR BIT(6)
65 #define XCSI_ISR_VC2FSYNCERR BIT(5)
66 #define XCSI_ISR_VC2FLVLERR BIT(4)
67 #define XCSI_ISR_VC1FSYNCERR BIT(3)
68 #define XCSI_ISR_VC1FLVLERR BIT(2)
69 #define XCSI_ISR_VC0FSYNCERR BIT(1)
70 #define XCSI_ISR_VC0FLVLERR BIT(0)
72 #define XCSI_ISR_ALLINTR_MASK (0xc07e3fff)
75 * Removed VCXFE mask as it doesn't exist in IER
76 * Removed STOP state irq as this will keep driver in irq handler only
78 #define XCSI_IER_INTR_MASK (XCSI_ISR_ALLINTR_MASK &\
79 ~(XCSI_ISR_STOP | XCSI_ISR_VCXFE))
81 #define XCSI_SPKTR_OFFSET 0x30
82 #define XCSI_SPKTR_DATA GENMASK(23, 8)
83 #define XCSI_SPKTR_VC GENMASK(7, 6)
84 #define XCSI_SPKTR_DT GENMASK(5, 0)
85 #define XCSI_SPKT_FIFO_DEPTH 31
87 #define XCSI_VCXR_OFFSET 0x34
88 #define XCSI_VCXR_VCERR GENMASK(23, 0)
89 #define XCSI_VCXR_FSYNCERR BIT(1)
90 #define XCSI_VCXR_FLVLERR BIT(0)
92 #define XCSI_CLKINFR_OFFSET 0x3C
93 #define XCSI_CLKINFR_STOP BIT(1)
95 #define XCSI_DLXINFR_OFFSET 0x40
96 #define XCSI_DLXINFR_STOP BIT(5)
97 #define XCSI_DLXINFR_SOTERR BIT(1)
98 #define XCSI_DLXINFR_SOTSYNCERR BIT(0)
99 #define XCSI_MAXDL_COUNT 0x4
101 #define XCSI_VCXINF1R_OFFSET 0x60
102 #define XCSI_VCXINF1R_LINECOUNT GENMASK(31, 16)
103 #define XCSI_VCXINF1R_LINECOUNT_SHIFT 16
104 #define XCSI_VCXINF1R_BYTECOUNT GENMASK(15, 0)
106 #define XCSI_VCXINF2R_OFFSET 0x64
107 #define XCSI_VCXINF2R_DT GENMASK(5, 0)
108 #define XCSI_MAXVCX_COUNT 16
111 * Sink pad connected to sensor source pad.
112 * Source pad connected to next module like demosaic.
114 #define XCSI_MEDIA_PADS 2
115 #define XCSI_DEFAULT_WIDTH 1920
116 #define XCSI_DEFAULT_HEIGHT 1080
118 /* MIPI CSI-2 Data Types from spec */
119 #define XCSI_DT_YUV4228B 0x1e
120 #define XCSI_DT_YUV42210B 0x1f
121 #define XCSI_DT_RGB444 0x20
122 #define XCSI_DT_RGB555 0x21
123 #define XCSI_DT_RGB565 0x22
124 #define XCSI_DT_RGB666 0x23
125 #define XCSI_DT_RGB888 0x24
126 #define XCSI_DT_RAW6 0x28
127 #define XCSI_DT_RAW7 0x29
128 #define XCSI_DT_RAW8 0x2a
129 #define XCSI_DT_RAW10 0x2b
130 #define XCSI_DT_RAW12 0x2c
131 #define XCSI_DT_RAW14 0x2d
132 #define XCSI_DT_RAW16 0x2e
133 #define XCSI_DT_RAW20 0x2f
135 #define XCSI_VCX_START 4
136 #define XCSI_MAX_VC 4
137 #define XCSI_MAX_VCX 16
139 #define XCSI_NEXTREG_OFFSET 4
141 /* There are 2 events frame sync and frame level error per VC */
142 #define XCSI_VCX_NUM_EVENTS ((XCSI_MAX_VCX - XCSI_MAX_VC) * 2)
145 * struct xcsi2rxss_event - Event log structure
147 * @name: Name of the event
149 struct xcsi2rxss_event {
154 static const struct xcsi2rxss_event xcsi2rxss_events[] = {
155 { XCSI_ISR_FR, "Frame Received" },
156 { XCSI_ISR_VCXFE, "VCX Frame Errors" },
157 { XCSI_ISR_WCC, "Word Count Errors" },
158 { XCSI_ISR_ILC, "Invalid Lane Count Error" },
159 { XCSI_ISR_SPFIFOF, "Short Packet FIFO OverFlow Error" },
160 { XCSI_ISR_SPFIFONE, "Short Packet FIFO Not Empty" },
161 { XCSI_ISR_SLBF, "Streamline Buffer Full Error" },
162 { XCSI_ISR_STOP, "Lane Stop State" },
163 { XCSI_ISR_SOTERR, "SOT Error" },
164 { XCSI_ISR_SOTSYNCERR, "SOT Sync Error" },
165 { XCSI_ISR_ECC2BERR, "2 Bit ECC Unrecoverable Error" },
166 { XCSI_ISR_ECC1BERR, "1 Bit ECC Recoverable Error" },
167 { XCSI_ISR_CRCERR, "CRC Error" },
168 { XCSI_ISR_DATAIDERR, "Data Id Error" },
169 { XCSI_ISR_VC3FSYNCERR, "Virtual Channel 3 Frame Sync Error" },
170 { XCSI_ISR_VC3FLVLERR, "Virtual Channel 3 Frame Level Error" },
171 { XCSI_ISR_VC2FSYNCERR, "Virtual Channel 2 Frame Sync Error" },
172 { XCSI_ISR_VC2FLVLERR, "Virtual Channel 2 Frame Level Error" },
173 { XCSI_ISR_VC1FSYNCERR, "Virtual Channel 1 Frame Sync Error" },
174 { XCSI_ISR_VC1FLVLERR, "Virtual Channel 1 Frame Level Error" },
175 { XCSI_ISR_VC0FSYNCERR, "Virtual Channel 0 Frame Sync Error" },
176 { XCSI_ISR_VC0FLVLERR, "Virtual Channel 0 Frame Level Error" }
179 #define XCSI_NUM_EVENTS ARRAY_SIZE(xcsi2rxss_events)
182 * This table provides a mapping between CSI-2 Data type
183 * and media bus formats
185 static const u32 xcsi2dt_mbus_lut[][2] = {
186 { XCSI_DT_YUV4228B, MEDIA_BUS_FMT_UYVY8_1X16 },
187 { XCSI_DT_YUV42210B, MEDIA_BUS_FMT_UYVY10_1X20 },
188 { XCSI_DT_RGB444, 0 },
189 { XCSI_DT_RGB555, 0 },
190 { XCSI_DT_RGB565, 0 },
191 { XCSI_DT_RGB666, 0 },
192 { XCSI_DT_RGB888, MEDIA_BUS_FMT_RBG888_1X24 },
195 { XCSI_DT_RAW8, MEDIA_BUS_FMT_SRGGB8_1X8 },
196 { XCSI_DT_RAW8, MEDIA_BUS_FMT_SBGGR8_1X8 },
197 { XCSI_DT_RAW8, MEDIA_BUS_FMT_SGBRG8_1X8 },
198 { XCSI_DT_RAW8, MEDIA_BUS_FMT_SGRBG8_1X8 },
199 { XCSI_DT_RAW10, MEDIA_BUS_FMT_SRGGB10_1X10 },
200 { XCSI_DT_RAW10, MEDIA_BUS_FMT_SBGGR10_1X10 },
201 { XCSI_DT_RAW10, MEDIA_BUS_FMT_SGBRG10_1X10 },
202 { XCSI_DT_RAW10, MEDIA_BUS_FMT_SGRBG10_1X10 },
203 { XCSI_DT_RAW12, MEDIA_BUS_FMT_SRGGB12_1X12 },
204 { XCSI_DT_RAW12, MEDIA_BUS_FMT_SBGGR12_1X12 },
205 { XCSI_DT_RAW12, MEDIA_BUS_FMT_SGBRG12_1X12 },
206 { XCSI_DT_RAW12, MEDIA_BUS_FMT_SGRBG12_1X12 },
207 { XCSI_DT_RAW16, MEDIA_BUS_FMT_SRGGB16_1X16 },
208 { XCSI_DT_RAW16, MEDIA_BUS_FMT_SBGGR16_1X16 },
209 { XCSI_DT_RAW16, MEDIA_BUS_FMT_SGBRG16_1X16 },
210 { XCSI_DT_RAW16, MEDIA_BUS_FMT_SGRBG16_1X16 },
211 { XCSI_DT_RAW20, 0 },
215 * struct xcsi2rxss_state - CSI-2 Rx Subsystem device structure
216 * @subdev: The v4l2 subdev structure
217 * @format: Active V4L2 formats on each pad
218 * @default_format: Default V4L2 format
219 * @events: counter for events
220 * @vcx_events: counter for vcx_events
221 * @dev: Platform structure
222 * @rsubdev: Remote subdev connected to sink pad
223 * @rst_gpio: reset to video_aresetn
224 * @clks: array of clocks
225 * @iomem: Base address of subsystem
226 * @max_num_lanes: Maximum number of lanes present
227 * @datatype: Data type filter
228 * @lock: mutex for accessing this structure
230 * @streaming: Flag for storing streaming state
231 * @enable_active_lanes: If number of active lanes can be modified
232 * @en_vcx: If more than 4 VC are enabled
234 * This structure contains the device driver related parameters
236 struct xcsi2rxss_state {
237 struct v4l2_subdev subdev;
238 struct v4l2_mbus_framefmt format;
239 struct v4l2_mbus_framefmt default_format;
240 u32 events[XCSI_NUM_EVENTS];
241 u32 vcx_events[XCSI_VCX_NUM_EVENTS];
243 struct v4l2_subdev *rsubdev;
244 struct gpio_desc *rst_gpio;
245 struct clk_bulk_data *clks;
249 /* used to protect access to this struct */
251 struct media_pad pads[XCSI_MEDIA_PADS];
253 bool enable_active_lanes;
257 static const struct clk_bulk_data xcsi2rxss_clks[] = {
258 { .id = "lite_aclk" },
259 { .id = "video_aclk" },
262 static inline struct xcsi2rxss_state *
263 to_xcsi2rxssstate(struct v4l2_subdev *subdev)
265 return container_of(subdev, struct xcsi2rxss_state, subdev);
269 * Register related operations
271 static inline u32 xcsi2rxss_read(struct xcsi2rxss_state *xcsi2rxss, u32 addr)
273 return ioread32(xcsi2rxss->iomem + addr);
276 static inline void xcsi2rxss_write(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
279 iowrite32(value, xcsi2rxss->iomem + addr);
282 static inline void xcsi2rxss_clr(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
285 xcsi2rxss_write(xcsi2rxss, addr,
286 xcsi2rxss_read(xcsi2rxss, addr) & ~clr);
289 static inline void xcsi2rxss_set(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
292 xcsi2rxss_write(xcsi2rxss, addr, xcsi2rxss_read(xcsi2rxss, addr) | set);
296 * This function returns the nth mbus for a data type.
297 * In case of error, mbus code returned is 0.
299 static u32 xcsi2rxss_get_nth_mbus(u32 dt, u32 n)
303 for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) {
304 if (xcsi2dt_mbus_lut[i][0] == dt) {
306 return xcsi2dt_mbus_lut[i][1];
313 /* This returns the data type for a media bus format else 0 */
314 static u32 xcsi2rxss_get_dt(u32 mbus)
318 for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) {
319 if (xcsi2dt_mbus_lut[i][1] == mbus)
320 return xcsi2dt_mbus_lut[i][0];
327 * xcsi2rxss_soft_reset - Does a soft reset of the MIPI CSI-2 Rx Subsystem
328 * @state: Xilinx CSI-2 Rx Subsystem structure pointer
330 * Core takes less than 100 video clock cycles to reset.
331 * So a larger timeout value is chosen for margin.
333 * Return: 0 - on success OR -ETIME if reset times out
335 static int xcsi2rxss_soft_reset(struct xcsi2rxss_state *state)
337 u32 timeout = 1000; /* us */
339 xcsi2rxss_set(state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET);
341 while (xcsi2rxss_read(state, XCSI_CSR_OFFSET) & XCSI_CSR_RIPCD) {
343 dev_err(state->dev, "soft reset timed out!\n");
351 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET);
355 static void xcsi2rxss_hard_reset(struct xcsi2rxss_state *state)
357 if (!state->rst_gpio)
360 /* minimum of 40 dphy_clk_200M cycles */
361 gpiod_set_value_cansleep(state->rst_gpio, 1);
363 gpiod_set_value_cansleep(state->rst_gpio, 0);
366 static void xcsi2rxss_reset_event_counters(struct xcsi2rxss_state *state)
370 for (i = 0; i < XCSI_NUM_EVENTS; i++)
371 state->events[i] = 0;
373 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++)
374 state->vcx_events[i] = 0;
377 /* Print event counters */
378 static void xcsi2rxss_log_counters(struct xcsi2rxss_state *state)
380 struct device *dev = state->dev;
383 for (i = 0; i < XCSI_NUM_EVENTS; i++) {
384 if (state->events[i] > 0) {
385 dev_info(dev, "%s events: %d\n",
386 xcsi2rxss_events[i].name,
392 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) {
393 if (state->vcx_events[i] > 0) {
395 "VC %d Frame %s err vcx events: %d\n",
396 (i / 2) + XCSI_VCX_START,
397 i & 1 ? "Sync" : "Level",
398 state->vcx_events[i]);
405 * xcsi2rxss_log_status - Logs the status of the CSI-2 Receiver
406 * @sd: Pointer to V4L2 subdevice structure
408 * This function prints the current status of Xilinx MIPI CSI-2
410 * Return: 0 on success
412 static int xcsi2rxss_log_status(struct v4l2_subdev *sd)
414 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
415 struct device *dev = xcsi2rxss->dev;
417 unsigned int i, max_vc;
419 mutex_lock(&xcsi2rxss->lock);
421 xcsi2rxss_log_counters(xcsi2rxss);
423 dev_info(dev, "***** Core Status *****\n");
424 data = xcsi2rxss_read(xcsi2rxss, XCSI_CSR_OFFSET);
425 dev_info(dev, "Short Packet FIFO Full = %s\n",
426 data & XCSI_CSR_SPFIFOFULL ? "true" : "false");
427 dev_info(dev, "Short Packet FIFO Not Empty = %s\n",
428 data & XCSI_CSR_SPFIFONE ? "true" : "false");
429 dev_info(dev, "Stream line buffer full = %s\n",
430 data & XCSI_CSR_SLBF ? "true" : "false");
431 dev_info(dev, "Soft reset/Core disable in progress = %s\n",
432 data & XCSI_CSR_RIPCD ? "true" : "false");
434 /* Clk & Lane Info */
435 dev_info(dev, "******** Clock Lane Info *********\n");
436 data = xcsi2rxss_read(xcsi2rxss, XCSI_CLKINFR_OFFSET);
437 dev_info(dev, "Clock Lane in Stop State = %s\n",
438 data & XCSI_CLKINFR_STOP ? "true" : "false");
440 dev_info(dev, "******** Data Lane Info *********\n");
441 dev_info(dev, "Lane\tSoT Error\tSoT Sync Error\tStop State\n");
442 reg = XCSI_DLXINFR_OFFSET;
443 for (i = 0; i < XCSI_MAXDL_COUNT; i++) {
444 data = xcsi2rxss_read(xcsi2rxss, reg);
446 dev_info(dev, "%d\t%s\t\t%s\t\t%s\n", i,
447 data & XCSI_DLXINFR_SOTERR ? "true" : "false",
448 data & XCSI_DLXINFR_SOTSYNCERR ? "true" : "false",
449 data & XCSI_DLXINFR_STOP ? "true" : "false");
451 reg += XCSI_NEXTREG_OFFSET;
454 /* Virtual Channel Image Information */
455 dev_info(dev, "********** Virtual Channel Info ************\n");
456 dev_info(dev, "VC\tLine Count\tByte Count\tData Type\n");
457 if (xcsi2rxss->en_vcx)
458 max_vc = XCSI_MAX_VCX;
460 max_vc = XCSI_MAX_VC;
462 reg = XCSI_VCXINF1R_OFFSET;
463 for (i = 0; i < max_vc; i++) {
464 u32 line_count, byte_count, data_type;
466 /* Get line and byte count from VCXINFR1 Register */
467 data = xcsi2rxss_read(xcsi2rxss, reg);
468 byte_count = data & XCSI_VCXINF1R_BYTECOUNT;
469 line_count = data & XCSI_VCXINF1R_LINECOUNT;
470 line_count >>= XCSI_VCXINF1R_LINECOUNT_SHIFT;
472 /* Get data type from VCXINFR2 Register */
473 reg += XCSI_NEXTREG_OFFSET;
474 data = xcsi2rxss_read(xcsi2rxss, reg);
475 data_type = data & XCSI_VCXINF2R_DT;
477 dev_info(dev, "%d\t%d\t\t%d\t\t0x%x\n", i, line_count,
478 byte_count, data_type);
480 /* Move to next pair of VC Info registers */
481 reg += XCSI_NEXTREG_OFFSET;
484 mutex_unlock(&xcsi2rxss->lock);
489 static struct v4l2_subdev *xcsi2rxss_get_remote_subdev(struct media_pad *local)
491 struct media_pad *remote;
493 remote = media_entity_remote_pad(local);
494 if (!remote || !is_media_entity_v4l2_subdev(remote->entity))
497 return media_entity_to_v4l2_subdev(remote->entity);
500 static int xcsi2rxss_start_stream(struct xcsi2rxss_state *state)
505 xcsi2rxss_set(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
507 ret = xcsi2rxss_soft_reset(state);
509 state->streaming = false;
513 /* enable interrupts */
514 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
515 xcsi2rxss_write(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
516 xcsi2rxss_set(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
518 state->streaming = true;
521 xcsi2rxss_get_remote_subdev(&state->pads[XVIP_PAD_SINK]);
523 ret = v4l2_subdev_call(state->rsubdev, video, s_stream, 1);
525 /* disable interrupts */
526 xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
527 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
530 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
531 state->streaming = false;
537 static void xcsi2rxss_stop_stream(struct xcsi2rxss_state *state)
539 v4l2_subdev_call(state->rsubdev, video, s_stream, 0);
541 /* disable interrupts */
542 xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
543 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
546 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
547 state->streaming = false;
551 * xcsi2rxss_irq_handler - Interrupt handler for CSI-2
553 * @data: Pointer to device state
555 * In the interrupt handler, a list of event counters are updated for
556 * corresponding interrupts. This is useful to get status / debug.
558 * Return: IRQ_HANDLED after handling interrupts
560 static irqreturn_t xcsi2rxss_irq_handler(int irq, void *data)
562 struct xcsi2rxss_state *state = (struct xcsi2rxss_state *)data;
563 struct device *dev = state->dev;
566 status = xcsi2rxss_read(state, XCSI_ISR_OFFSET) & XCSI_ISR_ALLINTR_MASK;
567 xcsi2rxss_write(state, XCSI_ISR_OFFSET, status);
569 /* Received a short packet */
570 if (status & XCSI_ISR_SPFIFONE) {
574 * Drain generic short packet FIFO by reading max 31
575 * (fifo depth) short packets from fifo or till fifo is empty.
577 for (count = 0; count < XCSI_SPKT_FIFO_DEPTH; ++count) {
578 u32 spfifostat, spkt;
580 spkt = xcsi2rxss_read(state, XCSI_SPKTR_OFFSET);
581 dev_dbg(dev, "Short packet = 0x%08x\n", spkt);
582 spfifostat = xcsi2rxss_read(state, XCSI_ISR_OFFSET);
583 spfifostat &= XCSI_ISR_SPFIFONE;
586 xcsi2rxss_write(state, XCSI_ISR_OFFSET, spfifostat);
590 /* Short packet FIFO overflow */
591 if (status & XCSI_ISR_SPFIFOF)
592 dev_dbg_ratelimited(dev, "Short packet FIFO overflowed\n");
595 * Stream line buffer full
596 * This means there is a backpressure from downstream IP
598 if (status & XCSI_ISR_SLBF) {
599 dev_alert_ratelimited(dev, "Stream Line Buffer Full!\n");
601 /* disable interrupts */
602 xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
603 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
606 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
609 * The IP needs to be hard reset before it can be used now.
610 * This will be done in streamoff.
614 * TODO: Notify the whole pipeline with v4l2_subdev_notify() to
619 /* Increment event counters */
620 if (status & XCSI_ISR_ALLINTR_MASK) {
623 for (i = 0; i < XCSI_NUM_EVENTS; i++) {
624 if (!(status & xcsi2rxss_events[i].mask))
627 dev_dbg_ratelimited(dev, "%s: %u\n",
628 xcsi2rxss_events[i].name,
632 if (status & XCSI_ISR_VCXFE && state->en_vcx) {
635 vcxstatus = xcsi2rxss_read(state, XCSI_VCXR_OFFSET);
636 vcxstatus &= XCSI_VCXR_VCERR;
637 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) {
638 if (!(vcxstatus & BIT(i)))
640 state->vcx_events[i]++;
642 xcsi2rxss_write(state, XCSI_VCXR_OFFSET, vcxstatus);
650 * xcsi2rxss_s_stream - It is used to start/stop the streaming.
651 * @sd: V4L2 Sub device
652 * @enable: Flag (True / False)
654 * This function controls the start or stop of streaming for the
655 * Xilinx MIPI CSI-2 Rx Subsystem.
657 * Return: 0 on success, errors otherwise
659 static int xcsi2rxss_s_stream(struct v4l2_subdev *sd, int enable)
661 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
664 mutex_lock(&xcsi2rxss->lock);
666 if (enable == xcsi2rxss->streaming)
670 xcsi2rxss_reset_event_counters(xcsi2rxss);
671 ret = xcsi2rxss_start_stream(xcsi2rxss);
673 xcsi2rxss_stop_stream(xcsi2rxss);
674 xcsi2rxss_hard_reset(xcsi2rxss);
678 mutex_unlock(&xcsi2rxss->lock);
682 static struct v4l2_mbus_framefmt *
683 __xcsi2rxss_get_pad_format(struct xcsi2rxss_state *xcsi2rxss,
684 struct v4l2_subdev_state *sd_state,
685 unsigned int pad, u32 which)
688 case V4L2_SUBDEV_FORMAT_TRY:
689 return v4l2_subdev_get_try_format(&xcsi2rxss->subdev,
691 case V4L2_SUBDEV_FORMAT_ACTIVE:
692 return &xcsi2rxss->format;
699 * xcsi2rxss_init_cfg - Initialise the pad format config to default
700 * @sd: Pointer to V4L2 Sub device structure
701 * @sd_state: Pointer to sub device state structure
703 * This function is used to initialize the pad format with the default
706 * Return: 0 on success
708 static int xcsi2rxss_init_cfg(struct v4l2_subdev *sd,
709 struct v4l2_subdev_state *sd_state)
711 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
712 struct v4l2_mbus_framefmt *format;
715 mutex_lock(&xcsi2rxss->lock);
716 for (i = 0; i < XCSI_MEDIA_PADS; i++) {
717 format = v4l2_subdev_get_try_format(sd, sd_state, i);
718 *format = xcsi2rxss->default_format;
720 mutex_unlock(&xcsi2rxss->lock);
726 * xcsi2rxss_get_format - Get the pad format
727 * @sd: Pointer to V4L2 Sub device structure
728 * @sd_state: Pointer to sub device state structure
729 * @fmt: Pointer to pad level media bus format
731 * This function is used to get the pad format information.
733 * Return: 0 on success
735 static int xcsi2rxss_get_format(struct v4l2_subdev *sd,
736 struct v4l2_subdev_state *sd_state,
737 struct v4l2_subdev_format *fmt)
739 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
741 mutex_lock(&xcsi2rxss->lock);
742 fmt->format = *__xcsi2rxss_get_pad_format(xcsi2rxss, sd_state,
745 mutex_unlock(&xcsi2rxss->lock);
751 * xcsi2rxss_set_format - This is used to set the pad format
752 * @sd: Pointer to V4L2 Sub device structure
753 * @sd_state: Pointer to sub device state structure
754 * @fmt: Pointer to pad level media bus format
756 * This function is used to set the pad format. Since the pad format is fixed
757 * in hardware, it can't be modified on run time. So when a format set is
758 * requested by application, all parameters except the format type is saved
759 * for the pad and the original pad format is sent back to the application.
761 * Return: 0 on success
763 static int xcsi2rxss_set_format(struct v4l2_subdev *sd,
764 struct v4l2_subdev_state *sd_state,
765 struct v4l2_subdev_format *fmt)
767 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
768 struct v4l2_mbus_framefmt *__format;
771 mutex_lock(&xcsi2rxss->lock);
774 * Only the format->code parameter matters for CSI as the
775 * CSI format cannot be changed at runtime.
776 * Ensure that format to set is copied to over to CSI pad format
778 __format = __xcsi2rxss_get_pad_format(xcsi2rxss, sd_state,
779 fmt->pad, fmt->which);
781 /* only sink pad format can be updated */
782 if (fmt->pad == XVIP_PAD_SOURCE) {
783 fmt->format = *__format;
784 mutex_unlock(&xcsi2rxss->lock);
789 * RAW8 is supported in all datatypes. So if requested media bus format
790 * is of RAW8 type, then allow to be set. In case core is configured to
791 * other RAW, YUV422 8/10 or RGB888, set appropriate media bus format.
793 dt = xcsi2rxss_get_dt(fmt->format.code);
794 if (dt != xcsi2rxss->datatype && dt != XCSI_DT_RAW8) {
795 dev_dbg(xcsi2rxss->dev, "Unsupported media bus format");
796 /* set the default format for the data type */
797 fmt->format.code = xcsi2rxss_get_nth_mbus(xcsi2rxss->datatype,
801 *__format = fmt->format;
802 mutex_unlock(&xcsi2rxss->lock);
808 * xcsi2rxss_enum_mbus_code - Handle pixel format enumeration
809 * @sd: pointer to v4l2 subdev structure
810 * @cfg: V4L2 subdev pad configuration
811 * @code: pointer to v4l2_subdev_mbus_code_enum structure
813 * Return: -EINVAL or zero on success
815 static int xcsi2rxss_enum_mbus_code(struct v4l2_subdev *sd,
816 struct v4l2_subdev_state *sd_state,
817 struct v4l2_subdev_mbus_code_enum *code)
819 struct xcsi2rxss_state *state = to_xcsi2rxssstate(sd);
823 /* RAW8 dt packets are available in all DT configurations */
824 if (code->index < 4) {
827 } else if (state->datatype != XCSI_DT_RAW8) {
829 dt = state->datatype;
834 code->code = xcsi2rxss_get_nth_mbus(dt, n);
841 /* -----------------------------------------------------------------------------
845 static const struct media_entity_operations xcsi2rxss_media_ops = {
846 .link_validate = v4l2_subdev_link_validate
849 static const struct v4l2_subdev_core_ops xcsi2rxss_core_ops = {
850 .log_status = xcsi2rxss_log_status,
853 static const struct v4l2_subdev_video_ops xcsi2rxss_video_ops = {
854 .s_stream = xcsi2rxss_s_stream
857 static const struct v4l2_subdev_pad_ops xcsi2rxss_pad_ops = {
858 .init_cfg = xcsi2rxss_init_cfg,
859 .get_fmt = xcsi2rxss_get_format,
860 .set_fmt = xcsi2rxss_set_format,
861 .enum_mbus_code = xcsi2rxss_enum_mbus_code,
862 .link_validate = v4l2_subdev_link_validate_default,
865 static const struct v4l2_subdev_ops xcsi2rxss_ops = {
866 .core = &xcsi2rxss_core_ops,
867 .video = &xcsi2rxss_video_ops,
868 .pad = &xcsi2rxss_pad_ops
871 static int xcsi2rxss_parse_of(struct xcsi2rxss_state *xcsi2rxss)
873 struct device *dev = xcsi2rxss->dev;
874 struct device_node *node = dev->of_node;
876 struct fwnode_handle *ep;
877 struct v4l2_fwnode_endpoint vep = {
878 .bus_type = V4L2_MBUS_CSI2_DPHY
880 bool en_csi_v20, vfb;
883 en_csi_v20 = of_property_read_bool(node, "xlnx,en-csi-v2-0");
885 xcsi2rxss->en_vcx = of_property_read_bool(node, "xlnx,en-vcx");
887 xcsi2rxss->enable_active_lanes =
888 of_property_read_bool(node, "xlnx,en-active-lanes");
890 ret = of_property_read_u32(node, "xlnx,csi-pxl-format",
891 &xcsi2rxss->datatype);
893 dev_err(dev, "missing xlnx,csi-pxl-format property\n");
897 switch (xcsi2rxss->datatype) {
898 case XCSI_DT_YUV4228B:
911 case XCSI_DT_YUV42210B:
916 dev_dbg(dev, "enable csi v2 for this pixel format");
923 dev_err(dev, "invalid csi-pxl-format property!\n");
927 vfb = of_property_read_bool(node, "xlnx,vfb");
929 dev_err(dev, "operation without VFB is not supported\n");
933 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
935 FWNODE_GRAPH_ENDPOINT_NEXT);
937 dev_err(dev, "no sink port found");
941 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
942 fwnode_handle_put(ep);
944 dev_err(dev, "error parsing sink port");
948 dev_dbg(dev, "mipi number lanes = %d\n",
949 vep.bus.mipi_csi2.num_data_lanes);
951 xcsi2rxss->max_num_lanes = vep.bus.mipi_csi2.num_data_lanes;
953 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
955 FWNODE_GRAPH_ENDPOINT_NEXT);
957 dev_err(dev, "no source port found");
961 fwnode_handle_put(ep);
963 dev_dbg(dev, "vcx %s, %u data lanes (%s), data type 0x%02x\n",
964 xcsi2rxss->en_vcx ? "enabled" : "disabled",
965 xcsi2rxss->max_num_lanes,
966 xcsi2rxss->enable_active_lanes ? "dynamic" : "static",
967 xcsi2rxss->datatype);
972 static int xcsi2rxss_probe(struct platform_device *pdev)
974 struct v4l2_subdev *subdev;
975 struct xcsi2rxss_state *xcsi2rxss;
976 int num_clks = ARRAY_SIZE(xcsi2rxss_clks);
977 struct device *dev = &pdev->dev;
980 xcsi2rxss = devm_kzalloc(dev, sizeof(*xcsi2rxss), GFP_KERNEL);
984 xcsi2rxss->dev = dev;
986 xcsi2rxss->clks = devm_kmemdup(dev, xcsi2rxss_clks,
987 sizeof(xcsi2rxss_clks), GFP_KERNEL);
988 if (!xcsi2rxss->clks)
992 xcsi2rxss->rst_gpio = devm_gpiod_get_optional(dev, "video-reset",
994 if (IS_ERR(xcsi2rxss->rst_gpio)) {
995 if (PTR_ERR(xcsi2rxss->rst_gpio) != -EPROBE_DEFER)
996 dev_err(dev, "Video Reset GPIO not setup in DT");
997 return PTR_ERR(xcsi2rxss->rst_gpio);
1000 ret = xcsi2rxss_parse_of(xcsi2rxss);
1004 xcsi2rxss->iomem = devm_platform_ioremap_resource(pdev, 0);
1005 if (IS_ERR(xcsi2rxss->iomem))
1006 return PTR_ERR(xcsi2rxss->iomem);
1008 irq = platform_get_irq(pdev, 0);
1012 ret = devm_request_threaded_irq(dev, irq, NULL,
1013 xcsi2rxss_irq_handler, IRQF_ONESHOT,
1014 dev_name(dev), xcsi2rxss);
1016 dev_err(dev, "Err = %d Interrupt handler reg failed!\n", ret);
1020 ret = clk_bulk_get(dev, num_clks, xcsi2rxss->clks);
1024 /* TODO: Enable/disable clocks at stream on/off time. */
1025 ret = clk_bulk_prepare_enable(num_clks, xcsi2rxss->clks);
1029 mutex_init(&xcsi2rxss->lock);
1031 xcsi2rxss_hard_reset(xcsi2rxss);
1032 xcsi2rxss_soft_reset(xcsi2rxss);
1034 /* Initialize V4L2 subdevice and media entity */
1035 xcsi2rxss->pads[XVIP_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1036 xcsi2rxss->pads[XVIP_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1038 /* Initialize the default format */
1039 xcsi2rxss->default_format.code =
1040 xcsi2rxss_get_nth_mbus(xcsi2rxss->datatype, 0);
1041 xcsi2rxss->default_format.field = V4L2_FIELD_NONE;
1042 xcsi2rxss->default_format.colorspace = V4L2_COLORSPACE_SRGB;
1043 xcsi2rxss->default_format.width = XCSI_DEFAULT_WIDTH;
1044 xcsi2rxss->default_format.height = XCSI_DEFAULT_HEIGHT;
1045 xcsi2rxss->format = xcsi2rxss->default_format;
1047 /* Initialize V4L2 subdevice and media entity */
1048 subdev = &xcsi2rxss->subdev;
1049 v4l2_subdev_init(subdev, &xcsi2rxss_ops);
1051 strscpy(subdev->name, dev_name(dev), sizeof(subdev->name));
1052 subdev->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
1053 subdev->entity.ops = &xcsi2rxss_media_ops;
1054 v4l2_set_subdevdata(subdev, xcsi2rxss);
1056 ret = media_entity_pads_init(&subdev->entity, XCSI_MEDIA_PADS,
1061 platform_set_drvdata(pdev, xcsi2rxss);
1063 ret = v4l2_async_register_subdev(subdev);
1065 dev_err(dev, "failed to register subdev\n");
1071 media_entity_cleanup(&subdev->entity);
1072 mutex_destroy(&xcsi2rxss->lock);
1073 clk_bulk_disable_unprepare(num_clks, xcsi2rxss->clks);
1075 clk_bulk_put(num_clks, xcsi2rxss->clks);
1079 static int xcsi2rxss_remove(struct platform_device *pdev)
1081 struct xcsi2rxss_state *xcsi2rxss = platform_get_drvdata(pdev);
1082 struct v4l2_subdev *subdev = &xcsi2rxss->subdev;
1083 int num_clks = ARRAY_SIZE(xcsi2rxss_clks);
1085 v4l2_async_unregister_subdev(subdev);
1086 media_entity_cleanup(&subdev->entity);
1087 mutex_destroy(&xcsi2rxss->lock);
1088 clk_bulk_disable_unprepare(num_clks, xcsi2rxss->clks);
1089 clk_bulk_put(num_clks, xcsi2rxss->clks);
1094 static const struct of_device_id xcsi2rxss_of_id_table[] = {
1095 { .compatible = "xlnx,mipi-csi2-rx-subsystem-5.0", },
1098 MODULE_DEVICE_TABLE(of, xcsi2rxss_of_id_table);
1100 static struct platform_driver xcsi2rxss_driver = {
1102 .name = "xilinx-csi2rxss",
1103 .of_match_table = xcsi2rxss_of_id_table,
1105 .probe = xcsi2rxss_probe,
1106 .remove = xcsi2rxss_remove,
1109 module_platform_driver(xcsi2rxss_driver);
1111 MODULE_AUTHOR("Vishal Sagar <vsagar@xilinx.com>");
1112 MODULE_DESCRIPTION("Xilinx MIPI CSI-2 Rx Subsystem Driver");
1113 MODULE_LICENSE("GPL v2");