2 * vsp1_drm.c -- R-Car VSP1 DRM API
4 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/slab.h>
18 #include <media/media-entity.h>
19 #include <media/v4l2-subdev.h>
20 #include <media/vsp1.h>
27 #include "vsp1_pipe.h"
28 #include "vsp1_rwpf.h"
30 #define BRX_NAME(e) (e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"
32 /* -----------------------------------------------------------------------------
36 static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
37 unsigned int completion)
39 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
40 bool complete = completion == VSP1_DL_FRAME_END_COMPLETED;
42 if (drm_pipe->du_complete)
43 drm_pipe->du_complete(drm_pipe->du_private, complete);
45 if (completion & VSP1_DL_FRAME_END_INTERNAL) {
46 drm_pipe->force_brx_release = false;
47 wake_up(&drm_pipe->wait_queue);
51 /* -----------------------------------------------------------------------------
52 * Pipeline Configuration
55 /* Setup one RPF and the connected BRx sink pad. */
56 static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
57 struct vsp1_pipeline *pipe,
58 struct vsp1_rwpf *rpf,
59 unsigned int brx_input)
61 struct v4l2_subdev_selection sel;
62 struct v4l2_subdev_format format;
63 const struct v4l2_rect *crop;
67 * Configure the format on the RPF sink pad and propagate it up to the
70 crop = &vsp1->drm->inputs[rpf->entity.index].crop;
72 memset(&format, 0, sizeof(format));
73 format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
74 format.pad = RWPF_PAD_SINK;
75 format.format.width = crop->width + crop->left;
76 format.format.height = crop->height + crop->top;
77 format.format.code = rpf->fmtinfo->mbus;
78 format.format.field = V4L2_FIELD_NONE;
80 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
86 "%s: set format %ux%u (%x) on RPF%u sink\n",
87 __func__, format.format.width, format.format.height,
88 format.format.code, rpf->entity.index);
90 memset(&sel, 0, sizeof(sel));
91 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
92 sel.pad = RWPF_PAD_SINK;
93 sel.target = V4L2_SEL_TGT_CROP;
96 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL,
102 "%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
103 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
107 * RPF source, hardcode the format to ARGB8888 to turn on format
108 * conversion if needed.
110 format.pad = RWPF_PAD_SOURCE;
112 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL,
118 "%s: got format %ux%u (%x) on RPF%u source\n",
119 __func__, format.format.width, format.format.height,
120 format.format.code, rpf->entity.index);
122 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
124 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
129 /* BRx sink, propagate the format from the RPF source. */
130 format.pad = brx_input;
132 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,
137 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
138 __func__, format.format.width, format.format.height,
139 format.format.code, BRX_NAME(pipe->brx), format.pad);
142 sel.target = V4L2_SEL_TGT_COMPOSE;
143 sel.r = vsp1->drm->inputs[rpf->entity.index].compose;
145 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_selection, NULL,
150 dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",
151 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
152 BRX_NAME(pipe->brx), sel.pad);
157 /* Setup the BRx source pad. */
158 static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
159 struct vsp1_pipeline *pipe);
160 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe);
162 static int vsp1_du_pipeline_setup_brx(struct vsp1_device *vsp1,
163 struct vsp1_pipeline *pipe)
165 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
166 struct v4l2_subdev_format format = {
167 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
169 struct vsp1_entity *brx;
174 * - If we need more than two inputs, use the BRU.
175 * - Otherwise, if we are not forced to release our BRx, keep it.
176 * - Else, use any free BRx (randomly starting with the BRU).
178 if (pipe->num_inputs > 2)
179 brx = &vsp1->bru->entity;
180 else if (pipe->brx && !drm_pipe->force_brx_release)
182 else if (!vsp1->bru->entity.pipe)
183 brx = &vsp1->bru->entity;
185 brx = &vsp1->brs->entity;
187 /* Switch BRx if needed. */
188 if (brx != pipe->brx) {
189 struct vsp1_entity *released_brx = NULL;
191 /* Release our BRx if we have one. */
193 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
194 __func__, pipe->lif->index,
195 BRX_NAME(pipe->brx));
198 * The BRx might be acquired by the other pipeline in
199 * the next step. We must thus remove it from the list
200 * of entities for this pipeline. The other pipeline's
201 * hardware configuration will reconfigure the BRx
204 * However, if the other pipeline doesn't acquire our
205 * BRx, we need to keep it in the list, otherwise the
206 * hardware configuration step won't disconnect it from
207 * the pipeline. To solve this, store the released BRx
208 * pointer to add it back to the list of entities later
209 * if it isn't acquired by the other pipeline.
211 released_brx = pipe->brx;
213 list_del(&pipe->brx->list_pipe);
214 pipe->brx->sink = NULL;
215 pipe->brx->pipe = NULL;
220 * If the BRx we need is in use, force the owner pipeline to
221 * switch to the other BRx and wait until the switch completes.
224 struct vsp1_drm_pipeline *owner_pipe;
226 dev_dbg(vsp1->dev, "%s: pipe %u: waiting for %s\n",
227 __func__, pipe->lif->index, BRX_NAME(brx));
229 owner_pipe = to_vsp1_drm_pipeline(brx->pipe);
230 owner_pipe->force_brx_release = true;
232 vsp1_du_pipeline_setup_inputs(vsp1, &owner_pipe->pipe);
233 vsp1_du_pipeline_configure(&owner_pipe->pipe);
235 ret = wait_event_timeout(owner_pipe->wait_queue,
236 !owner_pipe->force_brx_release,
237 msecs_to_jiffies(500));
240 "DRM pipeline %u reconfiguration timeout\n",
241 owner_pipe->pipe.lif->index);
245 * If the BRx we have released previously hasn't been acquired
246 * by the other pipeline, add it back to the entities list (with
247 * the pipe pointer NULL) to let vsp1_du_pipeline_configure()
248 * disconnect it from the hardware pipeline.
250 if (released_brx && !released_brx->pipe)
251 list_add_tail(&released_brx->list_pipe,
254 /* Add the BRx to the pipeline. */
255 dev_dbg(vsp1->dev, "%s: pipe %u: acquired %s\n",
256 __func__, pipe->lif->index, BRX_NAME(brx));
259 pipe->brx->pipe = pipe;
260 pipe->brx->sink = &pipe->output->entity;
261 pipe->brx->sink_pad = 0;
263 list_add_tail(&pipe->brx->list_pipe, &pipe->entities);
267 * Configure the format on the BRx source and verify that it matches the
268 * requested format. We don't set the media bus code as it is configured
269 * on the BRx sink pad 0 and propagated inside the entity, not on the
272 format.pad = pipe->brx->source_pad;
273 format.format.width = drm_pipe->width;
274 format.format.height = drm_pipe->height;
275 format.format.field = V4L2_FIELD_NONE;
277 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,
282 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
283 __func__, format.format.width, format.format.height,
284 format.format.code, BRX_NAME(pipe->brx), pipe->brx->source_pad);
286 if (format.format.width != drm_pipe->width ||
287 format.format.height != drm_pipe->height) {
288 dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__);
295 static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
297 return vsp1->drm->inputs[rpf->entity.index].zpos;
300 /* Setup the input side of the pipeline (RPFs and BRx). */
301 static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
302 struct vsp1_pipeline *pipe)
304 struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
305 struct vsp1_brx *brx;
309 /* Count the number of enabled inputs and sort them by Z-order. */
310 pipe->num_inputs = 0;
312 for (i = 0; i < vsp1->info->rpf_count; ++i) {
313 struct vsp1_rwpf *rpf = vsp1->rpf[i];
316 if (!pipe->inputs[i])
319 /* Insert the RPF in the sorted RPFs array. */
320 for (j = pipe->num_inputs++; j > 0; --j) {
321 if (rpf_zpos(vsp1, inputs[j-1]) <= rpf_zpos(vsp1, rpf))
323 inputs[j] = inputs[j-1];
330 * Setup the BRx. This must be done before setting up the RPF input
331 * pipelines as the BRx sink compose rectangles depend on the BRx source
334 ret = vsp1_du_pipeline_setup_brx(vsp1, pipe);
336 dev_err(vsp1->dev, "%s: failed to setup %s source\n", __func__,
337 BRX_NAME(pipe->brx));
341 brx = to_brx(&pipe->brx->subdev);
343 /* Setup the RPF input pipeline for every enabled input. */
344 for (i = 0; i < pipe->brx->source_pad; ++i) {
345 struct vsp1_rwpf *rpf = inputs[i];
348 brx->inputs[i].rpf = NULL;
352 if (!rpf->entity.pipe) {
353 rpf->entity.pipe = pipe;
354 list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
357 brx->inputs[i].rpf = rpf;
359 rpf->entity.sink = pipe->brx;
360 rpf->entity.sink_pad = i;
362 dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
363 __func__, rpf->entity.index, BRX_NAME(pipe->brx), i);
365 ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, i);
368 "%s: failed to setup RPF.%u\n",
369 __func__, rpf->entity.index);
377 /* Setup the output side of the pipeline (WPF and LIF). */
378 static int vsp1_du_pipeline_setup_output(struct vsp1_device *vsp1,
379 struct vsp1_pipeline *pipe)
381 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
382 struct v4l2_subdev_format format = { 0, };
385 format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
386 format.pad = RWPF_PAD_SINK;
387 format.format.width = drm_pipe->width;
388 format.format.height = drm_pipe->height;
389 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
390 format.format.field = V4L2_FIELD_NONE;
392 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
397 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",
398 __func__, format.format.width, format.format.height,
399 format.format.code, pipe->output->entity.index);
401 format.pad = RWPF_PAD_SOURCE;
402 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,
407 dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n",
408 __func__, format.format.width, format.format.height,
409 format.format.code, pipe->output->entity.index);
411 format.pad = LIF_PAD_SINK;
412 ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,
417 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n",
418 __func__, format.format.width, format.format.height,
419 format.format.code, pipe->lif->index);
422 * Verify that the format at the output of the pipeline matches the
423 * requested frame size and media bus code.
425 if (format.format.width != drm_pipe->width ||
426 format.format.height != drm_pipe->height ||
427 format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) {
428 dev_dbg(vsp1->dev, "%s: format mismatch on LIF%u\n", __func__,
436 /* Configure all entities in the pipeline. */
437 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
439 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
440 struct vsp1_entity *entity;
441 struct vsp1_entity *next;
442 struct vsp1_dl_list *dl;
444 dl = vsp1_dl_list_get(pipe->output->dlm);
446 list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
447 /* Disconnect unused entities from the pipeline. */
449 vsp1_dl_list_write(dl, entity->route->reg,
450 VI6_DPR_NODE_UNUSED);
453 list_del(&entity->list_pipe);
458 vsp1_entity_route_setup(entity, pipe, dl);
460 if (entity->ops->configure) {
461 entity->ops->configure(entity, pipe, dl,
462 VSP1_ENTITY_PARAMS_INIT);
463 entity->ops->configure(entity, pipe, dl,
464 VSP1_ENTITY_PARAMS_RUNTIME);
465 entity->ops->configure(entity, pipe, dl,
466 VSP1_ENTITY_PARAMS_PARTITION);
470 vsp1_dl_list_commit(dl, drm_pipe->force_brx_release);
473 /* -----------------------------------------------------------------------------
477 int vsp1_du_init(struct device *dev)
479 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
482 return -EPROBE_DEFER;
486 EXPORT_SYMBOL_GPL(vsp1_du_init);
489 * vsp1_du_setup_lif - Setup the output part of the VSP pipeline
490 * @dev: the VSP device
491 * @pipe_index: the DRM pipeline index
492 * @cfg: the LIF configuration
494 * Configure the output part of VSP DRM pipeline for the given frame @cfg.width
495 * and @cfg.height. This sets up formats on the BRx source pad, the WPF sink and
496 * source pads, and the LIF sink pad.
498 * The @pipe_index argument selects which DRM pipeline to setup. The number of
499 * available pipelines depend on the VSP instance.
501 * As the media bus code on the blend unit source pad is conditioned by the
502 * configuration of its sink 0 pad, we also set up the formats on all blend unit
503 * sinks, even if the configuration will be overwritten later by
504 * vsp1_du_setup_rpf(). This ensures that the blend unit configuration is set to
505 * a well defined state.
507 * Return 0 on success or a negative error code on failure.
509 int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
510 const struct vsp1_du_lif_config *cfg)
512 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
513 struct vsp1_drm_pipeline *drm_pipe;
514 struct vsp1_pipeline *pipe;
519 if (pipe_index >= vsp1->info->lif_count)
522 drm_pipe = &vsp1->drm->pipe[pipe_index];
523 pipe = &drm_pipe->pipe;
526 struct vsp1_brx *brx;
528 mutex_lock(&vsp1->drm->lock);
530 brx = to_brx(&pipe->brx->subdev);
533 * NULL configuration means the CRTC is being disabled, stop
534 * the pipeline and turn the light off.
536 ret = vsp1_pipeline_stop(pipe);
537 if (ret == -ETIMEDOUT)
538 dev_err(vsp1->dev, "DRM pipeline stop timeout\n");
540 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
541 struct vsp1_rwpf *rpf = pipe->inputs[i];
547 * Remove the RPF from the pipe and the list of BRx
550 WARN_ON(!rpf->entity.pipe);
551 rpf->entity.pipe = NULL;
552 list_del(&rpf->entity.list_pipe);
553 pipe->inputs[i] = NULL;
555 brx->inputs[rpf->brx_input].rpf = NULL;
558 drm_pipe->du_complete = NULL;
559 pipe->num_inputs = 0;
561 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
562 __func__, pipe->lif->index,
563 BRX_NAME(pipe->brx));
565 list_del(&pipe->brx->list_pipe);
566 pipe->brx->pipe = NULL;
569 mutex_unlock(&vsp1->drm->lock);
571 vsp1_dlm_reset(pipe->output->dlm);
572 vsp1_device_put(vsp1);
574 dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__);
579 drm_pipe->width = cfg->width;
580 drm_pipe->height = cfg->height;
582 dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u\n",
583 __func__, pipe_index, cfg->width, cfg->height);
585 mutex_lock(&vsp1->drm->lock);
587 /* Setup formats through the pipeline. */
588 ret = vsp1_du_pipeline_setup_inputs(vsp1, pipe);
592 ret = vsp1_du_pipeline_setup_output(vsp1, pipe);
596 /* Enable the VSP1. */
597 ret = vsp1_device_get(vsp1);
602 * Register a callback to allow us to notify the DRM driver of frame
605 drm_pipe->du_complete = cfg->callback;
606 drm_pipe->du_private = cfg->callback_data;
608 /* Disable the display interrupts. */
609 vsp1_write(vsp1, VI6_DISP_IRQ_STA, 0);
610 vsp1_write(vsp1, VI6_DISP_IRQ_ENB, 0);
612 /* Configure all entities in the pipeline. */
613 vsp1_du_pipeline_configure(pipe);
616 mutex_unlock(&vsp1->drm->lock);
621 /* Start the pipeline. */
622 spin_lock_irqsave(&pipe->irqlock, flags);
623 vsp1_pipeline_run(pipe);
624 spin_unlock_irqrestore(&pipe->irqlock, flags);
626 dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__);
630 EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);
633 * vsp1_du_atomic_begin - Prepare for an atomic update
634 * @dev: the VSP device
635 * @pipe_index: the DRM pipeline index
637 void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)
639 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
641 mutex_lock(&vsp1->drm->lock);
643 EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
646 * vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline
647 * @dev: the VSP device
648 * @pipe_index: the DRM pipeline index
649 * @rpf_index: index of the RPF to setup (0-based)
650 * @cfg: the RPF configuration
652 * Configure the VSP to perform image composition through RPF @rpf_index as
653 * described by the @cfg configuration. The image to compose is referenced by
654 * @cfg.mem and composed using the @cfg.src crop rectangle and the @cfg.dst
655 * composition rectangle. The Z-order is configurable with higher @zpos values
658 * If the @cfg configuration is NULL, the RPF will be disabled. Calling the
659 * function on a disabled RPF is allowed.
661 * Image format as stored in memory is expressed as a V4L2 @cfg.pixelformat
662 * value. The memory pitch is configurable to allow for padding at end of lines,
663 * or simply for images that extend beyond the crop rectangle boundaries. The
664 * @cfg.pitch value is expressed in bytes and applies to all planes for
665 * multiplanar formats.
667 * The source memory buffer is referenced by the DMA address of its planes in
668 * the @cfg.mem array. Up to two planes are supported. The second plane DMA
669 * address is ignored for formats using a single plane.
671 * This function isn't reentrant, the caller needs to serialize calls.
673 * Return 0 on success or a negative error code on failure.
675 int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
676 unsigned int rpf_index,
677 const struct vsp1_du_atomic_config *cfg)
679 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
680 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
681 const struct vsp1_format_info *fmtinfo;
682 struct vsp1_rwpf *rpf;
684 if (rpf_index >= vsp1->info->rpf_count)
687 rpf = vsp1->rpf[rpf_index];
690 dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__,
694 * Remove the RPF from the pipeline's inputs. Keep it in the
695 * pipeline's entity list to let vsp1_du_pipeline_configure()
696 * remove it from the hardware pipeline.
698 rpf->entity.pipe = NULL;
699 drm_pipe->pipe.inputs[rpf_index] = NULL;
704 "%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%08x), pitch %u dma { %pad, %pad, %pad } zpos %u\n",
706 cfg->src.left, cfg->src.top, cfg->src.width, cfg->src.height,
707 cfg->dst.left, cfg->dst.top, cfg->dst.width, cfg->dst.height,
708 cfg->pixelformat, cfg->pitch, &cfg->mem[0], &cfg->mem[1],
709 &cfg->mem[2], cfg->zpos);
712 * Store the format, stride, memory buffer address, crop and compose
713 * rectangles and Z-order position and for the input.
715 fmtinfo = vsp1_get_format_info(vsp1, cfg->pixelformat);
717 dev_dbg(vsp1->dev, "Unsupport pixel format %08x for RPF\n",
722 rpf->fmtinfo = fmtinfo;
723 rpf->format.num_planes = fmtinfo->planes;
724 rpf->format.plane_fmt[0].bytesperline = cfg->pitch;
725 rpf->format.plane_fmt[1].bytesperline = cfg->pitch;
726 rpf->alpha = cfg->alpha;
728 rpf->mem.addr[0] = cfg->mem[0];
729 rpf->mem.addr[1] = cfg->mem[1];
730 rpf->mem.addr[2] = cfg->mem[2];
732 vsp1->drm->inputs[rpf_index].crop = cfg->src;
733 vsp1->drm->inputs[rpf_index].compose = cfg->dst;
734 vsp1->drm->inputs[rpf_index].zpos = cfg->zpos;
736 drm_pipe->pipe.inputs[rpf_index] = rpf;
740 EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);
743 * vsp1_du_atomic_flush - Commit an atomic update
744 * @dev: the VSP device
745 * @pipe_index: the DRM pipeline index
747 void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
749 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
750 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
751 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
753 vsp1_du_pipeline_setup_inputs(vsp1, pipe);
754 vsp1_du_pipeline_configure(pipe);
755 mutex_unlock(&vsp1->drm->lock);
757 EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);
759 int vsp1_du_map_sg(struct device *dev, struct sg_table *sgt)
761 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
764 * As all the buffers allocated by the DU driver are coherent, we can
765 * skip cache sync. This will need to be revisited when support for
766 * non-coherent buffers will be added to the DU driver.
768 return dma_map_sg_attrs(vsp1->bus_master, sgt->sgl, sgt->nents,
769 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
771 EXPORT_SYMBOL_GPL(vsp1_du_map_sg);
773 void vsp1_du_unmap_sg(struct device *dev, struct sg_table *sgt)
775 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
777 dma_unmap_sg_attrs(vsp1->bus_master, sgt->sgl, sgt->nents,
778 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
780 EXPORT_SYMBOL_GPL(vsp1_du_unmap_sg);
782 /* -----------------------------------------------------------------------------
786 int vsp1_drm_init(struct vsp1_device *vsp1)
790 vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL);
794 mutex_init(&vsp1->drm->lock);
796 /* Create one DRM pipeline per LIF. */
797 for (i = 0; i < vsp1->info->lif_count; ++i) {
798 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i];
799 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
801 init_waitqueue_head(&drm_pipe->wait_queue);
803 vsp1_pipeline_init(pipe);
805 pipe->frame_end = vsp1_du_pipeline_frame_end;
808 * The output side of the DRM pipeline is static, add the
809 * corresponding entities manually.
811 pipe->output = vsp1->wpf[i];
812 pipe->lif = &vsp1->lif[i]->entity;
814 pipe->output->entity.pipe = pipe;
815 pipe->output->entity.sink = pipe->lif;
816 pipe->output->entity.sink_pad = 0;
817 list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);
819 pipe->lif->pipe = pipe;
820 list_add_tail(&pipe->lif->list_pipe, &pipe->entities);
823 /* Disable all RPFs initially. */
824 for (i = 0; i < vsp1->info->rpf_count; ++i) {
825 struct vsp1_rwpf *input = vsp1->rpf[i];
827 INIT_LIST_HEAD(&input->entity.list_pipe);
833 void vsp1_drm_cleanup(struct vsp1_device *vsp1)
835 mutex_destroy(&vsp1->drm->lock);