1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STM32 Digital Camera Memory Interface
5 * Copyright (C) STMicroelectronics SA 2017
6 * Authors: Yannick Fertre <yannick.fertre@st.com>
7 * Hugues Fruchet <hugues.fruchet@st.com>
8 * for STMicroelectronics.
10 * This driver is based on atmel_isi.c
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/delay.h>
17 #include <linux/dmaengine.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
23 #include <linux/of_device.h>
24 #include <linux/of_graph.h>
25 #include <linux/platform_device.h>
26 #include <linux/reset.h>
27 #include <linux/videodev2.h>
29 #include <media/v4l2-ctrls.h>
30 #include <media/v4l2-dev.h>
31 #include <media/v4l2-device.h>
32 #include <media/v4l2-event.h>
33 #include <media/v4l2-fwnode.h>
34 #include <media/v4l2-image-sizes.h>
35 #include <media/v4l2-ioctl.h>
36 #include <media/v4l2-rect.h>
37 #include <media/videobuf2-dma-contig.h>
39 #define DRV_NAME "stm32-dcmi"
41 /* Registers offset for DCMI */
42 #define DCMI_CR 0x00 /* Control Register */
43 #define DCMI_SR 0x04 /* Status Register */
44 #define DCMI_RIS 0x08 /* Raw Interrupt Status register */
45 #define DCMI_IER 0x0C /* Interrupt Enable Register */
46 #define DCMI_MIS 0x10 /* Masked Interrupt Status register */
47 #define DCMI_ICR 0x14 /* Interrupt Clear Register */
48 #define DCMI_ESCR 0x18 /* Embedded Synchronization Code Register */
49 #define DCMI_ESUR 0x1C /* Embedded Synchronization Unmask Register */
50 #define DCMI_CWSTRT 0x20 /* Crop Window STaRT */
51 #define DCMI_CWSIZE 0x24 /* Crop Window SIZE */
52 #define DCMI_DR 0x28 /* Data Register */
53 #define DCMI_IDR 0x2C /* IDentifier Register */
55 /* Bits definition for control register (DCMI_CR) */
56 #define CR_CAPTURE BIT(0)
58 #define CR_CROP BIT(2)
59 #define CR_JPEG BIT(3)
61 #define CR_PCKPOL BIT(5)
62 #define CR_HSPOL BIT(6)
63 #define CR_VSPOL BIT(7)
64 #define CR_FCRC_0 BIT(8)
65 #define CR_FCRC_1 BIT(9)
66 #define CR_EDM_0 BIT(10)
67 #define CR_EDM_1 BIT(11)
68 #define CR_ENABLE BIT(14)
70 /* Bits definition for status register (DCMI_SR) */
71 #define SR_HSYNC BIT(0)
72 #define SR_VSYNC BIT(1)
76 * Bits definition for interrupt registers
77 * (DCMI_RIS, DCMI_IER, DCMI_MIS, DCMI_ICR)
79 #define IT_FRAME BIT(0)
82 #define IT_VSYNC BIT(3)
83 #define IT_LINE BIT(4)
92 #define MAX_WIDTH 2592U
93 #define MIN_HEIGHT 16U
94 #define MAX_HEIGHT 2592U
96 #define TIMEOUT_MS 1000
98 struct dcmi_graph_entity {
99 struct device_node *node;
101 struct v4l2_async_subdev asd;
102 struct v4l2_subdev *subdev;
111 struct dcmi_framesize {
117 struct vb2_v4l2_buffer vb;
121 struct list_head list;
125 /* Protects the access of variables shared within the interrupt */
129 struct resource *res;
130 struct reset_control *rstc;
132 struct list_head buffers;
133 struct dcmi_buf *active;
135 struct v4l2_device v4l2_dev;
136 struct video_device *vdev;
137 struct v4l2_async_notifier notifier;
138 struct dcmi_graph_entity entity;
139 struct v4l2_format fmt;
140 struct v4l2_rect crop;
143 const struct dcmi_format **sd_formats;
144 unsigned int num_of_sd_formats;
145 const struct dcmi_format *sd_format;
146 struct dcmi_framesize *sd_framesizes;
147 unsigned int num_of_sd_framesizes;
148 struct dcmi_framesize sd_framesize;
149 struct v4l2_rect sd_bounds;
151 /* Protect this data structure */
153 struct vb2_queue queue;
155 struct v4l2_fwnode_bus_parallel bus;
156 struct completion complete;
159 struct dma_chan *dma_chan;
160 dma_cookie_t dma_cookie;
167 static inline struct stm32_dcmi *notifier_to_dcmi(struct v4l2_async_notifier *n)
169 return container_of(n, struct stm32_dcmi, notifier);
172 static inline u32 reg_read(void __iomem *base, u32 reg)
174 return readl_relaxed(base + reg);
177 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
179 writel_relaxed(val, base + reg);
182 static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
184 reg_write(base, reg, reg_read(base, reg) | mask);
187 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
189 reg_write(base, reg, reg_read(base, reg) & ~mask);
192 static int dcmi_start_capture(struct stm32_dcmi *dcmi, struct dcmi_buf *buf);
194 static void dcmi_buffer_done(struct stm32_dcmi *dcmi,
195 struct dcmi_buf *buf,
199 struct vb2_v4l2_buffer *vbuf;
204 list_del_init(&buf->list);
208 vbuf->sequence = dcmi->sequence++;
209 vbuf->field = V4L2_FIELD_NONE;
210 vbuf->vb2_buf.timestamp = ktime_get_ns();
211 vb2_set_plane_payload(&vbuf->vb2_buf, 0, bytesused);
212 vb2_buffer_done(&vbuf->vb2_buf,
213 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
214 dev_dbg(dcmi->dev, "buffer[%d] done seq=%d, bytesused=%zu\n",
215 vbuf->vb2_buf.index, vbuf->sequence, bytesused);
217 dcmi->buffers_count++;
221 static int dcmi_restart_capture(struct stm32_dcmi *dcmi)
223 struct dcmi_buf *buf;
225 spin_lock_irq(&dcmi->irqlock);
227 if (dcmi->state != RUNNING) {
228 spin_unlock_irq(&dcmi->irqlock);
232 /* Restart a new DMA transfer with next buffer */
233 if (list_empty(&dcmi->buffers)) {
234 dev_dbg(dcmi->dev, "Capture restart is deferred to next buffer queueing\n");
235 dcmi->state = WAIT_FOR_BUFFER;
236 spin_unlock_irq(&dcmi->irqlock);
239 buf = list_entry(dcmi->buffers.next, struct dcmi_buf, list);
242 spin_unlock_irq(&dcmi->irqlock);
244 return dcmi_start_capture(dcmi, buf);
247 static void dcmi_dma_callback(void *param)
249 struct stm32_dcmi *dcmi = (struct stm32_dcmi *)param;
250 struct dma_tx_state state;
251 enum dma_status status;
252 struct dcmi_buf *buf = dcmi->active;
254 spin_lock_irq(&dcmi->irqlock);
256 /* Check DMA status */
257 status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state);
260 case DMA_IN_PROGRESS:
261 dev_dbg(dcmi->dev, "%s: Received DMA_IN_PROGRESS\n", __func__);
264 dev_err(dcmi->dev, "%s: Received DMA_PAUSED\n", __func__);
267 dev_err(dcmi->dev, "%s: Received DMA_ERROR\n", __func__);
269 /* Return buffer to V4L2 in error state */
270 dcmi_buffer_done(dcmi, buf, 0, -EIO);
273 dev_dbg(dcmi->dev, "%s: Received DMA_COMPLETE\n", __func__);
275 /* Return buffer to V4L2 */
276 dcmi_buffer_done(dcmi, buf, buf->size, 0);
278 spin_unlock_irq(&dcmi->irqlock);
280 /* Restart capture */
281 if (dcmi_restart_capture(dcmi))
282 dev_err(dcmi->dev, "%s: Cannot restart capture on DMA complete\n",
286 dev_err(dcmi->dev, "%s: Received unknown status\n", __func__);
290 spin_unlock_irq(&dcmi->irqlock);
293 static int dcmi_start_dma(struct stm32_dcmi *dcmi,
294 struct dcmi_buf *buf)
296 struct dma_async_tx_descriptor *desc = NULL;
297 struct dma_slave_config config;
300 memset(&config, 0, sizeof(config));
302 config.src_addr = (dma_addr_t)dcmi->res->start + DCMI_DR;
303 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
304 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
305 config.dst_maxburst = 4;
307 /* Configure DMA channel */
308 ret = dmaengine_slave_config(dcmi->dma_chan, &config);
310 dev_err(dcmi->dev, "%s: DMA channel config failed (%d)\n",
315 /* Prepare a DMA transaction */
316 desc = dmaengine_prep_slave_single(dcmi->dma_chan, buf->paddr,
321 dev_err(dcmi->dev, "%s: DMA dmaengine_prep_slave_single failed for buffer phy=%pad size=%zu\n",
322 __func__, &buf->paddr, buf->size);
326 /* Set completion callback routine for notification */
327 desc->callback = dcmi_dma_callback;
328 desc->callback_param = dcmi;
330 /* Push current DMA transaction in the pending queue */
331 dcmi->dma_cookie = dmaengine_submit(desc);
332 if (dma_submit_error(dcmi->dma_cookie)) {
333 dev_err(dcmi->dev, "%s: DMA submission failed\n", __func__);
337 dma_async_issue_pending(dcmi->dma_chan);
342 static int dcmi_start_capture(struct stm32_dcmi *dcmi, struct dcmi_buf *buf)
349 ret = dcmi_start_dma(dcmi, buf);
351 dcmi->errors_count++;
356 reg_set(dcmi->regs, DCMI_CR, CR_CAPTURE);
361 static void dcmi_set_crop(struct stm32_dcmi *dcmi)
365 /* Crop resolution */
366 size = ((dcmi->crop.height - 1) << 16) |
367 ((dcmi->crop.width << 1) - 1);
368 reg_write(dcmi->regs, DCMI_CWSIZE, size);
370 /* Crop start point */
371 start = ((dcmi->crop.top) << 16) |
372 ((dcmi->crop.left << 1));
373 reg_write(dcmi->regs, DCMI_CWSTRT, start);
375 dev_dbg(dcmi->dev, "Cropping to %ux%u@%u:%u\n",
376 dcmi->crop.width, dcmi->crop.height,
377 dcmi->crop.left, dcmi->crop.top);
380 reg_set(dcmi->regs, DCMI_CR, CR_CROP);
383 static void dcmi_process_jpeg(struct stm32_dcmi *dcmi)
385 struct dma_tx_state state;
386 enum dma_status status;
387 struct dcmi_buf *buf = dcmi->active;
393 * Because of variable JPEG buffer size sent by sensor,
394 * DMA transfer never completes due to transfer size never reached.
395 * In order to ensure that all the JPEG data are transferred
396 * in active buffer memory, DMA is drained.
397 * Then DMA tx status gives the amount of data transferred
398 * to memory, which is then returned to V4L2 through the active
403 dmaengine_synchronize(dcmi->dma_chan);
405 /* Get DMA residue to get JPEG size */
406 status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state);
407 if (status != DMA_ERROR && state.residue < buf->size) {
408 /* Return JPEG buffer to V4L2 with received JPEG buffer size */
409 dcmi_buffer_done(dcmi, buf, buf->size - state.residue, 0);
411 dcmi->errors_count++;
412 dev_err(dcmi->dev, "%s: Cannot get JPEG size from DMA\n",
414 /* Return JPEG buffer to V4L2 in ERROR state */
415 dcmi_buffer_done(dcmi, buf, 0, -EIO);
418 /* Abort DMA operation */
419 dmaengine_terminate_all(dcmi->dma_chan);
421 /* Restart capture */
422 if (dcmi_restart_capture(dcmi))
423 dev_err(dcmi->dev, "%s: Cannot restart capture on JPEG received\n",
427 static irqreturn_t dcmi_irq_thread(int irq, void *arg)
429 struct stm32_dcmi *dcmi = arg;
431 spin_lock_irq(&dcmi->irqlock);
433 if ((dcmi->misr & IT_OVR) || (dcmi->misr & IT_ERR)) {
434 dcmi->errors_count++;
435 if (dcmi->misr & IT_OVR)
436 dcmi->overrun_count++;
439 if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG &&
440 dcmi->misr & IT_FRAME) {
442 spin_unlock_irq(&dcmi->irqlock);
443 dcmi_process_jpeg(dcmi);
447 spin_unlock_irq(&dcmi->irqlock);
451 static irqreturn_t dcmi_irq_callback(int irq, void *arg)
453 struct stm32_dcmi *dcmi = arg;
456 spin_lock_irqsave(&dcmi->irqlock, flags);
458 dcmi->misr = reg_read(dcmi->regs, DCMI_MIS);
460 /* Clear interrupt */
461 reg_set(dcmi->regs, DCMI_ICR, IT_FRAME | IT_OVR | IT_ERR);
463 spin_unlock_irqrestore(&dcmi->irqlock, flags);
465 return IRQ_WAKE_THREAD;
468 static int dcmi_queue_setup(struct vb2_queue *vq,
469 unsigned int *nbuffers,
470 unsigned int *nplanes,
471 unsigned int sizes[],
472 struct device *alloc_devs[])
474 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);
477 size = dcmi->fmt.fmt.pix.sizeimage;
479 /* Make sure the image size is large enough */
481 return sizes[0] < size ? -EINVAL : 0;
486 dev_dbg(dcmi->dev, "Setup queue, count=%d, size=%d\n",
492 static int dcmi_buf_init(struct vb2_buffer *vb)
494 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
495 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb);
497 INIT_LIST_HEAD(&buf->list);
502 static int dcmi_buf_prepare(struct vb2_buffer *vb)
504 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vb->vb2_queue);
505 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
506 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb);
509 size = dcmi->fmt.fmt.pix.sizeimage;
511 if (vb2_plane_size(vb, 0) < size) {
512 dev_err(dcmi->dev, "%s data will not fit into plane (%lu < %lu)\n",
513 __func__, vb2_plane_size(vb, 0), size);
517 vb2_set_plane_payload(vb, 0, size);
519 if (!buf->prepared) {
520 /* Get memory addresses */
522 vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
523 buf->size = vb2_plane_size(&buf->vb.vb2_buf, 0);
524 buf->prepared = true;
526 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, buf->size);
528 dev_dbg(dcmi->dev, "buffer[%d] phy=%pad size=%zu\n",
529 vb->index, &buf->paddr, buf->size);
535 static void dcmi_buf_queue(struct vb2_buffer *vb)
537 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vb->vb2_queue);
538 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
539 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb);
541 spin_lock_irq(&dcmi->irqlock);
543 /* Enqueue to video buffers list */
544 list_add_tail(&buf->list, &dcmi->buffers);
546 if (dcmi->state == WAIT_FOR_BUFFER) {
547 dcmi->state = RUNNING;
550 dev_dbg(dcmi->dev, "Starting capture on buffer[%d] queued\n",
551 buf->vb.vb2_buf.index);
553 spin_unlock_irq(&dcmi->irqlock);
554 if (dcmi_start_capture(dcmi, buf))
555 dev_err(dcmi->dev, "%s: Cannot restart capture on overflow or error\n",
560 spin_unlock_irq(&dcmi->irqlock);
563 static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count)
565 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);
566 struct dcmi_buf *buf, *node;
570 ret = clk_enable(dcmi->mclk);
572 dev_err(dcmi->dev, "%s: Failed to start streaming, cannot enable clock\n",
574 goto err_release_buffers;
577 /* Enable stream on the sub device */
578 ret = v4l2_subdev_call(dcmi->entity.subdev, video, s_stream, 1);
579 if (ret && ret != -ENOIOCTLCMD) {
580 dev_err(dcmi->dev, "%s: Failed to start streaming, subdev streamon error",
582 goto err_disable_clock;
585 spin_lock_irq(&dcmi->irqlock);
588 switch (dcmi->bus.bus_width) {
590 val |= CR_EDM_0 | CR_EDM_1;
599 /* Set bus width to 8 bits by default */
603 /* Set vertical synchronization polarity */
604 if (dcmi->bus.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
607 /* Set horizontal synchronization polarity */
608 if (dcmi->bus.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
611 /* Set pixel clock polarity */
612 if (dcmi->bus.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
615 reg_write(dcmi->regs, DCMI_CR, val);
621 /* Enable jpeg capture */
622 if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG)
623 reg_set(dcmi->regs, DCMI_CR, CR_CM);/* Snapshot mode */
626 reg_set(dcmi->regs, DCMI_CR, CR_ENABLE);
629 dcmi->errors_count = 0;
630 dcmi->overrun_count = 0;
631 dcmi->buffers_count = 0;
634 * Start transfer if at least one buffer has been queued,
635 * otherwise transfer is deferred at buffer queueing
637 if (list_empty(&dcmi->buffers)) {
638 dev_dbg(dcmi->dev, "Start streaming is deferred to next buffer queueing\n");
639 dcmi->state = WAIT_FOR_BUFFER;
640 spin_unlock_irq(&dcmi->irqlock);
644 buf = list_entry(dcmi->buffers.next, struct dcmi_buf, list);
647 dcmi->state = RUNNING;
649 dev_dbg(dcmi->dev, "Start streaming, starting capture\n");
651 spin_unlock_irq(&dcmi->irqlock);
652 ret = dcmi_start_capture(dcmi, buf);
654 dev_err(dcmi->dev, "%s: Start streaming failed, cannot start capture\n",
656 goto err_subdev_streamoff;
659 /* Enable interruptions */
660 reg_set(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR);
664 err_subdev_streamoff:
665 v4l2_subdev_call(dcmi->entity.subdev, video, s_stream, 0);
668 clk_disable(dcmi->mclk);
671 spin_lock_irq(&dcmi->irqlock);
673 * Return all buffers to vb2 in QUEUED state.
674 * This will give ownership back to userspace
676 list_for_each_entry_safe(buf, node, &dcmi->buffers, list) {
677 list_del_init(&buf->list);
678 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
681 spin_unlock_irq(&dcmi->irqlock);
686 static void dcmi_stop_streaming(struct vb2_queue *vq)
688 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);
689 struct dcmi_buf *buf, *node;
692 /* Disable stream on the sub device */
693 ret = v4l2_subdev_call(dcmi->entity.subdev, video, s_stream, 0);
694 if (ret && ret != -ENOIOCTLCMD)
695 dev_err(dcmi->dev, "%s: Failed to stop streaming, subdev streamoff error (%d)\n",
698 spin_lock_irq(&dcmi->irqlock);
700 /* Disable interruptions */
701 reg_clear(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR);
704 reg_clear(dcmi->regs, DCMI_CR, CR_ENABLE);
706 /* Return all queued buffers to vb2 in ERROR state */
707 list_for_each_entry_safe(buf, node, &dcmi->buffers, list) {
708 list_del_init(&buf->list);
709 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
713 dcmi->state = STOPPED;
715 spin_unlock_irq(&dcmi->irqlock);
717 /* Stop all pending DMA operations */
718 dmaengine_terminate_all(dcmi->dma_chan);
720 clk_disable(dcmi->mclk);
722 if (dcmi->errors_count)
723 dev_warn(dcmi->dev, "Some errors found while streaming: errors=%d (overrun=%d), buffers=%d\n",
724 dcmi->errors_count, dcmi->overrun_count,
725 dcmi->buffers_count);
726 dev_dbg(dcmi->dev, "Stop streaming, errors=%d (overrun=%d), buffers=%d\n",
727 dcmi->errors_count, dcmi->overrun_count,
728 dcmi->buffers_count);
731 static const struct vb2_ops dcmi_video_qops = {
732 .queue_setup = dcmi_queue_setup,
733 .buf_init = dcmi_buf_init,
734 .buf_prepare = dcmi_buf_prepare,
735 .buf_queue = dcmi_buf_queue,
736 .start_streaming = dcmi_start_streaming,
737 .stop_streaming = dcmi_stop_streaming,
738 .wait_prepare = vb2_ops_wait_prepare,
739 .wait_finish = vb2_ops_wait_finish,
742 static int dcmi_g_fmt_vid_cap(struct file *file, void *priv,
743 struct v4l2_format *fmt)
745 struct stm32_dcmi *dcmi = video_drvdata(file);
752 static const struct dcmi_format *find_format_by_fourcc(struct stm32_dcmi *dcmi,
755 unsigned int num_formats = dcmi->num_of_sd_formats;
756 const struct dcmi_format *fmt;
759 for (i = 0; i < num_formats; i++) {
760 fmt = dcmi->sd_formats[i];
761 if (fmt->fourcc == fourcc)
768 static void __find_outer_frame_size(struct stm32_dcmi *dcmi,
769 struct v4l2_pix_format *pix,
770 struct dcmi_framesize *framesize)
772 struct dcmi_framesize *match = NULL;
774 unsigned int min_err = UINT_MAX;
776 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) {
777 struct dcmi_framesize *fsize = &dcmi->sd_framesizes[i];
778 int w_err = (fsize->width - pix->width);
779 int h_err = (fsize->height - pix->height);
780 int err = w_err + h_err;
782 if (w_err >= 0 && h_err >= 0 && err < min_err) {
788 match = &dcmi->sd_framesizes[0];
793 static int dcmi_try_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f,
794 const struct dcmi_format **sd_format,
795 struct dcmi_framesize *sd_framesize)
797 const struct dcmi_format *sd_fmt;
798 struct dcmi_framesize sd_fsize;
799 struct v4l2_pix_format *pix = &f->fmt.pix;
800 struct v4l2_subdev_pad_config pad_cfg;
801 struct v4l2_subdev_format format = {
802 .which = V4L2_SUBDEV_FORMAT_TRY,
807 sd_fmt = find_format_by_fourcc(dcmi, pix->pixelformat);
809 sd_fmt = dcmi->sd_formats[dcmi->num_of_sd_formats - 1];
810 pix->pixelformat = sd_fmt->fourcc;
813 /* Limit to hardware capabilities */
814 pix->width = clamp(pix->width, MIN_WIDTH, MAX_WIDTH);
815 pix->height = clamp(pix->height, MIN_HEIGHT, MAX_HEIGHT);
817 /* No crop if JPEG is requested */
818 do_crop = dcmi->do_crop && (pix->pixelformat != V4L2_PIX_FMT_JPEG);
820 if (do_crop && dcmi->num_of_sd_framesizes) {
821 struct dcmi_framesize outer_sd_fsize;
823 * If crop is requested and sensor have discrete frame sizes,
824 * select the frame size that is just larger than request
826 __find_outer_frame_size(dcmi, pix, &outer_sd_fsize);
827 pix->width = outer_sd_fsize.width;
828 pix->height = outer_sd_fsize.height;
831 v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code);
832 ret = v4l2_subdev_call(dcmi->entity.subdev, pad, set_fmt,
837 /* Update pix regarding to what sensor can do */
838 v4l2_fill_pix_format(pix, &format.format);
840 /* Save resolution that sensor can actually do */
841 sd_fsize.width = pix->width;
842 sd_fsize.height = pix->height;
845 struct v4l2_rect c = dcmi->crop;
846 struct v4l2_rect max_rect;
849 * Adjust crop by making the intersection between
850 * format resolution request and crop request
854 max_rect.width = pix->width;
855 max_rect.height = pix->height;
856 v4l2_rect_map_inside(&c, &max_rect);
857 c.top = clamp_t(s32, c.top, 0, pix->height - c.height);
858 c.left = clamp_t(s32, c.left, 0, pix->width - c.width);
861 /* Adjust format resolution request to crop */
862 pix->width = dcmi->crop.width;
863 pix->height = dcmi->crop.height;
866 pix->field = V4L2_FIELD_NONE;
867 pix->bytesperline = pix->width * sd_fmt->bpp;
868 pix->sizeimage = pix->bytesperline * pix->height;
873 *sd_framesize = sd_fsize;
878 static int dcmi_set_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f)
880 struct v4l2_subdev_format format = {
881 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
883 const struct dcmi_format *sd_format;
884 struct dcmi_framesize sd_framesize;
885 struct v4l2_mbus_framefmt *mf = &format.format;
886 struct v4l2_pix_format *pix = &f->fmt.pix;
890 * Try format, fmt.width/height could have been changed
891 * to match sensor capability or crop request
892 * sd_format & sd_framesize will contain what subdev
893 * can do for this request.
895 ret = dcmi_try_fmt(dcmi, f, &sd_format, &sd_framesize);
899 /* Disable crop if JPEG is requested */
900 if (pix->pixelformat == V4L2_PIX_FMT_JPEG)
901 dcmi->do_crop = false;
903 /* pix to mbus format */
904 v4l2_fill_mbus_format(mf, pix,
905 sd_format->mbus_code);
906 mf->width = sd_framesize.width;
907 mf->height = sd_framesize.height;
909 ret = v4l2_subdev_call(dcmi->entity.subdev, pad,
910 set_fmt, NULL, &format);
914 dev_dbg(dcmi->dev, "Sensor format set to 0x%x %ux%u\n",
915 mf->code, mf->width, mf->height);
916 dev_dbg(dcmi->dev, "Buffer format set to %4.4s %ux%u\n",
917 (char *)&pix->pixelformat,
918 pix->width, pix->height);
921 dcmi->sd_format = sd_format;
922 dcmi->sd_framesize = sd_framesize;
927 static int dcmi_s_fmt_vid_cap(struct file *file, void *priv,
928 struct v4l2_format *f)
930 struct stm32_dcmi *dcmi = video_drvdata(file);
932 if (vb2_is_streaming(&dcmi->queue))
935 return dcmi_set_fmt(dcmi, f);
938 static int dcmi_try_fmt_vid_cap(struct file *file, void *priv,
939 struct v4l2_format *f)
941 struct stm32_dcmi *dcmi = video_drvdata(file);
943 return dcmi_try_fmt(dcmi, f, NULL, NULL);
946 static int dcmi_enum_fmt_vid_cap(struct file *file, void *priv,
947 struct v4l2_fmtdesc *f)
949 struct stm32_dcmi *dcmi = video_drvdata(file);
951 if (f->index >= dcmi->num_of_sd_formats)
954 f->pixelformat = dcmi->sd_formats[f->index]->fourcc;
958 static int dcmi_get_sensor_format(struct stm32_dcmi *dcmi,
959 struct v4l2_pix_format *pix)
961 struct v4l2_subdev_format fmt = {
962 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
966 ret = v4l2_subdev_call(dcmi->entity.subdev, pad, get_fmt, NULL, &fmt);
970 v4l2_fill_pix_format(pix, &fmt.format);
975 static int dcmi_set_sensor_format(struct stm32_dcmi *dcmi,
976 struct v4l2_pix_format *pix)
978 const struct dcmi_format *sd_fmt;
979 struct v4l2_subdev_format format = {
980 .which = V4L2_SUBDEV_FORMAT_TRY,
982 struct v4l2_subdev_pad_config pad_cfg;
985 sd_fmt = find_format_by_fourcc(dcmi, pix->pixelformat);
987 sd_fmt = dcmi->sd_formats[dcmi->num_of_sd_formats - 1];
988 pix->pixelformat = sd_fmt->fourcc;
991 v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code);
992 ret = v4l2_subdev_call(dcmi->entity.subdev, pad, set_fmt,
1000 static int dcmi_get_sensor_bounds(struct stm32_dcmi *dcmi,
1001 struct v4l2_rect *r)
1003 struct v4l2_subdev_selection bounds = {
1004 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1005 .target = V4L2_SEL_TGT_CROP_BOUNDS,
1007 unsigned int max_width, max_height, max_pixsize;
1008 struct v4l2_pix_format pix;
1013 * Get sensor bounds first
1015 ret = v4l2_subdev_call(dcmi->entity.subdev, pad, get_selection,
1019 if (ret != -ENOIOCTLCMD)
1023 * If selection is not implemented,
1024 * fallback by enumerating sensor frame sizes
1025 * and take the largest one
1030 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) {
1031 struct dcmi_framesize *fsize = &dcmi->sd_framesizes[i];
1032 unsigned int pixsize = fsize->width * fsize->height;
1034 if (pixsize > max_pixsize) {
1035 max_pixsize = pixsize;
1036 max_width = fsize->width;
1037 max_height = fsize->height;
1040 if (max_pixsize > 0) {
1043 r->width = max_width;
1044 r->height = max_height;
1049 * If frame sizes enumeration is not implemented,
1050 * fallback by getting current sensor frame size
1052 ret = dcmi_get_sensor_format(dcmi, &pix);
1058 r->width = pix.width;
1059 r->height = pix.height;
1064 static int dcmi_g_selection(struct file *file, void *fh,
1065 struct v4l2_selection *s)
1067 struct stm32_dcmi *dcmi = video_drvdata(file);
1069 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1072 switch (s->target) {
1073 case V4L2_SEL_TGT_CROP_DEFAULT:
1074 case V4L2_SEL_TGT_CROP_BOUNDS:
1075 s->r = dcmi->sd_bounds;
1077 case V4L2_SEL_TGT_CROP:
1078 if (dcmi->do_crop) {
1083 s->r.width = dcmi->fmt.fmt.pix.width;
1084 s->r.height = dcmi->fmt.fmt.pix.height;
1094 static int dcmi_s_selection(struct file *file, void *priv,
1095 struct v4l2_selection *s)
1097 struct stm32_dcmi *dcmi = video_drvdata(file);
1098 struct v4l2_rect r = s->r;
1099 struct v4l2_rect max_rect;
1100 struct v4l2_pix_format pix;
1102 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE ||
1103 s->target != V4L2_SEL_TGT_CROP)
1106 /* Reset sensor resolution to max resolution */
1107 pix.pixelformat = dcmi->fmt.fmt.pix.pixelformat;
1108 pix.width = dcmi->sd_bounds.width;
1109 pix.height = dcmi->sd_bounds.height;
1110 dcmi_set_sensor_format(dcmi, &pix);
1113 * Make the intersection between
1119 max_rect.width = pix.width;
1120 max_rect.height = pix.height;
1121 v4l2_rect_map_inside(&r, &max_rect);
1122 r.top = clamp_t(s32, r.top, 0, pix.height - r.height);
1123 r.left = clamp_t(s32, r.left, 0, pix.width - r.width);
1125 if (!(r.top == dcmi->sd_bounds.top &&
1126 r.left == dcmi->sd_bounds.left &&
1127 r.width == dcmi->sd_bounds.width &&
1128 r.height == dcmi->sd_bounds.height)) {
1129 /* Crop if request is different than sensor resolution */
1130 dcmi->do_crop = true;
1132 dev_dbg(dcmi->dev, "s_selection: crop %ux%u@(%u,%u) from %ux%u\n",
1133 r.width, r.height, r.left, r.top,
1134 pix.width, pix.height);
1137 dcmi->do_crop = false;
1138 dev_dbg(dcmi->dev, "s_selection: crop is disabled\n");
1145 static int dcmi_querycap(struct file *file, void *priv,
1146 struct v4l2_capability *cap)
1148 strlcpy(cap->driver, DRV_NAME, sizeof(cap->driver));
1149 strlcpy(cap->card, "STM32 Camera Memory Interface",
1151 strlcpy(cap->bus_info, "platform:dcmi", sizeof(cap->bus_info));
1155 static int dcmi_enum_input(struct file *file, void *priv,
1156 struct v4l2_input *i)
1161 i->type = V4L2_INPUT_TYPE_CAMERA;
1162 strlcpy(i->name, "Camera", sizeof(i->name));
1166 static int dcmi_g_input(struct file *file, void *priv, unsigned int *i)
1172 static int dcmi_s_input(struct file *file, void *priv, unsigned int i)
1179 static int dcmi_enum_framesizes(struct file *file, void *fh,
1180 struct v4l2_frmsizeenum *fsize)
1182 struct stm32_dcmi *dcmi = video_drvdata(file);
1183 const struct dcmi_format *sd_fmt;
1184 struct v4l2_subdev_frame_size_enum fse = {
1185 .index = fsize->index,
1186 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1190 sd_fmt = find_format_by_fourcc(dcmi, fsize->pixel_format);
1194 fse.code = sd_fmt->mbus_code;
1196 ret = v4l2_subdev_call(dcmi->entity.subdev, pad, enum_frame_size,
1201 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1202 fsize->discrete.width = fse.max_width;
1203 fsize->discrete.height = fse.max_height;
1208 static int dcmi_g_parm(struct file *file, void *priv,
1209 struct v4l2_streamparm *p)
1211 struct stm32_dcmi *dcmi = video_drvdata(file);
1213 return v4l2_g_parm_cap(video_devdata(file), dcmi->entity.subdev, p);
1216 static int dcmi_s_parm(struct file *file, void *priv,
1217 struct v4l2_streamparm *p)
1219 struct stm32_dcmi *dcmi = video_drvdata(file);
1221 return v4l2_s_parm_cap(video_devdata(file), dcmi->entity.subdev, p);
1224 static int dcmi_enum_frameintervals(struct file *file, void *fh,
1225 struct v4l2_frmivalenum *fival)
1227 struct stm32_dcmi *dcmi = video_drvdata(file);
1228 const struct dcmi_format *sd_fmt;
1229 struct v4l2_subdev_frame_interval_enum fie = {
1230 .index = fival->index,
1231 .width = fival->width,
1232 .height = fival->height,
1233 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1237 sd_fmt = find_format_by_fourcc(dcmi, fival->pixel_format);
1241 fie.code = sd_fmt->mbus_code;
1243 ret = v4l2_subdev_call(dcmi->entity.subdev, pad,
1244 enum_frame_interval, NULL, &fie);
1248 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1249 fival->discrete = fie.interval;
1254 static const struct of_device_id stm32_dcmi_of_match[] = {
1255 { .compatible = "st,stm32-dcmi"},
1258 MODULE_DEVICE_TABLE(of, stm32_dcmi_of_match);
1260 static int dcmi_open(struct file *file)
1262 struct stm32_dcmi *dcmi = video_drvdata(file);
1263 struct v4l2_subdev *sd = dcmi->entity.subdev;
1266 if (mutex_lock_interruptible(&dcmi->lock))
1267 return -ERESTARTSYS;
1269 ret = v4l2_fh_open(file);
1273 if (!v4l2_fh_is_singular_file(file))
1276 ret = v4l2_subdev_call(sd, core, s_power, 1);
1277 if (ret < 0 && ret != -ENOIOCTLCMD)
1280 ret = dcmi_set_fmt(dcmi, &dcmi->fmt);
1282 v4l2_subdev_call(sd, core, s_power, 0);
1285 v4l2_fh_release(file);
1287 mutex_unlock(&dcmi->lock);
1291 static int dcmi_release(struct file *file)
1293 struct stm32_dcmi *dcmi = video_drvdata(file);
1294 struct v4l2_subdev *sd = dcmi->entity.subdev;
1298 mutex_lock(&dcmi->lock);
1300 fh_singular = v4l2_fh_is_singular_file(file);
1302 ret = _vb2_fop_release(file, NULL);
1305 v4l2_subdev_call(sd, core, s_power, 0);
1307 mutex_unlock(&dcmi->lock);
1312 static const struct v4l2_ioctl_ops dcmi_ioctl_ops = {
1313 .vidioc_querycap = dcmi_querycap,
1315 .vidioc_try_fmt_vid_cap = dcmi_try_fmt_vid_cap,
1316 .vidioc_g_fmt_vid_cap = dcmi_g_fmt_vid_cap,
1317 .vidioc_s_fmt_vid_cap = dcmi_s_fmt_vid_cap,
1318 .vidioc_enum_fmt_vid_cap = dcmi_enum_fmt_vid_cap,
1319 .vidioc_g_selection = dcmi_g_selection,
1320 .vidioc_s_selection = dcmi_s_selection,
1322 .vidioc_enum_input = dcmi_enum_input,
1323 .vidioc_g_input = dcmi_g_input,
1324 .vidioc_s_input = dcmi_s_input,
1326 .vidioc_g_parm = dcmi_g_parm,
1327 .vidioc_s_parm = dcmi_s_parm,
1329 .vidioc_enum_framesizes = dcmi_enum_framesizes,
1330 .vidioc_enum_frameintervals = dcmi_enum_frameintervals,
1332 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1333 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1334 .vidioc_querybuf = vb2_ioctl_querybuf,
1335 .vidioc_qbuf = vb2_ioctl_qbuf,
1336 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1337 .vidioc_expbuf = vb2_ioctl_expbuf,
1338 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1339 .vidioc_streamon = vb2_ioctl_streamon,
1340 .vidioc_streamoff = vb2_ioctl_streamoff,
1342 .vidioc_log_status = v4l2_ctrl_log_status,
1343 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1344 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1347 static const struct v4l2_file_operations dcmi_fops = {
1348 .owner = THIS_MODULE,
1349 .unlocked_ioctl = video_ioctl2,
1351 .release = dcmi_release,
1352 .poll = vb2_fop_poll,
1353 .mmap = vb2_fop_mmap,
1355 .get_unmapped_area = vb2_fop_get_unmapped_area,
1357 .read = vb2_fop_read,
1360 static int dcmi_set_default_fmt(struct stm32_dcmi *dcmi)
1362 struct v4l2_format f = {
1363 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
1366 .height = CIF_HEIGHT,
1367 .field = V4L2_FIELD_NONE,
1368 .pixelformat = dcmi->sd_formats[0]->fourcc,
1373 ret = dcmi_try_fmt(dcmi, &f, NULL, NULL);
1376 dcmi->sd_format = dcmi->sd_formats[0];
1381 static const struct dcmi_format dcmi_formats[] = {
1383 .fourcc = V4L2_PIX_FMT_RGB565,
1384 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
1387 .fourcc = V4L2_PIX_FMT_YUYV,
1388 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
1391 .fourcc = V4L2_PIX_FMT_UYVY,
1392 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
1395 .fourcc = V4L2_PIX_FMT_JPEG,
1396 .mbus_code = MEDIA_BUS_FMT_JPEG_1X8,
1401 static int dcmi_formats_init(struct stm32_dcmi *dcmi)
1403 const struct dcmi_format *sd_fmts[ARRAY_SIZE(dcmi_formats)];
1404 unsigned int num_fmts = 0, i, j;
1405 struct v4l2_subdev *subdev = dcmi->entity.subdev;
1406 struct v4l2_subdev_mbus_code_enum mbus_code = {
1407 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1410 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
1411 NULL, &mbus_code)) {
1412 for (i = 0; i < ARRAY_SIZE(dcmi_formats); i++) {
1413 if (dcmi_formats[i].mbus_code != mbus_code.code)
1416 /* Code supported, have we got this fourcc yet? */
1417 for (j = 0; j < num_fmts; j++)
1418 if (sd_fmts[j]->fourcc ==
1419 dcmi_formats[i].fourcc)
1420 /* Already available */
1424 sd_fmts[num_fmts++] = dcmi_formats + i;
1432 dcmi->num_of_sd_formats = num_fmts;
1433 dcmi->sd_formats = devm_kcalloc(dcmi->dev,
1434 num_fmts, sizeof(struct dcmi_format *),
1436 if (!dcmi->sd_formats) {
1437 dev_err(dcmi->dev, "Could not allocate memory\n");
1441 memcpy(dcmi->sd_formats, sd_fmts,
1442 num_fmts * sizeof(struct dcmi_format *));
1443 dcmi->sd_format = dcmi->sd_formats[0];
1448 static int dcmi_framesizes_init(struct stm32_dcmi *dcmi)
1450 unsigned int num_fsize = 0;
1451 struct v4l2_subdev *subdev = dcmi->entity.subdev;
1452 struct v4l2_subdev_frame_size_enum fse = {
1453 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1454 .code = dcmi->sd_format->mbus_code,
1459 /* Allocate discrete framesizes array */
1460 while (!v4l2_subdev_call(subdev, pad, enum_frame_size,
1464 num_fsize = fse.index;
1468 dcmi->num_of_sd_framesizes = num_fsize;
1469 dcmi->sd_framesizes = devm_kcalloc(dcmi->dev, num_fsize,
1470 sizeof(struct dcmi_framesize),
1472 if (!dcmi->sd_framesizes) {
1473 dev_err(dcmi->dev, "Could not allocate memory\n");
1477 /* Fill array with sensor supported framesizes */
1478 dev_dbg(dcmi->dev, "Sensor supports %u frame sizes:\n", num_fsize);
1479 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) {
1481 ret = v4l2_subdev_call(subdev, pad, enum_frame_size,
1485 dcmi->sd_framesizes[fse.index].width = fse.max_width;
1486 dcmi->sd_framesizes[fse.index].height = fse.max_height;
1487 dev_dbg(dcmi->dev, "%ux%u\n", fse.max_width, fse.max_height);
1493 static int dcmi_graph_notify_complete(struct v4l2_async_notifier *notifier)
1495 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier);
1498 dcmi->vdev->ctrl_handler = dcmi->entity.subdev->ctrl_handler;
1499 ret = dcmi_formats_init(dcmi);
1501 dev_err(dcmi->dev, "No supported mediabus format found\n");
1505 ret = dcmi_framesizes_init(dcmi);
1507 dev_err(dcmi->dev, "Could not initialize framesizes\n");
1511 ret = dcmi_get_sensor_bounds(dcmi, &dcmi->sd_bounds);
1513 dev_err(dcmi->dev, "Could not get sensor bounds\n");
1517 ret = dcmi_set_default_fmt(dcmi);
1519 dev_err(dcmi->dev, "Could not set default format\n");
1523 ret = video_register_device(dcmi->vdev, VFL_TYPE_GRABBER, -1);
1525 dev_err(dcmi->dev, "Failed to register video device\n");
1529 dev_dbg(dcmi->dev, "Device registered as %s\n",
1530 video_device_node_name(dcmi->vdev));
1534 static void dcmi_graph_notify_unbind(struct v4l2_async_notifier *notifier,
1535 struct v4l2_subdev *sd,
1536 struct v4l2_async_subdev *asd)
1538 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier);
1540 dev_dbg(dcmi->dev, "Removing %s\n", video_device_node_name(dcmi->vdev));
1542 /* Checks internaly if vdev has been init or not */
1543 video_unregister_device(dcmi->vdev);
1546 static int dcmi_graph_notify_bound(struct v4l2_async_notifier *notifier,
1547 struct v4l2_subdev *subdev,
1548 struct v4l2_async_subdev *asd)
1550 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier);
1552 dev_dbg(dcmi->dev, "Subdev %s bound\n", subdev->name);
1554 dcmi->entity.subdev = subdev;
1559 static const struct v4l2_async_notifier_operations dcmi_graph_notify_ops = {
1560 .bound = dcmi_graph_notify_bound,
1561 .unbind = dcmi_graph_notify_unbind,
1562 .complete = dcmi_graph_notify_complete,
1565 static int dcmi_graph_parse(struct stm32_dcmi *dcmi, struct device_node *node)
1567 struct device_node *ep = NULL;
1568 struct device_node *remote;
1570 ep = of_graph_get_next_endpoint(node, ep);
1574 remote = of_graph_get_remote_port_parent(ep);
1579 /* Remote node to connect */
1580 dcmi->entity.node = remote;
1581 dcmi->entity.asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
1582 dcmi->entity.asd.match.fwnode = of_fwnode_handle(remote);
1586 static int dcmi_graph_init(struct stm32_dcmi *dcmi)
1588 struct v4l2_async_subdev **subdevs = NULL;
1591 /* Parse the graph to extract a list of subdevice DT nodes. */
1592 ret = dcmi_graph_parse(dcmi, dcmi->dev->of_node);
1594 dev_err(dcmi->dev, "Graph parsing failed\n");
1598 /* Register the subdevices notifier. */
1599 subdevs = devm_kzalloc(dcmi->dev, sizeof(*subdevs), GFP_KERNEL);
1601 of_node_put(dcmi->entity.node);
1605 subdevs[0] = &dcmi->entity.asd;
1607 dcmi->notifier.subdevs = subdevs;
1608 dcmi->notifier.num_subdevs = 1;
1609 dcmi->notifier.ops = &dcmi_graph_notify_ops;
1611 ret = v4l2_async_notifier_register(&dcmi->v4l2_dev, &dcmi->notifier);
1613 dev_err(dcmi->dev, "Notifier registration failed\n");
1614 of_node_put(dcmi->entity.node);
1621 static int dcmi_probe(struct platform_device *pdev)
1623 struct device_node *np = pdev->dev.of_node;
1624 const struct of_device_id *match = NULL;
1625 struct v4l2_fwnode_endpoint ep;
1626 struct stm32_dcmi *dcmi;
1627 struct vb2_queue *q;
1628 struct dma_chan *chan;
1633 match = of_match_device(of_match_ptr(stm32_dcmi_of_match), &pdev->dev);
1635 dev_err(&pdev->dev, "Could not find a match in devicetree\n");
1639 dcmi = devm_kzalloc(&pdev->dev, sizeof(struct stm32_dcmi), GFP_KERNEL);
1643 dcmi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1644 if (IS_ERR(dcmi->rstc)) {
1645 dev_err(&pdev->dev, "Could not get reset control\n");
1649 /* Get bus characteristics from devicetree */
1650 np = of_graph_get_next_endpoint(np, NULL);
1652 dev_err(&pdev->dev, "Could not find the endpoint\n");
1657 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
1659 dev_err(&pdev->dev, "Could not parse the endpoint\n");
1664 if (ep.bus_type == V4L2_MBUS_CSI2) {
1665 dev_err(&pdev->dev, "CSI bus not supported\n");
1669 dcmi->bus.flags = ep.bus.parallel.flags;
1670 dcmi->bus.bus_width = ep.bus.parallel.bus_width;
1671 dcmi->bus.data_shift = ep.bus.parallel.data_shift;
1675 irq = platform_get_irq(pdev, 0);
1677 dev_err(&pdev->dev, "Could not get irq\n");
1681 dcmi->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1683 dev_err(&pdev->dev, "Could not get resource\n");
1687 dcmi->regs = devm_ioremap_resource(&pdev->dev, dcmi->res);
1688 if (IS_ERR(dcmi->regs)) {
1689 dev_err(&pdev->dev, "Could not map registers\n");
1690 return PTR_ERR(dcmi->regs);
1693 ret = devm_request_threaded_irq(&pdev->dev, irq, dcmi_irq_callback,
1694 dcmi_irq_thread, IRQF_ONESHOT,
1695 dev_name(&pdev->dev), dcmi);
1697 dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
1701 mclk = devm_clk_get(&pdev->dev, "mclk");
1703 dev_err(&pdev->dev, "Unable to get mclk\n");
1704 return PTR_ERR(mclk);
1707 chan = dma_request_slave_channel(&pdev->dev, "tx");
1709 dev_info(&pdev->dev, "Unable to request DMA channel, defer probing\n");
1710 return -EPROBE_DEFER;
1713 ret = clk_prepare(mclk);
1715 dev_err(&pdev->dev, "Unable to prepare mclk %p\n", mclk);
1716 goto err_dma_release;
1719 spin_lock_init(&dcmi->irqlock);
1720 mutex_init(&dcmi->lock);
1721 init_completion(&dcmi->complete);
1722 INIT_LIST_HEAD(&dcmi->buffers);
1724 dcmi->dev = &pdev->dev;
1726 dcmi->state = STOPPED;
1727 dcmi->dma_chan = chan;
1731 /* Initialize the top-level structure */
1732 ret = v4l2_device_register(&pdev->dev, &dcmi->v4l2_dev);
1734 goto err_clk_unprepare;
1736 dcmi->vdev = video_device_alloc();
1739 goto err_device_unregister;
1743 dcmi->vdev->fops = &dcmi_fops;
1744 dcmi->vdev->v4l2_dev = &dcmi->v4l2_dev;
1745 dcmi->vdev->queue = &dcmi->queue;
1746 strlcpy(dcmi->vdev->name, KBUILD_MODNAME, sizeof(dcmi->vdev->name));
1747 dcmi->vdev->release = video_device_release;
1748 dcmi->vdev->ioctl_ops = &dcmi_ioctl_ops;
1749 dcmi->vdev->lock = &dcmi->lock;
1750 dcmi->vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
1752 video_set_drvdata(dcmi->vdev, dcmi);
1755 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1756 q->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
1757 q->lock = &dcmi->lock;
1759 q->buf_struct_size = sizeof(struct dcmi_buf);
1760 q->ops = &dcmi_video_qops;
1761 q->mem_ops = &vb2_dma_contig_memops;
1762 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1763 q->min_buffers_needed = 2;
1764 q->dev = &pdev->dev;
1766 ret = vb2_queue_init(q);
1768 dev_err(&pdev->dev, "Failed to initialize vb2 queue\n");
1769 goto err_device_release;
1772 ret = dcmi_graph_init(dcmi);
1774 goto err_device_release;
1777 ret = reset_control_assert(dcmi->rstc);
1779 dev_err(&pdev->dev, "Failed to assert the reset line\n");
1780 goto err_device_release;
1783 usleep_range(3000, 5000);
1785 ret = reset_control_deassert(dcmi->rstc);
1787 dev_err(&pdev->dev, "Failed to deassert the reset line\n");
1788 goto err_device_release;
1791 dev_info(&pdev->dev, "Probe done\n");
1793 platform_set_drvdata(pdev, dcmi);
1797 video_device_release(dcmi->vdev);
1798 err_device_unregister:
1799 v4l2_device_unregister(&dcmi->v4l2_dev);
1801 clk_unprepare(dcmi->mclk);
1803 dma_release_channel(dcmi->dma_chan);
1808 static int dcmi_remove(struct platform_device *pdev)
1810 struct stm32_dcmi *dcmi = platform_get_drvdata(pdev);
1812 v4l2_async_notifier_unregister(&dcmi->notifier);
1813 v4l2_device_unregister(&dcmi->v4l2_dev);
1814 clk_unprepare(dcmi->mclk);
1815 dma_release_channel(dcmi->dma_chan);
1820 static struct platform_driver stm32_dcmi_driver = {
1821 .probe = dcmi_probe,
1822 .remove = dcmi_remove,
1825 .of_match_table = of_match_ptr(stm32_dcmi_of_match),
1829 module_platform_driver(stm32_dcmi_driver);
1831 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
1832 MODULE_AUTHOR("Hugues Fruchet <hugues.fruchet@st.com>");
1833 MODULE_DESCRIPTION("STMicroelectronics STM32 Digital Camera Memory Interface driver");
1834 MODULE_LICENSE("GPL");
1835 MODULE_SUPPORTED_DEVICE("video");