1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Register definition file for s3c24xx/s3c64xx SoC CAMIF driver
5 * Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
6 * Copyright (C) 2012 Tomasz Figa <tomasz.figa@gmail.com>
12 #include "camif-core.h"
13 #include <media/drv-intf/s3c_camif.h>
16 * The id argument indicates the processing path:
17 * id = 0 - codec (FIMC C), 1 - preview (FIMC P).
20 /* Camera input format */
21 #define S3C_CAMIF_REG_CISRCFMT 0x00
22 #define CISRCFMT_ITU601_8BIT (1 << 31)
23 #define CISRCFMT_ITU656_8BIT (0 << 31)
24 #define CISRCFMT_ORDER422_YCBYCR (0 << 14)
25 #define CISRCFMT_ORDER422_YCRYCB (1 << 14)
26 #define CISRCFMT_ORDER422_CBYCRY (2 << 14)
27 #define CISRCFMT_ORDER422_CRYCBY (3 << 14)
28 #define CISRCFMT_ORDER422_MASK (3 << 14)
29 #define CISRCFMT_SIZE_CAM_MASK (0x1fff << 16 | 0x1fff)
32 #define S3C_CAMIF_REG_CIWDOFST 0x04
33 #define CIWDOFST_WINOFSEN (1 << 31)
34 #define CIWDOFST_CLROVCOFIY (1 << 30)
35 #define CIWDOFST_CLROVRLB_PR (1 << 28)
36 /* #define CIWDOFST_CLROVPRFIY (1 << 27) */
37 #define CIWDOFST_CLROVCOFICB (1 << 15)
38 #define CIWDOFST_CLROVCOFICR (1 << 14)
39 #define CIWDOFST_CLROVPRFICB (1 << 13)
40 #define CIWDOFST_CLROVPRFICR (1 << 12)
41 #define CIWDOFST_OFST_MASK (0x7ff << 16 | 0x7ff)
44 #define S3C_CAMIF_REG_CIWDOFST2 0x14
45 #define CIWDOFST2_OFST2_MASK (0xfff << 16 | 0xfff)
48 #define S3C_CAMIF_REG_CIGCTRL 0x08
49 #define CIGCTRL_SWRST (1 << 31)
50 #define CIGCTRL_CAMRST (1 << 30)
51 #define CIGCTRL_TESTPATTERN_NORMAL (0 << 27)
52 #define CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27)
53 #define CIGCTRL_TESTPATTERN_HOR_INC (2 << 27)
54 #define CIGCTRL_TESTPATTERN_VER_INC (3 << 27)
55 #define CIGCTRL_TESTPATTERN_MASK (3 << 27)
56 #define CIGCTRL_INVPOLPCLK (1 << 26)
57 #define CIGCTRL_INVPOLVSYNC (1 << 25)
58 #define CIGCTRL_INVPOLHREF (1 << 24)
59 #define CIGCTRL_IRQ_OVFEN (1 << 22)
60 #define CIGCTRL_HREF_MASK (1 << 21)
61 #define CIGCTRL_IRQ_LEVEL (1 << 20)
62 /* IRQ_CLR_C, IRQ_CLR_P */
63 #define CIGCTRL_IRQ_CLR(id) (1 << (19 - (id)))
64 #define CIGCTRL_FIELDMODE (1 << 2)
65 #define CIGCTRL_INVPOLFIELD (1 << 1)
66 #define CIGCTRL_CAM_INTERLACE (1 << 0)
68 /* Y DMA output frame start address. n = 0..3. */
69 #define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4)
70 /* Cb plane output DMA start address. n = 0..3. Only codec path. */
71 #define S3C_CAMIF_REG_CICBSA(id, n) (0x28 + (id) * 0x54 + (n) * 4)
72 /* Cr plane output DMA start address. n = 0..3. Only codec path. */
73 #define S3C_CAMIF_REG_CICRSA(id, n) (0x38 + (id) * 0x54 + (n) * 4)
75 /* CICOTRGFMT, CIPRTRGFMT - Target format */
76 #define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs)))
77 #define CITRGFMT_IN422 (1 << 31) /* only for s3c24xx */
78 #define CITRGFMT_OUT422 (1 << 30) /* only for s3c24xx */
79 #define CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) /* only for s3c6410 */
80 #define CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) /* only for s3c6410 */
81 #define CITRGFMT_OUTFORMAT_YCBCR422I (2 << 29) /* only for s3c6410 */
82 #define CITRGFMT_OUTFORMAT_RGB (3 << 29) /* only for s3c6410 */
83 #define CITRGFMT_OUTFORMAT_MASK (3 << 29) /* only for s3c6410 */
84 #define CITRGFMT_TARGETHSIZE(x) ((x) << 16)
85 #define CITRGFMT_FLIP_NORMAL (0 << 14)
86 #define CITRGFMT_FLIP_X_MIRROR (1 << 14)
87 #define CITRGFMT_FLIP_Y_MIRROR (2 << 14)
88 #define CITRGFMT_FLIP_180 (3 << 14)
89 #define CITRGFMT_FLIP_MASK (3 << 14)
90 /* Preview path only */
91 #define CITRGFMT_ROT90_PR (1 << 13)
92 #define CITRGFMT_TARGETVSIZE(x) ((x) << 0)
93 #define CITRGFMT_TARGETSIZE_MASK ((0x1fff << 16) | 0x1fff)
95 /* CICOCTRL, CIPRCTRL. Output DMA control. */
96 #define S3C_CAMIF_REG_CICTRL(id, _offs) (0x4c + (id) * (0x34 + (_offs)))
97 #define CICTRL_BURST_MASK (0xfffff << 4)
98 /* xBURSTn - 5-bits width */
99 #define CICTRL_YBURST1(x) ((x) << 19)
100 #define CICTRL_YBURST2(x) ((x) << 14)
101 #define CICTRL_RGBBURST1(x) ((x) << 19)
102 #define CICTRL_RGBBURST2(x) ((x) << 14)
103 #define CICTRL_CBURST1(x) ((x) << 9)
104 #define CICTRL_CBURST2(x) ((x) << 4)
105 #define CICTRL_LASTIRQ_ENABLE (1 << 2)
106 #define CICTRL_ORDER422_MASK (3 << 0)
108 /* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */
109 #define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) (0x50 + (id) * (0x34 + (_offs)))
111 /* CICOSCPREDST, CIPRSCPREDST. Pre-scaler control 2. */
112 #define S3C_CAMIF_REG_CISCPREDST(id, _offs) (0x54 + (id) * (0x34 + (_offs)))
114 /* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */
115 #define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs)))
116 #define CISCCTRL_SCALERBYPASS (1 << 31)
117 /* s3c244x preview path only, s3c64xx both */
118 #define CIPRSCCTRL_SAMPLE (1 << 31)
119 /* 0 - 16-bit RGB, 1 - 24-bit RGB */
120 #define CIPRSCCTRL_RGB_FORMAT_24BIT (1 << 30) /* only for s3c244x */
121 #define CIPRSCCTRL_SCALEUP_H (1 << 29) /* only for s3c244x */
122 #define CIPRSCCTRL_SCALEUP_V (1 << 28) /* only for s3c244x */
124 #define CISCCTRL_SCALEUP_H (1 << 30)
125 #define CISCCTRL_SCALEUP_V (1 << 29)
126 #define CISCCTRL_SCALEUP_MASK (0x3 << 29)
127 #define CISCCTRL_CSCR2Y_WIDE (1 << 28)
128 #define CISCCTRL_CSCY2R_WIDE (1 << 27)
129 #define CISCCTRL_LCDPATHEN_FIFO (1 << 26)
130 #define CISCCTRL_INTERLACE (1 << 25)
131 #define CISCCTRL_SCALERSTART (1 << 15)
132 #define CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
133 #define CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
134 #define CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
135 #define CISCCTRL_INRGB_FMT_MASK (3 << 13)
136 #define CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
137 #define CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
138 #define CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
139 #define CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
140 #define CISCCTRL_EXTRGB_EXTENSION (1 << 10)
141 #define CISCCTRL_ONE2ONE (1 << 9)
142 #define CISCCTRL_MAIN_RATIO_MASK (0x1ff << 16 | 0x1ff)
144 /* CICOTAREA, CIPRTAREA. Target area for DMA (Hsize x Vsize). */
145 #define S3C_CAMIF_REG_CITAREA(id, _offs) (0x5c + (id) * (0x34 + (_offs)))
146 #define CITAREA_MASK 0xfffffff
148 /* Codec (id = 0) or preview (id = 1) path status. */
149 #define S3C_CAMIF_REG_CISTATUS(id, _offs) (0x64 + (id) * (0x34 + (_offs)))
150 #define CISTATUS_OVFIY_STATUS (1 << 31)
151 #define CISTATUS_OVFICB_STATUS (1 << 30)
152 #define CISTATUS_OVFICR_STATUS (1 << 29)
153 #define CISTATUS_OVF_MASK (0x7 << 29)
154 #define CIPRSTATUS_OVF_MASK (0x3 << 30)
155 #define CISTATUS_VSYNC_STATUS (1 << 28)
156 #define CISTATUS_FRAMECNT_MASK (3 << 26)
157 #define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3)
158 #define CISTATUS_WINOFSTEN_STATUS (1 << 25)
159 #define CISTATUS_IMGCPTEN_STATUS (1 << 22)
160 #define CISTATUS_IMGCPTENSC_STATUS (1 << 21)
161 #define CISTATUS_VSYNC_A_STATUS (1 << 20)
162 #define CISTATUS_FRAMEEND_STATUS (1 << 19) /* 17 on s3c64xx */
164 /* Image capture enable */
165 #define S3C_CAMIF_REG_CIIMGCPT(_offs) (0xa0 + (_offs))
166 #define CIIMGCPT_IMGCPTEN (1 << 31)
167 #define CIIMGCPT_IMGCPTEN_SC(id) (1 << (30 - (id)))
168 /* Frame control: 1 - one-shot, 0 - free run */
169 #define CIIMGCPT_CPT_FREN_ENABLE(id) (1 << (25 - (id)))
170 #define CIIMGCPT_CPT_FRMOD_ENABLE (0 << 18)
171 #define CIIMGCPT_CPT_FRMOD_CNT (1 << 18)
173 /* Capture sequence */
174 #define S3C_CAMIF_REG_CICPTSEQ 0xc4
177 #define S3C_CAMIF_REG_CIIMGEFF(_offs) (0xb0 + (_offs))
178 #define CIIMGEFF_IE_ENABLE(id) (1 << (30 + (id)))
179 #define CIIMGEFF_IE_ENABLE_MASK (3 << 30)
180 /* Image effect: 1 - after scaler, 0 - before scaler */
181 #define CIIMGEFF_IE_AFTER_SC (1 << 29)
182 #define CIIMGEFF_FIN_MASK (7 << 26)
183 #define CIIMGEFF_FIN_BYPASS (0 << 26)
184 #define CIIMGEFF_FIN_ARBITRARY (1 << 26)
185 #define CIIMGEFF_FIN_NEGATIVE (2 << 26)
186 #define CIIMGEFF_FIN_ARTFREEZE (3 << 26)
187 #define CIIMGEFF_FIN_EMBOSSING (4 << 26)
188 #define CIIMGEFF_FIN_SILHOUETTE (5 << 26)
189 #define CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | 0xff)
190 #define CIIMGEFF_PAT_CB(x) ((x) << 13)
191 #define CIIMGEFF_PAT_CR(x) (x)
193 /* MSCOY0SA, MSPRY0SA. Y/Cb/Cr frame start address for input DMA. */
194 #define S3C_CAMIF_REG_MSY0SA(id) (0xd4 + ((id) * 0x2c))
195 #define S3C_CAMIF_REG_MSCB0SA(id) (0xd8 + ((id) * 0x2c))
196 #define S3C_CAMIF_REG_MSCR0SA(id) (0xdc + ((id) * 0x2c))
198 /* MSCOY0END, MSCOY0END. Y/Cb/Cr frame end address for input DMA. */
199 #define S3C_CAMIF_REG_MSY0END(id) (0xe0 + ((id) * 0x2c))
200 #define S3C_CAMIF_REG_MSCB0END(id) (0xe4 + ((id) * 0x2c))
201 #define S3C_CAMIF_REG_MSCR0END(id) (0xe8 + ((id) * 0x2c))
203 /* MSPRYOFF, MSPRYOFF. Y/Cb/Cr offset. n: 0 - codec, 1 - preview. */
204 #define S3C_CAMIF_REG_MSYOFF(id) (0x118 + ((id) * 0x2c))
205 #define S3C_CAMIF_REG_MSCBOFF(id) (0x11c + ((id) * 0x2c))
206 #define S3C_CAMIF_REG_MSCROFF(id) (0x120 + ((id) * 0x2c))
208 /* Real input DMA data size. n = 0 - codec, 1 - preview. */
209 #define S3C_CAMIF_REG_MSWIDTH(id) (0xf8 + (id) * 0x2c)
210 #define AUTOLOAD_ENABLE (1 << 31)
211 #define ADDR_CH_DIS (1 << 30)
212 #define MSHEIGHT(x) (((x) & 0x3ff) << 16)
213 #define MSWIDTH(x) ((x) & 0x3ff)
215 /* Input DMA control. n = 0 - codec, 1 - preview */
216 #define S3C_CAMIF_REG_MSCTRL(id) (0xfc + (id) * 0x2c)
217 #define MSCTRL_ORDER422_M_YCBYCR (0 << 4)
218 #define MSCTRL_ORDER422_M_YCRYCB (1 << 4)
219 #define MSCTRL_ORDER422_M_CBYCRY (2 << 4)
220 #define MSCTRL_ORDER422_M_CRYCBY (3 << 4)
221 /* 0 - camera, 1 - DMA */
222 #define MSCTRL_SEL_DMA_CAM (1 << 3)
223 #define MSCTRL_INFORMAT_M_YCBCR420 (0 << 1)
224 #define MSCTRL_INFORMAT_M_YCBCR422 (1 << 1)
225 #define MSCTRL_INFORMAT_M_YCBCR422I (2 << 1)
226 #define MSCTRL_INFORMAT_M_RGB (3 << 1)
227 #define MSCTRL_ENVID_M (1 << 0)
229 /* CICOSCOSY, CIPRSCOSY. Scan line Y/Cb/Cr offset. */
230 #define S3C_CAMIF_REG_CISSY(id) (0x12c + (id) * 0x0c)
231 #define S3C_CAMIF_REG_CISSCB(id) (0x130 + (id) * 0x0c)
232 #define S3C_CAMIF_REG_CISSCR(id) (0x134 + (id) * 0x0c)
233 #define S3C_CISS_OFFS_INITIAL(x) ((x) << 16)
234 #define S3C_CISS_OFFS_LINE(x) ((x) << 0)
236 /* ------------------------------------------------------------------ */
238 void camif_hw_reset(struct camif_dev *camif);
239 void camif_hw_clear_pending_irq(struct camif_vp *vp);
240 void camif_hw_clear_fifo_overflow(struct camif_vp *vp);
241 void camif_hw_set_lastirq(struct camif_vp *vp, int enable);
242 void camif_hw_set_input_path(struct camif_vp *vp);
243 void camif_hw_enable_scaler(struct camif_vp *vp, bool on);
244 void camif_hw_enable_capture(struct camif_vp *vp);
245 void camif_hw_disable_capture(struct camif_vp *vp);
246 void camif_hw_set_camera_bus(struct camif_dev *camif);
247 void camif_hw_set_source_format(struct camif_dev *camif);
248 void camif_hw_set_camera_crop(struct camif_dev *camif);
249 void camif_hw_set_scaler(struct camif_vp *vp);
250 void camif_hw_set_flip(struct camif_vp *vp);
251 void camif_hw_set_output_dma(struct camif_vp *vp);
252 void camif_hw_set_target_format(struct camif_vp *vp);
253 void camif_hw_set_test_pattern(struct camif_dev *camif, unsigned int pattern);
254 void camif_hw_set_effect(struct camif_dev *camif, unsigned int effect,
255 unsigned int cr, unsigned int cb);
256 void camif_hw_set_output_addr(struct camif_vp *vp, struct camif_addr *paddr,
258 void camif_hw_dump_regs(struct camif_dev *camif, const char *label);
260 static inline u32 camif_hw_get_status(struct camif_vp *vp)
262 return readl(vp->camif->io_base + S3C_CAMIF_REG_CISTATUS(vp->id,
266 #endif /* CAMIF_REGS_H_ */