1 // SPDX-License-Identifier: GPL-2.0
3 * V4L2 Driver for Renesas Capture Engine Unit (CEU) interface
4 * Copyright (C) 2017-2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Based on soc-camera driver "soc_camera/sh_mobile_ceu_camera.c"
7 * Copyright (C) 2008 Magnus Damm
9 * Based on V4L2 Driver for PXA camera host - "pxa_camera.c",
10 * Copyright (C) 2006, Sascha Hauer, Pengutronix
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/err.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_graph.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/time.h>
31 #include <linux/videodev2.h>
33 #include <media/v4l2-async.h>
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-ctrls.h>
36 #include <media/v4l2-dev.h>
37 #include <media/v4l2-device.h>
38 #include <media/v4l2-event.h>
39 #include <media/v4l2-fwnode.h>
40 #include <media/v4l2-image-sizes.h>
41 #include <media/v4l2-ioctl.h>
42 #include <media/v4l2-mediabus.h>
43 #include <media/videobuf2-dma-contig.h>
45 #include <media/drv-intf/renesas-ceu.h>
47 #define DRIVER_NAME "renesas-ceu"
49 /* CEU registers offsets and masks. */
50 #define CEU_CAPSR 0x00 /* Capture start register */
51 #define CEU_CAPCR 0x04 /* Capture control register */
52 #define CEU_CAMCR 0x08 /* Capture interface control register */
53 #define CEU_CAMOR 0x10 /* Capture interface offset register */
54 #define CEU_CAPWR 0x14 /* Capture interface width register */
55 #define CEU_CAIFR 0x18 /* Capture interface input format register */
56 #define CEU_CRCNTR 0x28 /* CEU register control register */
57 #define CEU_CRCMPR 0x2c /* CEU register forcible control register */
58 #define CEU_CFLCR 0x30 /* Capture filter control register */
59 #define CEU_CFSZR 0x34 /* Capture filter size clip register */
60 #define CEU_CDWDR 0x38 /* Capture destination width register */
61 #define CEU_CDAYR 0x3c /* Capture data address Y register */
62 #define CEU_CDACR 0x40 /* Capture data address C register */
63 #define CEU_CFWCR 0x5c /* Firewall operation control register */
64 #define CEU_CDOCR 0x64 /* Capture data output control register */
65 #define CEU_CEIER 0x70 /* Capture event interrupt enable register */
66 #define CEU_CETCR 0x74 /* Capture event flag clear register */
67 #define CEU_CSTSR 0x7c /* Capture status register */
68 #define CEU_CSRTR 0x80 /* Capture software reset register */
70 /* Data synchronous fetch mode. */
71 #define CEU_CAMCR_JPEG BIT(4)
73 /* Input components ordering: CEU_CAMCR.DTARY field. */
74 #define CEU_CAMCR_DTARY_8_UYVY (0x00 << 8)
75 #define CEU_CAMCR_DTARY_8_VYUY (0x01 << 8)
76 #define CEU_CAMCR_DTARY_8_YUYV (0x02 << 8)
77 #define CEU_CAMCR_DTARY_8_YVYU (0x03 << 8)
78 /* TODO: input components ordering for 16 bits input. */
80 /* Bus transfer MTU. */
81 #define CEU_CAPCR_BUS_WIDTH256 (0x3 << 20)
83 /* Bus width configuration. */
84 #define CEU_CAMCR_DTIF_16BITS BIT(12)
86 /* No downsampling to planar YUV420 in image fetch mode. */
87 #define CEU_CDOCR_NO_DOWSAMPLE BIT(4)
89 /* Swap all input data in 8-bit, 16-bits and 32-bits units (Figure 46.45). */
90 #define CEU_CDOCR_SWAP_ENDIANNESS (7)
92 /* Capture reset and enable bits. */
93 #define CEU_CAPSR_CPKIL BIT(16)
94 #define CEU_CAPSR_CE BIT(0)
96 /* CEU operating flag bit. */
97 #define CEU_CAPCR_CTNCP BIT(16)
98 #define CEU_CSTRST_CPTON BIT(0)
100 /* Platform specific IRQ source flags. */
101 #define CEU_CETCR_ALL_IRQS_RZ 0x397f313
102 #define CEU_CETCR_ALL_IRQS_SH4 0x3d7f313
104 /* Prohibited register access interrupt bit. */
105 #define CEU_CETCR_IGRW BIT(4)
106 /* One-frame capture end interrupt. */
107 #define CEU_CEIER_CPE BIT(0)
109 #define CEU_CEIER_VBP BIT(20)
110 #define CEU_CEIER_MASK (CEU_CEIER_CPE | CEU_CEIER_VBP)
112 #define CEU_MAX_WIDTH 2560
113 #define CEU_MAX_HEIGHT 1920
114 #define CEU_MAX_BPL 8188
115 #define CEU_W_MAX(w) ((w) < CEU_MAX_WIDTH ? (w) : CEU_MAX_WIDTH)
116 #define CEU_H_MAX(h) ((h) < CEU_MAX_HEIGHT ? (h) : CEU_MAX_HEIGHT)
119 * ceu_bus_fmt - describe a 8-bits yuyv format the sensor can produce
121 * @mbus_code: bus format code
122 * @fmt_order: CEU_CAMCR.DTARY ordering of input components (Y, Cb, Cr)
123 * @fmt_order_swap: swapped CEU_CAMCR.DTARY ordering of input components
125 * @swapped: does Cr appear before Cb?
126 * @bps: number of bits sent over bus for each sample
127 * @bpp: number of bits per pixels unit
129 struct ceu_mbus_fmt {
139 * ceu_buffer - Link vb2 buffer to the list of available buffers.
142 struct vb2_v4l2_buffer vb;
143 struct list_head queue;
146 static inline struct ceu_buffer *vb2_to_ceu(struct vb2_v4l2_buffer *vbuf)
148 return container_of(vbuf, struct ceu_buffer, vb);
152 * ceu_subdev - Wraps v4l2 sub-device and provides async subdevice.
155 struct v4l2_subdev *v4l2_sd;
156 struct v4l2_async_subdev asd;
158 /* per-subdevice mbus configuration options */
159 unsigned int mbus_flags;
160 struct ceu_mbus_fmt mbus_fmt;
163 static struct ceu_subdev *to_ceu_subdev(struct v4l2_async_subdev *asd)
165 return container_of(asd, struct ceu_subdev, asd);
169 * ceu_device - CEU device instance
173 struct video_device vdev;
174 struct v4l2_device v4l2_dev;
176 /* subdevices descriptors */
177 struct ceu_subdev *subdevs;
178 /* the subdevice currently in use */
179 struct ceu_subdev *sd;
180 unsigned int sd_index;
183 /* platform specific mask with all IRQ sources flagged */
186 /* currently configured field and pixel format */
187 enum v4l2_field field;
188 struct v4l2_pix_format_mplane v4l2_pix;
190 /* async subdev notification helpers */
191 struct v4l2_async_notifier notifier;
192 /* pointers to "struct ceu_subdevice -> asd" */
193 struct v4l2_async_subdev **asds;
195 /* vb2 queue, capture buffer list and active buffer pointer */
196 struct vb2_queue vb2_vq;
197 struct list_head capture;
198 struct vb2_v4l2_buffer *active;
199 unsigned int sequence;
201 /* mlock - lock access to interface reset and vb2 queue */
204 /* lock - lock access to capture buffer queue and active buffer */
207 /* base - CEU memory base address */
211 static inline struct ceu_device *v4l2_to_ceu(struct v4l2_device *v4l2_dev)
213 return container_of(v4l2_dev, struct ceu_device, v4l2_dev);
216 /* --- CEU memory output formats --- */
219 * ceu_fmt - describe a memory output format supported by CEU interface.
221 * @fourcc: memory layout fourcc format code
222 * @bpp: number of bits for each pixel stored in memory
230 * ceu_format_list - List of supported memory output formats
232 * If sensor provides any YUYV bus format, all the following planar memory
233 * formats are available thanks to CEU re-ordering and sub-sampling
236 static const struct ceu_fmt ceu_fmt_list[] = {
238 .fourcc = V4L2_PIX_FMT_NV16,
242 .fourcc = V4L2_PIX_FMT_NV61,
246 .fourcc = V4L2_PIX_FMT_NV12,
250 .fourcc = V4L2_PIX_FMT_NV21,
254 .fourcc = V4L2_PIX_FMT_YUYV,
259 static const struct ceu_fmt *get_ceu_fmt_from_fourcc(unsigned int fourcc)
261 const struct ceu_fmt *fmt = &ceu_fmt_list[0];
264 for (i = 0; i < ARRAY_SIZE(ceu_fmt_list); i++, fmt++)
265 if (fmt->fourcc == fourcc)
271 static bool ceu_fmt_mplane(struct v4l2_pix_format_mplane *pix)
273 switch (pix->pixelformat) {
274 case V4L2_PIX_FMT_YUYV:
276 case V4L2_PIX_FMT_NV16:
277 case V4L2_PIX_FMT_NV61:
278 case V4L2_PIX_FMT_NV12:
279 case V4L2_PIX_FMT_NV21:
286 /* --- CEU HW operations --- */
288 static void ceu_write(struct ceu_device *priv, unsigned int reg_offs, u32 data)
290 iowrite32(data, priv->base + reg_offs);
293 static u32 ceu_read(struct ceu_device *priv, unsigned int reg_offs)
295 return ioread32(priv->base + reg_offs);
299 * ceu_soft_reset() - Software reset the CEU interface.
300 * @ceu_device: CEU device.
302 * Returns 0 for success, -EIO for error.
304 static int ceu_soft_reset(struct ceu_device *ceudev)
308 ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CPKIL);
310 for (i = 0; i < 100; i++) {
311 if (!(ceu_read(ceudev, CEU_CSTSR) & CEU_CSTRST_CPTON))
317 dev_err(ceudev->dev, "soft reset time out\n");
321 for (i = 0; i < 100; i++) {
322 if (!(ceu_read(ceudev, CEU_CAPSR) & CEU_CAPSR_CPKIL))
327 /* If we get here, CEU has not reset properly. */
331 /* --- CEU Capture Operations --- */
334 * ceu_hw_config() - Configure CEU interface registers.
336 static int ceu_hw_config(struct ceu_device *ceudev)
338 u32 camcr, cdocr, cfzsr, cdwdr, capwr;
339 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
340 struct ceu_subdev *ceu_sd = ceudev->sd;
341 struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt;
342 unsigned int mbus_flags = ceu_sd->mbus_flags;
344 /* Start configuring CEU registers */
345 ceu_write(ceudev, CEU_CAIFR, 0);
346 ceu_write(ceudev, CEU_CFWCR, 0);
347 ceu_write(ceudev, CEU_CRCNTR, 0);
348 ceu_write(ceudev, CEU_CRCMPR, 0);
350 /* Set the frame capture period for both image capture and data sync. */
351 capwr = (pix->height << 16) | pix->width * mbus_fmt->bpp / 8;
354 * Swap input data endianness by default.
355 * In data fetch mode bytes are received in chunks of 8 bytes.
356 * D0, D1, D2, D3, D4, D5, D6, D7 (D0 received first)
357 * The data is however by default written to memory in reverse order:
358 * D7, D6, D5, D4, D3, D2, D1, D0 (D7 written to lowest byte)
360 * Use CEU_CDOCR[2:0] to swap data ordering.
362 cdocr = CEU_CDOCR_SWAP_ENDIANNESS;
365 * Configure CAMCR and CDOCR:
366 * match input components ordering with memory output format and
367 * handle downsampling to YUV420.
369 * If the memory output planar format is 'swapped' (Cr before Cb) and
370 * input format is not, use the swapped version of CAMCR.DTARY.
372 * If the memory output planar format is not 'swapped' (Cb before Cr)
373 * and input format is, use the swapped version of CAMCR.DTARY.
375 * CEU by default downsample to planar YUV420 (CDCOR[4] = 0).
376 * If output is planar YUV422 set CDOCR[4] = 1
378 * No downsample for data fetch sync mode.
380 switch (pix->pixelformat) {
381 /* Data fetch sync mode */
382 case V4L2_PIX_FMT_YUYV:
383 /* TODO: handle YUYV permutations through DTARY bits. */
384 camcr = CEU_CAMCR_JPEG;
385 cdocr |= CEU_CDOCR_NO_DOWSAMPLE;
386 cfzsr = (pix->height << 16) | pix->width;
387 cdwdr = pix->plane_fmt[0].bytesperline;
390 /* Non-swapped planar image capture mode. */
391 case V4L2_PIX_FMT_NV16:
392 cdocr |= CEU_CDOCR_NO_DOWSAMPLE;
394 case V4L2_PIX_FMT_NV12:
395 if (mbus_fmt->swapped)
396 camcr = mbus_fmt->fmt_order_swap;
398 camcr = mbus_fmt->fmt_order;
400 cfzsr = (pix->height << 16) | pix->width;
404 /* Swapped planar image capture mode. */
405 case V4L2_PIX_FMT_NV61:
406 cdocr |= CEU_CDOCR_NO_DOWSAMPLE;
408 case V4L2_PIX_FMT_NV21:
409 if (mbus_fmt->swapped)
410 camcr = mbus_fmt->fmt_order;
412 camcr = mbus_fmt->fmt_order_swap;
414 cfzsr = (pix->height << 16) | pix->width;
422 camcr |= mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? 1 << 1 : 0;
423 camcr |= mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? 1 << 0 : 0;
425 /* TODO: handle 16 bit bus width with DTIF bit in CAMCR */
426 ceu_write(ceudev, CEU_CAMCR, camcr);
427 ceu_write(ceudev, CEU_CDOCR, cdocr);
428 ceu_write(ceudev, CEU_CAPCR, CEU_CAPCR_BUS_WIDTH256);
431 * TODO: make CAMOR offsets configurable.
432 * CAMOR wants to know the number of blanks between a VS/HS signal
433 * and valid data. This value should actually come from the sensor...
435 ceu_write(ceudev, CEU_CAMOR, 0);
437 /* TODO: 16 bit bus width require re-calculation of cdwdr and cfzsr */
438 ceu_write(ceudev, CEU_CAPWR, capwr);
439 ceu_write(ceudev, CEU_CFSZR, cfzsr);
440 ceu_write(ceudev, CEU_CDWDR, cdwdr);
446 * ceu_capture() - Trigger start of a capture sequence.
448 * Program the CEU DMA registers with addresses where to transfer image data.
450 static int ceu_capture(struct ceu_device *ceudev)
452 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
453 dma_addr_t phys_addr_top;
456 vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf, 0);
457 ceu_write(ceudev, CEU_CDAYR, phys_addr_top);
459 /* Ignore CbCr plane for non multi-planar image formats. */
460 if (ceu_fmt_mplane(pix)) {
462 vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf,
464 ceu_write(ceudev, CEU_CDACR, phys_addr_top);
468 * Trigger new capture start: once for each frame, as we work in
469 * one-frame capture mode.
471 ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CE);
476 static irqreturn_t ceu_irq(int irq, void *data)
478 struct ceu_device *ceudev = data;
479 struct vb2_v4l2_buffer *vbuf;
480 struct ceu_buffer *buf;
483 /* Clean interrupt status. */
484 status = ceu_read(ceudev, CEU_CETCR);
485 ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask);
487 /* Unexpected interrupt. */
488 if (!(status & CEU_CEIER_MASK))
491 spin_lock(&ceudev->lock);
493 /* Stale interrupt from a released buffer, ignore it. */
494 vbuf = ceudev->active;
496 spin_unlock(&ceudev->lock);
501 * When a VBP interrupt occurs, no capture end interrupt will occur
502 * and the image of that frame is not captured correctly.
504 if (status & CEU_CEIER_VBP) {
505 dev_err(ceudev->dev, "VBP interrupt: abort capture\n");
509 /* Prepare to return the 'previous' buffer. */
510 vbuf->vb2_buf.timestamp = ktime_get_ns();
511 vbuf->sequence = ceudev->sequence++;
512 vbuf->field = ceudev->field;
514 /* Prepare a new 'active' buffer and trigger a new capture. */
515 if (!list_empty(&ceudev->capture)) {
516 buf = list_first_entry(&ceudev->capture, struct ceu_buffer,
518 list_del(&buf->queue);
519 ceudev->active = &buf->vb;
524 /* Return the 'previous' buffer. */
525 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE);
527 spin_unlock(&ceudev->lock);
532 /* Return the 'previous' buffer and all queued ones. */
533 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_ERROR);
535 list_for_each_entry(buf, &ceudev->capture, queue)
536 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
538 spin_unlock(&ceudev->lock);
543 /* --- CEU Videobuf2 operations --- */
545 static void ceu_update_plane_sizes(struct v4l2_plane_pix_format *plane,
546 unsigned int bpl, unsigned int szimage)
548 memset(plane, 0, sizeof(*plane));
550 plane->sizeimage = szimage;
551 if (plane->bytesperline < bpl || plane->bytesperline > CEU_MAX_BPL)
552 plane->bytesperline = bpl;
556 * ceu_calc_plane_sizes() - Fill per-plane 'struct v4l2_plane_pix_format'
557 * information according to the currently configured
559 * @ceu_device: CEU device.
560 * @ceu_fmt: Active image format.
561 * @pix: Pixel format information (store line width and image sizes)
563 static void ceu_calc_plane_sizes(struct ceu_device *ceudev,
564 const struct ceu_fmt *ceu_fmt,
565 struct v4l2_pix_format_mplane *pix)
567 unsigned int bpl, szimage;
569 switch (pix->pixelformat) {
570 case V4L2_PIX_FMT_YUYV:
572 bpl = pix->width * ceu_fmt->bpp / 8;
573 szimage = pix->height * bpl;
574 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
577 case V4L2_PIX_FMT_NV12:
578 case V4L2_PIX_FMT_NV21:
581 szimage = pix->height * pix->width;
582 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
583 ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage / 2);
586 case V4L2_PIX_FMT_NV16:
587 case V4L2_PIX_FMT_NV61:
591 szimage = pix->height * pix->width;
592 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
593 ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage);
599 * ceu_vb2_setup() - is called to check whether the driver can accept the
600 * requested number of buffers and to fill in plane sizes
601 * for the current frame format, if required.
603 static int ceu_vb2_setup(struct vb2_queue *vq, unsigned int *count,
604 unsigned int *num_planes, unsigned int sizes[],
605 struct device *alloc_devs[])
607 struct ceu_device *ceudev = vb2_get_drv_priv(vq);
608 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
611 /* num_planes is set: just check plane sizes. */
613 for (i = 0; i < pix->num_planes; i++)
614 if (sizes[i] < pix->plane_fmt[i].sizeimage)
620 /* num_planes not set: called from REQBUFS, just set plane sizes. */
621 *num_planes = pix->num_planes;
622 for (i = 0; i < pix->num_planes; i++)
623 sizes[i] = pix->plane_fmt[i].sizeimage;
628 static void ceu_vb2_queue(struct vb2_buffer *vb)
630 struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue);
631 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
632 struct ceu_buffer *buf = vb2_to_ceu(vbuf);
633 unsigned long irqflags;
635 spin_lock_irqsave(&ceudev->lock, irqflags);
636 list_add_tail(&buf->queue, &ceudev->capture);
637 spin_unlock_irqrestore(&ceudev->lock, irqflags);
640 static int ceu_vb2_prepare(struct vb2_buffer *vb)
642 struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue);
643 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
646 for (i = 0; i < pix->num_planes; i++) {
647 if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) {
649 "Plane size too small (%lu < %u)\n",
650 vb2_plane_size(vb, i),
651 pix->plane_fmt[i].sizeimage);
655 vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage);
661 static int ceu_start_streaming(struct vb2_queue *vq, unsigned int count)
663 struct ceu_device *ceudev = vb2_get_drv_priv(vq);
664 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
665 struct ceu_buffer *buf;
666 unsigned long irqflags;
669 /* Program the CEU interface according to the CEU image format. */
670 ret = ceu_hw_config(ceudev);
672 goto error_return_bufs;
674 ret = v4l2_subdev_call(v4l2_sd, video, s_stream, 1);
675 if (ret && ret != -ENOIOCTLCMD) {
677 "Subdevice failed to start streaming: %d\n", ret);
678 goto error_return_bufs;
681 spin_lock_irqsave(&ceudev->lock, irqflags);
682 ceudev->sequence = 0;
684 /* Grab the first available buffer and trigger the first capture. */
685 buf = list_first_entry(&ceudev->capture, struct ceu_buffer,
688 spin_unlock_irqrestore(&ceudev->lock, irqflags);
690 "No buffer available for capture.\n");
691 goto error_stop_sensor;
694 list_del(&buf->queue);
695 ceudev->active = &buf->vb;
697 /* Clean and program interrupts for first capture. */
698 ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask);
699 ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK);
703 spin_unlock_irqrestore(&ceudev->lock, irqflags);
708 v4l2_subdev_call(v4l2_sd, video, s_stream, 0);
711 spin_lock_irqsave(&ceudev->lock, irqflags);
712 list_for_each_entry(buf, &ceudev->capture, queue)
713 vb2_buffer_done(&ceudev->active->vb2_buf,
714 VB2_BUF_STATE_QUEUED);
715 ceudev->active = NULL;
716 spin_unlock_irqrestore(&ceudev->lock, irqflags);
721 static void ceu_stop_streaming(struct vb2_queue *vq)
723 struct ceu_device *ceudev = vb2_get_drv_priv(vq);
724 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
725 struct ceu_buffer *buf;
726 unsigned long irqflags;
728 /* Clean and disable interrupt sources. */
729 ceu_write(ceudev, CEU_CETCR,
730 ceu_read(ceudev, CEU_CETCR) & ceudev->irq_mask);
731 ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK);
733 v4l2_subdev_call(v4l2_sd, video, s_stream, 0);
735 spin_lock_irqsave(&ceudev->lock, irqflags);
736 if (ceudev->active) {
737 vb2_buffer_done(&ceudev->active->vb2_buf,
738 VB2_BUF_STATE_ERROR);
739 ceudev->active = NULL;
742 /* Release all queued buffers. */
743 list_for_each_entry(buf, &ceudev->capture, queue)
744 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
745 INIT_LIST_HEAD(&ceudev->capture);
747 spin_unlock_irqrestore(&ceudev->lock, irqflags);
749 ceu_soft_reset(ceudev);
752 static const struct vb2_ops ceu_vb2_ops = {
753 .queue_setup = ceu_vb2_setup,
754 .buf_queue = ceu_vb2_queue,
755 .buf_prepare = ceu_vb2_prepare,
756 .wait_prepare = vb2_ops_wait_prepare,
757 .wait_finish = vb2_ops_wait_finish,
758 .start_streaming = ceu_start_streaming,
759 .stop_streaming = ceu_stop_streaming,
762 /* --- CEU image formats handling --- */
765 * ceu_try_fmt() - test format on CEU and sensor
766 * @ceudev: The CEU device.
767 * @v4l2_fmt: format to test.
769 * Returns 0 for success, < 0 for errors.
771 static int ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
773 struct ceu_subdev *ceu_sd = ceudev->sd;
774 struct v4l2_pix_format_mplane *pix = &v4l2_fmt->fmt.pix_mp;
775 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
776 struct v4l2_subdev_pad_config pad_cfg;
777 const struct ceu_fmt *ceu_fmt;
781 * Set format on sensor sub device: bus format used to produce memory
782 * format is selected at initialization time.
784 struct v4l2_subdev_format sd_format = {
785 .which = V4L2_SUBDEV_FORMAT_TRY,
787 .code = ceu_sd->mbus_fmt.mbus_code,
791 switch (pix->pixelformat) {
792 case V4L2_PIX_FMT_YUYV:
793 case V4L2_PIX_FMT_NV16:
794 case V4L2_PIX_FMT_NV61:
795 case V4L2_PIX_FMT_NV12:
796 case V4L2_PIX_FMT_NV21:
800 pix->pixelformat = V4L2_PIX_FMT_NV16;
804 ceu_fmt = get_ceu_fmt_from_fourcc(pix->pixelformat);
806 /* CFSZR requires height and width to be 4-pixel aligned. */
807 v4l_bound_align_image(&pix->width, 2, CEU_MAX_WIDTH, 4,
808 &pix->height, 4, CEU_MAX_HEIGHT, 4, 0);
810 v4l2_fill_mbus_format_mplane(&sd_format.format, pix);
811 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, &pad_cfg, &sd_format);
815 /* Apply size returned by sensor as the CEU can't scale. */
816 v4l2_fill_pix_format_mplane(pix, &sd_format.format);
818 /* Calculate per-plane sizes based on image format. */
819 ceu_calc_plane_sizes(ceudev, ceu_fmt, pix);
825 * ceu_set_fmt() - Apply the supplied format to both sensor and CEU
827 static int ceu_set_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
829 struct ceu_subdev *ceu_sd = ceudev->sd;
830 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
834 * Set format on sensor sub device: bus format used to produce memory
835 * format is selected at initialization time.
837 struct v4l2_subdev_format format = {
838 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
840 .code = ceu_sd->mbus_fmt.mbus_code,
844 ret = ceu_try_fmt(ceudev, v4l2_fmt);
848 v4l2_fill_mbus_format_mplane(&format.format, &v4l2_fmt->fmt.pix_mp);
849 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, NULL, &format);
853 ceudev->v4l2_pix = v4l2_fmt->fmt.pix_mp;
854 ceudev->field = V4L2_FIELD_NONE;
860 * ceu_set_default_fmt() - Apply default NV16 memory output format with VGA
863 static int ceu_set_default_fmt(struct ceu_device *ceudev)
867 struct v4l2_format v4l2_fmt = {
868 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
871 .height = VGA_HEIGHT,
872 .field = V4L2_FIELD_NONE,
873 .pixelformat = V4L2_PIX_FMT_NV16,
877 .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2,
878 .bytesperline = VGA_WIDTH * 2,
881 .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2,
882 .bytesperline = VGA_WIDTH * 2,
888 ret = ceu_try_fmt(ceudev, &v4l2_fmt);
892 ceudev->v4l2_pix = v4l2_fmt.fmt.pix_mp;
893 ceudev->field = V4L2_FIELD_NONE;
899 * ceu_init_mbus_fmt() - Query sensor for supported formats and initialize
900 * CEU media bus format used to produce memory formats.
902 * Find out if sensor can produce a permutation of 8-bits YUYV bus format.
903 * From a single 8-bits YUYV bus format the CEU can produce several memory
905 * - NV[12|21|16|61] through image fetch mode;
906 * - YUYV422 if sensor provides YUYV422
908 * TODO: Other YUYV422 permutations through data fetch sync mode and DTARY
909 * TODO: Binary data (eg. JPEG) and raw formats through data fetch sync mode
911 static int ceu_init_mbus_fmt(struct ceu_device *ceudev)
913 struct ceu_subdev *ceu_sd = ceudev->sd;
914 struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt;
915 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
916 bool yuyv_bus_fmt = false;
918 struct v4l2_subdev_mbus_code_enum sd_mbus_fmt = {
919 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
923 /* Find out if sensor can produce any permutation of 8-bits YUYV422. */
924 while (!yuyv_bus_fmt &&
925 !v4l2_subdev_call(v4l2_sd, pad, enum_mbus_code,
926 NULL, &sd_mbus_fmt)) {
927 switch (sd_mbus_fmt.code) {
928 case MEDIA_BUS_FMT_YUYV8_2X8:
929 case MEDIA_BUS_FMT_YVYU8_2X8:
930 case MEDIA_BUS_FMT_UYVY8_2X8:
931 case MEDIA_BUS_FMT_VYUY8_2X8:
936 * Only support 8-bits YUYV bus formats at the moment;
938 * TODO: add support for binary formats (data sync
951 * Save the first encountered YUYV format as "mbus_fmt" and use it
952 * to output all planar YUV422 and YUV420 (NV*) formats to memory as
953 * well as for data synch fetch mode (YUYV - YVYU etc. ).
955 mbus_fmt->mbus_code = sd_mbus_fmt.code;
958 /* Annotate the selected bus format components ordering. */
959 switch (sd_mbus_fmt.code) {
960 case MEDIA_BUS_FMT_YUYV8_2X8:
961 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_YUYV;
962 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_YVYU;
963 mbus_fmt->swapped = false;
967 case MEDIA_BUS_FMT_YVYU8_2X8:
968 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_YVYU;
969 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_YUYV;
970 mbus_fmt->swapped = true;
974 case MEDIA_BUS_FMT_UYVY8_2X8:
975 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_UYVY;
976 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_VYUY;
977 mbus_fmt->swapped = false;
981 case MEDIA_BUS_FMT_VYUY8_2X8:
982 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_VYUY;
983 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_UYVY;
984 mbus_fmt->swapped = true;
992 /* --- Runtime PM Handlers --- */
995 * ceu_runtime_resume() - soft-reset the interface and turn sensor power on.
997 static int __maybe_unused ceu_runtime_resume(struct device *dev)
999 struct ceu_device *ceudev = dev_get_drvdata(dev);
1000 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
1002 v4l2_subdev_call(v4l2_sd, core, s_power, 1);
1004 ceu_soft_reset(ceudev);
1010 * ceu_runtime_suspend() - disable capture and interrupts and soft-reset.
1011 * Turn sensor power off.
1013 static int __maybe_unused ceu_runtime_suspend(struct device *dev)
1015 struct ceu_device *ceudev = dev_get_drvdata(dev);
1016 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
1018 v4l2_subdev_call(v4l2_sd, core, s_power, 0);
1020 ceu_write(ceudev, CEU_CEIER, 0);
1021 ceu_soft_reset(ceudev);
1026 /* --- File Operations --- */
1028 static int ceu_open(struct file *file)
1030 struct ceu_device *ceudev = video_drvdata(file);
1033 ret = v4l2_fh_open(file);
1037 mutex_lock(&ceudev->mlock);
1038 /* Causes soft-reset and sensor power on on first open */
1039 pm_runtime_get_sync(ceudev->dev);
1040 mutex_unlock(&ceudev->mlock);
1045 static int ceu_release(struct file *file)
1047 struct ceu_device *ceudev = video_drvdata(file);
1049 vb2_fop_release(file);
1051 mutex_lock(&ceudev->mlock);
1052 /* Causes soft-reset and sensor power down on last close */
1053 pm_runtime_put(ceudev->dev);
1054 mutex_unlock(&ceudev->mlock);
1059 static const struct v4l2_file_operations ceu_fops = {
1060 .owner = THIS_MODULE,
1062 .release = ceu_release,
1063 .unlocked_ioctl = video_ioctl2,
1064 .mmap = vb2_fop_mmap,
1065 .poll = vb2_fop_poll,
1068 /* --- Video Device IOCTLs --- */
1070 static int ceu_querycap(struct file *file, void *priv,
1071 struct v4l2_capability *cap)
1073 struct ceu_device *ceudev = video_drvdata(file);
1075 strlcpy(cap->card, "Renesas CEU", sizeof(cap->card));
1076 strlcpy(cap->driver, DRIVER_NAME, sizeof(cap->driver));
1077 snprintf(cap->bus_info, sizeof(cap->bus_info),
1078 "platform:renesas-ceu-%s", dev_name(ceudev->dev));
1083 static int ceu_enum_fmt_vid_cap(struct file *file, void *priv,
1084 struct v4l2_fmtdesc *f)
1086 const struct ceu_fmt *fmt;
1088 if (f->index >= ARRAY_SIZE(ceu_fmt_list))
1091 fmt = &ceu_fmt_list[f->index];
1092 f->pixelformat = fmt->fourcc;
1097 static int ceu_try_fmt_vid_cap(struct file *file, void *priv,
1098 struct v4l2_format *f)
1100 struct ceu_device *ceudev = video_drvdata(file);
1102 return ceu_try_fmt(ceudev, f);
1105 static int ceu_s_fmt_vid_cap(struct file *file, void *priv,
1106 struct v4l2_format *f)
1108 struct ceu_device *ceudev = video_drvdata(file);
1110 if (vb2_is_streaming(&ceudev->vb2_vq))
1113 return ceu_set_fmt(ceudev, f);
1116 static int ceu_g_fmt_vid_cap(struct file *file, void *priv,
1117 struct v4l2_format *f)
1119 struct ceu_device *ceudev = video_drvdata(file);
1121 f->fmt.pix_mp = ceudev->v4l2_pix;
1126 static int ceu_enum_input(struct file *file, void *priv,
1127 struct v4l2_input *inp)
1129 struct ceu_device *ceudev = video_drvdata(file);
1130 struct ceu_subdev *ceusd;
1132 if (inp->index >= ceudev->num_sd)
1135 ceusd = &ceudev->subdevs[inp->index];
1137 inp->type = V4L2_INPUT_TYPE_CAMERA;
1139 snprintf(inp->name, sizeof(inp->name), "Camera%u: %s",
1140 inp->index, ceusd->v4l2_sd->name);
1145 static int ceu_g_input(struct file *file, void *priv, unsigned int *i)
1147 struct ceu_device *ceudev = video_drvdata(file);
1149 *i = ceudev->sd_index;
1154 static int ceu_s_input(struct file *file, void *priv, unsigned int i)
1156 struct ceu_device *ceudev = video_drvdata(file);
1157 struct ceu_subdev *ceu_sd_old;
1160 if (i >= ceudev->num_sd)
1163 if (vb2_is_streaming(&ceudev->vb2_vq))
1166 if (i == ceudev->sd_index)
1169 ceu_sd_old = ceudev->sd;
1170 ceudev->sd = &ceudev->subdevs[i];
1173 * Make sure we can generate output image formats and apply
1176 ret = ceu_init_mbus_fmt(ceudev);
1178 ceudev->sd = ceu_sd_old;
1182 ret = ceu_set_default_fmt(ceudev);
1184 ceudev->sd = ceu_sd_old;
1188 /* Now that we're sure we can use the sensor, power off the old one. */
1189 v4l2_subdev_call(ceu_sd_old->v4l2_sd, core, s_power, 0);
1190 v4l2_subdev_call(ceudev->sd->v4l2_sd, core, s_power, 1);
1192 ceudev->sd_index = i;
1197 static int ceu_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1199 struct ceu_device *ceudev = video_drvdata(file);
1201 return v4l2_g_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a);
1204 static int ceu_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1206 struct ceu_device *ceudev = video_drvdata(file);
1208 return v4l2_s_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a);
1211 static int ceu_enum_framesizes(struct file *file, void *fh,
1212 struct v4l2_frmsizeenum *fsize)
1214 struct ceu_device *ceudev = video_drvdata(file);
1215 struct ceu_subdev *ceu_sd = ceudev->sd;
1216 const struct ceu_fmt *ceu_fmt;
1217 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
1220 struct v4l2_subdev_frame_size_enum fse = {
1221 .code = ceu_sd->mbus_fmt.mbus_code,
1222 .index = fsize->index,
1223 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1226 /* Just check if user supplied pixel format is supported. */
1227 ceu_fmt = get_ceu_fmt_from_fourcc(fsize->pixel_format);
1231 ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_size,
1236 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1237 fsize->discrete.width = CEU_W_MAX(fse.max_width);
1238 fsize->discrete.height = CEU_H_MAX(fse.max_height);
1243 static int ceu_enum_frameintervals(struct file *file, void *fh,
1244 struct v4l2_frmivalenum *fival)
1246 struct ceu_device *ceudev = video_drvdata(file);
1247 struct ceu_subdev *ceu_sd = ceudev->sd;
1248 const struct ceu_fmt *ceu_fmt;
1249 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
1252 struct v4l2_subdev_frame_interval_enum fie = {
1253 .code = ceu_sd->mbus_fmt.mbus_code,
1254 .index = fival->index,
1255 .width = fival->width,
1256 .height = fival->height,
1257 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1260 /* Just check if user supplied pixel format is supported. */
1261 ceu_fmt = get_ceu_fmt_from_fourcc(fival->pixel_format);
1265 ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_interval, NULL,
1270 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1271 fival->discrete = fie.interval;
1276 static const struct v4l2_ioctl_ops ceu_ioctl_ops = {
1277 .vidioc_querycap = ceu_querycap,
1279 .vidioc_enum_fmt_vid_cap_mplane = ceu_enum_fmt_vid_cap,
1280 .vidioc_try_fmt_vid_cap_mplane = ceu_try_fmt_vid_cap,
1281 .vidioc_s_fmt_vid_cap_mplane = ceu_s_fmt_vid_cap,
1282 .vidioc_g_fmt_vid_cap_mplane = ceu_g_fmt_vid_cap,
1284 .vidioc_enum_input = ceu_enum_input,
1285 .vidioc_g_input = ceu_g_input,
1286 .vidioc_s_input = ceu_s_input,
1288 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1289 .vidioc_querybuf = vb2_ioctl_querybuf,
1290 .vidioc_qbuf = vb2_ioctl_qbuf,
1291 .vidioc_expbuf = vb2_ioctl_expbuf,
1292 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1293 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1294 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1295 .vidioc_streamon = vb2_ioctl_streamon,
1296 .vidioc_streamoff = vb2_ioctl_streamoff,
1298 .vidioc_g_parm = ceu_g_parm,
1299 .vidioc_s_parm = ceu_s_parm,
1300 .vidioc_enum_framesizes = ceu_enum_framesizes,
1301 .vidioc_enum_frameintervals = ceu_enum_frameintervals,
1303 .vidioc_log_status = v4l2_ctrl_log_status,
1304 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1305 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1309 * ceu_vdev_release() - release CEU video device memory when last reference
1310 * to this driver is closed
1312 static void ceu_vdev_release(struct video_device *vdev)
1314 struct ceu_device *ceudev = video_get_drvdata(vdev);
1319 static int ceu_notify_bound(struct v4l2_async_notifier *notifier,
1320 struct v4l2_subdev *v4l2_sd,
1321 struct v4l2_async_subdev *asd)
1323 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
1324 struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev);
1325 struct ceu_subdev *ceu_sd = to_ceu_subdev(asd);
1327 ceu_sd->v4l2_sd = v4l2_sd;
1333 static int ceu_notify_complete(struct v4l2_async_notifier *notifier)
1335 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
1336 struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev);
1337 struct video_device *vdev = &ceudev->vdev;
1338 struct vb2_queue *q = &ceudev->vb2_vq;
1339 struct v4l2_subdev *v4l2_sd;
1342 /* Initialize vb2 queue. */
1343 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1344 q->io_modes = VB2_MMAP | VB2_DMABUF;
1345 q->drv_priv = ceudev;
1346 q->ops = &ceu_vb2_ops;
1347 q->mem_ops = &vb2_dma_contig_memops;
1348 q->buf_struct_size = sizeof(struct ceu_buffer);
1349 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1350 q->min_buffers_needed = 2;
1351 q->lock = &ceudev->mlock;
1352 q->dev = ceudev->v4l2_dev.dev;
1354 ret = vb2_queue_init(q);
1359 * Make sure at least one sensor is primary and use it to initialize
1363 ceudev->sd = &ceudev->subdevs[0];
1364 ceudev->sd_index = 0;
1367 v4l2_sd = ceudev->sd->v4l2_sd;
1369 ret = ceu_init_mbus_fmt(ceudev);
1373 ret = ceu_set_default_fmt(ceudev);
1377 /* Register the video device. */
1378 strlcpy(vdev->name, DRIVER_NAME, sizeof(vdev->name));
1379 vdev->v4l2_dev = v4l2_dev;
1380 vdev->lock = &ceudev->mlock;
1381 vdev->queue = &ceudev->vb2_vq;
1382 vdev->ctrl_handler = v4l2_sd->ctrl_handler;
1383 vdev->fops = &ceu_fops;
1384 vdev->ioctl_ops = &ceu_ioctl_ops;
1385 vdev->release = ceu_vdev_release;
1386 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
1388 video_set_drvdata(vdev, ceudev);
1390 ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
1392 v4l2_err(vdev->v4l2_dev,
1393 "video_register_device failed: %d\n", ret);
1400 static const struct v4l2_async_notifier_operations ceu_notify_ops = {
1401 .bound = ceu_notify_bound,
1402 .complete = ceu_notify_complete,
1406 * ceu_init_async_subdevs() - Initialize CEU subdevices and async_subdevs in
1407 * ceu device. Both DT and platform data parsing use
1410 * Returns 0 for success, -ENOMEM for failure.
1412 static int ceu_init_async_subdevs(struct ceu_device *ceudev, unsigned int n_sd)
1414 /* Reserve memory for 'n_sd' ceu_subdev descriptors. */
1415 ceudev->subdevs = devm_kcalloc(ceudev->dev, n_sd,
1416 sizeof(*ceudev->subdevs), GFP_KERNEL);
1417 if (!ceudev->subdevs)
1421 * Reserve memory for 'n_sd' pointers to async_subdevices.
1422 * ceudev->asds members will point to &ceu_subdev.asd
1424 ceudev->asds = devm_kcalloc(ceudev->dev, n_sd,
1425 sizeof(*ceudev->asds), GFP_KERNEL);
1430 ceudev->sd_index = 0;
1437 * ceu_parse_platform_data() - Initialize async_subdevices using platform
1438 * device provided data.
1440 static int ceu_parse_platform_data(struct ceu_device *ceudev,
1441 const struct ceu_platform_data *pdata)
1443 const struct ceu_async_subdev *async_sd;
1444 struct ceu_subdev *ceu_sd;
1448 if (pdata->num_subdevs == 0)
1451 ret = ceu_init_async_subdevs(ceudev, pdata->num_subdevs);
1455 for (i = 0; i < pdata->num_subdevs; i++) {
1456 /* Setup the ceu subdevice and the async subdevice. */
1457 async_sd = &pdata->subdevs[i];
1458 ceu_sd = &ceudev->subdevs[i];
1460 INIT_LIST_HEAD(&ceu_sd->asd.list);
1462 ceu_sd->mbus_flags = async_sd->flags;
1463 ceu_sd->asd.match_type = V4L2_ASYNC_MATCH_I2C;
1464 ceu_sd->asd.match.i2c.adapter_id = async_sd->i2c_adapter_id;
1465 ceu_sd->asd.match.i2c.address = async_sd->i2c_address;
1467 ceudev->asds[i] = &ceu_sd->asd;
1470 return pdata->num_subdevs;
1474 * ceu_parse_dt() - Initialize async_subdevs parsing device tree graph.
1476 static int ceu_parse_dt(struct ceu_device *ceudev)
1478 struct device_node *of = ceudev->dev->of_node;
1479 struct v4l2_fwnode_endpoint fw_ep;
1480 struct ceu_subdev *ceu_sd;
1481 struct device_node *ep;
1486 num_ep = of_graph_get_endpoint_count(of);
1490 ret = ceu_init_async_subdevs(ceudev, num_ep);
1494 for (i = 0; i < num_ep; i++) {
1495 ep = of_graph_get_endpoint_by_regs(of, 0, i);
1497 dev_err(ceudev->dev,
1498 "No subdevice connected on endpoint %u.\n", i);
1500 goto error_put_node;
1503 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &fw_ep);
1505 dev_err(ceudev->dev,
1506 "Unable to parse endpoint #%u.\n", i);
1507 goto error_put_node;
1510 if (fw_ep.bus_type != V4L2_MBUS_PARALLEL) {
1511 dev_err(ceudev->dev,
1512 "Only parallel input supported.\n");
1514 goto error_put_node;
1517 /* Setup the ceu subdevice and the async subdevice. */
1518 ceu_sd = &ceudev->subdevs[i];
1519 INIT_LIST_HEAD(&ceu_sd->asd.list);
1521 ceu_sd->mbus_flags = fw_ep.bus.parallel.flags;
1522 ceu_sd->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
1523 ceu_sd->asd.match.fwnode =
1524 fwnode_graph_get_remote_port_parent(
1525 of_fwnode_handle(ep));
1527 ceudev->asds[i] = &ceu_sd->asd;
1539 * struct ceu_data - Platform specific CEU data
1540 * @irq_mask: CETCR mask with all interrupt sources enabled. The mask differs
1541 * between SH4 and RZ platforms.
1547 static const struct ceu_data ceu_data_rz = {
1548 .irq_mask = CEU_CETCR_ALL_IRQS_RZ,
1551 static const struct ceu_data ceu_data_sh4 = {
1552 .irq_mask = CEU_CETCR_ALL_IRQS_SH4,
1555 #if IS_ENABLED(CONFIG_OF)
1556 static const struct of_device_id ceu_of_match[] = {
1557 { .compatible = "renesas,r7s72100-ceu", .data = &ceu_data_rz },
1558 { .compatible = "renesas,r8a7740-ceu", .data = &ceu_data_rz },
1561 MODULE_DEVICE_TABLE(of, ceu_of_match);
1564 static int ceu_probe(struct platform_device *pdev)
1566 struct device *dev = &pdev->dev;
1567 const struct ceu_data *ceu_data;
1568 struct ceu_device *ceudev;
1569 struct resource *res;
1574 ceudev = kzalloc(sizeof(*ceudev), GFP_KERNEL);
1578 platform_set_drvdata(pdev, ceudev);
1581 INIT_LIST_HEAD(&ceudev->capture);
1582 spin_lock_init(&ceudev->lock);
1583 mutex_init(&ceudev->mlock);
1585 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1586 ceudev->base = devm_ioremap_resource(dev, res);
1587 if (IS_ERR(ceudev->base)) {
1588 ret = PTR_ERR(ceudev->base);
1589 goto error_free_ceudev;
1592 ret = platform_get_irq(pdev, 0);
1594 dev_err(dev, "Failed to get irq: %d\n", ret);
1595 goto error_free_ceudev;
1599 ret = devm_request_irq(dev, irq, ceu_irq,
1600 0, dev_name(dev), ceudev);
1602 dev_err(&pdev->dev, "Unable to request CEU interrupt.\n");
1603 goto error_free_ceudev;
1606 pm_runtime_enable(dev);
1608 ret = v4l2_device_register(dev, &ceudev->v4l2_dev);
1610 goto error_pm_disable;
1612 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
1613 ceu_data = of_match_device(ceu_of_match, dev)->data;
1614 num_subdevs = ceu_parse_dt(ceudev);
1615 } else if (dev->platform_data) {
1616 /* Assume SH4 if booting with platform data. */
1617 ceu_data = &ceu_data_sh4;
1618 num_subdevs = ceu_parse_platform_data(ceudev,
1619 dev->platform_data);
1621 num_subdevs = -EINVAL;
1624 if (num_subdevs < 0) {
1626 goto error_v4l2_unregister;
1628 ceudev->irq_mask = ceu_data->irq_mask;
1630 ceudev->notifier.v4l2_dev = &ceudev->v4l2_dev;
1631 ceudev->notifier.subdevs = ceudev->asds;
1632 ceudev->notifier.num_subdevs = num_subdevs;
1633 ceudev->notifier.ops = &ceu_notify_ops;
1634 ret = v4l2_async_notifier_register(&ceudev->v4l2_dev,
1637 goto error_v4l2_unregister;
1639 dev_info(dev, "Renesas Capture Engine Unit %s\n", dev_name(dev));
1643 error_v4l2_unregister:
1644 v4l2_device_unregister(&ceudev->v4l2_dev);
1646 pm_runtime_disable(dev);
1653 static int ceu_remove(struct platform_device *pdev)
1655 struct ceu_device *ceudev = platform_get_drvdata(pdev);
1657 pm_runtime_disable(ceudev->dev);
1659 v4l2_async_notifier_unregister(&ceudev->notifier);
1661 v4l2_device_unregister(&ceudev->v4l2_dev);
1663 video_unregister_device(&ceudev->vdev);
1668 static const struct dev_pm_ops ceu_pm_ops = {
1669 SET_RUNTIME_PM_OPS(ceu_runtime_suspend,
1674 static struct platform_driver ceu_driver = {
1676 .name = DRIVER_NAME,
1678 .of_match_table = of_match_ptr(ceu_of_match),
1681 .remove = ceu_remove,
1684 module_platform_driver(ceu_driver);
1686 MODULE_DESCRIPTION("Renesas CEU camera driver");
1687 MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org>");
1688 MODULE_LICENSE("GPL v2");