drivers/media/platform/rcar-vin/rcar-dma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Renesas R-Car VIN
   4  *
   5  * Copyright (C) 2016 Renesas Electronics Corp.
   6  * Copyright (C) 2011-2013 Renesas Solutions Corp.
   7  * Copyright (C) 2013 Cogent Embedded, Inc., <source@cogentembedded.com>
   8  * Copyright (C) 2008 Magnus Damm
   9  *
  10  * Based on the soc-camera rcar_vin driver
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/pm_runtime.h>
  16
  17 #include <media/videobuf2-dma-contig.h>
  18
  19 #include "rcar-vin.h"
  20
  21 /* -----------------------------------------------------------------------------
  22  * HW Functions
  23  */
  24
  25 /* Register offsets for R-Car VIN */
  26 #define VNMC_REG        0x00    /* Video n Main Control Register */
  27 #define VNMS_REG        0x04    /* Video n Module Status Register */
  28 #define VNFC_REG        0x08    /* Video n Frame Capture Register */
  29 #define VNSLPRC_REG     0x0C    /* Video n Start Line Pre-Clip Register */
  30 #define VNELPRC_REG     0x10    /* Video n End Line Pre-Clip Register */
  31 #define VNSPPRC_REG     0x14    /* Video n Start Pixel Pre-Clip Register */
  32 #define VNEPPRC_REG     0x18    /* Video n End Pixel Pre-Clip Register */
  33 #define VNIS_REG        0x2C    /* Video n Image Stride Register */
  34 #define VNMB_REG(m)     (0x30 + ((m) << 2)) /* Video n Memory Base m Register */
  35 #define VNIE_REG        0x40    /* Video n Interrupt Enable Register */
  36 #define VNINTS_REG      0x44    /* Video n Interrupt Status Register */
  37 #define VNSI_REG        0x48    /* Video n Scanline Interrupt Register */
  38 #define VNMTC_REG       0x4C    /* Video n Memory Transfer Control Register */
  39 #define VNDMR_REG       0x58    /* Video n Data Mode Register */
  40 #define VNDMR2_REG      0x5C    /* Video n Data Mode Register 2 */
  41 #define VNUVAOF_REG     0x60    /* Video n UV Address Offset Register */
  42
  43 /* Register offsets specific for Gen2 */
  44 #define VNSLPOC_REG     0x1C    /* Video n Start Line Post-Clip Register */
  45 #define VNELPOC_REG     0x20    /* Video n End Line Post-Clip Register */
  46 #define VNSPPOC_REG     0x24    /* Video n Start Pixel Post-Clip Register */
  47 #define VNEPPOC_REG     0x28    /* Video n End Pixel Post-Clip Register */
  48 #define VNYS_REG        0x50    /* Video n Y Scale Register */
  49 #define VNXS_REG        0x54    /* Video n X Scale Register */
  50 #define VNC1A_REG       0x80    /* Video n Coefficient Set C1A Register */
  51 #define VNC1B_REG       0x84    /* Video n Coefficient Set C1B Register */
  52 #define VNC1C_REG       0x88    /* Video n Coefficient Set C1C Register */
  53 #define VNC2A_REG       0x90    /* Video n Coefficient Set C2A Register */
  54 #define VNC2B_REG       0x94    /* Video n Coefficient Set C2B Register */
  55 #define VNC2C_REG       0x98    /* Video n Coefficient Set C2C Register */
  56 #define VNC3A_REG       0xA0    /* Video n Coefficient Set C3A Register */
  57 #define VNC3B_REG       0xA4    /* Video n Coefficient Set C3B Register */
  58 #define VNC3C_REG       0xA8    /* Video n Coefficient Set C3C Register */
  59 #define VNC4A_REG       0xB0    /* Video n Coefficient Set C4A Register */
  60 #define VNC4B_REG       0xB4    /* Video n Coefficient Set C4B Register */
  61 #define VNC4C_REG       0xB8    /* Video n Coefficient Set C4C Register */
  62 #define VNC5A_REG       0xC0    /* Video n Coefficient Set C5A Register */
  63 #define VNC5B_REG       0xC4    /* Video n Coefficient Set C5B Register */
  64 #define VNC5C_REG       0xC8    /* Video n Coefficient Set C5C Register */
  65 #define VNC6A_REG       0xD0    /* Video n Coefficient Set C6A Register */
  66 #define VNC6B_REG       0xD4    /* Video n Coefficient Set C6B Register */
  67 #define VNC6C_REG       0xD8    /* Video n Coefficient Set C6C Register */
  68 #define VNC7A_REG       0xE0    /* Video n Coefficient Set C7A Register */
  69 #define VNC7B_REG       0xE4    /* Video n Coefficient Set C7B Register */
  70 #define VNC7C_REG       0xE8    /* Video n Coefficient Set C7C Register */
  71 #define VNC8A_REG       0xF0    /* Video n Coefficient Set C8A Register */
  72 #define VNC8B_REG       0xF4    /* Video n Coefficient Set C8B Register */
  73 #define VNC8C_REG       0xF8    /* Video n Coefficient Set C8C Register */
  74
  75 /* Register offsets specific for Gen3 */
  76 #define VNCSI_IFMD_REG          0x20 /* Video n CSI2 Interface Mode Register */
  77
  78 /* Register bit fields for R-Car VIN */
  79 /* Video n Main Control Register bits */
  80 #define VNMC_DPINE              (1 << 27) /* Gen3 specific */
  81 #define VNMC_SCLE               (1 << 26) /* Gen3 specific */
  82 #define VNMC_FOC                (1 << 21)
  83 #define VNMC_YCAL               (1 << 19)
  84 #define VNMC_INF_YUV8_BT656     (0 << 16)
  85 #define VNMC_INF_YUV8_BT601     (1 << 16)
  86 #define VNMC_INF_YUV10_BT656    (2 << 16)
  87 #define VNMC_INF_YUV10_BT601    (3 << 16)
  88 #define VNMC_INF_RAW8           (4 << 16)
  89 #define VNMC_INF_YUV16          (5 << 16)
  90 #define VNMC_INF_RGB888         (6 << 16)
  91 #define VNMC_VUP                (1 << 10)
  92 #define VNMC_IM_ODD             (0 << 3)
  93 #define VNMC_IM_ODD_EVEN        (1 << 3)
  94 #define VNMC_IM_EVEN            (2 << 3)
  95 #define VNMC_IM_FULL            (3 << 3)
  96 #define VNMC_BPS                (1 << 1)
  97 #define VNMC_ME                 (1 << 0)
  98
  99 /* Video n Module Status Register bits */
 100 #define VNMS_FBS_MASK           (3 << 3)
 101 #define VNMS_FBS_SHIFT          3
 102 #define VNMS_FS                 (1 << 2)
 103 #define VNMS_AV                 (1 << 1)
 104 #define VNMS_CA                 (1 << 0)
 105
 106 /* Video n Frame Capture Register bits */
 107 #define VNFC_C_FRAME            (1 << 1)
 108 #define VNFC_S_FRAME            (1 << 0)
 109
 110 /* Video n Interrupt Enable Register bits */
 111 #define VNIE_FIE                (1 << 4)
 112 #define VNIE_EFE                (1 << 1)
 113
 114 /* Video n Data Mode Register bits */
 115 #define VNDMR_A8BIT(n)          (((n) & 0xff) << 24)
 116 #define VNDMR_A8BIT_MASK        (0xff << 24)
 117 #define VNDMR_EXRGB             (1 << 8)
 118 #define VNDMR_BPSM              (1 << 4)
 119 #define VNDMR_ABIT              (1 << 2)
 120 #define VNDMR_DTMD_YCSEP        (1 << 1)
 121 #define VNDMR_DTMD_ARGB         (1 << 0)
 122 #define VNDMR_DTMD_YCSEP_420    (3 << 0)
 123
 124 /* Video n Data Mode Register 2 bits */
 125 #define VNDMR2_VPS              (1 << 30)
 126 #define VNDMR2_HPS              (1 << 29)
 127 #define VNDMR2_CES              (1 << 28)
 128 #define VNDMR2_YDS              (1 << 22)
 129 #define VNDMR2_FTEV             (1 << 17)
 130 #define VNDMR2_VLV(n)           ((n & 0xf) << 12)
 131
 132 /* Video n CSI2 Interface Mode Register (Gen3) */
 133 #define VNCSI_IFMD_DES1         (1 << 26)
 134 #define VNCSI_IFMD_DES0         (1 << 25)
 135 #define VNCSI_IFMD_CSI_CHSEL(n) (((n) & 0xf) << 0)
 136 #define VNCSI_IFMD_CSI_CHSEL_MASK 0xf
 137
 138 struct rvin_buffer {
 139         struct vb2_v4l2_buffer vb;
 140         struct list_head list;
 141 };
 142
 143 #define to_buf_list(vb2_buffer) (&container_of(vb2_buffer, \
 144                                                struct rvin_buffer, \
 145                                                vb)->list)
 146
 147 static void rvin_write(struct rvin_dev *vin, u32 value, u32 offset)
 148 {
 149         iowrite32(value, vin->base + offset);
 150 }
 151
 152 static u32 rvin_read(struct rvin_dev *vin, u32 offset)
 153 {
 154         return ioread32(vin->base + offset);
 155 }
 156
 157 /* -----------------------------------------------------------------------------
 158  * Crop and Scaling Gen2
 159  */
 160
 161 struct vin_coeff {
 162         unsigned short xs_value;
 163         u32 coeff_set[24];
 164 };
 165
 166 static const struct vin_coeff vin_coeff_set[] = {
 167         { 0x0000, {
 168                           0x00000000, 0x00000000, 0x00000000,
 169                           0x00000000, 0x00000000, 0x00000000,
 170                           0x00000000, 0x00000000, 0x00000000,
 171                           0x00000000, 0x00000000, 0x00000000,
 172                           0x00000000, 0x00000000, 0x00000000,
 173                           0x00000000, 0x00000000, 0x00000000,
 174                           0x00000000, 0x00000000, 0x00000000,
 175                           0x00000000, 0x00000000, 0x00000000 },
 176         },
 177         { 0x1000, {
 178                           0x000fa400, 0x000fa400, 0x09625902,
 179                           0x000003f8, 0x00000403, 0x3de0d9f0,
 180                           0x001fffed, 0x00000804, 0x3cc1f9c3,
 181                           0x001003de, 0x00000c01, 0x3cb34d7f,
 182                           0x002003d2, 0x00000c00, 0x3d24a92d,
 183                           0x00200bca, 0x00000bff, 0x3df600d2,
 184                           0x002013cc, 0x000007ff, 0x3ed70c7e,
 185                           0x00100fde, 0x00000000, 0x3f87c036 },
 186         },
 187         { 0x1200, {
 188                           0x002ffff1, 0x002ffff1, 0x02a0a9c8,
 189                           0x002003e7, 0x001ffffa, 0x000185bc,
 190                           0x002007dc, 0x000003ff, 0x3e52859c,
 191                           0x00200bd4, 0x00000002, 0x3d53996b,
 192                           0x00100fd0, 0x00000403, 0x3d04ad2d,
 193                           0x00000bd5, 0x00000403, 0x3d35ace7,
 194                           0x3ff003e4, 0x00000801, 0x3dc674a1,
 195                           0x3fffe800, 0x00000800, 0x3e76f461 },
 196         },
 197         { 0x1400, {
 198                           0x00100be3, 0x00100be3, 0x04d1359a,
 199                           0x00000fdb, 0x002003ed, 0x0211fd93,
 200                           0x00000fd6, 0x002003f4, 0x0002d97b,
 201                           0x000007d6, 0x002ffffb, 0x3e93b956,
 202                           0x3ff003da, 0x001003ff, 0x3db49926,
 203                           0x3fffefe9, 0x00100001, 0x3d655cee,
 204                           0x3fffd400, 0x00000003, 0x3d65f4b6,
 205                           0x000fb421, 0x00000402, 0x3dc6547e },
 206         },
 207         { 0x1600, {
 208                           0x00000bdd, 0x00000bdd, 0x06519578,
 209                           0x3ff007da, 0x00000be3, 0x03c24973,
 210                           0x3ff003d9, 0x00000be9, 0x01b30d5f,
 211                           0x3ffff7df, 0x001003f1, 0x0003c542,
 212                           0x000fdfec, 0x001003f7, 0x3ec4711d,
 213                           0x000fc400, 0x002ffffd, 0x3df504f1,
 214                           0x001fa81a, 0x002ffc00, 0x3d957cc2,
 215                           0x002f8c3c, 0x00100000, 0x3db5c891 },
 216         },
 217         { 0x1800, {
 218                           0x3ff003dc, 0x3ff003dc, 0x0791e558,
 219                           0x000ff7dd, 0x3ff007de, 0x05328554,
 220                           0x000fe7e3, 0x3ff00be2, 0x03232546,
 221                           0x000fd7ee, 0x000007e9, 0x0143bd30,
 222                           0x001fb800, 0x000007ee, 0x00044511,
 223                           0x002fa015, 0x000007f4, 0x3ef4bcee,
 224                           0x002f8832, 0x001003f9, 0x3e4514c7,
 225                           0x001f7853, 0x001003fd, 0x3de54c9f },
 226         },
 227         { 0x1a00, {
 228                           0x000fefe0, 0x000fefe0, 0x08721d3c,
 229                           0x001fdbe7, 0x000ffbde, 0x0652a139,
 230                           0x001fcbf0, 0x000003df, 0x0463292e,
 231                           0x002fb3ff, 0x3ff007e3, 0x0293a91d,
 232                           0x002f9c12, 0x3ff00be7, 0x01241905,
 233                           0x001f8c29, 0x000007ed, 0x3fe470eb,
 234                           0x000f7c46, 0x000007f2, 0x3f04b8ca,
 235                           0x3fef7865, 0x000007f6, 0x3e74e4a8 },
 236         },
 237         { 0x1c00, {
 238                           0x001fd3e9, 0x001fd3e9, 0x08f23d26,
 239                           0x002fbff3, 0x001fe3e4, 0x0712ad23,
 240                           0x002fa800, 0x000ff3e0, 0x05631d1b,
 241                           0x001f9810, 0x000ffbe1, 0x03b3890d,
 242                           0x000f8c23, 0x000003e3, 0x0233e8fa,
 243                           0x3fef843b, 0x000003e7, 0x00f430e4,
 244                           0x3fbf8456, 0x3ff00bea, 0x00046cc8,
 245                           0x3f8f8c72, 0x3ff00bef, 0x3f3490ac },
 246         },
 247         { 0x1e00, {
 248                           0x001fbbf4, 0x001fbbf4, 0x09425112,
 249                           0x001fa800, 0x002fc7ed, 0x0792b110,
 250                           0x000f980e, 0x001fdbe6, 0x0613110a,
 251                           0x3fff8c20, 0x001fe7e3, 0x04a368fd,
 252                           0x3fcf8c33, 0x000ff7e2, 0x0343b8ed,
 253                           0x3f9f8c4a, 0x000fffe3, 0x0203f8da,
 254                           0x3f5f9c61, 0x000003e6, 0x00e428c5,
 255                           0x3f1fb07b, 0x000003eb, 0x3fe440af },
 256         },
 257         { 0x2000, {
 258                           0x000fa400, 0x000fa400, 0x09625902,
 259                           0x3fff980c, 0x001fb7f5, 0x0812b0ff,
 260                           0x3fdf901c, 0x001fc7ed, 0x06b2fcfa,
 261                           0x3faf902d, 0x001fd3e8, 0x055348f1,
 262                           0x3f7f983f, 0x001fe3e5, 0x04038ce3,
 263                           0x3f3fa454, 0x001fefe3, 0x02e3c8d1,
 264                           0x3f0fb86a, 0x001ff7e4, 0x01c3e8c0,
 265                           0x3ecfd880, 0x000fffe6, 0x00c404ac },
 266         },
 267         { 0x2200, {
 268                           0x3fdf9c0b, 0x3fdf9c0b, 0x09725cf4,
 269                           0x3fbf9818, 0x3fffa400, 0x0842a8f1,
 270                           0x3f8f9827, 0x000fb3f7, 0x0702f0ec,
 271                           0x3f5fa037, 0x000fc3ef, 0x05d330e4,
 272                           0x3f2fac49, 0x001fcfea, 0x04a364d9,
 273                           0x3effc05c, 0x001fdbe7, 0x038394ca,
 274                           0x3ecfdc6f, 0x001fe7e6, 0x0273b0bb,
 275                           0x3ea00083, 0x001fefe6, 0x0183c0a9 },
 276         },
 277         { 0x2400, {
 278                           0x3f9fa014, 0x3f9fa014, 0x098260e6,
 279                           0x3f7f9c23, 0x3fcf9c0a, 0x08629ce5,
 280                           0x3f4fa431, 0x3fefa400, 0x0742d8e1,
 281                           0x3f1fb440, 0x3fffb3f8, 0x062310d9,
 282                           0x3eefc850, 0x000fbbf2, 0x050340d0,
 283                           0x3ecfe062, 0x000fcbec, 0x041364c2,
 284                           0x3ea00073, 0x001fd3ea, 0x03037cb5,
 285                           0x3e902086, 0x001fdfe8, 0x022388a5 },
 286         },
 287         { 0x2600, {
 288                           0x3f5fa81e, 0x3f5fa81e, 0x096258da,
 289                           0x3f3fac2b, 0x3f8fa412, 0x088290d8,
 290                           0x3f0fbc38, 0x3fafa408, 0x0772c8d5,
 291                           0x3eefcc47, 0x3fcfa800, 0x0672f4ce,
 292                           0x3ecfe456, 0x3fefaffa, 0x05531cc6,
 293                           0x3eb00066, 0x3fffbbf3, 0x047334bb,
 294                           0x3ea01c77, 0x000fc7ee, 0x039348ae,
 295                           0x3ea04486, 0x000fd3eb, 0x02b350a1 },
 296         },
 297         { 0x2800, {
 298                           0x3f2fb426, 0x3f2fb426, 0x094250ce,
 299                           0x3f0fc032, 0x3f4fac1b, 0x086284cd,
 300                           0x3eefd040, 0x3f7fa811, 0x0782acc9,
 301                           0x3ecfe84c, 0x3f9fa807, 0x06a2d8c4,
 302                           0x3eb0005b, 0x3fbfac00, 0x05b2f4bc,
 303                           0x3eb0186a, 0x3fdfb3fa, 0x04c308b4,
 304                           0x3eb04077, 0x3fefbbf4, 0x03f31ca8,
 305                           0x3ec06884, 0x000fbff2, 0x03031c9e },
 306         },
 307         { 0x2a00, {
 308                           0x3f0fc42d, 0x3f0fc42d, 0x090240c4,
 309                           0x3eefd439, 0x3f2fb822, 0x08526cc2,
 310                           0x3edfe845, 0x3f4fb018, 0x078294bf,
 311                           0x3ec00051, 0x3f6fac0f, 0x06b2b4bb,
 312                           0x3ec0185f, 0x3f8fac07, 0x05e2ccb4,
 313                           0x3ec0386b, 0x3fafac00, 0x0502e8ac,
 314                           0x3ed05c77, 0x3fcfb3fb, 0x0432f0a3,
 315                           0x3ef08482, 0x3fdfbbf6, 0x0372f898 },
 316         },
 317         { 0x2c00, {
 318                           0x3eefdc31, 0x3eefdc31, 0x08e238b8,
 319                           0x3edfec3d, 0x3f0fc828, 0x082258b9,
 320                           0x3ed00049, 0x3f1fc01e, 0x077278b6,
 321                           0x3ed01455, 0x3f3fb815, 0x06c294b2,
 322                           0x3ed03460, 0x3f5fb40d, 0x0602acac,
 323                           0x3ef0506c, 0x3f7fb006, 0x0542c0a4,
 324                           0x3f107476, 0x3f9fb400, 0x0472c89d,
 325                           0x3f309c80, 0x3fbfb7fc, 0x03b2cc94 },
 326         },
 327         { 0x2e00, {
 328                           0x3eefec37, 0x3eefec37, 0x088220b0,
 329                           0x3ee00041, 0x3effdc2d, 0x07f244ae,
 330                           0x3ee0144c, 0x3f0fd023, 0x07625cad,
 331                           0x3ef02c57, 0x3f1fc81a, 0x06c274a9,
 332                           0x3f004861, 0x3f3fbc13, 0x060288a6,
 333                           0x3f20686b, 0x3f5fb80c, 0x05529c9e,
 334                           0x3f408c74, 0x3f6fb805, 0x04b2ac96,
 335                           0x3f80ac7e, 0x3f8fb800, 0x0402ac8e },
 336         },
 337         { 0x3000, {
 338                           0x3ef0003a, 0x3ef0003a, 0x084210a6,
 339                           0x3ef01045, 0x3effec32, 0x07b228a7,
 340                           0x3f00284e, 0x3f0fdc29, 0x073244a4,
 341                           0x3f104058, 0x3f0fd420, 0x06a258a2,
 342                           0x3f305c62, 0x3f2fc818, 0x0612689d,
 343                           0x3f508069, 0x3f3fc011, 0x05728496,
 344                           0x3f80a072, 0x3f4fc00a, 0x04d28c90,
 345                           0x3fc0c07b, 0x3f6fbc04, 0x04429088 },
 346         },
 347         { 0x3200, {
 348                           0x3f00103e, 0x3f00103e, 0x07f1fc9e,
 349                           0x3f102447, 0x3f000035, 0x0782149d,
 350                           0x3f203c4f, 0x3f0ff02c, 0x07122c9c,
 351                           0x3f405458, 0x3f0fe424, 0x06924099,
 352                           0x3f607061, 0x3f1fd41d, 0x06024c97,
 353                           0x3f909068, 0x3f2fcc16, 0x05726490,
 354                           0x3fc0b070, 0x3f3fc80f, 0x04f26c8a,
 355                           0x0000d077, 0x3f4fc409, 0x04627484 },
 356         },
 357         { 0x3400, {
 358                           0x3f202040, 0x3f202040, 0x07a1e898,
 359                           0x3f303449, 0x3f100c38, 0x0741fc98,
 360                           0x3f504c50, 0x3f10002f, 0x06e21495,
 361                           0x3f706459, 0x3f1ff028, 0x06722492,
 362                           0x3fa08060, 0x3f1fe421, 0x05f2348f,
 363                           0x3fd09c67, 0x3f1fdc19, 0x05824c89,
 364                           0x0000bc6e, 0x3f2fd014, 0x04f25086,
 365                           0x0040dc74, 0x3f3fcc0d, 0x04825c7f },
 366         },
 367         { 0x3600, {
 368                           0x3f403042, 0x3f403042, 0x0761d890,
 369                           0x3f504848, 0x3f301c3b, 0x0701f090,
 370                           0x3f805c50, 0x3f200c33, 0x06a2008f,
 371                           0x3fa07458, 0x3f10002b, 0x06520c8d,
 372                           0x3fd0905e, 0x3f1ff424, 0x05e22089,
 373                           0x0000ac65, 0x3f1fe81d, 0x05823483,
 374                           0x0030cc6a, 0x3f2fdc18, 0x04f23c81,
 375                           0x0080e871, 0x3f2fd412, 0x0482407c },
 376         },
 377         { 0x3800, {
 378                           0x3f604043, 0x3f604043, 0x0721c88a,
 379                           0x3f80544a, 0x3f502c3c, 0x06d1d88a,
 380                           0x3fb06851, 0x3f301c35, 0x0681e889,
 381                           0x3fd08456, 0x3f30082f, 0x0611fc88,
 382                           0x00009c5d, 0x3f200027, 0x05d20884,
 383                           0x0030b863, 0x3f2ff421, 0x05621880,
 384                           0x0070d468, 0x3f2fe81b, 0x0502247c,
 385                           0x00c0ec6f, 0x3f2fe015, 0x04a22877 },
 386         },
 387         { 0x3a00, {
 388                           0x3f904c44, 0x3f904c44, 0x06e1b884,
 389                           0x3fb0604a, 0x3f70383e, 0x0691c885,
 390                           0x3fe07451, 0x3f502c36, 0x0661d483,
 391                           0x00009055, 0x3f401831, 0x0601ec81,
 392                           0x0030a85b, 0x3f300c2a, 0x05b1f480,
 393                           0x0070c061, 0x3f300024, 0x0562047a,
 394                           0x00b0d867, 0x3f3ff41e, 0x05020c77,
 395                           0x00f0f46b, 0x3f2fec19, 0x04a21474 },
 396         },
 397         { 0x3c00, {
 398                           0x3fb05c43, 0x3fb05c43, 0x06c1b07e,
 399                           0x3fe06c4b, 0x3f902c3f, 0x0681c081,
 400                           0x0000844f, 0x3f703838, 0x0631cc7d,
 401                           0x00309855, 0x3f602433, 0x05d1d47e,
 402                           0x0060b459, 0x3f50142e, 0x0581e47b,
 403                           0x00a0c85f, 0x3f400828, 0x0531f078,
 404                           0x00e0e064, 0x3f300021, 0x0501fc73,
 405                           0x00b0fc6a, 0x3f3ff41d, 0x04a20873 },
 406         },
 407         { 0x3e00, {
 408                           0x3fe06444, 0x3fe06444, 0x0681a07a,
 409                           0x00007849, 0x3fc0503f, 0x0641b07a,
 410                           0x0020904d, 0x3fa0403a, 0x05f1c07a,
 411                           0x0060a453, 0x3f803034, 0x05c1c878,
 412                           0x0090b858, 0x3f70202f, 0x0571d477,
 413                           0x00d0d05d, 0x3f501829, 0x0531e073,
 414                           0x0110e462, 0x3f500825, 0x04e1e471,
 415                           0x01510065, 0x3f40001f, 0x04a1f06d },
 416         },
 417         { 0x4000, {
 418                           0x00007044, 0x00007044, 0x06519476,
 419                           0x00208448, 0x3fe05c3f, 0x0621a476,
 420                           0x0050984d, 0x3fc04c3a, 0x05e1b075,
 421                           0x0080ac52, 0x3fa03c35, 0x05a1b875,
 422                           0x00c0c056, 0x3f803030, 0x0561c473,
 423                           0x0100d45b, 0x3f70202b, 0x0521d46f,
 424                           0x0140e860, 0x3f601427, 0x04d1d46e,
 425                           0x01810064, 0x3f500822, 0x0491dc6b },
 426         },
 427         { 0x5000, {
 428                           0x0110a442, 0x0110a442, 0x0551545e,
 429                           0x0140b045, 0x00e0983f, 0x0531585f,
 430                           0x0160c047, 0x00c08c3c, 0x0511645e,
 431                           0x0190cc4a, 0x00908039, 0x04f1685f,
 432                           0x01c0dc4c, 0x00707436, 0x04d1705e,
 433                           0x0200e850, 0x00506833, 0x04b1785b,
 434                           0x0230f453, 0x00305c30, 0x0491805a,
 435                           0x02710056, 0x0010542d, 0x04718059 },
 436         },
 437         { 0x6000, {
 438                           0x01c0bc40, 0x01c0bc40, 0x04c13052,
 439                           0x01e0c841, 0x01a0b43d, 0x04c13851,
 440                           0x0210cc44, 0x0180a83c, 0x04a13453,
 441                           0x0230d845, 0x0160a03a, 0x04913c52,
 442                           0x0260e047, 0x01409838, 0x04714052,
 443                           0x0280ec49, 0x01208c37, 0x04514c50,
 444                           0x02b0f44b, 0x01008435, 0x04414c50,
 445                           0x02d1004c, 0x00e07c33, 0x0431544f },
 446         },
 447         { 0x7000, {
 448                           0x0230c83e, 0x0230c83e, 0x04711c4c,
 449                           0x0250d03f, 0x0210c43c, 0x0471204b,
 450                           0x0270d840, 0x0200b83c, 0x0451244b,
 451                           0x0290dc42, 0x01e0b43a, 0x0441244c,
 452                           0x02b0e443, 0x01c0b038, 0x0441284b,
 453                           0x02d0ec44, 0x01b0a438, 0x0421304a,
 454                           0x02f0f445, 0x0190a036, 0x04213449,
 455                           0x0310f847, 0x01709c34, 0x04213848 },
 456         },
 457         { 0x8000, {
 458                           0x0280d03d, 0x0280d03d, 0x04310c48,
 459                           0x02a0d43e, 0x0270c83c, 0x04311047,
 460                           0x02b0dc3e, 0x0250c83a, 0x04311447,
 461                           0x02d0e040, 0x0240c03a, 0x04211446,
 462                           0x02e0e840, 0x0220bc39, 0x04111847,
 463                           0x0300e842, 0x0210b438, 0x04012445,
 464                           0x0310f043, 0x0200b037, 0x04012045,
 465                           0x0330f444, 0x01e0ac36, 0x03f12445 },
 466         },
 467         { 0xefff, {
 468                           0x0340dc3a, 0x0340dc3a, 0x03b0ec40,
 469                           0x0340e03a, 0x0330e039, 0x03c0f03e,
 470                           0x0350e03b, 0x0330dc39, 0x03c0ec3e,
 471                           0x0350e43a, 0x0320dc38, 0x03c0f43e,
 472                           0x0360e43b, 0x0320d839, 0x03b0f03e,
 473                           0x0360e83b, 0x0310d838, 0x03c0fc3b,
 474                           0x0370e83b, 0x0310d439, 0x03a0f83d,
 475                           0x0370e83c, 0x0300d438, 0x03b0fc3c },
 476         }
 477 };
 478
 479 static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs)
 480 {
 481         int i;
 482         const struct vin_coeff *p_prev_set = NULL;
 483         const struct vin_coeff *p_set = NULL;
 484
 485         /* Look for suitable coefficient values */
 486         for (i = 0; i < ARRAY_SIZE(vin_coeff_set); i++) {
 487                 p_prev_set = p_set;
 488                 p_set = &vin_coeff_set[i];
 489
 490                 if (xs < p_set->xs_value)
 491                         break;
 492         }
 493
 494         /* Use previous value if its XS value is closer */
 495         if (p_prev_set &&
 496             xs - p_prev_set->xs_value < p_set->xs_value - xs)
 497                 p_set = p_prev_set;
 498
 499         /* Set coefficient registers */
 500         rvin_write(vin, p_set->coeff_set[0], VNC1A_REG);
 501         rvin_write(vin, p_set->coeff_set[1], VNC1B_REG);
 502         rvin_write(vin, p_set->coeff_set[2], VNC1C_REG);
 503
 504         rvin_write(vin, p_set->coeff_set[3], VNC2A_REG);
 505         rvin_write(vin, p_set->coeff_set[4], VNC2B_REG);
 506         rvin_write(vin, p_set->coeff_set[5], VNC2C_REG);
 507
 508         rvin_write(vin, p_set->coeff_set[6], VNC3A_REG);
 509         rvin_write(vin, p_set->coeff_set[7], VNC3B_REG);
 510         rvin_write(vin, p_set->coeff_set[8], VNC3C_REG);
 511
 512         rvin_write(vin, p_set->coeff_set[9], VNC4A_REG);
 513         rvin_write(vin, p_set->coeff_set[10], VNC4B_REG);
 514         rvin_write(vin, p_set->coeff_set[11], VNC4C_REG);
 515
 516         rvin_write(vin, p_set->coeff_set[12], VNC5A_REG);
 517         rvin_write(vin, p_set->coeff_set[13], VNC5B_REG);
 518         rvin_write(vin, p_set->coeff_set[14], VNC5C_REG);
 519
 520         rvin_write(vin, p_set->coeff_set[15], VNC6A_REG);
 521         rvin_write(vin, p_set->coeff_set[16], VNC6B_REG);
 522         rvin_write(vin, p_set->coeff_set[17], VNC6C_REG);
 523
 524         rvin_write(vin, p_set->coeff_set[18], VNC7A_REG);
 525         rvin_write(vin, p_set->coeff_set[19], VNC7B_REG);
 526         rvin_write(vin, p_set->coeff_set[20], VNC7C_REG);
 527
 528         rvin_write(vin, p_set->coeff_set[21], VNC8A_REG);
 529         rvin_write(vin, p_set->coeff_set[22], VNC8B_REG);
 530         rvin_write(vin, p_set->coeff_set[23], VNC8C_REG);
 531 }
 532
 533 static void rvin_crop_scale_comp_gen2(struct rvin_dev *vin)
 534 {
 535         unsigned int crop_height;
 536         u32 xs, ys;
 537
 538         /* Set scaling coefficient */
 539         crop_height = vin->crop.height;
 540         if (V4L2_FIELD_HAS_BOTH(vin->format.field))
 541                 crop_height *= 2;
 542
 543         ys = 0;
 544         if (crop_height != vin->compose.height)
 545                 ys = (4096 * crop_height) / vin->compose.height;
 546         rvin_write(vin, ys, VNYS_REG);
 547
 548         xs = 0;
 549         if (vin->crop.width != vin->compose.width)
 550                 xs = (4096 * vin->crop.width) / vin->compose.width;
 551
 552         /* Horizontal upscaling is up to double size */
 553         if (xs > 0 && xs < 2048)
 554                 xs = 2048;
 555
 556         rvin_write(vin, xs, VNXS_REG);
 557
 558         /* Horizontal upscaling is done out by scaling down from double size */
 559         if (xs < 4096)
 560                 xs *= 2;
 561
 562         rvin_set_coeff(vin, xs);
 563
 564         /* Set Start/End Pixel/Line Post-Clip */
 565         rvin_write(vin, 0, VNSPPOC_REG);
 566         rvin_write(vin, 0, VNSLPOC_REG);
 567         rvin_write(vin, vin->format.width - 1, VNEPPOC_REG);
 568
 569         if (V4L2_FIELD_HAS_BOTH(vin->format.field))
 570                 rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG);
 571         else
 572                 rvin_write(vin, vin->format.height - 1, VNELPOC_REG);
 573
 574         vin_dbg(vin,
 575                 "Pre-Clip: %ux%u@%u:%u YS: %d XS: %d Post-Clip: %ux%u@%u:%u\n",
 576                 vin->crop.width, vin->crop.height, vin->crop.left,
 577                 vin->crop.top, ys, xs, vin->format.width, vin->format.height,
 578                 0, 0);
 579 }
 580
 581 void rvin_crop_scale_comp(struct rvin_dev *vin)
 582 {
 583         const struct rvin_video_format *fmt;
 584         u32 stride;
 585
 586         /* Set Start/End Pixel/Line Pre-Clip */
 587         rvin_write(vin, vin->crop.left, VNSPPRC_REG);
 588         rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG);
 589         rvin_write(vin, vin->crop.top, VNSLPRC_REG);
 590         rvin_write(vin, vin->crop.top + vin->crop.height - 1, VNELPRC_REG);
 591
 592         /* TODO: Add support for the UDS scaler. */
 593         if (vin->info->model != RCAR_GEN3)
 594                 rvin_crop_scale_comp_gen2(vin);
 595
 596         fmt = rvin_format_from_pixel(vin, vin->format.pixelformat);
 597         stride = vin->format.bytesperline / fmt->bpp;
 598
 599         /* For RAW8 format bpp is 1, but the hardware process RAW8
 600          * format in 2 pixel unit hence configure VNIS_REG as stride / 2.
 601          */
 602         switch (vin->format.pixelformat) {
 603         case V4L2_PIX_FMT_SBGGR8:
 604         case V4L2_PIX_FMT_SGBRG8:
 605         case V4L2_PIX_FMT_SGRBG8:
 606         case V4L2_PIX_FMT_SRGGB8:
 607                 stride /= 2;
 608                 break;
 609         default:
 610                 break;
 611         }
 612
 613         rvin_write(vin, stride, VNIS_REG);
 614 }
 615
 616 /* -----------------------------------------------------------------------------
 617  * Hardware setup
 618  */
 619
 620 static int rvin_setup(struct rvin_dev *vin)
 621 {
 622         u32 vnmc, dmr, dmr2, interrupts;
 623         bool progressive = false, output_is_yuv = false, input_is_yuv = false;
 624
 625         switch (vin->format.field) {
 626         case V4L2_FIELD_TOP:
 627                 vnmc = VNMC_IM_ODD;
 628                 break;
 629         case V4L2_FIELD_BOTTOM:
 630                 vnmc = VNMC_IM_EVEN;
 631                 break;
 632         case V4L2_FIELD_INTERLACED:
 633                 /* Default to TB */
 634                 vnmc = VNMC_IM_FULL;
 635                 /* Use BT if video standard can be read and is 60 Hz format */
 636                 if (!vin->info->use_mc && vin->std & V4L2_STD_525_60)
 637                         vnmc = VNMC_IM_FULL | VNMC_FOC;
 638                 break;
 639         case V4L2_FIELD_INTERLACED_TB:
 640                 vnmc = VNMC_IM_FULL;
 641                 break;
 642         case V4L2_FIELD_INTERLACED_BT:
 643                 vnmc = VNMC_IM_FULL | VNMC_FOC;
 644                 break;
 645         case V4L2_FIELD_SEQ_TB:
 646         case V4L2_FIELD_SEQ_BT:
 647         case V4L2_FIELD_NONE:
 648                 vnmc = VNMC_IM_ODD_EVEN;
 649                 progressive = true;
 650                 break;
 651         case V4L2_FIELD_ALTERNATE:
 652                 vnmc = VNMC_IM_ODD_EVEN;
 653                 break;
 654         default:
 655                 vnmc = VNMC_IM_ODD;
 656                 break;
 657         }
 658
 659         /*
 660          * Input interface
 661          */
 662         switch (vin->mbus_code) {
 663         case MEDIA_BUS_FMT_YUYV8_1X16:
 664                 /* BT.601/BT.1358 16bit YCbCr422 */
 665                 vnmc |= VNMC_INF_YUV16;
 666                 input_is_yuv = true;
 667                 break;
 668         case MEDIA_BUS_FMT_UYVY8_1X16:
 669                 vnmc |= VNMC_INF_YUV16 | VNMC_YCAL;
 670                 input_is_yuv = true;
 671                 break;
 672         case MEDIA_BUS_FMT_UYVY8_2X8:
 673                 /* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */
 674                 if (!vin->is_csi &&
 675                     vin->parallel->mbus_type == V4L2_MBUS_BT656)
 676                         vnmc |= VNMC_INF_YUV8_BT656;
 677                 else
 678                         vnmc |= VNMC_INF_YUV8_BT601;
 679
 680                 input_is_yuv = true;
 681                 break;
 682         case MEDIA_BUS_FMT_RGB888_1X24:
 683                 vnmc |= VNMC_INF_RGB888;
 684                 break;
 685         case MEDIA_BUS_FMT_UYVY10_2X10:
 686                 /* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */
 687                 if (!vin->is_csi &&
 688                     vin->parallel->mbus_type == V4L2_MBUS_BT656)
 689                         vnmc |= VNMC_INF_YUV10_BT656;
 690                 else
 691                         vnmc |= VNMC_INF_YUV10_BT601;
 692
 693                 input_is_yuv = true;
 694                 break;
 695         case MEDIA_BUS_FMT_SBGGR8_1X8:
 696         case MEDIA_BUS_FMT_SGBRG8_1X8:
 697         case MEDIA_BUS_FMT_SGRBG8_1X8:
 698         case MEDIA_BUS_FMT_SRGGB8_1X8:
 699                 vnmc |= VNMC_INF_RAW8;
 700                 break;
 701         default:
 702                 break;
 703         }
 704
 705         /* Enable VSYNC Field Toggle mode after one VSYNC input */
 706         if (vin->info->model == RCAR_GEN3)
 707                 dmr2 = VNDMR2_FTEV;
 708         else
 709                 dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
 710
 711         if (!vin->is_csi) {
 712                 /* Hsync Signal Polarity Select */
 713                 if (!(vin->parallel->bus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
 714                         dmr2 |= VNDMR2_HPS;
 715
 716                 /* Vsync Signal Polarity Select */
 717                 if (!(vin->parallel->bus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
 718                         dmr2 |= VNDMR2_VPS;
 719
 720                 /* Data Enable Polarity Select */
 721                 if (vin->parallel->bus.flags & V4L2_MBUS_DATA_ENABLE_LOW)
 722                         dmr2 |= VNDMR2_CES;
 723
 724                 switch (vin->mbus_code) {
 725                 case MEDIA_BUS_FMT_UYVY8_2X8:
 726                         if (vin->parallel->bus.bus_width == 8 &&
 727                             vin->parallel->bus.data_shift == 8)
 728                                 dmr2 |= VNDMR2_YDS;
 729                         break;
 730                 default:
 731                         break;
 732                 }
 733         }
 734
 735         /*
 736          * Output format
 737          */
 738         switch (vin->format.pixelformat) {
 739         case V4L2_PIX_FMT_NV12:
 740         case V4L2_PIX_FMT_NV16:
 741                 rvin_write(vin,
 742                            ALIGN(vin->format.bytesperline * vin->format.height,
 743                                  0x80), VNUVAOF_REG);
 744                 dmr = vin->format.pixelformat == V4L2_PIX_FMT_NV12 ?
 745                         VNDMR_DTMD_YCSEP_420 : VNDMR_DTMD_YCSEP;
 746                 output_is_yuv = true;
 747                 break;
 748         case V4L2_PIX_FMT_YUYV:
 749                 dmr = VNDMR_BPSM;
 750                 output_is_yuv = true;
 751                 break;
 752         case V4L2_PIX_FMT_UYVY:
 753                 dmr = 0;
 754                 output_is_yuv = true;
 755                 break;
 756         case V4L2_PIX_FMT_XRGB555:
 757                 dmr = VNDMR_DTMD_ARGB;
 758                 break;
 759         case V4L2_PIX_FMT_RGB565:
 760                 dmr = 0;
 761                 break;
 762         case V4L2_PIX_FMT_XBGR32:
 763                 /* Note: not supported on M1 */
 764                 dmr = VNDMR_EXRGB;
 765                 break;
 766         case V4L2_PIX_FMT_ARGB555:
 767                 dmr = (vin->alpha ? VNDMR_ABIT : 0) | VNDMR_DTMD_ARGB;
 768                 break;
 769         case V4L2_PIX_FMT_ABGR32:
 770                 dmr = VNDMR_A8BIT(vin->alpha) | VNDMR_EXRGB | VNDMR_DTMD_ARGB;
 771                 break;
 772         case V4L2_PIX_FMT_SBGGR8:
 773         case V4L2_PIX_FMT_SGBRG8:
 774         case V4L2_PIX_FMT_SGRBG8:
 775         case V4L2_PIX_FMT_SRGGB8:
 776                 dmr = 0;
 777                 break;
 778         default:
 779                 vin_err(vin, "Invalid pixelformat (0x%x)\n",
 780                         vin->format.pixelformat);
 781                 return -EINVAL;
 782         }
 783
 784         /* Always update on field change */
 785         vnmc |= VNMC_VUP;
 786
 787         /* If input and output use the same colorspace, use bypass mode */
 788         if (input_is_yuv == output_is_yuv)
 789                 vnmc |= VNMC_BPS;
 790
 791         if (vin->info->model == RCAR_GEN3) {
 792                 /* Select between CSI-2 and parallel input */
 793                 if (vin->is_csi)
 794                         vnmc &= ~VNMC_DPINE;
 795                 else
 796                         vnmc |= VNMC_DPINE;
 797         }
 798
 799         /* Progressive or interlaced mode */
 800         interrupts = progressive ? VNIE_FIE : VNIE_EFE;
 801
 802         /* Ack interrupts */
 803         rvin_write(vin, interrupts, VNINTS_REG);
 804         /* Enable interrupts */
 805         rvin_write(vin, interrupts, VNIE_REG);
 806         /* Start capturing */
 807         rvin_write(vin, dmr, VNDMR_REG);
 808         rvin_write(vin, dmr2, VNDMR2_REG);
 809
 810         /* Enable module */
 811         rvin_write(vin, vnmc | VNMC_ME, VNMC_REG);
 812
 813         return 0;
 814 }
 815
 816 static void rvin_disable_interrupts(struct rvin_dev *vin)
 817 {
 818         rvin_write(vin, 0, VNIE_REG);
 819 }
 820
 821 static u32 rvin_get_interrupt_status(struct rvin_dev *vin)
 822 {
 823         return rvin_read(vin, VNINTS_REG);
 824 }
 825
 826 static void rvin_ack_interrupt(struct rvin_dev *vin)
 827 {
 828         rvin_write(vin, rvin_read(vin, VNINTS_REG), VNINTS_REG);
 829 }
 830
 831 static bool rvin_capture_active(struct rvin_dev *vin)
 832 {
 833         return rvin_read(vin, VNMS_REG) & VNMS_CA;
 834 }
 835
 836 static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms)
 837 {
 838         if (vin->format.field == V4L2_FIELD_ALTERNATE) {
 839                 /* If FS is set it is an Even field. */
 840                 if (vnms & VNMS_FS)
 841                         return V4L2_FIELD_BOTTOM;
 842                 return V4L2_FIELD_TOP;
 843         }
 844
 845         return vin->format.field;
 846 }
 847
 848 static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr)
 849 {
 850         const struct rvin_video_format *fmt;
 851         int offsetx, offsety;
 852         dma_addr_t offset;
 853
 854         fmt = rvin_format_from_pixel(vin, vin->format.pixelformat);
 855
 856         /*
 857          * There is no HW support for composition do the beast we can
 858          * by modifying the buffer offset
 859          */
 860         offsetx = vin->compose.left * fmt->bpp;
 861         offsety = vin->compose.top * vin->format.bytesperline;
 862         offset = addr + offsetx + offsety;
 863
 864         /*
 865          * The address needs to be 128 bytes aligned. Driver should never accept
 866          * settings that do not satisfy this in the first place...
 867          */
 868         if (WARN_ON((offsetx | offsety | offset) & HW_BUFFER_MASK))
 869                 return;
 870
 871         rvin_write(vin, offset, VNMB_REG(slot));
 872 }
 873
 874 /*
 875  * Moves a buffer from the queue to the HW slot. If no buffer is
 876  * available use the scratch buffer. The scratch buffer is never
 877  * returned to userspace, its only function is to enable the capture
 878  * loop to keep running.
 879  */
 880 static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot)
 881 {
 882         struct rvin_buffer *buf;
 883         struct vb2_v4l2_buffer *vbuf;
 884         dma_addr_t phys_addr;
 885         int prev;
 886
 887         /* A already populated slot shall never be overwritten. */
 888         if (WARN_ON(vin->buf_hw[slot].buffer))
 889                 return;
 890
 891         prev = (slot == 0 ? HW_BUFFER_NUM : slot) - 1;
 892
 893         if (vin->buf_hw[prev].type == HALF_TOP) {
 894                 vbuf = vin->buf_hw[prev].buffer;
 895                 vin->buf_hw[slot].buffer = vbuf;
 896                 vin->buf_hw[slot].type = HALF_BOTTOM;
 897                 switch (vin->format.pixelformat) {
 898                 case V4L2_PIX_FMT_NV12:
 899                 case V4L2_PIX_FMT_NV16:
 900                         phys_addr = vin->buf_hw[prev].phys +
 901                                 vin->format.sizeimage / 4;
 902                         break;
 903                 default:
 904                         phys_addr = vin->buf_hw[prev].phys +
 905                                 vin->format.sizeimage / 2;
 906                         break;
 907                 }
 908         } else if (vin->state != RUNNING || list_empty(&vin->buf_list)) {
 909                 vin->buf_hw[slot].buffer = NULL;
 910                 vin->buf_hw[slot].type = FULL;
 911                 phys_addr = vin->scratch_phys;
 912         } else {
 913                 /* Keep track of buffer we give to HW */
 914                 buf = list_entry(vin->buf_list.next, struct rvin_buffer, list);
 915                 vbuf = &buf->vb;
 916                 list_del_init(to_buf_list(vbuf));
 917                 vin->buf_hw[slot].buffer = vbuf;
 918
 919                 vin->buf_hw[slot].type =
 920                         V4L2_FIELD_IS_SEQUENTIAL(vin->format.field) ?
 921                         HALF_TOP : FULL;
 922
 923                 /* Setup DMA */
 924                 phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
 925         }
 926
 927         vin_dbg(vin, "Filling HW slot: %d type: %d buffer: %p\n",
 928                 slot, vin->buf_hw[slot].type, vin->buf_hw[slot].buffer);
 929
 930         vin->buf_hw[slot].phys = phys_addr;
 931         rvin_set_slot_addr(vin, slot, phys_addr);
 932 }
 933
 934 static int rvin_capture_start(struct rvin_dev *vin)
 935 {
 936         int slot, ret;
 937
 938         for (slot = 0; slot < HW_BUFFER_NUM; slot++) {
 939                 vin->buf_hw[slot].buffer = NULL;
 940                 vin->buf_hw[slot].type = FULL;
 941         }
 942
 943         for (slot = 0; slot < HW_BUFFER_NUM; slot++)
 944                 rvin_fill_hw_slot(vin, slot);
 945
 946         rvin_crop_scale_comp(vin);
 947
 948         ret = rvin_setup(vin);
 949         if (ret)
 950                 return ret;
 951
 952         vin_dbg(vin, "Starting to capture\n");
 953
 954         /* Continuous Frame Capture Mode */
 955         rvin_write(vin, VNFC_C_FRAME, VNFC_REG);
 956
 957         vin->state = STARTING;
 958
 959         return 0;
 960 }
 961
 962 static void rvin_capture_stop(struct rvin_dev *vin)
 963 {
 964         /* Set continuous & single transfer off */
 965         rvin_write(vin, 0, VNFC_REG);
 966
 967         /* Disable module */
 968         rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG);
 969 }
 970
 971 /* -----------------------------------------------------------------------------
 972  * DMA Functions
 973  */
 974
 975 #define RVIN_TIMEOUT_MS 100
 976 #define RVIN_RETRIES 10
 977
 978 static irqreturn_t rvin_irq(int irq, void *data)
 979 {
 980         struct rvin_dev *vin = data;
 981         u32 int_status, vnms;
 982         int slot;
 983         unsigned int handled = 0;
 984         unsigned long flags;
 985
 986         spin_lock_irqsave(&vin->qlock, flags);
 987
 988         int_status = rvin_get_interrupt_status(vin);
 989         if (!int_status)
 990                 goto done;
 991
 992         rvin_ack_interrupt(vin);
 993         handled = 1;
 994
 995         /* Nothing to do if capture status is 'STOPPED' */
 996         if (vin->state == STOPPED) {
 997                 vin_dbg(vin, "IRQ while state stopped\n");
 998                 goto done;
 999         }
1000
1001         /* Prepare for capture and update state */
1002         vnms = rvin_read(vin, VNMS_REG);
1003         slot = (vnms & VNMS_FBS_MASK) >> VNMS_FBS_SHIFT;
1004
1005         /*
1006          * To hand buffers back in a known order to userspace start
1007          * to capture first from slot 0.
1008          */
1009         if (vin->state == STARTING) {
1010                 if (slot != 0) {
1011                         vin_dbg(vin, "Starting sync slot: %d\n", slot);
1012                         goto done;
1013                 }
1014
1015                 vin_dbg(vin, "Capture start synced!\n");
1016                 vin->state = RUNNING;
1017         }
1018
1019         /* Capture frame */
1020         if (vin->buf_hw[slot].buffer) {
1021                 /*
1022                  * Nothing to do but refill the hardware slot if
1023                  * capture only filled first half of vb2 buffer.
1024                  */
1025                 if (vin->buf_hw[slot].type == HALF_TOP) {
1026                         vin->buf_hw[slot].buffer = NULL;
1027                         rvin_fill_hw_slot(vin, slot);
1028                         goto done;
1029                 }
1030
1031                 vin->buf_hw[slot].buffer->field =
1032                         rvin_get_active_field(vin, vnms);
1033                 vin->buf_hw[slot].buffer->sequence = vin->sequence;
1034                 vin->buf_hw[slot].buffer->vb2_buf.timestamp = ktime_get_ns();
1035                 vb2_buffer_done(&vin->buf_hw[slot].buffer->vb2_buf,
1036                                 VB2_BUF_STATE_DONE);
1037                 vin->buf_hw[slot].buffer = NULL;
1038         } else {
1039                 /* Scratch buffer was used, dropping frame. */
1040                 vin_dbg(vin, "Dropping frame %u\n", vin->sequence);
1041         }
1042
1043         vin->sequence++;
1044
1045         /* Prepare for next frame */
1046         rvin_fill_hw_slot(vin, slot);
1047 done:
1048         spin_unlock_irqrestore(&vin->qlock, flags);
1049
1050         return IRQ_RETVAL(handled);
1051 }
1052
1053 static void return_unused_buffers(struct rvin_dev *vin,
1054                                   enum vb2_buffer_state state)
1055 {
1056         struct rvin_buffer *buf, *node;
1057         unsigned long flags;
1058
1059         spin_lock_irqsave(&vin->qlock, flags);
1060
1061         list_for_each_entry_safe(buf, node, &vin->buf_list, list) {
1062                 vb2_buffer_done(&buf->vb.vb2_buf, state);
1063                 list_del(&buf->list);
1064         }
1065
1066         spin_unlock_irqrestore(&vin->qlock, flags);
1067 }
1068
1069 static int rvin_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
1070                             unsigned int *nplanes, unsigned int sizes[],
1071                             struct device *alloc_devs[])
1072
1073 {
1074         struct rvin_dev *vin = vb2_get_drv_priv(vq);
1075
1076         /* Make sure the image size is large enough. */
1077         if (*nplanes)
1078                 return sizes[0] < vin->format.sizeimage ? -EINVAL : 0;
1079
1080         *nplanes = 1;
1081         sizes[0] = vin->format.sizeimage;
1082
1083         return 0;
1084 };
1085
1086 static int rvin_buffer_prepare(struct vb2_buffer *vb)
1087 {
1088         struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue);
1089         unsigned long size = vin->format.sizeimage;
1090
1091         if (vb2_plane_size(vb, 0) < size) {
1092                 vin_err(vin, "buffer too small (%lu < %lu)\n",
1093                         vb2_plane_size(vb, 0), size);
1094                 return -EINVAL;
1095         }
1096
1097         vb2_set_plane_payload(vb, 0, size);
1098
1099         return 0;
1100 }
1101
1102 static void rvin_buffer_queue(struct vb2_buffer *vb)
1103 {
1104         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1105         struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue);
1106         unsigned long flags;
1107
1108         spin_lock_irqsave(&vin->qlock, flags);
1109
1110         list_add_tail(to_buf_list(vbuf), &vin->buf_list);
1111
1112         spin_unlock_irqrestore(&vin->qlock, flags);
1113 }
1114
1115 static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd,
1116                                    struct media_pad *pad)
1117 {
1118         struct v4l2_subdev_format fmt = {
1119                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1120         };
1121
1122         fmt.pad = pad->index;
1123         if (v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt))
1124                 return -EPIPE;
1125
1126         switch (fmt.format.code) {
1127         case MEDIA_BUS_FMT_YUYV8_1X16:
1128         case MEDIA_BUS_FMT_UYVY8_1X16:
1129         case MEDIA_BUS_FMT_UYVY8_2X8:
1130         case MEDIA_BUS_FMT_UYVY10_2X10:
1131         case MEDIA_BUS_FMT_RGB888_1X24:
1132                 break;
1133         case MEDIA_BUS_FMT_SBGGR8_1X8:
1134                 if (vin->format.pixelformat != V4L2_PIX_FMT_SBGGR8)
1135                         return -EPIPE;
1136                 break;
1137         case MEDIA_BUS_FMT_SGBRG8_1X8:
1138                 if (vin->format.pixelformat != V4L2_PIX_FMT_SGBRG8)
1139                         return -EPIPE;
1140                 break;
1141         case MEDIA_BUS_FMT_SGRBG8_1X8:
1142                 if (vin->format.pixelformat != V4L2_PIX_FMT_SGRBG8)
1143                         return -EPIPE;
1144                 break;
1145         case MEDIA_BUS_FMT_SRGGB8_1X8:
1146                 if (vin->format.pixelformat != V4L2_PIX_FMT_SRGGB8)
1147                         return -EPIPE;
1148                 break;
1149         default:
1150                 return -EPIPE;
1151         }
1152         vin->mbus_code = fmt.format.code;
1153
1154         switch (fmt.format.field) {
1155         case V4L2_FIELD_TOP:
1156         case V4L2_FIELD_BOTTOM:
1157         case V4L2_FIELD_NONE:
1158         case V4L2_FIELD_INTERLACED_TB:
1159         case V4L2_FIELD_INTERLACED_BT:
1160         case V4L2_FIELD_INTERLACED:
1161         case V4L2_FIELD_SEQ_TB:
1162         case V4L2_FIELD_SEQ_BT:
1163                 /* Supported natively */
1164                 break;
1165         case V4L2_FIELD_ALTERNATE:
1166                 switch (vin->format.field) {
1167                 case V4L2_FIELD_TOP:
1168                 case V4L2_FIELD_BOTTOM:
1169                 case V4L2_FIELD_NONE:
1170                 case V4L2_FIELD_ALTERNATE:
1171                         break;
1172                 case V4L2_FIELD_INTERLACED_TB:
1173                 case V4L2_FIELD_INTERLACED_BT:
1174                 case V4L2_FIELD_INTERLACED:
1175                 case V4L2_FIELD_SEQ_TB:
1176                 case V4L2_FIELD_SEQ_BT:
1177                         /* Use VIN hardware to combine the two fields */
1178                         fmt.format.height *= 2;
1179                         break;
1180                 default:
1181                         return -EPIPE;
1182                 }
1183                 break;
1184         default:
1185                 return -EPIPE;
1186         }
1187
1188         if (fmt.format.width != vin->format.width ||
1189             fmt.format.height != vin->format.height ||
1190             fmt.format.code != vin->mbus_code)
1191                 return -EPIPE;
1192
1193         return 0;
1194 }
1195
1196 static int rvin_set_stream(struct rvin_dev *vin, int on)
1197 {
1198         struct media_pipeline *pipe;
1199         struct media_device *mdev;
1200         struct v4l2_subdev *sd;
1201         struct media_pad *pad;
1202         int ret;
1203
1204         /* No media controller used, simply pass operation to subdevice. */
1205         if (!vin->info->use_mc) {
1206                 ret = v4l2_subdev_call(vin->parallel->subdev, video, s_stream,
1207                                        on);
1208
1209                 return ret == -ENOIOCTLCMD ? 0 : ret;
1210         }
1211
1212         pad = media_entity_remote_pad(&vin->pad);
1213         if (!pad)
1214                 return -EPIPE;
1215
1216         sd = media_entity_to_v4l2_subdev(pad->entity);
1217
1218         if (!on) {
1219                 media_pipeline_stop(&vin->vdev.entity);
1220                 return v4l2_subdev_call(sd, video, s_stream, 0);
1221         }
1222
1223         ret = rvin_mc_validate_format(vin, sd, pad);
1224         if (ret)
1225                 return ret;
1226
1227         /*
1228          * The graph lock needs to be taken to protect concurrent
1229          * starts of multiple VIN instances as they might share
1230          * a common subdevice down the line and then should use
1231          * the same pipe.
1232          */
1233         mdev = vin->vdev.entity.graph_obj.mdev;
1234         mutex_lock(&mdev->graph_mutex);
1235         pipe = sd->entity.pipe ? sd->entity.pipe : &vin->vdev.pipe;
1236         ret = __media_pipeline_start(&vin->vdev.entity, pipe);
1237         mutex_unlock(&mdev->graph_mutex);
1238         if (ret)
1239                 return ret;
1240
1241         ret = v4l2_subdev_call(sd, video, s_stream, 1);
1242         if (ret == -ENOIOCTLCMD)
1243                 ret = 0;
1244         if (ret)
1245                 media_pipeline_stop(&vin->vdev.entity);
1246
1247         return ret;
1248 }
1249
1250 int rvin_start_streaming(struct rvin_dev *vin)
1251 {
1252         unsigned long flags;
1253         int ret;
1254
1255         ret = rvin_set_stream(vin, 1);
1256         if (ret)
1257                 return ret;
1258
1259         spin_lock_irqsave(&vin->qlock, flags);
1260
1261         vin->sequence = 0;
1262
1263         ret = rvin_capture_start(vin);
1264         if (ret)
1265                 rvin_set_stream(vin, 0);
1266
1267         spin_unlock_irqrestore(&vin->qlock, flags);
1268
1269         return ret;
1270 }
1271
1272 static int rvin_start_streaming_vq(struct vb2_queue *vq, unsigned int count)
1273 {
1274         struct rvin_dev *vin = vb2_get_drv_priv(vq);
1275         int ret = -ENOMEM;
1276
1277         /* Allocate scratch buffer. */
1278         vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage,
1279                                           &vin->scratch_phys, GFP_KERNEL);
1280         if (!vin->scratch)
1281                 goto err_scratch;
1282
1283         ret = rvin_start_streaming(vin);
1284         if (ret)
1285                 goto err_start;
1286
1287         return 0;
1288 err_start:
1289         dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
1290                           vin->scratch_phys);
1291 err_scratch:
1292         return_unused_buffers(vin, VB2_BUF_STATE_QUEUED);
1293
1294         return ret;
1295 }
1296
1297 void rvin_stop_streaming(struct rvin_dev *vin)
1298 {
1299         unsigned int i, retries;
1300         unsigned long flags;
1301         bool buffersFreed;
1302
1303         spin_lock_irqsave(&vin->qlock, flags);
1304
1305         vin->state = STOPPING;
1306
1307         /* Wait until only scratch buffer is used, max 3 interrupts. */
1308         retries = 0;
1309         while (retries++ < RVIN_RETRIES) {
1310                 buffersFreed = true;
1311                 for (i = 0; i < HW_BUFFER_NUM; i++)
1312                         if (vin->buf_hw[i].buffer)
1313                                 buffersFreed = false;
1314
1315                 if (buffersFreed)
1316                         break;
1317
1318                 spin_unlock_irqrestore(&vin->qlock, flags);
1319                 msleep(RVIN_TIMEOUT_MS);
1320                 spin_lock_irqsave(&vin->qlock, flags);
1321         }
1322
1323         /* Wait for streaming to stop */
1324         retries = 0;
1325         while (retries++ < RVIN_RETRIES) {
1326
1327                 rvin_capture_stop(vin);
1328
1329                 /* Check if HW is stopped */
1330                 if (!rvin_capture_active(vin)) {
1331                         vin->state = STOPPED;
1332                         break;
1333                 }
1334
1335                 spin_unlock_irqrestore(&vin->qlock, flags);
1336                 msleep(RVIN_TIMEOUT_MS);
1337                 spin_lock_irqsave(&vin->qlock, flags);
1338         }
1339
1340         if (!buffersFreed || vin->state != STOPPED) {
1341                 /*
1342                  * If this happens something have gone horribly wrong.
1343                  * Set state to stopped to prevent the interrupt handler
1344                  * to make things worse...
1345                  */
1346                 vin_err(vin, "Failed stop HW, something is seriously broken\n");
1347                 vin->state = STOPPED;
1348         }
1349
1350         spin_unlock_irqrestore(&vin->qlock, flags);
1351
1352         rvin_set_stream(vin, 0);
1353
1354         /* disable interrupts */
1355         rvin_disable_interrupts(vin);
1356 }
1357
1358 static void rvin_stop_streaming_vq(struct vb2_queue *vq)
1359 {
1360         struct rvin_dev *vin = vb2_get_drv_priv(vq);
1361
1362         rvin_stop_streaming(vin);
1363
1364         /* Free scratch buffer. */
1365         dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
1366                           vin->scratch_phys);
1367
1368         return_unused_buffers(vin, VB2_BUF_STATE_ERROR);
1369 }
1370
1371 static const struct vb2_ops rvin_qops = {
1372         .queue_setup            = rvin_queue_setup,
1373         .buf_prepare            = rvin_buffer_prepare,
1374         .buf_queue              = rvin_buffer_queue,
1375         .start_streaming        = rvin_start_streaming_vq,
1376         .stop_streaming         = rvin_stop_streaming_vq,
1377         .wait_prepare           = vb2_ops_wait_prepare,
1378         .wait_finish            = vb2_ops_wait_finish,
1379 };
1380
1381 void rvin_dma_unregister(struct rvin_dev *vin)
1382 {
1383         mutex_destroy(&vin->lock);
1384
1385         v4l2_device_unregister(&vin->v4l2_dev);
1386 }
1387
1388 int rvin_dma_register(struct rvin_dev *vin, int irq)
1389 {
1390         struct vb2_queue *q = &vin->queue;
1391         int i, ret;
1392
1393         /* Initialize the top-level structure */
1394         ret = v4l2_device_register(vin->dev, &vin->v4l2_dev);
1395         if (ret)
1396                 return ret;
1397
1398         mutex_init(&vin->lock);
1399         INIT_LIST_HEAD(&vin->buf_list);
1400
1401         spin_lock_init(&vin->qlock);
1402
1403         vin->state = STOPPED;
1404
1405         for (i = 0; i < HW_BUFFER_NUM; i++)
1406                 vin->buf_hw[i].buffer = NULL;
1407
1408         /* buffer queue */
1409         q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1410         q->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
1411         q->lock = &vin->lock;
1412         q->drv_priv = vin;
1413         q->buf_struct_size = sizeof(struct rvin_buffer);
1414         q->ops = &rvin_qops;
1415         q->mem_ops = &vb2_dma_contig_memops;
1416         q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1417         q->min_buffers_needed = 4;
1418         q->dev = vin->dev;
1419
1420         ret = vb2_queue_init(q);
1421         if (ret < 0) {
1422                 vin_err(vin, "failed to initialize VB2 queue\n");
1423                 goto error;
1424         }
1425
1426         /* irq */
1427         ret = devm_request_irq(vin->dev, irq, rvin_irq, IRQF_SHARED,
1428                                KBUILD_MODNAME, vin);
1429         if (ret) {
1430                 vin_err(vin, "failed to request irq\n");
1431                 goto error;
1432         }
1433
1434         return 0;
1435 error:
1436         rvin_dma_unregister(vin);
1437
1438         return ret;
1439 }
1440
1441 /* -----------------------------------------------------------------------------
1442  * Gen3 CHSEL manipulation
1443  */
1444
1445 /*
1446  * There is no need to have locking around changing the routing
1447  * as it's only possible to do so when no VIN in the group is
1448  * streaming so nothing can race with the VNMC register.
1449  */
1450 int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel)
1451 {
1452         u32 ifmd, vnmc;
1453         int ret;
1454
1455         ret = pm_runtime_get_sync(vin->dev);
1456         if (ret < 0) {
1457                 pm_runtime_put_noidle(vin->dev);
1458                 return ret;
1459         }
1460
1461         /* Make register writes take effect immediately. */
1462         vnmc = rvin_read(vin, VNMC_REG);
1463         rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG);
1464
1465         ifmd = VNCSI_IFMD_DES1 | VNCSI_IFMD_DES0 | VNCSI_IFMD_CSI_CHSEL(chsel);
1466
1467         rvin_write(vin, ifmd, VNCSI_IFMD_REG);
1468
1469         vin_dbg(vin, "Set IFMD 0x%x\n", ifmd);
1470
1471         vin->chsel = chsel;
1472
1473         /* Restore VNMC. */
1474         rvin_write(vin, vnmc, VNMC_REG);
1475
1476         pm_runtime_put(vin->dev);
1477
1478         return 0;
1479 }
1480
1481 void rvin_set_alpha(struct rvin_dev *vin, unsigned int alpha)
1482 {
1483         unsigned long flags;
1484         u32 dmr;
1485
1486         spin_lock_irqsave(&vin->qlock, flags);
1487
1488         vin->alpha = alpha;
1489
1490         if (vin->state == STOPPED)
1491                 goto out;
1492
1493         switch (vin->format.pixelformat) {
1494         case V4L2_PIX_FMT_ARGB555:
1495                 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_ABIT;
1496                 if (vin->alpha)
1497                         dmr |= VNDMR_ABIT;
1498                 break;
1499         case V4L2_PIX_FMT_ABGR32:
1500                 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_A8BIT_MASK;
1501                 dmr |= VNDMR_A8BIT(vin->alpha);
1502                 break;
1503         default:
1504                 goto out;
1505         }
1506
1507         rvin_write(vin, dmr,  VNDMR_REG);
1508 out:
1509         spin_unlock_irqrestore(&vin->qlock, flags);
1510 }