1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Registers definitions
7 * Copyright (C) 2010 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments, Inc
10 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 * Sakari Ailus <sakari.ailus@iki.fi>
14 #ifndef OMAP3_ISP_REG_H
15 #define OMAP3_ISP_REG_H
17 #define CM_CAM_MCLK_HZ 172800000 /* Hz */
19 /* ISP module register offset */
21 #define ISP_REVISION (0x000)
22 #define ISP_SYSCONFIG (0x004)
23 #define ISP_SYSSTATUS (0x008)
24 #define ISP_IRQ0ENABLE (0x00C)
25 #define ISP_IRQ0STATUS (0x010)
26 #define ISP_IRQ1ENABLE (0x014)
27 #define ISP_IRQ1STATUS (0x018)
28 #define ISP_TCTRL_GRESET_LENGTH (0x030)
29 #define ISP_TCTRL_PSTRB_REPLAY (0x034)
30 #define ISP_CTRL (0x040)
31 #define ISP_SECURE (0x044)
32 #define ISP_TCTRL_CTRL (0x050)
33 #define ISP_TCTRL_FRAME (0x054)
34 #define ISP_TCTRL_PSTRB_DELAY (0x058)
35 #define ISP_TCTRL_STRB_DELAY (0x05C)
36 #define ISP_TCTRL_SHUT_DELAY (0x060)
37 #define ISP_TCTRL_PSTRB_LENGTH (0x064)
38 #define ISP_TCTRL_STRB_LENGTH (0x068)
39 #define ISP_TCTRL_SHUT_LENGTH (0x06C)
40 #define ISP_PING_PONG_ADDR (0x070)
41 #define ISP_PING_PONG_MEM_RANGE (0x074)
42 #define ISP_PING_PONG_BUF_SIZE (0x078)
44 /* CCP2 receiver registers */
46 #define ISPCCP2_REVISION (0x000)
47 #define ISPCCP2_SYSCONFIG (0x004)
48 #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
49 #define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1
50 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12
51 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE \
52 (0x0 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
53 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_NO \
54 (0x1 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
55 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART \
56 (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
57 #define ISPCCP2_SYSSTATUS (0x008)
58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
59 #define ISPCCP2_LC01_IRQENABLE (0x00C)
60 #define ISPCCP2_LC01_IRQSTATUS (0x010)
61 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
62 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
63 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
65 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
66 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
67 #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ BIT(4)
68 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ BIT(3)
69 #define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ BIT(2)
70 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ BIT(1)
71 #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ BIT(0)
73 #define ISPCCP2_LC23_IRQENABLE (0x014)
74 #define ISPCCP2_LC23_IRQSTATUS (0x018)
75 #define ISPCCP2_LCM_IRQENABLE (0x02C)
76 #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ BIT(0)
77 #define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ BIT(1)
78 #define ISPCCP2_LCM_IRQSTATUS (0x030)
79 #define ISPCCP2_CTRL (0x040)
80 #define ISPCCP2_CTRL_IF_EN BIT(0)
81 #define ISPCCP2_CTRL_PHY_SEL BIT(1)
82 #define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1)
83 #define ISPCCP2_CTRL_PHY_SEL_STROBE (1 << 1)
84 #define ISPCCP2_CTRL_PHY_SEL_MASK 0x1
85 #define ISPCCP2_CTRL_PHY_SEL_SHIFT 1
86 #define ISPCCP2_CTRL_IO_OUT_SEL BIT(2)
87 #define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1
88 #define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT 2
89 #define ISPCCP2_CTRL_MODE BIT(4)
90 #define ISPCCP2_CTRL_VP_CLK_FORCE_ON BIT(9)
91 #define ISPCCP2_CTRL_INV BIT(10)
92 #define ISPCCP2_CTRL_INV_MASK 0x1
93 #define ISPCCP2_CTRL_INV_SHIFT 10
94 #define ISPCCP2_CTRL_VP_ONLY_EN BIT(11)
95 #define ISPCCP2_CTRL_VP_CLK_POL BIT(12)
96 #define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1
97 #define ISPCCP2_CTRL_VP_CLK_POL_SHIFT 12
98 #define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15
99 #define ISPCCP2_CTRL_VPCLK_DIV_MASK 0x1ffff /* [31:15] */
100 #define ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT 8 /* 3430 bits */
101 #define ISPCCP2_CTRL_VP_OUT_CTRL_MASK 0x3 /* 3430 bits */
102 #define ISPCCP2_DBG (0x044)
103 #define ISPCCP2_GNQ (0x048)
104 #define ISPCCP2_LCx_CTRL(x) ((0x050)+0x30*(x))
105 #define ISPCCP2_LCx_CTRL_CHAN_EN BIT(0)
106 #define ISPCCP2_LCx_CTRL_CRC_EN BIT(19)
107 #define ISPCCP2_LCx_CTRL_CRC_MASK 0x1
108 #define ISPCCP2_LCx_CTRL_CRC_SHIFT 2
109 #define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0 19
110 #define ISPCCP2_LCx_CTRL_REGION_EN BIT(1)
111 #define ISPCCP2_LCx_CTRL_REGION_MASK 0x1
112 #define ISPCCP2_LCx_CTRL_REGION_SHIFT 1
113 #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 0x3f
114 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0 0x2
115 #define ISPCCP2_LCx_CTRL_FORMAT_MASK 0x1f
116 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT 0x3
117 #define ISPCCP2_LCx_CODE(x) ((0x054)+0x30*(x))
118 #define ISPCCP2_LCx_STAT_START(x) ((0x058)+0x30*(x))
119 #define ISPCCP2_LCx_STAT_SIZE(x) ((0x05C)+0x30*(x))
120 #define ISPCCP2_LCx_SOF_ADDR(x) ((0x060)+0x30*(x))
121 #define ISPCCP2_LCx_EOF_ADDR(x) ((0x064)+0x30*(x))
122 #define ISPCCP2_LCx_DAT_START(x) ((0x068)+0x30*(x))
123 #define ISPCCP2_LCx_DAT_SIZE(x) ((0x06C)+0x30*(x))
124 #define ISPCCP2_LCx_DAT_MASK 0xFFF
125 #define ISPCCP2_LCx_DAT_SHIFT 16
126 #define ISPCCP2_LCx_DAT_PING_ADDR(x) ((0x070)+0x30*(x))
127 #define ISPCCP2_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x))
128 #define ISPCCP2_LCx_DAT_OFST(x) ((0x078)+0x30*(x))
129 #define ISPCCP2_LCM_CTRL (0x1D0)
130 #define ISPCCP2_LCM_CTRL_CHAN_EN BIT(0)
131 #define ISPCCP2_LCM_CTRL_DST_PORT BIT(2)
132 #define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT 2
133 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT 3
134 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK 0x11
135 #define ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT 5
136 #define ISPCCP2_LCM_CTRL_BURST_SIZE_MASK 0x7
137 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT 16
138 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK 0x7
139 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT 20
140 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK 0x3
141 #define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED BIT(22)
142 #define ISPCCP2_LCM_CTRL_SRC_PACK BIT(23)
143 #define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT 24
144 #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK 0x7
145 #define ISPCCP2_LCM_VSIZE (0x1D4)
146 #define ISPCCP2_LCM_VSIZE_SHIFT 16
147 #define ISPCCP2_LCM_HSIZE (0x1D8)
148 #define ISPCCP2_LCM_HSIZE_SHIFT 16
149 #define ISPCCP2_LCM_PREFETCH (0x1DC)
150 #define ISPCCP2_LCM_PREFETCH_SHIFT 3
151 #define ISPCCP2_LCM_SRC_ADDR (0x1E0)
152 #define ISPCCP2_LCM_SRC_OFST (0x1E4)
153 #define ISPCCP2_LCM_DST_ADDR (0x1E8)
154 #define ISPCCP2_LCM_DST_OFST (0x1EC)
156 /* CCDC module register offset */
158 #define ISPCCDC_PID (0x000)
159 #define ISPCCDC_PCR (0x004)
160 #define ISPCCDC_SYN_MODE (0x008)
161 #define ISPCCDC_HD_VD_WID (0x00C)
162 #define ISPCCDC_PIX_LINES (0x010)
163 #define ISPCCDC_HORZ_INFO (0x014)
164 #define ISPCCDC_VERT_START (0x018)
165 #define ISPCCDC_VERT_LINES (0x01C)
166 #define ISPCCDC_CULLING (0x020)
167 #define ISPCCDC_HSIZE_OFF (0x024)
168 #define ISPCCDC_SDOFST (0x028)
169 #define ISPCCDC_SDR_ADDR (0x02C)
170 #define ISPCCDC_CLAMP (0x030)
171 #define ISPCCDC_DCSUB (0x034)
172 #define ISPCCDC_COLPTN (0x038)
173 #define ISPCCDC_BLKCMP (0x03C)
174 #define ISPCCDC_FPC (0x040)
175 #define ISPCCDC_FPC_ADDR (0x044)
176 #define ISPCCDC_VDINT (0x048)
177 #define ISPCCDC_ALAW (0x04C)
178 #define ISPCCDC_REC656IF (0x050)
179 #define ISPCCDC_CFG (0x054)
180 #define ISPCCDC_FMTCFG (0x058)
181 #define ISPCCDC_FMT_HORZ (0x05C)
182 #define ISPCCDC_FMT_VERT (0x060)
183 #define ISPCCDC_FMT_ADDR0 (0x064)
184 #define ISPCCDC_FMT_ADDR1 (0x068)
185 #define ISPCCDC_FMT_ADDR2 (0x06C)
186 #define ISPCCDC_FMT_ADDR3 (0x070)
187 #define ISPCCDC_FMT_ADDR4 (0x074)
188 #define ISPCCDC_FMT_ADDR5 (0x078)
189 #define ISPCCDC_FMT_ADDR6 (0x07C)
190 #define ISPCCDC_FMT_ADDR7 (0x080)
191 #define ISPCCDC_PRGEVEN0 (0x084)
192 #define ISPCCDC_PRGEVEN1 (0x088)
193 #define ISPCCDC_PRGODD0 (0x08C)
194 #define ISPCCDC_PRGODD1 (0x090)
195 #define ISPCCDC_VP_OUT (0x094)
197 #define ISPCCDC_LSC_CONFIG (0x098)
198 #define ISPCCDC_LSC_INITIAL (0x09C)
199 #define ISPCCDC_LSC_TABLE_BASE (0x0A0)
200 #define ISPCCDC_LSC_TABLE_OFFSET (0x0A4)
203 #define ISPSBL_PCR 0x4
204 #define ISPSBL_PCR_H3A_AEAWB_WBL_OVF BIT(16)
205 #define ISPSBL_PCR_H3A_AF_WBL_OVF BIT(17)
206 #define ISPSBL_PCR_RSZ4_WBL_OVF BIT(18)
207 #define ISPSBL_PCR_RSZ3_WBL_OVF BIT(19)
208 #define ISPSBL_PCR_RSZ2_WBL_OVF BIT(20)
209 #define ISPSBL_PCR_RSZ1_WBL_OVF BIT(21)
210 #define ISPSBL_PCR_PRV_WBL_OVF BIT(22)
211 #define ISPSBL_PCR_CCDC_WBL_OVF BIT(23)
212 #define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF BIT(24)
213 #define ISPSBL_PCR_CSIA_WBL_OVF BIT(25)
214 #define ISPSBL_PCR_CSIB_WBL_OVF BIT(26)
215 #define ISPSBL_CCDC_WR_0 (0x028)
216 #define ISPSBL_CCDC_WR_0_DATA_READY BIT(21)
217 #define ISPSBL_CCDC_WR_1 (0x02C)
218 #define ISPSBL_CCDC_WR_2 (0x030)
219 #define ISPSBL_CCDC_WR_3 (0x034)
221 #define ISPSBL_SDR_REQ_EXP 0xF8
222 #define ISPSBL_SDR_REQ_HIST_EXP_SHIFT 0
223 #define ISPSBL_SDR_REQ_HIST_EXP_MASK (0x3FF)
224 #define ISPSBL_SDR_REQ_RSZ_EXP_SHIFT 10
225 #define ISPSBL_SDR_REQ_RSZ_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_RSZ_EXP_SHIFT)
226 #define ISPSBL_SDR_REQ_PRV_EXP_SHIFT 20
227 #define ISPSBL_SDR_REQ_PRV_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_PRV_EXP_SHIFT)
229 /* Histogram registers */
230 #define ISPHIST_PID (0x000)
231 #define ISPHIST_PCR (0x004)
232 #define ISPHIST_CNT (0x008)
233 #define ISPHIST_WB_GAIN (0x00C)
234 #define ISPHIST_R0_HORZ (0x010)
235 #define ISPHIST_R0_VERT (0x014)
236 #define ISPHIST_R1_HORZ (0x018)
237 #define ISPHIST_R1_VERT (0x01C)
238 #define ISPHIST_R2_HORZ (0x020)
239 #define ISPHIST_R2_VERT (0x024)
240 #define ISPHIST_R3_HORZ (0x028)
241 #define ISPHIST_R3_VERT (0x02C)
242 #define ISPHIST_ADDR (0x030)
243 #define ISPHIST_DATA (0x034)
244 #define ISPHIST_RADD (0x038)
245 #define ISPHIST_RADD_OFF (0x03C)
246 #define ISPHIST_H_V_INFO (0x040)
248 /* H3A module registers */
249 #define ISPH3A_PID (0x000)
250 #define ISPH3A_PCR (0x004)
251 #define ISPH3A_AEWWIN1 (0x04C)
252 #define ISPH3A_AEWINSTART (0x050)
253 #define ISPH3A_AEWINBLK (0x054)
254 #define ISPH3A_AEWSUBWIN (0x058)
255 #define ISPH3A_AEWBUFST (0x05C)
256 #define ISPH3A_AFPAX1 (0x008)
257 #define ISPH3A_AFPAX2 (0x00C)
258 #define ISPH3A_AFPAXSTART (0x010)
259 #define ISPH3A_AFIIRSH (0x014)
260 #define ISPH3A_AFBUFST (0x018)
261 #define ISPH3A_AFCOEF010 (0x01C)
262 #define ISPH3A_AFCOEF032 (0x020)
263 #define ISPH3A_AFCOEF054 (0x024)
264 #define ISPH3A_AFCOEF076 (0x028)
265 #define ISPH3A_AFCOEF098 (0x02C)
266 #define ISPH3A_AFCOEF0010 (0x030)
267 #define ISPH3A_AFCOEF110 (0x034)
268 #define ISPH3A_AFCOEF132 (0x038)
269 #define ISPH3A_AFCOEF154 (0x03C)
270 #define ISPH3A_AFCOEF176 (0x040)
271 #define ISPH3A_AFCOEF198 (0x044)
272 #define ISPH3A_AFCOEF1010 (0x048)
274 #define ISPPRV_PCR (0x004)
275 #define ISPPRV_HORZ_INFO (0x008)
276 #define ISPPRV_VERT_INFO (0x00C)
277 #define ISPPRV_RSDR_ADDR (0x010)
278 #define ISPPRV_RADR_OFFSET (0x014)
279 #define ISPPRV_DSDR_ADDR (0x018)
280 #define ISPPRV_DRKF_OFFSET (0x01C)
281 #define ISPPRV_WSDR_ADDR (0x020)
282 #define ISPPRV_WADD_OFFSET (0x024)
283 #define ISPPRV_AVE (0x028)
284 #define ISPPRV_HMED (0x02C)
285 #define ISPPRV_NF (0x030)
286 #define ISPPRV_WB_DGAIN (0x034)
287 #define ISPPRV_WBGAIN (0x038)
288 #define ISPPRV_WBSEL (0x03C)
289 #define ISPPRV_CFA (0x040)
290 #define ISPPRV_BLKADJOFF (0x044)
291 #define ISPPRV_RGB_MAT1 (0x048)
292 #define ISPPRV_RGB_MAT2 (0x04C)
293 #define ISPPRV_RGB_MAT3 (0x050)
294 #define ISPPRV_RGB_MAT4 (0x054)
295 #define ISPPRV_RGB_MAT5 (0x058)
296 #define ISPPRV_RGB_OFF1 (0x05C)
297 #define ISPPRV_RGB_OFF2 (0x060)
298 #define ISPPRV_CSC0 (0x064)
299 #define ISPPRV_CSC1 (0x068)
300 #define ISPPRV_CSC2 (0x06C)
301 #define ISPPRV_CSC_OFFSET (0x070)
302 #define ISPPRV_CNT_BRT (0x074)
303 #define ISPPRV_CSUP (0x078)
304 #define ISPPRV_SETUP_YC (0x07C)
305 #define ISPPRV_SET_TBL_ADDR (0x080)
306 #define ISPPRV_SET_TBL_DATA (0x084)
307 #define ISPPRV_CDC_THR0 (0x090)
308 #define ISPPRV_CDC_THR1 (ISPPRV_CDC_THR0 + (0x4))
309 #define ISPPRV_CDC_THR2 (ISPPRV_CDC_THR0 + (0x4) * 2)
310 #define ISPPRV_CDC_THR3 (ISPPRV_CDC_THR0 + (0x4) * 3)
312 #define ISPPRV_REDGAMMA_TABLE_ADDR 0x0000
313 #define ISPPRV_GREENGAMMA_TABLE_ADDR 0x0400
314 #define ISPPRV_BLUEGAMMA_TABLE_ADDR 0x0800
315 #define ISPPRV_NF_TABLE_ADDR 0x0C00
316 #define ISPPRV_YENH_TABLE_ADDR 0x1000
317 #define ISPPRV_CFA_TABLE_ADDR 0x1400
319 #define ISPRSZ_MIN_OUTPUT 64
320 #define ISPRSZ_MAX_OUTPUT 3312
322 /* Resizer module register offset */
323 #define ISPRSZ_PID (0x000)
324 #define ISPRSZ_PCR (0x004)
325 #define ISPRSZ_CNT (0x008)
326 #define ISPRSZ_OUT_SIZE (0x00C)
327 #define ISPRSZ_IN_START (0x010)
328 #define ISPRSZ_IN_SIZE (0x014)
329 #define ISPRSZ_SDR_INADD (0x018)
330 #define ISPRSZ_SDR_INOFF (0x01C)
331 #define ISPRSZ_SDR_OUTADD (0x020)
332 #define ISPRSZ_SDR_OUTOFF (0x024)
333 #define ISPRSZ_HFILT10 (0x028)
334 #define ISPRSZ_HFILT32 (0x02C)
335 #define ISPRSZ_HFILT54 (0x030)
336 #define ISPRSZ_HFILT76 (0x034)
337 #define ISPRSZ_HFILT98 (0x038)
338 #define ISPRSZ_HFILT1110 (0x03C)
339 #define ISPRSZ_HFILT1312 (0x040)
340 #define ISPRSZ_HFILT1514 (0x044)
341 #define ISPRSZ_HFILT1716 (0x048)
342 #define ISPRSZ_HFILT1918 (0x04C)
343 #define ISPRSZ_HFILT2120 (0x050)
344 #define ISPRSZ_HFILT2322 (0x054)
345 #define ISPRSZ_HFILT2524 (0x058)
346 #define ISPRSZ_HFILT2726 (0x05C)
347 #define ISPRSZ_HFILT2928 (0x060)
348 #define ISPRSZ_HFILT3130 (0x064)
349 #define ISPRSZ_VFILT10 (0x068)
350 #define ISPRSZ_VFILT32 (0x06C)
351 #define ISPRSZ_VFILT54 (0x070)
352 #define ISPRSZ_VFILT76 (0x074)
353 #define ISPRSZ_VFILT98 (0x078)
354 #define ISPRSZ_VFILT1110 (0x07C)
355 #define ISPRSZ_VFILT1312 (0x080)
356 #define ISPRSZ_VFILT1514 (0x084)
357 #define ISPRSZ_VFILT1716 (0x088)
358 #define ISPRSZ_VFILT1918 (0x08C)
359 #define ISPRSZ_VFILT2120 (0x090)
360 #define ISPRSZ_VFILT2322 (0x094)
361 #define ISPRSZ_VFILT2524 (0x098)
362 #define ISPRSZ_VFILT2726 (0x09C)
363 #define ISPRSZ_VFILT2928 (0x0A0)
364 #define ISPRSZ_VFILT3130 (0x0A4)
365 #define ISPRSZ_YENH (0x0A8)
367 #define ISP_INT_CLR 0xFF113F11
368 #define ISPPRV_PCR_EN 1
369 #define ISPPRV_PCR_BUSY BIT(1)
370 #define ISPPRV_PCR_SOURCE BIT(2)
371 #define ISPPRV_PCR_ONESHOT BIT(3)
372 #define ISPPRV_PCR_WIDTH BIT(4)
373 #define ISPPRV_PCR_INVALAW BIT(5)
374 #define ISPPRV_PCR_DRKFEN BIT(6)
375 #define ISPPRV_PCR_DRKFCAP BIT(7)
376 #define ISPPRV_PCR_HMEDEN BIT(8)
377 #define ISPPRV_PCR_NFEN BIT(9)
378 #define ISPPRV_PCR_CFAEN BIT(10)
379 #define ISPPRV_PCR_CFAFMT_SHIFT 11
380 #define ISPPRV_PCR_CFAFMT_MASK 0x7800
381 #define ISPPRV_PCR_CFAFMT_BAYER (0 << 11)
382 #define ISPPRV_PCR_CFAFMT_SONYVGA (1 << 11)
383 #define ISPPRV_PCR_CFAFMT_RGBFOVEON (2 << 11)
384 #define ISPPRV_PCR_CFAFMT_DNSPL (3 << 11)
385 #define ISPPRV_PCR_CFAFMT_HONEYCOMB (4 << 11)
386 #define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON (5 << 11)
387 #define ISPPRV_PCR_YNENHEN BIT(15)
388 #define ISPPRV_PCR_SUPEN BIT(16)
389 #define ISPPRV_PCR_YCPOS_SHIFT 17
390 #define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17)
391 #define ISPPRV_PCR_YCPOS_YCbYCr (1 << 17)
392 #define ISPPRV_PCR_YCPOS_CbYCrY (2 << 17)
393 #define ISPPRV_PCR_YCPOS_CrYCbY (3 << 17)
394 #define ISPPRV_PCR_RSZPORT BIT(19)
395 #define ISPPRV_PCR_SDRPORT BIT(20)
396 #define ISPPRV_PCR_SCOMP_EN BIT(21)
397 #define ISPPRV_PCR_SCOMP_SFT_SHIFT (22)
398 #define ISPPRV_PCR_SCOMP_SFT_MASK (7 << 22)
399 #define ISPPRV_PCR_GAMMA_BYPASS BIT(26)
400 #define ISPPRV_PCR_DCOREN BIT(27)
401 #define ISPPRV_PCR_DCCOUP BIT(28)
402 #define ISPPRV_PCR_DRK_FAIL BIT(31)
404 #define ISPPRV_HORZ_INFO_EPH_SHIFT 0
405 #define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff
406 #define ISPPRV_HORZ_INFO_SPH_SHIFT 16
407 #define ISPPRV_HORZ_INFO_SPH_MASK 0x3fff0
409 #define ISPPRV_VERT_INFO_ELV_SHIFT 0
410 #define ISPPRV_VERT_INFO_ELV_MASK 0x3fff
411 #define ISPPRV_VERT_INFO_SLV_SHIFT 16
412 #define ISPPRV_VERT_INFO_SLV_MASK 0x3fff0
414 #define ISPPRV_AVE_EVENDIST_SHIFT 2
415 #define ISPPRV_AVE_EVENDIST_1 0x0
416 #define ISPPRV_AVE_EVENDIST_2 0x1
417 #define ISPPRV_AVE_EVENDIST_3 0x2
418 #define ISPPRV_AVE_EVENDIST_4 0x3
419 #define ISPPRV_AVE_ODDDIST_SHIFT 4
420 #define ISPPRV_AVE_ODDDIST_1 0x0
421 #define ISPPRV_AVE_ODDDIST_2 0x1
422 #define ISPPRV_AVE_ODDDIST_3 0x2
423 #define ISPPRV_AVE_ODDDIST_4 0x3
425 #define ISPPRV_HMED_THRESHOLD_SHIFT 0
426 #define ISPPRV_HMED_EVENDIST BIT(8)
427 #define ISPPRV_HMED_ODDDIST BIT(9)
429 #define ISPPRV_WBGAIN_COEF0_SHIFT 0
430 #define ISPPRV_WBGAIN_COEF1_SHIFT 8
431 #define ISPPRV_WBGAIN_COEF2_SHIFT 16
432 #define ISPPRV_WBGAIN_COEF3_SHIFT 24
434 #define ISPPRV_WBSEL_COEF0 0x0
435 #define ISPPRV_WBSEL_COEF1 0x1
436 #define ISPPRV_WBSEL_COEF2 0x2
437 #define ISPPRV_WBSEL_COEF3 0x3
439 #define ISPPRV_WBSEL_N0_0_SHIFT 0
440 #define ISPPRV_WBSEL_N0_1_SHIFT 2
441 #define ISPPRV_WBSEL_N0_2_SHIFT 4
442 #define ISPPRV_WBSEL_N0_3_SHIFT 6
443 #define ISPPRV_WBSEL_N1_0_SHIFT 8
444 #define ISPPRV_WBSEL_N1_1_SHIFT 10
445 #define ISPPRV_WBSEL_N1_2_SHIFT 12
446 #define ISPPRV_WBSEL_N1_3_SHIFT 14
447 #define ISPPRV_WBSEL_N2_0_SHIFT 16
448 #define ISPPRV_WBSEL_N2_1_SHIFT 18
449 #define ISPPRV_WBSEL_N2_2_SHIFT 20
450 #define ISPPRV_WBSEL_N2_3_SHIFT 22
451 #define ISPPRV_WBSEL_N3_0_SHIFT 24
452 #define ISPPRV_WBSEL_N3_1_SHIFT 26
453 #define ISPPRV_WBSEL_N3_2_SHIFT 28
454 #define ISPPRV_WBSEL_N3_3_SHIFT 30
456 #define ISPPRV_CFA_GRADTH_HOR_SHIFT 0
457 #define ISPPRV_CFA_GRADTH_VER_SHIFT 8
459 #define ISPPRV_BLKADJOFF_B_SHIFT 0
460 #define ISPPRV_BLKADJOFF_G_SHIFT 8
461 #define ISPPRV_BLKADJOFF_R_SHIFT 16
463 #define ISPPRV_RGB_MAT1_MTX_RR_SHIFT 0
464 #define ISPPRV_RGB_MAT1_MTX_GR_SHIFT 16
466 #define ISPPRV_RGB_MAT2_MTX_BR_SHIFT 0
467 #define ISPPRV_RGB_MAT2_MTX_RG_SHIFT 16
469 #define ISPPRV_RGB_MAT3_MTX_GG_SHIFT 0
470 #define ISPPRV_RGB_MAT3_MTX_BG_SHIFT 16
472 #define ISPPRV_RGB_MAT4_MTX_RB_SHIFT 0
473 #define ISPPRV_RGB_MAT4_MTX_GB_SHIFT 16
475 #define ISPPRV_RGB_MAT5_MTX_BB_SHIFT 0
477 #define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT 0
478 #define ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT 16
480 #define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT 0
482 #define ISPPRV_CSC0_RY_SHIFT 0
483 #define ISPPRV_CSC0_GY_SHIFT 10
484 #define ISPPRV_CSC0_BY_SHIFT 20
486 #define ISPPRV_CSC1_RCB_SHIFT 0
487 #define ISPPRV_CSC1_GCB_SHIFT 10
488 #define ISPPRV_CSC1_BCB_SHIFT 20
490 #define ISPPRV_CSC2_RCR_SHIFT 0
491 #define ISPPRV_CSC2_GCR_SHIFT 10
492 #define ISPPRV_CSC2_BCR_SHIFT 20
494 #define ISPPRV_CSC_OFFSET_CR_SHIFT 0
495 #define ISPPRV_CSC_OFFSET_CB_SHIFT 8
496 #define ISPPRV_CSC_OFFSET_Y_SHIFT 16
498 #define ISPPRV_CNT_BRT_BRT_SHIFT 0
499 #define ISPPRV_CNT_BRT_CNT_SHIFT 8
501 #define ISPPRV_CONTRAST_MAX 0x10
502 #define ISPPRV_CONTRAST_MIN 0xFF
503 #define ISPPRV_BRIGHT_MIN 0x00
504 #define ISPPRV_BRIGHT_MAX 0xFF
506 #define ISPPRV_CSUP_CSUPG_SHIFT 0
507 #define ISPPRV_CSUP_THRES_SHIFT 8
508 #define ISPPRV_CSUP_HPYF_SHIFT 16
510 #define ISPPRV_SETUP_YC_MINC_SHIFT 0
511 #define ISPPRV_SETUP_YC_MAXC_SHIFT 8
512 #define ISPPRV_SETUP_YC_MINY_SHIFT 16
513 #define ISPPRV_SETUP_YC_MAXY_SHIFT 24
514 #define ISPPRV_YC_MAX 0xFF
515 #define ISPPRV_YC_MIN 0x0
517 /* Define bit fields within selected registers */
518 #define ISP_REVISION_SHIFT 0
520 #define ISP_SYSCONFIG_AUTOIDLE BIT(0)
521 #define ISP_SYSCONFIG_SOFTRESET BIT(1)
522 #define ISP_SYSCONFIG_MIDLEMODE_SHIFT 12
523 #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0
524 #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1
525 #define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x2
527 #define ISP_SYSSTATUS_RESETDONE 0
529 #define IRQ0ENABLE_CSIA_IRQ BIT(0)
530 #define IRQ0ENABLE_CSIC_IRQ BIT(1)
531 #define IRQ0ENABLE_CCP2_LCM_IRQ BIT(3)
532 #define IRQ0ENABLE_CCP2_LC0_IRQ BIT(4)
533 #define IRQ0ENABLE_CCP2_LC1_IRQ BIT(5)
534 #define IRQ0ENABLE_CCP2_LC2_IRQ BIT(6)
535 #define IRQ0ENABLE_CCP2_LC3_IRQ BIT(7)
536 #define IRQ0ENABLE_CSIB_IRQ (IRQ0ENABLE_CCP2_LCM_IRQ | \
537 IRQ0ENABLE_CCP2_LC0_IRQ | \
538 IRQ0ENABLE_CCP2_LC1_IRQ | \
539 IRQ0ENABLE_CCP2_LC2_IRQ | \
540 IRQ0ENABLE_CCP2_LC3_IRQ)
542 #define IRQ0ENABLE_CCDC_VD0_IRQ BIT(8)
543 #define IRQ0ENABLE_CCDC_VD1_IRQ BIT(9)
544 #define IRQ0ENABLE_CCDC_VD2_IRQ BIT(10)
545 #define IRQ0ENABLE_CCDC_ERR_IRQ BIT(11)
546 #define IRQ0ENABLE_H3A_AF_DONE_IRQ BIT(12)
547 #define IRQ0ENABLE_H3A_AWB_DONE_IRQ BIT(13)
548 #define IRQ0ENABLE_HIST_DONE_IRQ BIT(16)
549 #define IRQ0ENABLE_CCDC_LSC_DONE_IRQ BIT(17)
550 #define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ BIT(18)
551 #define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ BIT(19)
552 #define IRQ0ENABLE_PRV_DONE_IRQ BIT(20)
553 #define IRQ0ENABLE_RSZ_DONE_IRQ BIT(24)
554 #define IRQ0ENABLE_OVF_IRQ BIT(25)
555 #define IRQ0ENABLE_PING_IRQ BIT(26)
556 #define IRQ0ENABLE_PONG_IRQ BIT(27)
557 #define IRQ0ENABLE_MMU_ERR_IRQ BIT(28)
558 #define IRQ0ENABLE_OCP_ERR_IRQ BIT(29)
559 #define IRQ0ENABLE_SEC_ERR_IRQ BIT(30)
560 #define IRQ0ENABLE_HS_VS_IRQ BIT(31)
562 #define IRQ0STATUS_CSIA_IRQ BIT(0)
563 #define IRQ0STATUS_CSI2C_IRQ BIT(1)
564 #define IRQ0STATUS_CCP2_LCM_IRQ BIT(3)
565 #define IRQ0STATUS_CCP2_LC0_IRQ BIT(4)
566 #define IRQ0STATUS_CSIB_IRQ (IRQ0STATUS_CCP2_LCM_IRQ | \
567 IRQ0STATUS_CCP2_LC0_IRQ)
569 #define IRQ0STATUS_CSIB_LC1_IRQ BIT(5)
570 #define IRQ0STATUS_CSIB_LC2_IRQ BIT(6)
571 #define IRQ0STATUS_CSIB_LC3_IRQ BIT(7)
572 #define IRQ0STATUS_CCDC_VD0_IRQ BIT(8)
573 #define IRQ0STATUS_CCDC_VD1_IRQ BIT(9)
574 #define IRQ0STATUS_CCDC_VD2_IRQ BIT(10)
575 #define IRQ0STATUS_CCDC_ERR_IRQ BIT(11)
576 #define IRQ0STATUS_H3A_AF_DONE_IRQ BIT(12)
577 #define IRQ0STATUS_H3A_AWB_DONE_IRQ BIT(13)
578 #define IRQ0STATUS_HIST_DONE_IRQ BIT(16)
579 #define IRQ0STATUS_CCDC_LSC_DONE_IRQ BIT(17)
580 #define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ BIT(18)
581 #define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ BIT(19)
582 #define IRQ0STATUS_PRV_DONE_IRQ BIT(20)
583 #define IRQ0STATUS_RSZ_DONE_IRQ BIT(24)
584 #define IRQ0STATUS_OVF_IRQ BIT(25)
585 #define IRQ0STATUS_PING_IRQ BIT(26)
586 #define IRQ0STATUS_PONG_IRQ BIT(27)
587 #define IRQ0STATUS_MMU_ERR_IRQ BIT(28)
588 #define IRQ0STATUS_OCP_ERR_IRQ BIT(29)
589 #define IRQ0STATUS_SEC_ERR_IRQ BIT(30)
590 #define IRQ0STATUS_HS_VS_IRQ BIT(31)
592 #define TCTRL_GRESET_LEN 0
594 #define TCTRL_PSTRB_REPLAY_DELAY 0
595 #define TCTRL_PSTRB_REPLAY_COUNTER_SHIFT 25
597 #define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL 0x0
598 #define ISPCTRL_PAR_SER_CLK_SEL_CSIA 0x1
599 #define ISPCTRL_PAR_SER_CLK_SEL_CSIB 0x2
600 #define ISPCTRL_PAR_SER_CLK_SEL_CSIC 0x3
601 #define ISPCTRL_PAR_SER_CLK_SEL_MASK 0x3
603 #define ISPCTRL_PAR_BRIDGE_SHIFT 2
604 #define ISPCTRL_PAR_BRIDGE_DISABLE (0x0 << 2)
605 #define ISPCTRL_PAR_BRIDGE_LENDIAN (0x2 << 2)
606 #define ISPCTRL_PAR_BRIDGE_BENDIAN (0x3 << 2)
607 #define ISPCTRL_PAR_BRIDGE_MASK (0x3 << 2)
609 #define ISPCTRL_PAR_CLK_POL_SHIFT 4
610 #define ISPCTRL_PAR_CLK_POL_INV BIT(4)
611 #define ISPCTRL_PING_PONG_EN BIT(5)
612 #define ISPCTRL_SHIFT_SHIFT 6
613 #define ISPCTRL_SHIFT_0 (0x0 << 6)
614 #define ISPCTRL_SHIFT_2 (0x1 << 6)
615 #define ISPCTRL_SHIFT_4 (0x2 << 6)
616 #define ISPCTRL_SHIFT_MASK (0x3 << 6)
618 #define ISPCTRL_CCDC_CLK_EN BIT(8)
619 #define ISPCTRL_SCMP_CLK_EN BIT(9)
620 #define ISPCTRL_H3A_CLK_EN BIT(10)
621 #define ISPCTRL_HIST_CLK_EN BIT(11)
622 #define ISPCTRL_PREV_CLK_EN BIT(12)
623 #define ISPCTRL_RSZ_CLK_EN BIT(13)
624 #define ISPCTRL_SYNC_DETECT_SHIFT 14
625 #define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
626 #define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
627 #define ISPCTRL_SYNC_DETECT_VSFALL (0x2 << ISPCTRL_SYNC_DETECT_SHIFT)
628 #define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
629 #define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
631 #define ISPCTRL_CCDC_RAM_EN BIT(16)
632 #define ISPCTRL_PREV_RAM_EN BIT(17)
633 #define ISPCTRL_SBL_RD_RAM_EN BIT(18)
634 #define ISPCTRL_SBL_WR1_RAM_EN BIT(19)
635 #define ISPCTRL_SBL_WR0_RAM_EN BIT(20)
636 #define ISPCTRL_SBL_AUTOIDLE BIT(21)
637 #define ISPCTRL_SBL_SHARED_WPORTC BIT(26)
638 #define ISPCTRL_SBL_SHARED_RPORTA BIT(27)
639 #define ISPCTRL_SBL_SHARED_RPORTB BIT(28)
640 #define ISPCTRL_JPEG_FLUSH BIT(30)
641 #define ISPCTRL_CCDC_FLUSH BIT(31)
643 #define ISPSECURE_SECUREMODE 0
645 #define ISPTCTRL_CTRL_DIV_LOW 0x0
646 #define ISPTCTRL_CTRL_DIV_HIGH 0x1
647 #define ISPTCTRL_CTRL_DIV_BYPASS 0x1F
649 #define ISPTCTRL_CTRL_DIVA_SHIFT 0
650 #define ISPTCTRL_CTRL_DIVA_MASK (0x1F << ISPTCTRL_CTRL_DIVA_SHIFT)
652 #define ISPTCTRL_CTRL_DIVB_SHIFT 5
653 #define ISPTCTRL_CTRL_DIVB_MASK (0x1F << ISPTCTRL_CTRL_DIVB_SHIFT)
655 #define ISPTCTRL_CTRL_DIVC_SHIFT 10
656 #define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10)
658 #define ISPTCTRL_CTRL_SHUTEN BIT(21)
659 #define ISPTCTRL_CTRL_PSTRBEN BIT(22)
660 #define ISPTCTRL_CTRL_STRBEN BIT(23)
661 #define ISPTCTRL_CTRL_SHUTPOL BIT(24)
662 #define ISPTCTRL_CTRL_STRBPSTRBPOL BIT(26)
664 #define ISPTCTRL_CTRL_INSEL_SHIFT 27
665 #define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27)
666 #define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27)
667 #define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27)
669 #define ISPTCTRL_CTRL_GRESETEn BIT(29)
670 #define ISPTCTRL_CTRL_GRESETPOL BIT(30)
671 #define ISPTCTRL_CTRL_GRESETDIR BIT(31)
673 #define ISPTCTRL_FRAME_SHUT_SHIFT 0
674 #define ISPTCTRL_FRAME_PSTRB_SHIFT 6
675 #define ISPTCTRL_FRAME_STRB_SHIFT 12
677 #define ISPCCDC_PID_PREV_SHIFT 0
678 #define ISPCCDC_PID_CID_SHIFT 8
679 #define ISPCCDC_PID_TID_SHIFT 16
681 #define ISPCCDC_PCR_EN 1
682 #define ISPCCDC_PCR_BUSY BIT(1)
684 #define ISPCCDC_SYN_MODE_VDHDOUT 0x1
685 #define ISPCCDC_SYN_MODE_FLDOUT BIT(1)
686 #define ISPCCDC_SYN_MODE_VDPOL BIT(2)
687 #define ISPCCDC_SYN_MODE_HDPOL BIT(3)
688 #define ISPCCDC_SYN_MODE_FLDPOL BIT(4)
689 #define ISPCCDC_SYN_MODE_EXWEN BIT(5)
690 #define ISPCCDC_SYN_MODE_DATAPOL BIT(6)
691 #define ISPCCDC_SYN_MODE_FLDMODE BIT(7)
692 #define ISPCCDC_SYN_MODE_DATSIZ_MASK (0x7 << 8)
693 #define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8)
694 #define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8)
695 #define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8)
696 #define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8)
697 #define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8)
698 #define ISPCCDC_SYN_MODE_PACK8 BIT(11)
699 #define ISPCCDC_SYN_MODE_INPMOD_MASK (3 << 12)
700 #define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12)
701 #define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 (1 << 12)
702 #define ISPCCDC_SYN_MODE_INPMOD_YCBCR8 (2 << 12)
703 #define ISPCCDC_SYN_MODE_LPF BIT(14)
704 #define ISPCCDC_SYN_MODE_FLDSTAT BIT(15)
705 #define ISPCCDC_SYN_MODE_VDHDEN BIT(16)
706 #define ISPCCDC_SYN_MODE_WEN BIT(17)
707 #define ISPCCDC_SYN_MODE_VP2SDR BIT(18)
708 #define ISPCCDC_SYN_MODE_SDR2RSZ BIT(19)
710 #define ISPCCDC_HD_VD_WID_VDW_SHIFT 0
711 #define ISPCCDC_HD_VD_WID_HDW_SHIFT 16
713 #define ISPCCDC_PIX_LINES_HLPRF_SHIFT 0
714 #define ISPCCDC_PIX_LINES_PPLN_SHIFT 16
716 #define ISPCCDC_HORZ_INFO_NPH_SHIFT 0
717 #define ISPCCDC_HORZ_INFO_NPH_MASK 0x00007fff
718 #define ISPCCDC_HORZ_INFO_SPH_SHIFT 16
719 #define ISPCCDC_HORZ_INFO_SPH_MASK 0x7fff0000
721 #define ISPCCDC_VERT_START_SLV1_SHIFT 0
722 #define ISPCCDC_VERT_START_SLV0_SHIFT 16
723 #define ISPCCDC_VERT_START_SLV0_MASK 0x7fff0000
725 #define ISPCCDC_VERT_LINES_NLV_SHIFT 0
726 #define ISPCCDC_VERT_LINES_NLV_MASK 0x00007fff
728 #define ISPCCDC_CULLING_CULV_SHIFT 0
729 #define ISPCCDC_CULLING_CULHODD_SHIFT 16
730 #define ISPCCDC_CULLING_CULHEVN_SHIFT 24
732 #define ISPCCDC_HSIZE_OFF_SHIFT 0
734 #define ISPCCDC_SDOFST_FIINV BIT(14)
735 #define ISPCCDC_SDOFST_FOFST_SHIFT 12
736 #define ISPCCDC_SDOFST_FOFST_MASK (3 << 12)
737 #define ISPCCDC_SDOFST_LOFST3_SHIFT 0
738 #define ISPCCDC_SDOFST_LOFST2_SHIFT 3
739 #define ISPCCDC_SDOFST_LOFST1_SHIFT 6
740 #define ISPCCDC_SDOFST_LOFST0_SHIFT 9
742 #define ISPCCDC_CLAMP_OBGAIN_SHIFT 0
743 #define ISPCCDC_CLAMP_OBST_SHIFT 10
744 #define ISPCCDC_CLAMP_OBSLN_SHIFT 25
745 #define ISPCCDC_CLAMP_OBSLEN_SHIFT 28
746 #define ISPCCDC_CLAMP_CLAMPEN BIT(31)
748 #define ISPCCDC_COLPTN_R_Ye 0x0
749 #define ISPCCDC_COLPTN_Gr_Cy 0x1
750 #define ISPCCDC_COLPTN_Gb_G 0x2
751 #define ISPCCDC_COLPTN_B_Mg 0x3
752 #define ISPCCDC_COLPTN_CP0PLC0_SHIFT 0
753 #define ISPCCDC_COLPTN_CP0PLC1_SHIFT 2
754 #define ISPCCDC_COLPTN_CP0PLC2_SHIFT 4
755 #define ISPCCDC_COLPTN_CP0PLC3_SHIFT 6
756 #define ISPCCDC_COLPTN_CP1PLC0_SHIFT 8
757 #define ISPCCDC_COLPTN_CP1PLC1_SHIFT 10
758 #define ISPCCDC_COLPTN_CP1PLC2_SHIFT 12
759 #define ISPCCDC_COLPTN_CP1PLC3_SHIFT 14
760 #define ISPCCDC_COLPTN_CP2PLC0_SHIFT 16
761 #define ISPCCDC_COLPTN_CP2PLC1_SHIFT 18
762 #define ISPCCDC_COLPTN_CP2PLC2_SHIFT 20
763 #define ISPCCDC_COLPTN_CP2PLC3_SHIFT 22
764 #define ISPCCDC_COLPTN_CP3PLC0_SHIFT 24
765 #define ISPCCDC_COLPTN_CP3PLC1_SHIFT 26
766 #define ISPCCDC_COLPTN_CP3PLC2_SHIFT 28
767 #define ISPCCDC_COLPTN_CP3PLC3_SHIFT 30
769 #define ISPCCDC_BLKCMP_B_MG_SHIFT 0
770 #define ISPCCDC_BLKCMP_GB_G_SHIFT 8
771 #define ISPCCDC_BLKCMP_GR_CY_SHIFT 16
772 #define ISPCCDC_BLKCMP_R_YE_SHIFT 24
774 #define ISPCCDC_FPC_FPNUM_SHIFT 0
775 #define ISPCCDC_FPC_FPCEN BIT(15)
776 #define ISPCCDC_FPC_FPERR BIT(16)
778 #define ISPCCDC_VDINT_1_SHIFT 0
779 #define ISPCCDC_VDINT_1_MASK 0x00007fff
780 #define ISPCCDC_VDINT_0_SHIFT 16
781 #define ISPCCDC_VDINT_0_MASK 0x7fff0000
783 #define ISPCCDC_ALAW_GWDI_12_3 (0x3 << 0)
784 #define ISPCCDC_ALAW_GWDI_11_2 (0x4 << 0)
785 #define ISPCCDC_ALAW_GWDI_10_1 (0x5 << 0)
786 #define ISPCCDC_ALAW_GWDI_9_0 (0x6 << 0)
787 #define ISPCCDC_ALAW_CCDTBL BIT(3)
789 #define ISPCCDC_REC656IF_R656ON 1
790 #define ISPCCDC_REC656IF_ECCFVH BIT(1)
792 #define ISPCCDC_CFG_BW656 BIT(5)
793 #define ISPCCDC_CFG_FIDMD_SHIFT 6
794 #define ISPCCDC_CFG_WENLOG BIT(8)
795 #define ISPCCDC_CFG_WENLOG_AND (0 << 8)
796 #define ISPCCDC_CFG_WENLOG_OR (1 << 8)
797 #define ISPCCDC_CFG_Y8POS BIT(11)
798 #define ISPCCDC_CFG_BSWD BIT(12)
799 #define ISPCCDC_CFG_MSBINVI BIT(13)
800 #define ISPCCDC_CFG_VDLC BIT(15)
802 #define ISPCCDC_FMTCFG_FMTEN 0x1
803 #define ISPCCDC_FMTCFG_LNALT BIT(1)
804 #define ISPCCDC_FMTCFG_LNUM_SHIFT 2
805 #define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT 4
806 #define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT 8
807 #define ISPCCDC_FMTCFG_VPIN_MASK 0x00007000
808 #define ISPCCDC_FMTCFG_VPIN_12_3 (0x3 << 12)
809 #define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12)
810 #define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12)
811 #define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12)
812 #define ISPCCDC_FMTCFG_VPEN BIT(15)
814 #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK 0x003f0000
815 #define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT 16
816 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY2 (0x0 << 16)
817 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY3 (0x1 << 16)
818 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY4 (0x2 << 16)
819 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY5 (0x3 << 16)
820 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY6 (0x4 << 16)
822 #define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT 0
823 #define ISPCCDC_FMT_HORZ_FMTSPH_SHIFT 16
825 #define ISPCCDC_FMT_VERT_FMTLNV_SHIFT 0
826 #define ISPCCDC_FMT_VERT_FMTSLV_SHIFT 16
828 #define ISPCCDC_FMT_HORZ_FMTSPH_MASK 0x1fff0000
829 #define ISPCCDC_FMT_HORZ_FMTLNH_MASK 0x00001fff
831 #define ISPCCDC_FMT_VERT_FMTSLV_MASK 0x1fff0000
832 #define ISPCCDC_FMT_VERT_FMTLNV_MASK 0x00001fff
834 #define ISPCCDC_VP_OUT_HORZ_ST_SHIFT 0
835 #define ISPCCDC_VP_OUT_HORZ_NUM_SHIFT 4
836 #define ISPCCDC_VP_OUT_VERT_NUM_SHIFT 17
838 #define ISPRSZ_PID_PREV_SHIFT 0
839 #define ISPRSZ_PID_CID_SHIFT 8
840 #define ISPRSZ_PID_TID_SHIFT 16
842 #define ISPRSZ_PCR_ENABLE BIT(0)
843 #define ISPRSZ_PCR_BUSY BIT(1)
844 #define ISPRSZ_PCR_ONESHOT BIT(2)
846 #define ISPRSZ_CNT_HRSZ_SHIFT 0
847 #define ISPRSZ_CNT_HRSZ_MASK \
848 (0x3FF << ISPRSZ_CNT_HRSZ_SHIFT)
849 #define ISPRSZ_CNT_VRSZ_SHIFT 10
850 #define ISPRSZ_CNT_VRSZ_MASK \
851 (0x3FF << ISPRSZ_CNT_VRSZ_SHIFT)
852 #define ISPRSZ_CNT_HSTPH_SHIFT 20
853 #define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT)
854 #define ISPRSZ_CNT_VSTPH_SHIFT 23
855 #define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT)
856 #define ISPRSZ_CNT_YCPOS BIT(26)
857 #define ISPRSZ_CNT_INPTYP BIT(27)
858 #define ISPRSZ_CNT_INPSRC BIT(28)
859 #define ISPRSZ_CNT_CBILIN BIT(29)
861 #define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0
862 #define ISPRSZ_OUT_SIZE_HORZ_MASK \
863 (0xFFF << ISPRSZ_OUT_SIZE_HORZ_SHIFT)
864 #define ISPRSZ_OUT_SIZE_VERT_SHIFT 16
865 #define ISPRSZ_OUT_SIZE_VERT_MASK \
866 (0xFFF << ISPRSZ_OUT_SIZE_VERT_SHIFT)
868 #define ISPRSZ_IN_START_HORZ_ST_SHIFT 0
869 #define ISPRSZ_IN_START_HORZ_ST_MASK \
870 (0x1FFF << ISPRSZ_IN_START_HORZ_ST_SHIFT)
871 #define ISPRSZ_IN_START_VERT_ST_SHIFT 16
872 #define ISPRSZ_IN_START_VERT_ST_MASK \
873 (0x1FFF << ISPRSZ_IN_START_VERT_ST_SHIFT)
875 #define ISPRSZ_IN_SIZE_HORZ_SHIFT 0
876 #define ISPRSZ_IN_SIZE_HORZ_MASK \
877 (0x1FFF << ISPRSZ_IN_SIZE_HORZ_SHIFT)
878 #define ISPRSZ_IN_SIZE_VERT_SHIFT 16
879 #define ISPRSZ_IN_SIZE_VERT_MASK \
880 (0x1FFF << ISPRSZ_IN_SIZE_VERT_SHIFT)
882 #define ISPRSZ_SDR_INADD_ADDR_SHIFT 0
883 #define ISPRSZ_SDR_INADD_ADDR_MASK 0xFFFFFFFF
885 #define ISPRSZ_SDR_INOFF_OFFSET_SHIFT 0
886 #define ISPRSZ_SDR_INOFF_OFFSET_MASK \
887 (0xFFFF << ISPRSZ_SDR_INOFF_OFFSET_SHIFT)
889 #define ISPRSZ_SDR_OUTADD_ADDR_SHIFT 0
890 #define ISPRSZ_SDR_OUTADD_ADDR_MASK 0xFFFFFFFF
893 #define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT 0
894 #define ISPRSZ_SDR_OUTOFF_OFFSET_MASK \
895 (0xFFFF << ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT)
897 #define ISPRSZ_HFILT_COEF0_SHIFT 0
898 #define ISPRSZ_HFILT_COEF0_MASK \
899 (0x3FF << ISPRSZ_HFILT_COEF0_SHIFT)
900 #define ISPRSZ_HFILT_COEF1_SHIFT 16
901 #define ISPRSZ_HFILT_COEF1_MASK \
902 (0x3FF << ISPRSZ_HFILT_COEF1_SHIFT)
904 #define ISPRSZ_HFILT32_COEF2_SHIFT 0
905 #define ISPRSZ_HFILT32_COEF2_MASK 0x3FF
906 #define ISPRSZ_HFILT32_COEF3_SHIFT 16
907 #define ISPRSZ_HFILT32_COEF3_MASK 0x3FF0000
909 #define ISPRSZ_HFILT54_COEF4_SHIFT 0
910 #define ISPRSZ_HFILT54_COEF4_MASK 0x3FF
911 #define ISPRSZ_HFILT54_COEF5_SHIFT 16
912 #define ISPRSZ_HFILT54_COEF5_MASK 0x3FF0000
914 #define ISPRSZ_HFILT76_COEFF6_SHIFT 0
915 #define ISPRSZ_HFILT76_COEFF6_MASK 0x3FF
916 #define ISPRSZ_HFILT76_COEFF7_SHIFT 16
917 #define ISPRSZ_HFILT76_COEFF7_MASK 0x3FF0000
919 #define ISPRSZ_HFILT98_COEFF8_SHIFT 0
920 #define ISPRSZ_HFILT98_COEFF8_MASK 0x3FF
921 #define ISPRSZ_HFILT98_COEFF9_SHIFT 16
922 #define ISPRSZ_HFILT98_COEFF9_MASK 0x3FF0000
924 #define ISPRSZ_HFILT1110_COEF10_SHIFT 0
925 #define ISPRSZ_HFILT1110_COEF10_MASK 0x3FF
926 #define ISPRSZ_HFILT1110_COEF11_SHIFT 16
927 #define ISPRSZ_HFILT1110_COEF11_MASK 0x3FF0000
929 #define ISPRSZ_HFILT1312_COEFF12_SHIFT 0
930 #define ISPRSZ_HFILT1312_COEFF12_MASK 0x3FF
931 #define ISPRSZ_HFILT1312_COEFF13_SHIFT 16
932 #define ISPRSZ_HFILT1312_COEFF13_MASK 0x3FF0000
934 #define ISPRSZ_HFILT1514_COEFF14_SHIFT 0
935 #define ISPRSZ_HFILT1514_COEFF14_MASK 0x3FF
936 #define ISPRSZ_HFILT1514_COEFF15_SHIFT 16
937 #define ISPRSZ_HFILT1514_COEFF15_MASK 0x3FF0000
939 #define ISPRSZ_HFILT1716_COEF16_SHIFT 0
940 #define ISPRSZ_HFILT1716_COEF16_MASK 0x3FF
941 #define ISPRSZ_HFILT1716_COEF17_SHIFT 16
942 #define ISPRSZ_HFILT1716_COEF17_MASK 0x3FF0000
944 #define ISPRSZ_HFILT1918_COEF18_SHIFT 0
945 #define ISPRSZ_HFILT1918_COEF18_MASK 0x3FF
946 #define ISPRSZ_HFILT1918_COEF19_SHIFT 16
947 #define ISPRSZ_HFILT1918_COEF19_MASK 0x3FF0000
949 #define ISPRSZ_HFILT2120_COEF20_SHIFT 0
950 #define ISPRSZ_HFILT2120_COEF20_MASK 0x3FF
951 #define ISPRSZ_HFILT2120_COEF21_SHIFT 16
952 #define ISPRSZ_HFILT2120_COEF21_MASK 0x3FF0000
954 #define ISPRSZ_HFILT2322_COEF22_SHIFT 0
955 #define ISPRSZ_HFILT2322_COEF22_MASK 0x3FF
956 #define ISPRSZ_HFILT2322_COEF23_SHIFT 16
957 #define ISPRSZ_HFILT2322_COEF23_MASK 0x3FF0000
959 #define ISPRSZ_HFILT2524_COEF24_SHIFT 0
960 #define ISPRSZ_HFILT2524_COEF24_MASK 0x3FF
961 #define ISPRSZ_HFILT2524_COEF25_SHIFT 16
962 #define ISPRSZ_HFILT2524_COEF25_MASK 0x3FF0000
964 #define ISPRSZ_HFILT2726_COEF26_SHIFT 0
965 #define ISPRSZ_HFILT2726_COEF26_MASK 0x3FF
966 #define ISPRSZ_HFILT2726_COEF27_SHIFT 16
967 #define ISPRSZ_HFILT2726_COEF27_MASK 0x3FF0000
969 #define ISPRSZ_HFILT2928_COEF28_SHIFT 0
970 #define ISPRSZ_HFILT2928_COEF28_MASK 0x3FF
971 #define ISPRSZ_HFILT2928_COEF29_SHIFT 16
972 #define ISPRSZ_HFILT2928_COEF29_MASK 0x3FF0000
974 #define ISPRSZ_HFILT3130_COEF30_SHIFT 0
975 #define ISPRSZ_HFILT3130_COEF30_MASK 0x3FF
976 #define ISPRSZ_HFILT3130_COEF31_SHIFT 16
977 #define ISPRSZ_HFILT3130_COEF31_MASK 0x3FF0000
979 #define ISPRSZ_VFILT_COEF0_SHIFT 0
980 #define ISPRSZ_VFILT_COEF0_MASK \
981 (0x3FF << ISPRSZ_VFILT_COEF0_SHIFT)
982 #define ISPRSZ_VFILT_COEF1_SHIFT 16
983 #define ISPRSZ_VFILT_COEF1_MASK \
984 (0x3FF << ISPRSZ_VFILT_COEF1_SHIFT)
986 #define ISPRSZ_VFILT10_COEF0_SHIFT 0
987 #define ISPRSZ_VFILT10_COEF0_MASK 0x3FF
988 #define ISPRSZ_VFILT10_COEF1_SHIFT 16
989 #define ISPRSZ_VFILT10_COEF1_MASK 0x3FF0000
991 #define ISPRSZ_VFILT32_COEF2_SHIFT 0
992 #define ISPRSZ_VFILT32_COEF2_MASK 0x3FF
993 #define ISPRSZ_VFILT32_COEF3_SHIFT 16
994 #define ISPRSZ_VFILT32_COEF3_MASK 0x3FF0000
996 #define ISPRSZ_VFILT54_COEF4_SHIFT 0
997 #define ISPRSZ_VFILT54_COEF4_MASK 0x3FF
998 #define ISPRSZ_VFILT54_COEF5_SHIFT 16
999 #define ISPRSZ_VFILT54_COEF5_MASK 0x3FF0000
1001 #define ISPRSZ_VFILT76_COEFF6_SHIFT 0
1002 #define ISPRSZ_VFILT76_COEFF6_MASK 0x3FF
1003 #define ISPRSZ_VFILT76_COEFF7_SHIFT 16
1004 #define ISPRSZ_VFILT76_COEFF7_MASK 0x3FF0000
1006 #define ISPRSZ_VFILT98_COEFF8_SHIFT 0
1007 #define ISPRSZ_VFILT98_COEFF8_MASK 0x3FF
1008 #define ISPRSZ_VFILT98_COEFF9_SHIFT 16
1009 #define ISPRSZ_VFILT98_COEFF9_MASK 0x3FF0000
1011 #define ISPRSZ_VFILT1110_COEF10_SHIFT 0
1012 #define ISPRSZ_VFILT1110_COEF10_MASK 0x3FF
1013 #define ISPRSZ_VFILT1110_COEF11_SHIFT 16
1014 #define ISPRSZ_VFILT1110_COEF11_MASK 0x3FF0000
1016 #define ISPRSZ_VFILT1312_COEFF12_SHIFT 0
1017 #define ISPRSZ_VFILT1312_COEFF12_MASK 0x3FF
1018 #define ISPRSZ_VFILT1312_COEFF13_SHIFT 16
1019 #define ISPRSZ_VFILT1312_COEFF13_MASK 0x3FF0000
1021 #define ISPRSZ_VFILT1514_COEFF14_SHIFT 0
1022 #define ISPRSZ_VFILT1514_COEFF14_MASK 0x3FF
1023 #define ISPRSZ_VFILT1514_COEFF15_SHIFT 16
1024 #define ISPRSZ_VFILT1514_COEFF15_MASK 0x3FF0000
1026 #define ISPRSZ_VFILT1716_COEF16_SHIFT 0
1027 #define ISPRSZ_VFILT1716_COEF16_MASK 0x3FF
1028 #define ISPRSZ_VFILT1716_COEF17_SHIFT 16
1029 #define ISPRSZ_VFILT1716_COEF17_MASK 0x3FF0000
1031 #define ISPRSZ_VFILT1918_COEF18_SHIFT 0
1032 #define ISPRSZ_VFILT1918_COEF18_MASK 0x3FF
1033 #define ISPRSZ_VFILT1918_COEF19_SHIFT 16
1034 #define ISPRSZ_VFILT1918_COEF19_MASK 0x3FF0000
1036 #define ISPRSZ_VFILT2120_COEF20_SHIFT 0
1037 #define ISPRSZ_VFILT2120_COEF20_MASK 0x3FF
1038 #define ISPRSZ_VFILT2120_COEF21_SHIFT 16
1039 #define ISPRSZ_VFILT2120_COEF21_MASK 0x3FF0000
1041 #define ISPRSZ_VFILT2322_COEF22_SHIFT 0
1042 #define ISPRSZ_VFILT2322_COEF22_MASK 0x3FF
1043 #define ISPRSZ_VFILT2322_COEF23_SHIFT 16
1044 #define ISPRSZ_VFILT2322_COEF23_MASK 0x3FF0000
1046 #define ISPRSZ_VFILT2524_COEF24_SHIFT 0
1047 #define ISPRSZ_VFILT2524_COEF24_MASK 0x3FF
1048 #define ISPRSZ_VFILT2524_COEF25_SHIFT 16
1049 #define ISPRSZ_VFILT2524_COEF25_MASK 0x3FF0000
1051 #define ISPRSZ_VFILT2726_COEF26_SHIFT 0
1052 #define ISPRSZ_VFILT2726_COEF26_MASK 0x3FF
1053 #define ISPRSZ_VFILT2726_COEF27_SHIFT 16
1054 #define ISPRSZ_VFILT2726_COEF27_MASK 0x3FF0000
1056 #define ISPRSZ_VFILT2928_COEF28_SHIFT 0
1057 #define ISPRSZ_VFILT2928_COEF28_MASK 0x3FF
1058 #define ISPRSZ_VFILT2928_COEF29_SHIFT 16
1059 #define ISPRSZ_VFILT2928_COEF29_MASK 0x3FF0000
1061 #define ISPRSZ_VFILT3130_COEF30_SHIFT 0
1062 #define ISPRSZ_VFILT3130_COEF30_MASK 0x3FF
1063 #define ISPRSZ_VFILT3130_COEF31_SHIFT 16
1064 #define ISPRSZ_VFILT3130_COEF31_MASK 0x3FF0000
1066 #define ISPRSZ_YENH_CORE_SHIFT 0
1067 #define ISPRSZ_YENH_CORE_MASK \
1068 (0xFF << ISPRSZ_YENH_CORE_SHIFT)
1069 #define ISPRSZ_YENH_SLOP_SHIFT 8
1070 #define ISPRSZ_YENH_SLOP_MASK \
1071 (0xF << ISPRSZ_YENH_SLOP_SHIFT)
1072 #define ISPRSZ_YENH_GAIN_SHIFT 12
1073 #define ISPRSZ_YENH_GAIN_MASK \
1074 (0xF << ISPRSZ_YENH_GAIN_SHIFT)
1075 #define ISPRSZ_YENH_ALGO_SHIFT 16
1076 #define ISPRSZ_YENH_ALGO_MASK \
1077 (0x3 << ISPRSZ_YENH_ALGO_SHIFT)
1079 #define ISPH3A_PCR_AEW_ALAW_EN_SHIFT 1
1080 #define ISPH3A_PCR_AF_MED_TH_SHIFT 3
1081 #define ISPH3A_PCR_AF_RGBPOS_SHIFT 11
1082 #define ISPH3A_PCR_AEW_AVE2LMT_SHIFT 22
1083 #define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000
1084 #define ISPH3A_PCR_BUSYAF BIT(15)
1085 #define ISPH3A_PCR_BUSYAEAWB BIT(18)
1087 #define ISPH3A_AEWWIN1_WINHC_SHIFT 0
1088 #define ISPH3A_AEWWIN1_WINHC_MASK 0x3F
1089 #define ISPH3A_AEWWIN1_WINVC_SHIFT 6
1090 #define ISPH3A_AEWWIN1_WINVC_MASK 0x1FC0
1091 #define ISPH3A_AEWWIN1_WINW_SHIFT 13
1092 #define ISPH3A_AEWWIN1_WINW_MASK 0xFE000
1093 #define ISPH3A_AEWWIN1_WINH_SHIFT 24
1094 #define ISPH3A_AEWWIN1_WINH_MASK 0x7F000000
1096 #define ISPH3A_AEWINSTART_WINSH_SHIFT 0
1097 #define ISPH3A_AEWINSTART_WINSH_MASK 0x0FFF
1098 #define ISPH3A_AEWINSTART_WINSV_SHIFT 16
1099 #define ISPH3A_AEWINSTART_WINSV_MASK 0x0FFF0000
1101 #define ISPH3A_AEWINBLK_WINH_SHIFT 0
1102 #define ISPH3A_AEWINBLK_WINH_MASK 0x7F
1103 #define ISPH3A_AEWINBLK_WINSV_SHIFT 16
1104 #define ISPH3A_AEWINBLK_WINSV_MASK 0x0FFF0000
1106 #define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT 0
1107 #define ISPH3A_AEWSUBWIN_AEWINCH_MASK 0x0F
1108 #define ISPH3A_AEWSUBWIN_AEWINCV_SHIFT 8
1109 #define ISPH3A_AEWSUBWIN_AEWINCV_MASK 0x0F00
1111 #define ISPHIST_PCR_ENABLE_SHIFT 0
1112 #define ISPHIST_PCR_ENABLE_MASK 0x01
1113 #define ISPHIST_PCR_ENABLE (1 << ISPHIST_PCR_ENABLE_SHIFT)
1114 #define ISPHIST_PCR_BUSY 0x02
1116 #define ISPHIST_CNT_DATASIZE_SHIFT 8
1117 #define ISPHIST_CNT_DATASIZE_MASK 0x0100
1118 #define ISPHIST_CNT_CLEAR_SHIFT 7
1119 #define ISPHIST_CNT_CLEAR_MASK 0x080
1120 #define ISPHIST_CNT_CLEAR (1 << ISPHIST_CNT_CLEAR_SHIFT)
1121 #define ISPHIST_CNT_CFA_SHIFT 6
1122 #define ISPHIST_CNT_CFA_MASK 0x040
1123 #define ISPHIST_CNT_BINS_SHIFT 4
1124 #define ISPHIST_CNT_BINS_MASK 0x030
1125 #define ISPHIST_CNT_SOURCE_SHIFT 3
1126 #define ISPHIST_CNT_SOURCE_MASK 0x08
1127 #define ISPHIST_CNT_SHIFT_SHIFT 0
1128 #define ISPHIST_CNT_SHIFT_MASK 0x07
1130 #define ISPHIST_WB_GAIN_WG00_SHIFT 24
1131 #define ISPHIST_WB_GAIN_WG00_MASK 0xFF000000
1132 #define ISPHIST_WB_GAIN_WG01_SHIFT 16
1133 #define ISPHIST_WB_GAIN_WG01_MASK 0xFF0000
1134 #define ISPHIST_WB_GAIN_WG02_SHIFT 8
1135 #define ISPHIST_WB_GAIN_WG02_MASK 0xFF00
1136 #define ISPHIST_WB_GAIN_WG03_SHIFT 0
1137 #define ISPHIST_WB_GAIN_WG03_MASK 0xFF
1139 #define ISPHIST_REG_START_END_MASK 0x3FFF
1140 #define ISPHIST_REG_START_SHIFT 16
1141 #define ISPHIST_REG_END_SHIFT 0
1142 #define ISPHIST_REG_START_MASK (ISPHIST_REG_START_END_MASK << \
1143 ISPHIST_REG_START_SHIFT)
1144 #define ISPHIST_REG_END_MASK (ISPHIST_REG_START_END_MASK << \
1145 ISPHIST_REG_END_SHIFT)
1147 #define ISPHIST_REG_MASK (ISPHIST_REG_START_MASK | \
1148 ISPHIST_REG_END_MASK)
1150 #define ISPHIST_ADDR_SHIFT 0
1151 #define ISPHIST_ADDR_MASK 0x3FF
1153 #define ISPHIST_DATA_SHIFT 0
1154 #define ISPHIST_DATA_MASK 0xFFFFF
1156 #define ISPHIST_RADD_SHIFT 0
1157 #define ISPHIST_RADD_MASK 0xFFFFFFFF
1159 #define ISPHIST_RADD_OFF_SHIFT 0
1160 #define ISPHIST_RADD_OFF_MASK 0xFFFF
1162 #define ISPHIST_HV_INFO_HSIZE_SHIFT 16
1163 #define ISPHIST_HV_INFO_HSIZE_MASK 0x3FFF0000
1164 #define ISPHIST_HV_INFO_VSIZE_SHIFT 0
1165 #define ISPHIST_HV_INFO_VSIZE_MASK 0x3FFF
1167 #define ISPHIST_HV_INFO_MASK 0x3FFF3FFF
1169 #define ISPCCDC_LSC_ENABLE BIT(0)
1170 #define ISPCCDC_LSC_BUSY BIT(7)
1171 #define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700
1172 #define ISPCCDC_LSC_GAIN_MODE_N_SHIFT 8
1173 #define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800
1174 #define ISPCCDC_LSC_GAIN_MODE_M_SHIFT 12
1175 #define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE
1176 #define ISPCCDC_LSC_GAIN_FORMAT_SHIFT 1
1177 #define ISPCCDC_LSC_AFTER_REFORMATTER_MASK BIT(6)
1179 #define ISPCCDC_LSC_INITIAL_X_MASK 0x3F
1180 #define ISPCCDC_LSC_INITIAL_X_SHIFT 0
1181 #define ISPCCDC_LSC_INITIAL_Y_MASK 0x3F0000
1182 #define ISPCCDC_LSC_INITIAL_Y_SHIFT 16
1184 /* -----------------------------------------------------------------------------
1185 * CSI2 receiver registers (ES2.0)
1188 #define ISPCSI2_REVISION (0x000)
1189 #define ISPCSI2_SYSCONFIG (0x010)
1190 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12
1191 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK \
1192 (0x3 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1193 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_FORCE \
1194 (0x0 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1195 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO \
1196 (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1197 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART \
1198 (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1199 #define ISPCSI2_SYSCONFIG_SOFT_RESET BIT(1)
1200 #define ISPCSI2_SYSCONFIG_AUTO_IDLE BIT(0)
1202 #define ISPCSI2_SYSSTATUS (0x014)
1203 #define ISPCSI2_SYSSTATUS_RESET_DONE BIT(0)
1205 #define ISPCSI2_IRQSTATUS (0x018)
1206 #define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ BIT(14)
1207 #define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ BIT(13)
1208 #define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ BIT(12)
1209 #define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ BIT(11)
1210 #define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ BIT(10)
1211 #define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ BIT(9)
1212 #define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ BIT(8)
1213 #define ISPCSI2_IRQSTATUS_CONTEXT(n) BIT(n)
1215 #define ISPCSI2_IRQENABLE (0x01c)
1216 #define ISPCSI2_CTRL (0x040)
1217 #define ISPCSI2_CTRL_VP_CLK_EN BIT(15)
1218 #define ISPCSI2_CTRL_VP_ONLY_EN BIT(11)
1219 #define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT 8
1220 #define ISPCSI2_CTRL_VP_OUT_CTRL_MASK \
1221 (3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
1222 #define ISPCSI2_CTRL_DBG_EN BIT(7)
1223 #define ISPCSI2_CTRL_BURST_SIZE_SHIFT 5
1224 #define ISPCSI2_CTRL_BURST_SIZE_MASK \
1225 (3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT)
1226 #define ISPCSI2_CTRL_FRAME BIT(3)
1227 #define ISPCSI2_CTRL_ECC_EN BIT(2)
1228 #define ISPCSI2_CTRL_SECURE BIT(1)
1229 #define ISPCSI2_CTRL_IF_EN BIT(0)
1231 #define ISPCSI2_DBG_H (0x044)
1232 #define ISPCSI2_GNQ (0x048)
1233 #define ISPCSI2_PHY_CFG (0x050)
1234 #define ISPCSI2_PHY_CFG_RESET_CTRL BIT(30)
1235 #define ISPCSI2_PHY_CFG_RESET_DONE BIT(29)
1236 #define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT 27
1237 #define ISPCSI2_PHY_CFG_PWR_CMD_MASK \
1238 (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1239 #define ISPCSI2_PHY_CFG_PWR_CMD_OFF \
1240 (0x0 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1241 #define ISPCSI2_PHY_CFG_PWR_CMD_ON \
1242 (0x1 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1243 #define ISPCSI2_PHY_CFG_PWR_CMD_ULPW \
1244 (0x2 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1245 #define ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT 25
1246 #define ISPCSI2_PHY_CFG_PWR_STATUS_MASK \
1247 (0x3 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1248 #define ISPCSI2_PHY_CFG_PWR_STATUS_OFF \
1249 (0x0 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1250 #define ISPCSI2_PHY_CFG_PWR_STATUS_ON \
1251 (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1252 #define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW \
1253 (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1254 #define ISPCSI2_PHY_CFG_PWR_AUTO BIT(24)
1256 #define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n) (3 + ((n) * 4))
1257 #define ISPCSI2_PHY_CFG_DATA_POL_MASK(n) \
1258 (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1259 #define ISPCSI2_PHY_CFG_DATA_POL_PN(n) \
1260 (0x0 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1261 #define ISPCSI2_PHY_CFG_DATA_POL_NP(n) \
1262 (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1264 #define ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n) ((n) * 4)
1265 #define ISPCSI2_PHY_CFG_DATA_POSITION_MASK(n) \
1266 (0x7 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1267 #define ISPCSI2_PHY_CFG_DATA_POSITION_NC(n) \
1268 (0x0 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1269 #define ISPCSI2_PHY_CFG_DATA_POSITION_1(n) \
1270 (0x1 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1271 #define ISPCSI2_PHY_CFG_DATA_POSITION_2(n) \
1272 (0x2 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1273 #define ISPCSI2_PHY_CFG_DATA_POSITION_3(n) \
1274 (0x3 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1275 #define ISPCSI2_PHY_CFG_DATA_POSITION_4(n) \
1276 (0x4 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1277 #define ISPCSI2_PHY_CFG_DATA_POSITION_5(n) \
1278 (0x5 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1280 #define ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT 3
1281 #define ISPCSI2_PHY_CFG_CLOCK_POL_MASK \
1282 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1283 #define ISPCSI2_PHY_CFG_CLOCK_POL_PN \
1284 (0x0 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1285 #define ISPCSI2_PHY_CFG_CLOCK_POL_NP \
1286 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1288 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT 0
1289 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK \
1290 (0x7 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1291 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_1 \
1292 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1293 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_2 \
1294 (0x2 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1295 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_3 \
1296 (0x3 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1297 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_4 \
1298 (0x4 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1299 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_5 \
1300 (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1302 #define ISPCSI2_PHY_IRQSTATUS (0x054)
1303 #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT BIT(26)
1304 #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER BIT(25)
1305 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 BIT(24)
1306 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 BIT(23)
1307 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 BIT(22)
1308 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 BIT(21)
1309 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 BIT(20)
1310 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 BIT(19)
1311 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 BIT(18)
1312 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 BIT(17)
1313 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 BIT(16)
1314 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 BIT(15)
1315 #define ISPCSI2_PHY_IRQSTATUS_ERRESC5 BIT(14)
1316 #define ISPCSI2_PHY_IRQSTATUS_ERRESC4 BIT(13)
1317 #define ISPCSI2_PHY_IRQSTATUS_ERRESC3 BIT(12)
1318 #define ISPCSI2_PHY_IRQSTATUS_ERRESC2 BIT(11)
1319 #define ISPCSI2_PHY_IRQSTATUS_ERRESC1 BIT(10)
1320 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 BIT(9)
1321 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 BIT(8)
1322 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 BIT(7)
1323 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 BIT(6)
1324 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 BIT(5)
1325 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 BIT(4)
1326 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 BIT(3)
1327 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 BIT(2)
1328 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 BIT(1)
1329 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 BIT(0)
1331 #define ISPCSI2_SHORT_PACKET (0x05c)
1332 #define ISPCSI2_PHY_IRQENABLE (0x060)
1333 #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT BIT(26)
1334 #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER BIT(25)
1335 #define ISPCSI2_PHY_IRQENABLE_STATEULPM5 BIT(24)
1336 #define ISPCSI2_PHY_IRQENABLE_STATEULPM4 BIT(23)
1337 #define ISPCSI2_PHY_IRQENABLE_STATEULPM3 BIT(22)
1338 #define ISPCSI2_PHY_IRQENABLE_STATEULPM2 BIT(21)
1339 #define ISPCSI2_PHY_IRQENABLE_STATEULPM1 BIT(20)
1340 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 BIT(19)
1341 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 BIT(18)
1342 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 BIT(17)
1343 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 BIT(16)
1344 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 BIT(15)
1345 #define ISPCSI2_PHY_IRQENABLE_ERRESC5 BIT(14)
1346 #define ISPCSI2_PHY_IRQENABLE_ERRESC4 BIT(13)
1347 #define ISPCSI2_PHY_IRQENABLE_ERRESC3 BIT(12)
1348 #define ISPCSI2_PHY_IRQENABLE_ERRESC2 BIT(11)
1349 #define ISPCSI2_PHY_IRQENABLE_ERRESC1 BIT(10)
1350 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 BIT(9)
1351 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 BIT(8)
1352 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 BIT(7)
1353 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 BIT(6)
1354 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 BIT(5)
1355 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 BIT(4)
1356 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 BIT(3)
1357 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 BIT(2)
1358 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 BIT(1)
1359 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 BIT(0)
1361 #define ISPCSI2_DBG_P (0x068)
1362 #define ISPCSI2_TIMING (0x06c)
1363 #define ISPCSI2_TIMING_FORCE_RX_MODE_IO(n) (1 << ((16 * ((n) - 1)) + 15))
1364 #define ISPCSI2_TIMING_STOP_STATE_X16_IO(n) (1 << ((16 * ((n) - 1)) + 14))
1365 #define ISPCSI2_TIMING_STOP_STATE_X4_IO(n) (1 << ((16 * ((n) - 1)) + 13))
1366 #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n) (16 * ((n) - 1))
1367 #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(n) \
1368 (0x1fff << ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n))
1370 #define ISPCSI2_CTX_CTRL1(n) ((0x070) + 0x20 * (n))
1371 #define ISPCSI2_CTX_CTRL1_COUNT_SHIFT 8
1372 #define ISPCSI2_CTX_CTRL1_COUNT_MASK \
1373 (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
1374 #define ISPCSI2_CTX_CTRL1_EOF_EN BIT(7)
1375 #define ISPCSI2_CTX_CTRL1_EOL_EN BIT(6)
1376 #define ISPCSI2_CTX_CTRL1_CS_EN BIT(5)
1377 #define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK BIT(4)
1378 #define ISPCSI2_CTX_CTRL1_PING_PONG BIT(3)
1379 #define ISPCSI2_CTX_CTRL1_CTX_EN BIT(0)
1381 #define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n))
1382 #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT 13
1383 #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK \
1384 (0x3 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT)
1385 #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT 11
1386 #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK \
1387 (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT)
1388 #define ISPCSI2_CTX_CTRL2_DPCM_PRED BIT(10)
1389 #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0
1390 #define ISPCSI2_CTX_CTRL2_FORMAT_MASK \
1391 (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT)
1392 #define ISPCSI2_CTX_CTRL2_FRAME_SHIFT 16
1393 #define ISPCSI2_CTX_CTRL2_FRAME_MASK \
1394 (0xffff << ISPCSI2_CTX_CTRL2_FRAME_SHIFT)
1396 #define ISPCSI2_CTX_DAT_OFST(n) ((0x078) + 0x20 * (n))
1397 #define ISPCSI2_CTX_DAT_OFST_OFST_SHIFT 0
1398 #define ISPCSI2_CTX_DAT_OFST_OFST_MASK \
1399 (0x1ffe0 << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT)
1401 #define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07c) + 0x20 * (n))
1402 #define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n))
1403 #define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n))
1404 #define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ BIT(8)
1405 #define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ BIT(7)
1406 #define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ BIT(6)
1407 #define ISPCSI2_CTX_IRQENABLE_CS_IRQ BIT(5)
1408 #define ISPCSI2_CTX_IRQENABLE_LE_IRQ BIT(3)
1409 #define ISPCSI2_CTX_IRQENABLE_LS_IRQ BIT(2)
1410 #define ISPCSI2_CTX_IRQENABLE_FE_IRQ BIT(1)
1411 #define ISPCSI2_CTX_IRQENABLE_FS_IRQ BIT(0)
1413 #define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n))
1414 #define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ BIT(8)
1415 #define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ BIT(7)
1416 #define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ BIT(6)
1417 #define ISPCSI2_CTX_IRQSTATUS_CS_IRQ BIT(5)
1418 #define ISPCSI2_CTX_IRQSTATUS_LE_IRQ BIT(3)
1419 #define ISPCSI2_CTX_IRQSTATUS_LS_IRQ BIT(2)
1420 #define ISPCSI2_CTX_IRQSTATUS_FE_IRQ BIT(1)
1421 #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ BIT(0)
1423 #define ISPCSI2_CTX_CTRL3(n) ((0x08c) + 0x20 * (n))
1424 #define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT 5
1425 #define ISPCSI2_CTX_CTRL3_ALPHA_MASK \
1426 (0x3fff << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT)
1428 /* This instance is for OMAP3630 only */
1429 #define ISPCSI2_CTX_TRANSCODEH(n) (0x000 + 0x8 * (n))
1430 #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT 16
1431 #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_MASK \
1432 (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1433 #define ISPCSI2_CTX_TRANSCODEH_HSKIP_SHIFT 0
1434 #define ISPCSI2_CTX_TRANSCODEH_HSKIP_MASK \
1435 (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1436 #define ISPCSI2_CTX_TRANSCODEV(n) (0x004 + 0x8 * (n))
1437 #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT 16
1438 #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_MASK \
1439 (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1440 #define ISPCSI2_CTX_TRANSCODEV_VSKIP_SHIFT 0
1441 #define ISPCSI2_CTX_TRANSCODEV_VSKIP_MASK \
1442 (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1444 /* -----------------------------------------------------------------------------
1448 #define ISPCSIPHY_REG0 (0x000)
1449 #define ISPCSIPHY_REG0_THS_TERM_SHIFT 8
1450 #define ISPCSIPHY_REG0_THS_TERM_MASK \
1451 (0xff << ISPCSIPHY_REG0_THS_TERM_SHIFT)
1452 #define ISPCSIPHY_REG0_THS_SETTLE_SHIFT 0
1453 #define ISPCSIPHY_REG0_THS_SETTLE_MASK \
1454 (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT)
1456 #define ISPCSIPHY_REG1 (0x004)
1457 #define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK BIT(29)
1458 /* This field is for OMAP3630 only */
1459 #define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS BIT(25)
1460 #define ISPCSIPHY_REG1_TCLK_TERM_SHIFT 18
1461 #define ISPCSIPHY_REG1_TCLK_TERM_MASK \
1462 (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT)
1463 #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_SHIFT 10
1464 #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_MASK \
1465 (0xff << ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN)
1466 /* This field is for OMAP3430 only */
1467 #define ISPCSIPHY_REG1_TCLK_MISS_SHIFT 8
1468 #define ISPCSIPHY_REG1_TCLK_MISS_MASK \
1469 (0x3 << ISPCSIPHY_REG1_TCLK_MISS_SHIFT)
1470 /* This field is for OMAP3630 only */
1471 #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT 8
1472 #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_MASK \
1473 (0x3 << ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT)
1474 #define ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT 0
1475 #define ISPCSIPHY_REG1_TCLK_SETTLE_MASK \
1476 (0xff << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT)
1478 /* This register is for OMAP3630 only */
1479 #define ISPCSIPHY_REG2 (0x008)
1480 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT 30
1481 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK \
1482 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT)
1483 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT 28
1484 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK \
1485 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT)
1486 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT 26
1487 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK \
1488 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT)
1489 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT 24
1490 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK \
1491 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT)
1492 #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT 0
1493 #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_MASK \
1494 (0x7fffff << ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT)
1496 /* -----------------------------------------------------------------------------
1497 * CONTROL registers for CSI-2 phy routing
1500 /* OMAP343X_CONTROL_CSIRXFE */
1501 #define OMAP343X_CONTROL_CSIRXFE_CSIB_INV BIT(7)
1502 #define OMAP343X_CONTROL_CSIRXFE_RESENABLE BIT(8)
1503 #define OMAP343X_CONTROL_CSIRXFE_SELFORM BIT(10)
1504 #define OMAP343X_CONTROL_CSIRXFE_PWRDNZ BIT(12)
1505 #define OMAP343X_CONTROL_CSIRXFE_RESET BIT(13)
1507 /* OMAP3630_CONTROL_CAMERA_PHY_CTRL */
1508 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT 2
1509 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT 0
1510 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY 0x0
1511 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE 0x1
1512 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK 0x2
1513 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI 0x3
1514 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK 0x3
1515 /* CCP2B: set to receive data from PHY2 instead of PHY1 */
1516 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 BIT(4)
1518 #endif /* OMAP3_ISP_REG_H */
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