1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung S5P/EXYNOS SoC series MIPI-CSI receiver driver
5 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
6 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/errno.h>
13 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/memory.h>
18 #include <linux/module.h>
20 #include <linux/of_graph.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/sizes.h>
26 #include <linux/slab.h>
27 #include <linux/spinlock.h>
28 #include <linux/videodev2.h>
29 #include <media/drv-intf/exynos-fimc.h>
30 #include <media/v4l2-fwnode.h>
31 #include <media/v4l2-subdev.h>
33 #include "mipi-csis.h"
36 module_param(debug, int, 0644);
37 MODULE_PARM_DESC(debug, "Debug level (0-2)");
39 /* Register map definition */
41 /* CSIS global control */
42 #define S5PCSIS_CTRL 0x00
43 #define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31)
44 #define S5PCSIS_CTRL_DPDN_SWAP (1UL << 31)
45 #define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20)
46 #define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16)
47 #define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8)
48 #define S5PCSIS_CTRL_RESET (1 << 4)
49 #define S5PCSIS_CTRL_ENABLE (1 << 0)
52 #define S5PCSIS_DPHYCTRL 0x04
53 #define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27)
54 #define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0)
56 #define S5PCSIS_CONFIG 0x08
57 #define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2)
58 #define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2)
59 #define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2)
60 #define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2)
61 /* User defined formats, x = 1...4 */
62 #define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2)
63 #define S5PCSIS_CFG_FMT_MASK (0x3f << 2)
64 #define S5PCSIS_CFG_NR_LANE_MASK 3
67 #define S5PCSIS_INTMSK 0x10
68 #define S5PCSIS_INTMSK_EVEN_BEFORE (1UL << 31)
69 #define S5PCSIS_INTMSK_EVEN_AFTER (1 << 30)
70 #define S5PCSIS_INTMSK_ODD_BEFORE (1 << 29)
71 #define S5PCSIS_INTMSK_ODD_AFTER (1 << 28)
72 #define S5PCSIS_INTMSK_FRAME_START (1 << 27)
73 #define S5PCSIS_INTMSK_FRAME_END (1 << 26)
74 #define S5PCSIS_INTMSK_ERR_SOT_HS (1 << 12)
75 #define S5PCSIS_INTMSK_ERR_LOST_FS (1 << 5)
76 #define S5PCSIS_INTMSK_ERR_LOST_FE (1 << 4)
77 #define S5PCSIS_INTMSK_ERR_OVER (1 << 3)
78 #define S5PCSIS_INTMSK_ERR_ECC (1 << 2)
79 #define S5PCSIS_INTMSK_ERR_CRC (1 << 1)
80 #define S5PCSIS_INTMSK_ERR_UNKNOWN (1 << 0)
81 #define S5PCSIS_INTMSK_EXYNOS4_EN_ALL 0xf000103f
82 #define S5PCSIS_INTMSK_EXYNOS5_EN_ALL 0xfc00103f
84 /* Interrupt source */
85 #define S5PCSIS_INTSRC 0x14
86 #define S5PCSIS_INTSRC_EVEN_BEFORE (1UL << 31)
87 #define S5PCSIS_INTSRC_EVEN_AFTER (1 << 30)
88 #define S5PCSIS_INTSRC_EVEN (0x3 << 30)
89 #define S5PCSIS_INTSRC_ODD_BEFORE (1 << 29)
90 #define S5PCSIS_INTSRC_ODD_AFTER (1 << 28)
91 #define S5PCSIS_INTSRC_ODD (0x3 << 28)
92 #define S5PCSIS_INTSRC_NON_IMAGE_DATA (0xf << 28)
93 #define S5PCSIS_INTSRC_FRAME_START (1 << 27)
94 #define S5PCSIS_INTSRC_FRAME_END (1 << 26)
95 #define S5PCSIS_INTSRC_ERR_SOT_HS (0xf << 12)
96 #define S5PCSIS_INTSRC_ERR_LOST_FS (1 << 5)
97 #define S5PCSIS_INTSRC_ERR_LOST_FE (1 << 4)
98 #define S5PCSIS_INTSRC_ERR_OVER (1 << 3)
99 #define S5PCSIS_INTSRC_ERR_ECC (1 << 2)
100 #define S5PCSIS_INTSRC_ERR_CRC (1 << 1)
101 #define S5PCSIS_INTSRC_ERR_UNKNOWN (1 << 0)
102 #define S5PCSIS_INTSRC_ERRORS 0xf03f
104 /* Pixel resolution */
105 #define S5PCSIS_RESOL 0x2c
106 #define CSIS_MAX_PIX_WIDTH 0xffff
107 #define CSIS_MAX_PIX_HEIGHT 0xffff
109 /* Non-image packet data buffers */
110 #define S5PCSIS_PKTDATA_ODD 0x2000
111 #define S5PCSIS_PKTDATA_EVEN 0x3000
112 #define S5PCSIS_PKTDATA_SIZE SZ_4K
119 static char *csi_clock_name[] = {
120 [CSIS_CLK_MUX] = "sclk_csis",
121 [CSIS_CLK_GATE] = "csis",
123 #define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
124 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL
126 static const char * const csis_supply_name[] = {
127 "vddcore", /* CSIS Core (1.0V, 1.1V or 1.2V) suppply */
128 "vddio", /* CSIS I/O and PLL (1.8V) supply */
130 #define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name)
138 struct s5pcsis_event {
140 const char * const name;
141 unsigned int counter;
144 static const struct s5pcsis_event s5pcsis_events[] = {
146 { S5PCSIS_INTSRC_ERR_SOT_HS, "SOT Error" },
147 { S5PCSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" },
148 { S5PCSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" },
149 { S5PCSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" },
150 { S5PCSIS_INTSRC_ERR_ECC, "ECC Error" },
151 { S5PCSIS_INTSRC_ERR_CRC, "CRC Error" },
152 { S5PCSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" },
153 /* Non-image data receive events */
154 { S5PCSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" },
155 { S5PCSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" },
156 { S5PCSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" },
157 { S5PCSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" },
158 /* Frame start/end */
159 { S5PCSIS_INTSRC_FRAME_START, "Frame Start" },
160 { S5PCSIS_INTSRC_FRAME_END, "Frame End" },
162 #define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events)
169 struct csis_drvdata {
170 /* Mask of all used interrupts in S5PCSIS_INTMSK register */
175 * struct csis_state - the driver's internal state data structure
176 * @lock: mutex serializing the subdev and power management operations,
177 * protecting @format and @flags members
178 * @pads: CSIS pads array
179 * @sd: v4l2_subdev associated with CSIS device instance
180 * @index: the hardware instance index
181 * @pdev: CSIS platform device
182 * @phy: pointer to the CSIS generic PHY
183 * @regs: mmapped I/O registers memory
184 * @supplies: CSIS regulator supplies
185 * @clock: CSIS clocks
186 * @irq: requested s5p-mipi-csis irq number
187 * @interrupt_mask: interrupt mask of the all used interrupts
188 * @flags: the state variable for power and streaming control
189 * @clk_frequency: device bus clock frequency
190 * @hs_settle: HS-RX settle time
191 * @num_lanes: number of MIPI-CSI data lanes used
192 * @max_num_lanes: maximum number of MIPI-CSI data lanes supported
193 * @wclk_ext: CSI wrapper clock: 0 - bus clock, 1 - external SCLK_CAM
194 * @csis_fmt: current CSIS pixel format
195 * @format: common media bus format for the source and sink pad
196 * @slock: spinlock protecting structure members below
197 * @pkt_buf: the frame embedded (non-image) data buffer
198 * @events: MIPI-CSIS event (error) counters
202 struct media_pad pads[CSIS_PADS_NUM];
203 struct v4l2_subdev sd;
205 struct platform_device *pdev;
208 struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES];
209 struct clk *clock[NUM_CSIS_CLOCKS];
220 const struct csis_pix_format *csis_fmt;
221 struct v4l2_mbus_framefmt format;
224 struct csis_pktbuf pkt_buf;
225 struct s5pcsis_event events[S5PCSIS_NUM_EVENTS];
229 * struct csis_pix_format - CSIS pixel format description
230 * @pix_width_alignment: horizontal pixel alignment, width will be
231 * multiple of 2^pix_width_alignment
232 * @code: corresponding media bus code
233 * @fmt_reg: S5PCSIS_CONFIG register value
234 * @data_alignment: MIPI-CSI data alignment in bits
236 struct csis_pix_format {
237 unsigned int pix_width_alignment;
243 static const struct csis_pix_format s5pcsis_formats[] = {
245 .code = MEDIA_BUS_FMT_VYUY8_2X8,
246 .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
247 .data_alignment = 32,
249 .code = MEDIA_BUS_FMT_JPEG_1X8,
250 .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
251 .data_alignment = 32,
253 .code = MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8,
254 .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
255 .data_alignment = 32,
257 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
258 .fmt_reg = S5PCSIS_CFG_FMT_RAW8,
259 .data_alignment = 24,
261 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
262 .fmt_reg = S5PCSIS_CFG_FMT_RAW10,
263 .data_alignment = 24,
265 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
266 .fmt_reg = S5PCSIS_CFG_FMT_RAW12,
267 .data_alignment = 24,
271 #define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
272 #define s5pcsis_read(__csis, __r) readl(__csis->regs + __r)
274 static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev)
276 return container_of(sdev, struct csis_state, sd);
279 static const struct csis_pix_format *find_csis_format(
280 struct v4l2_mbus_framefmt *mf)
284 for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++)
285 if (mf->code == s5pcsis_formats[i].code)
286 return &s5pcsis_formats[i];
290 static void s5pcsis_enable_interrupts(struct csis_state *state, bool on)
292 u32 val = s5pcsis_read(state, S5PCSIS_INTMSK);
294 val |= state->interrupt_mask;
296 val &= ~state->interrupt_mask;
297 s5pcsis_write(state, S5PCSIS_INTMSK, val);
300 static void s5pcsis_reset(struct csis_state *state)
302 u32 val = s5pcsis_read(state, S5PCSIS_CTRL);
304 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET);
308 static void s5pcsis_system_enable(struct csis_state *state, int on)
312 val = s5pcsis_read(state, S5PCSIS_CTRL);
314 val |= S5PCSIS_CTRL_ENABLE;
316 val &= ~S5PCSIS_CTRL_ENABLE;
317 s5pcsis_write(state, S5PCSIS_CTRL, val);
319 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
320 val &= ~S5PCSIS_DPHYCTRL_ENABLE;
322 mask = (1 << (state->num_lanes + 1)) - 1;
323 val |= (mask & S5PCSIS_DPHYCTRL_ENABLE);
325 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
328 /* Called with the state.lock mutex held */
329 static void __s5pcsis_set_format(struct csis_state *state)
331 struct v4l2_mbus_framefmt *mf = &state->format;
334 v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n",
335 mf->code, mf->width, mf->height);
338 val = s5pcsis_read(state, S5PCSIS_CONFIG);
339 val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg;
340 s5pcsis_write(state, S5PCSIS_CONFIG, val);
342 /* Pixel resolution */
343 val = (mf->width << 16) | mf->height;
344 s5pcsis_write(state, S5PCSIS_RESOL, val);
347 static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle)
349 u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
351 val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27);
352 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
355 static void s5pcsis_set_params(struct csis_state *state)
359 val = s5pcsis_read(state, S5PCSIS_CONFIG);
360 val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (state->num_lanes - 1);
361 s5pcsis_write(state, S5PCSIS_CONFIG, val);
363 __s5pcsis_set_format(state);
364 s5pcsis_set_hsync_settle(state, state->hs_settle);
366 val = s5pcsis_read(state, S5PCSIS_CTRL);
367 if (state->csis_fmt->data_alignment == 32)
368 val |= S5PCSIS_CTRL_ALIGN_32BIT;
370 val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
372 val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
374 val |= S5PCSIS_CTRL_WCLK_EXTCLK;
375 s5pcsis_write(state, S5PCSIS_CTRL, val);
377 /* Update the shadow register. */
378 val = s5pcsis_read(state, S5PCSIS_CTRL);
379 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
382 static void s5pcsis_clk_put(struct csis_state *state)
386 for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
387 if (IS_ERR(state->clock[i]))
389 clk_unprepare(state->clock[i]);
390 clk_put(state->clock[i]);
391 state->clock[i] = ERR_PTR(-EINVAL);
395 static int s5pcsis_clk_get(struct csis_state *state)
397 struct device *dev = &state->pdev->dev;
400 for (i = 0; i < NUM_CSIS_CLOCKS; i++)
401 state->clock[i] = ERR_PTR(-EINVAL);
403 for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
404 state->clock[i] = clk_get(dev, csi_clock_name[i]);
405 if (IS_ERR(state->clock[i])) {
406 ret = PTR_ERR(state->clock[i]);
409 ret = clk_prepare(state->clock[i]);
411 clk_put(state->clock[i]);
412 state->clock[i] = ERR_PTR(-EINVAL);
418 s5pcsis_clk_put(state);
419 dev_err(dev, "failed to get clock: %s\n", csi_clock_name[i]);
423 static void dump_regs(struct csis_state *state, const char *label)
427 const char * const name;
430 { 0x04, "DPHYCTRL" },
435 { 0x38, "SDW_CONFIG" },
439 v4l2_info(&state->sd, "--- %s ---\n", label);
441 for (i = 0; i < ARRAY_SIZE(registers); i++) {
442 u32 cfg = s5pcsis_read(state, registers[i].offset);
443 v4l2_info(&state->sd, "%10s: 0x%08x\n", registers[i].name, cfg);
447 static void s5pcsis_start_stream(struct csis_state *state)
449 s5pcsis_reset(state);
450 s5pcsis_set_params(state);
451 s5pcsis_system_enable(state, true);
452 s5pcsis_enable_interrupts(state, true);
455 static void s5pcsis_stop_stream(struct csis_state *state)
457 s5pcsis_enable_interrupts(state, false);
458 s5pcsis_system_enable(state, false);
461 static void s5pcsis_clear_counters(struct csis_state *state)
466 spin_lock_irqsave(&state->slock, flags);
467 for (i = 0; i < S5PCSIS_NUM_EVENTS; i++)
468 state->events[i].counter = 0;
469 spin_unlock_irqrestore(&state->slock, flags);
472 static void s5pcsis_log_counters(struct csis_state *state, bool non_errors)
474 int i = non_errors ? S5PCSIS_NUM_EVENTS : S5PCSIS_NUM_EVENTS - 4;
477 spin_lock_irqsave(&state->slock, flags);
479 for (i--; i >= 0; i--) {
480 if (state->events[i].counter > 0 || debug)
481 v4l2_info(&state->sd, "%s events: %d\n",
482 state->events[i].name,
483 state->events[i].counter);
485 spin_unlock_irqrestore(&state->slock, flags);
489 * V4L2 subdev operations
491 static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
493 struct csis_state *state = sd_to_csis_state(sd);
494 struct device *dev = &state->pdev->dev;
497 return pm_runtime_resume_and_get(dev);
499 return pm_runtime_put_sync(dev);
502 static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable)
504 struct csis_state *state = sd_to_csis_state(sd);
507 v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n",
508 __func__, enable, state->flags);
511 s5pcsis_clear_counters(state);
512 ret = pm_runtime_resume_and_get(&state->pdev->dev);
517 mutex_lock(&state->lock);
519 if (state->flags & ST_SUSPENDED) {
523 s5pcsis_start_stream(state);
524 state->flags |= ST_STREAMING;
526 s5pcsis_stop_stream(state);
527 state->flags &= ~ST_STREAMING;
529 s5pcsis_log_counters(state, true);
532 mutex_unlock(&state->lock);
534 pm_runtime_put(&state->pdev->dev);
539 static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd,
540 struct v4l2_subdev_state *sd_state,
541 struct v4l2_subdev_mbus_code_enum *code)
543 if (code->index >= ARRAY_SIZE(s5pcsis_formats))
546 code->code = s5pcsis_formats[code->index].code;
550 static struct csis_pix_format const *s5pcsis_try_format(
551 struct v4l2_mbus_framefmt *mf)
553 struct csis_pix_format const *csis_fmt;
555 csis_fmt = find_csis_format(mf);
556 if (csis_fmt == NULL)
557 csis_fmt = &s5pcsis_formats[0];
559 mf->code = csis_fmt->code;
560 v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
561 csis_fmt->pix_width_alignment,
562 &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
567 static struct v4l2_mbus_framefmt *__s5pcsis_get_format(
568 struct csis_state *state, struct v4l2_subdev_state *sd_state,
569 enum v4l2_subdev_format_whence which)
571 if (which == V4L2_SUBDEV_FORMAT_TRY)
572 return sd_state ? v4l2_subdev_get_try_format(&state->sd,
575 return &state->format;
578 static int s5pcsis_set_fmt(struct v4l2_subdev *sd,
579 struct v4l2_subdev_state *sd_state,
580 struct v4l2_subdev_format *fmt)
582 struct csis_state *state = sd_to_csis_state(sd);
583 struct csis_pix_format const *csis_fmt;
584 struct v4l2_mbus_framefmt *mf;
586 mf = __s5pcsis_get_format(state, sd_state, fmt->which);
588 if (fmt->pad == CSIS_PAD_SOURCE) {
590 mutex_lock(&state->lock);
592 mutex_unlock(&state->lock);
596 csis_fmt = s5pcsis_try_format(&fmt->format);
598 mutex_lock(&state->lock);
600 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
601 state->csis_fmt = csis_fmt;
602 mutex_unlock(&state->lock);
607 static int s5pcsis_get_fmt(struct v4l2_subdev *sd,
608 struct v4l2_subdev_state *sd_state,
609 struct v4l2_subdev_format *fmt)
611 struct csis_state *state = sd_to_csis_state(sd);
612 struct v4l2_mbus_framefmt *mf;
614 mf = __s5pcsis_get_format(state, sd_state, fmt->which);
618 mutex_lock(&state->lock);
620 mutex_unlock(&state->lock);
624 static int s5pcsis_s_rx_buffer(struct v4l2_subdev *sd, void *buf,
627 struct csis_state *state = sd_to_csis_state(sd);
630 *size = min_t(unsigned int, *size, S5PCSIS_PKTDATA_SIZE);
632 spin_lock_irqsave(&state->slock, flags);
633 state->pkt_buf.data = buf;
634 state->pkt_buf.len = *size;
635 spin_unlock_irqrestore(&state->slock, flags);
640 static int s5pcsis_log_status(struct v4l2_subdev *sd)
642 struct csis_state *state = sd_to_csis_state(sd);
644 mutex_lock(&state->lock);
645 s5pcsis_log_counters(state, true);
646 if (debug && (state->flags & ST_POWERED))
647 dump_regs(state, __func__);
648 mutex_unlock(&state->lock);
652 static const struct v4l2_subdev_core_ops s5pcsis_core_ops = {
653 .s_power = s5pcsis_s_power,
654 .log_status = s5pcsis_log_status,
657 static const struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
658 .enum_mbus_code = s5pcsis_enum_mbus_code,
659 .get_fmt = s5pcsis_get_fmt,
660 .set_fmt = s5pcsis_set_fmt,
663 static const struct v4l2_subdev_video_ops s5pcsis_video_ops = {
664 .s_rx_buffer = s5pcsis_s_rx_buffer,
665 .s_stream = s5pcsis_s_stream,
668 static const struct v4l2_subdev_ops s5pcsis_subdev_ops = {
669 .core = &s5pcsis_core_ops,
670 .pad = &s5pcsis_pad_ops,
671 .video = &s5pcsis_video_ops,
674 static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
676 struct csis_state *state = dev_id;
677 struct csis_pktbuf *pktbuf = &state->pkt_buf;
681 status = s5pcsis_read(state, S5PCSIS_INTSRC);
682 spin_lock_irqsave(&state->slock, flags);
684 if ((status & S5PCSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) {
687 if (status & S5PCSIS_INTSRC_EVEN)
688 offset = S5PCSIS_PKTDATA_EVEN;
690 offset = S5PCSIS_PKTDATA_ODD;
692 memcpy(pktbuf->data, (u8 __force *)state->regs + offset,
698 /* Update the event/error counters */
699 if ((status & S5PCSIS_INTSRC_ERRORS) || debug) {
701 for (i = 0; i < S5PCSIS_NUM_EVENTS; i++) {
702 if (!(status & state->events[i].mask))
704 state->events[i].counter++;
705 v4l2_dbg(2, debug, &state->sd, "%s: %d\n",
706 state->events[i].name,
707 state->events[i].counter);
709 v4l2_dbg(2, debug, &state->sd, "status: %08x\n", status);
711 spin_unlock_irqrestore(&state->slock, flags);
713 s5pcsis_write(state, S5PCSIS_INTSRC, status);
717 static int s5pcsis_parse_dt(struct platform_device *pdev,
718 struct csis_state *state)
720 struct device_node *node = pdev->dev.of_node;
721 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
724 if (of_property_read_u32(node, "clock-frequency",
725 &state->clk_frequency))
726 state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
727 if (of_property_read_u32(node, "bus-width",
728 &state->max_num_lanes))
731 node = of_graph_get_next_endpoint(node, NULL);
733 dev_err(&pdev->dev, "No port node at %pOF\n",
737 /* Get port node and validate MIPI-CSI channel id. */
738 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &endpoint);
742 state->index = endpoint.base.port - FIMC_INPUT_MIPI_CSI2_0;
743 if (state->index >= CSIS_MAX_ENTITIES) {
748 /* Get MIPI CSI-2 bus configuration from the endpoint node. */
749 of_property_read_u32(node, "samsung,csis-hs-settle",
751 state->wclk_ext = of_property_read_bool(node,
752 "samsung,csis-wclk");
754 state->num_lanes = endpoint.bus.mipi_csi2.num_data_lanes;
761 static int s5pcsis_pm_resume(struct device *dev, bool runtime);
762 static const struct of_device_id s5pcsis_of_match[];
764 static int s5pcsis_probe(struct platform_device *pdev)
766 const struct of_device_id *of_id;
767 const struct csis_drvdata *drv_data;
768 struct device *dev = &pdev->dev;
769 struct resource *mem_res;
770 struct csis_state *state;
774 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
778 mutex_init(&state->lock);
779 spin_lock_init(&state->slock);
782 of_id = of_match_node(s5pcsis_of_match, dev->of_node);
783 if (WARN_ON(of_id == NULL))
786 drv_data = of_id->data;
787 state->interrupt_mask = drv_data->interrupt_mask;
789 ret = s5pcsis_parse_dt(pdev, state);
793 if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) {
794 dev_err(dev, "Unsupported number of data lanes: %d (max. %d)\n",
795 state->num_lanes, state->max_num_lanes);
799 state->phy = devm_phy_get(dev, "csis");
800 if (IS_ERR(state->phy))
801 return PTR_ERR(state->phy);
803 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
804 state->regs = devm_ioremap_resource(dev, mem_res);
805 if (IS_ERR(state->regs))
806 return PTR_ERR(state->regs);
808 state->irq = platform_get_irq(pdev, 0);
812 for (i = 0; i < CSIS_NUM_SUPPLIES; i++)
813 state->supplies[i].supply = csis_supply_name[i];
815 ret = devm_regulator_bulk_get(dev, CSIS_NUM_SUPPLIES,
820 ret = s5pcsis_clk_get(state);
824 if (state->clk_frequency)
825 ret = clk_set_rate(state->clock[CSIS_CLK_MUX],
826 state->clk_frequency);
828 dev_WARN(dev, "No clock frequency specified!\n");
832 ret = clk_enable(state->clock[CSIS_CLK_MUX]);
836 ret = devm_request_irq(dev, state->irq, s5pcsis_irq_handler,
837 0, dev_name(dev), state);
839 dev_err(dev, "Interrupt request failed\n");
843 v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops);
844 state->sd.owner = THIS_MODULE;
845 snprintf(state->sd.name, sizeof(state->sd.name), "%s.%d",
846 CSIS_SUBDEV_NAME, state->index);
847 state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
848 state->csis_fmt = &s5pcsis_formats[0];
850 state->format.code = s5pcsis_formats[0].code;
851 state->format.width = S5PCSIS_DEF_PIX_WIDTH;
852 state->format.height = S5PCSIS_DEF_PIX_HEIGHT;
854 state->sd.entity.function = MEDIA_ENT_F_IO_V4L;
855 state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
856 state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
857 ret = media_entity_pads_init(&state->sd.entity,
858 CSIS_PADS_NUM, state->pads);
862 /* This allows to retrieve the platform device id by the host driver */
863 v4l2_set_subdevdata(&state->sd, pdev);
865 /* .. and a pointer to the subdev. */
866 platform_set_drvdata(pdev, &state->sd);
867 memcpy(state->events, s5pcsis_events, sizeof(state->events));
869 pm_runtime_enable(dev);
870 if (!pm_runtime_enabled(dev)) {
871 ret = s5pcsis_pm_resume(dev, true);
876 dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n",
877 state->num_lanes, state->hs_settle, state->wclk_ext,
878 state->clk_frequency);
882 media_entity_cleanup(&state->sd.entity);
884 clk_disable(state->clock[CSIS_CLK_MUX]);
886 s5pcsis_clk_put(state);
890 static int s5pcsis_pm_suspend(struct device *dev, bool runtime)
892 struct v4l2_subdev *sd = dev_get_drvdata(dev);
893 struct csis_state *state = sd_to_csis_state(sd);
896 v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
897 __func__, state->flags);
899 mutex_lock(&state->lock);
900 if (state->flags & ST_POWERED) {
901 s5pcsis_stop_stream(state);
902 ret = phy_power_off(state->phy);
905 ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES,
909 clk_disable(state->clock[CSIS_CLK_GATE]);
910 state->flags &= ~ST_POWERED;
912 state->flags |= ST_SUSPENDED;
915 mutex_unlock(&state->lock);
916 return ret ? -EAGAIN : 0;
919 static int s5pcsis_pm_resume(struct device *dev, bool runtime)
921 struct v4l2_subdev *sd = dev_get_drvdata(dev);
922 struct csis_state *state = sd_to_csis_state(sd);
925 v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
926 __func__, state->flags);
928 mutex_lock(&state->lock);
929 if (!runtime && !(state->flags & ST_SUSPENDED))
932 if (!(state->flags & ST_POWERED)) {
933 ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES,
937 ret = phy_power_on(state->phy);
939 state->flags |= ST_POWERED;
941 regulator_bulk_disable(CSIS_NUM_SUPPLIES,
945 clk_enable(state->clock[CSIS_CLK_GATE]);
947 if (state->flags & ST_STREAMING)
948 s5pcsis_start_stream(state);
950 state->flags &= ~ST_SUSPENDED;
952 mutex_unlock(&state->lock);
953 return ret ? -EAGAIN : 0;
956 #ifdef CONFIG_PM_SLEEP
957 static int s5pcsis_suspend(struct device *dev)
959 return s5pcsis_pm_suspend(dev, false);
962 static int s5pcsis_resume(struct device *dev)
964 return s5pcsis_pm_resume(dev, false);
969 static int s5pcsis_runtime_suspend(struct device *dev)
971 return s5pcsis_pm_suspend(dev, true);
974 static int s5pcsis_runtime_resume(struct device *dev)
976 return s5pcsis_pm_resume(dev, true);
980 static int s5pcsis_remove(struct platform_device *pdev)
982 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
983 struct csis_state *state = sd_to_csis_state(sd);
985 pm_runtime_disable(&pdev->dev);
986 s5pcsis_pm_suspend(&pdev->dev, true);
987 clk_disable(state->clock[CSIS_CLK_MUX]);
988 pm_runtime_set_suspended(&pdev->dev);
989 s5pcsis_clk_put(state);
991 media_entity_cleanup(&state->sd.entity);
996 static const struct dev_pm_ops s5pcsis_pm_ops = {
997 SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume,
999 SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume)
1002 static const struct csis_drvdata exynos4_csis_drvdata = {
1003 .interrupt_mask = S5PCSIS_INTMSK_EXYNOS4_EN_ALL,
1006 static const struct csis_drvdata exynos5_csis_drvdata = {
1007 .interrupt_mask = S5PCSIS_INTMSK_EXYNOS5_EN_ALL,
1010 static const struct of_device_id s5pcsis_of_match[] = {
1012 .compatible = "samsung,s5pv210-csis",
1013 .data = &exynos4_csis_drvdata,
1015 .compatible = "samsung,exynos4210-csis",
1016 .data = &exynos4_csis_drvdata,
1018 .compatible = "samsung,exynos5250-csis",
1019 .data = &exynos5_csis_drvdata,
1023 MODULE_DEVICE_TABLE(of, s5pcsis_of_match);
1025 static struct platform_driver s5pcsis_driver = {
1026 .probe = s5pcsis_probe,
1027 .remove = s5pcsis_remove,
1029 .of_match_table = s5pcsis_of_match,
1030 .name = CSIS_DRIVER_NAME,
1031 .pm = &s5pcsis_pm_ops,
1035 module_platform_driver(s5pcsis_driver);
1037 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1038 MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI-CSI2 receiver driver");
1039 MODULE_LICENSE("GPL");